A method for manufacturing a semiconductor structure and a semiconductor structure

Abstract

Embodiments of the present disclosure provide a preparation method of a semiconductor structure and the semiconductor structure. The preparation method comprises: providing a substrate, the substrate comprising at least an array region and a peripheral region, and an active region disposed on the array region and the peripheral region; forming a first dielectric layer on the substrate; performing a first etching process to remove part of the first dielectric layer and part of the substrate, so as to form a plurality of first grooves located in the array region and exposing part of the active region, and at least one second groove located in the peripheral region and exposing part of the active region; forming a first semiconductor layer, the first semiconductor layer covering part of the first grooves; forming a second dielectric layer on the first semiconductor layer, the second dielectric layer filling the first grooves and covering at least a surface of the array region; and performing a planarization process to remove the second dielectric layer and part of the first dielectric layer and the first semiconductor layer, so that a surface of the remaining first semiconductor layer is flush with a surface of the first dielectric layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular, to a method for manufacturing a semiconductor structure and the semiconductor structure. BACKGROUND

[0002] With the development and progress of technology, semiconductor devices are constantly developing towards miniaturization and high integration. Dynamic random access memory (DRAM) as an important semiconductor device can be used as data storage or program storage for electronic devices during operation to perform data processing. However, in the actual application process of dynamic random access memory, there is often a problem of low reliability. SUMMARY

[0003] Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, the method comprising:

[0004] providing a substrate, the substrate comprising at least an array region and a peripheral region, and an active region disposed on the array region and the peripheral region; forming a first dielectric layer on the substrate;

[0005] performing a first etching process to remove part of the first dielectric layer and part of the substrate to form a plurality of first grooves in the array region and exposing part of the active region, and at least one second groove in the peripheral region and exposing part of the active region;

[0006] forming a first semiconductor layer, the first semiconductor layer covering part of the first grooves;

[0007] forming a second dielectric layer on the first semiconductor layer, the second dielectric layer filling the first grooves and covering at least a surface of the array region;

[0008] performing a planarization process to remove the second dielectric layer and part of the first dielectric layer and the first semiconductor layer, so that the surface of the remaining first semiconductor layer is flush with the surface of the first dielectric layer.

[0009] In some embodiments, forming a first dielectric layer on the substrate comprises:

[0010] forming a first sub-layer, the first sub-layer covering a surface of the substrate;

[0011] forming a second sub-layer, the second sub-layer covering a surface of the first sub-layer.

[0012] In some embodiments, forming a plurality of first grooves in the array region and exposing part of the active region, and at least one second groove in the peripheral region and exposing part of the active region comprises:

[0013] performing a first etching process to remove part of the first dielectric layer and part of the substrate to form a plurality of the first recesses exposing part of the active region in the array region, and to form a plurality of sub-recesses exposing part of the active region and being interconnected with each other in the peripheral region, the plurality of the sub-recesses constituting the second recesses.

[0014] In some embodiments, after performing the first etching process and before forming the first semiconductor layer, the preparation method further comprises:

[0015] forming an insulating material layer covering the sidewalls and the bottom of the first recesses and covering the second recesses and the surface of the substrate;

[0016] performing a second etching process to remove part of the insulating material layer covering the bottom of the first recesses, and to remove part of the insulating material layer covering the bottom surface of the second recesses and the surface of the substrate, the insulating material layer remaining on the sidewall surfaces of the first recesses and the second recesses constituting an insulating layer.

[0017] In some embodiments, forming the first semiconductor layer comprises:

[0018] forming a first semiconductor material layer filling the first recesses and covering the second recesses and the surface of the substrate;

[0019] performing a back-etching process to remove part of the first semiconductor material layer covering the second recesses and the surface of the substrate, and to remove part of the first semiconductor material layer located in the first recesses to form the first semiconductor layer, wherein the upper surface of the first semiconductor layer is lower than the upper surface of the first recesses.

[0020] In some embodiments, forming the second dielectric layer on the first semiconductor layer comprises:

[0021] forming the second dielectric layer filling part of the first recesses not covered by the first semiconductor layer, and covering the array region, the second recesses and the surface of the peripheral region surrounding the second recesses.

[0022] In some embodiments, performing the planarization process comprises:

[0023] performing a planarization process to remove the second dielectric layer on the surface of the array region and on the surface of the peripheral region surrounding the second recesses, and to remove part of the first dielectric layer and part of the first semiconductor layer, so that the surface of the remaining first semiconductor layer is flush with the surface of the first dielectric layer.

[0024] In some embodiments, the planarization process includes a physical mechanical polishing process.

[0025] In some embodiments, at least part of the material of the first dielectric layer is the same as the material of the second dielectric layer.

[0026] In some embodiments, after performing the planarization process, the preparation method further includes:

[0027] forming a first mask layer, the first mask layer covering the array region;

[0028] removing, with the first mask layer as a mask, the first dielectric layer in the peripheral region and the insulating layer and the second dielectric layer covering the surface of the second recess, to expose the second recess.

[0029] In some embodiments, after exposing the second recess, the preparation method further includes:

[0030] forming a second mask layer in the peripheral region, a normal projection of the second mask layer on the substrate exposing the second recess;

[0031] performing an in-situ oxidation process on the active region exposed by the second recess, to form an oxide layer on the surface of the second recess;

[0032] removing the first mask layer and the second mask layer.

[0033] In some embodiments, after removing the first mask layer and the second mask layer, the preparation method further includes:

[0034] forming a second semiconductor material layer, the second semiconductor material layer covering the array region, the oxide layer and the surface of the peripheral region around the second recess;

[0035] performing a thinning process on the second semiconductor material layer on the surface of the array region and the surface of the peripheral region around the second recess, the remaining second semiconductor material layer constituting a second semiconductor layer; wherein the second semiconductor layer in the array region has a flush surface;

[0036] forming a conductive material layer, the conductive material layer covering the surface of the second semiconductor layer.

[0037] In some embodiments, after forming the conductive material layer, the method further includes:

[0038] performing a third etching process, to remove part of the conductive material layer and part of the second semiconductor layer, to form a bit line structure in the array region and a peripheral gate structure in the peripheral region.

[0039] The embodiments of the present disclosure further provide a semiconductor structure, comprising:

[0040] a substrate, the substrate comprising at least an array region and a peripheral region, and an active region disposed on the array region and the peripheral region;

[0041] a plurality of first recesses located on the array region and exposing part of the active region, and at least one second recess located on the peripheral region and exposing part of the active region; wherein the second recess comprises a plurality of sub-recesses;

[0042] a first semiconductor layer, the first semiconductor layer filling the first recesses;

[0043] a first dielectric layer, the first dielectric layer covering a surface of the substrate between the first recesses and a surface of the first dielectric layer being flush with a surface of the first semiconductor layer.

[0044] In some embodiments, the semiconductor structure further comprises an insulating layer located on a sidewall of the first recess, and the first semiconductor layer fills at least part of a cavity of the first recess which is not covered by the insulating layer.

[0045] The preparation method of the semiconductor structure and the semiconductor structure provided by the embodiments of the present disclosure, wherein the preparation method comprises the following steps: providing a substrate, wherein the substrate comprises at least an array region and a peripheral region, and an active region is arranged on the array region and the peripheral region; forming a first dielectric layer on the substrate; performing a first etching process to remove part of the first dielectric layer and part of the substrate, so as to form a plurality of first grooves located in the array region and exposing part of the active region, and at least one second groove located in the peripheral region and exposing part of the active region; forming a first semiconductor layer, wherein the first semiconductor layer covers part of the first grooves; forming a second dielectric layer located on the first semiconductor layer, wherein the second dielectric layer fills the first grooves and covers at least the surface of the array region; and performing a planarization process to remove the second dielectric layer and part of the first dielectric layer and the first semiconductor layer, so that the surface of the remaining first semiconductor layer is flush with the surface of the first dielectric layer. Since the first semiconductor layer only fills part of the grooves, the surfaces of the first semiconductor layer and the first dielectric layer are in an uneven state, and after the second dielectric layer is formed on the first semiconductor layer, the surface of the array region can be in a flat state. Then, after the second dielectric layer, part of the first dielectric layer and part of the first semiconductor layer are removed by performing the planarization process, the surface of the array region is correspondingly in a flat state (i.e., the surface of the remaining first semiconductor layer is flush with the surface of the first dielectric layer), which provides a good condition for the subsequent process. It can be understood that when other structures such as bit line structures are continuously formed on the array region subsequently, the bit line structures finally obtained can also correspondingly have better surface flatness and structural uniformity. Therefore, the preparation method provided by the embodiments of the present disclosure can effectively improve the stability and reliability of the semiconductor structure finally obtained. In addition, the formation of the grooves in the peripheral region is beneficial to the structures (for example, transistor structures) formed in the peripheral region subsequently to have better performance.

[0046] The details of one or more embodiments of the present disclosure are presented in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without creative labor.

[0048] Figure 1 The flowchart of the preparation method of the semiconductor structure provided by the embodiments of the present disclosure;

[0049] Figures 2 to 17A process flow chart of the semiconductor structure provided by the embodiments of the present disclosure in a preparation process is shown. DETAILED DESCRIPTION

[0050] Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. While example embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0051] In the following description, numerous specific details are given to provide a thorough understanding of the present disclosure. However, it will be apparent that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known structures and techniques have not been described in detail in order to avoid obscuring the present disclosure. In the following description, specific terminology and description have been used for the purposes of providing a thorough and complete disclosure of the present disclosure. It is understood that the present disclosure is not limited to the specific terms and description.

[0052] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numerals designate like elements throughout the specification.

[0053] It is to be understood that the terms "on", "adjacent", "connected to", or "coupled to" as used herein do not necessarily denote direct and immediate connections, but can also include connections through intervening elements or layers. On the contrary, the term "directly on", "directly adjacent", "directly connected to", or "directly coupled to" denotes no intervening elements or layers. It is to be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Conversely, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0054] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is inverted, then a dependent element or feature described as "below" or "beneath" another element or feature is oriented "above" or "over" the other element or feature. Thus, the exemplary term "below" or "beneath" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0056] In the structure of dynamic random memory (DRAM), a bit line plug is an important component, one end of which is connected with an active region in a substrate, and the other end of which is connected with a bit line structure. In the actual preparation process of the bit line plug, a method of forming a plurality of grooves in the substrate first, then filling a contact material layer in the grooves, and then performing an etching process is usually adopted to obtain the bit line plug. However, in actual operation, problems such as uneven distribution of etching gas or improper control of etching time are often encountered, so that in actual process, it is difficult to obtain a bit line plug with good structural uniformity, and further, the performance of other structures formed subsequently on the bit line plug will also be adversely affected.

[0057] Based on this, the following technical scheme of the embodiment of the disclosure is proposed:

[0058] The embodiment of the disclosure provides a preparation method of a semiconductor structure, as shown in the figure, the preparation method comprises the following steps: Figure 1 As shown in the figure, the preparation method comprises the following steps:

[0059] Step S101: providing a substrate, the substrate at least comprising an array region and a peripheral region, and the array region and the peripheral region are both provided with an active region; a first dielectric layer is formed on the substrate;

[0060] Step S102: performing a first etching process to remove part of the first dielectric layer and part of the substrate to form a plurality of first recesses located in the array region and exposing part of the active region, and at least one second recess located in the peripheral region and exposing part of the active region;

[0061] Step S103: forming a first semiconductor layer, the first semiconductor layer covering part of the first recesses;

[0062] Step S104: forming a second dielectric layer on the first semiconductor layer, the second dielectric layer filling the first recesses and covering at least the surface of the array region;

[0063] Step S105: performing a planarization process to remove part of the second dielectric layer, part of the first dielectric layer and part of the first semiconductor layer, so that the surface of the remaining first semiconductor layer is flush with the surface of the first dielectric layer.

[0064] Since the first semiconductor layer only fills part of the recesses, the surfaces of the first semiconductor layer and the first dielectric layer are in an uneven state. After forming the second dielectric layer on the first semiconductor layer, the surface of the array region can be made flat. Then, after the second dielectric layer, part of the first dielectric layer and part of the first semiconductor layer are removed by performing the planarization process, the surface of the array region is correspondingly made flat (i.e. the surface of the remaining first semiconductor layer is flush with the surface of the first dielectric layer), which provides good conditions for the subsequent process. It can be understood that when other structures such as bit line structures are subsequently formed on the array region, the bit line structures finally obtained can also correspondingly have better surface flatness and structural uniformity. Therefore, the preparation method provided by the embodiments of the present disclosure can effectively improve the stability and reliability of the semiconductor structure finally obtained. In addition, the formation of recesses in the peripheral region is also beneficial to the subsequent formation of structures (for example, transistor structures) in the peripheral region to obtain better performance.

[0065] To make the above-mentioned objects, features and advantages of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure will be described in detail below with reference to the drawings. In the detailed description of the embodiments of the present disclosure, the schematic diagrams will be partially enlarged without the general proportion for the convenience of description, and the schematic diagrams are only examples which should not limit the protection scope of the present disclosure herein.

[0066] Figures 2 to 17 The process flow chart of the semiconductor structure provided by the embodiments of the present disclosure in the preparation process.

[0067] The preparation method of the semiconductor structure provided by the embodiments of the present disclosure will be further described in detail below with reference to the drawings.

[0068] Firstly, step S101 is performed, for example, Figure 2 andFigure 3 As shown, a substrate 10 is provided, the substrate 10 at least includes an array region 21 and a peripheral region 22, and the array region 21 and the peripheral region 22 are both provided with an active region 13; a first dielectric layer 11 is formed on the substrate 10.

[0069] In some embodiments, the substrate 10 further includes an isolation structure STI, the isolation structure STI isolates the substrate into a plurality of active regions 13.

[0070] Here, the substrate can be a semiconductor substrate; the material of the semiconductor substrate specifically includes an elemental semiconductor material (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), or a III-V compound semiconductor material (for example, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), or a II-VI compound semiconductor material, or an organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon substrate.

[0071] In some embodiments, the material of the isolation structure STI includes but is not limited to at least one of an oxide, a nitride, and an oxynitride, or a combination thereof. In some specific embodiments, the material of the isolation structure STI can be a silicon oxide, a silicon nitride, or a composite layer composed of silicon oxide. However, it is not limited to this, and in actual processes, the isolation structure STI can also be other materials, which can be flexibly selected according to actual conditions, and is not particularly limited here.

[0072] Continuing to refer to Figure 3 As shown, it can be seen that, in some embodiments, forming the first dielectric layer 11 on the substrate 10 includes:

[0073] forming a first sub-layer L1, the first sub-layer L1 covering the surface of the substrate 10;

[0074] forming a second sub-layer L2, the second sub-layer L2 covering the surface of the first sub-layer L1.

[0075] Here, the material of the first sub-layer includes but is not limited to an oxide material, and the material of the second sub-layer includes but is not limited to a nitride material. In some specific embodiments, the material of the first sub-layer includes but is not limited to silicon oxide, etc., and the material of the second sub-layer includes but is not limited to silicon nitride, etc.

[0076] In actual operations, the formation of the first dielectric layer can be formed using one or more thin film deposition processes; specifically, the thin film deposition process includes but is not limited to a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, or a combination thereof.

[0077] Next, step S102 is performed, as shown in Figure 4As shown, a first etching process is performed to remove part of the first dielectric layer 11 and part of the substrate 10 to form a plurality of first recesses T1 located in the array region 21 and exposing part of the active region 13, and at least one second recess T2 located in the peripheral region 22 and exposing part of the active region 13.

[0078] In some embodiments, forming the plurality of first recesses T1 located in the array region 21 and exposing part of the active region 13, and the at least one second recess T2 located in the peripheral region 22 and exposing part of the active region 13, comprises:

[0079] The first etching process is performed to remove part of the first dielectric layer 11 and part of the substrate 10 to form a plurality of first recesses T1 exposing part of the active region 13 in the array region 21, and a plurality of sub-recesses 131 exposing part of the active region 13 and being interconnected with each other in the peripheral region 22, the plurality of sub-recesses 131 constituting the second recess T2.

[0080] Optionally, the first etching process can include, but is not limited to, at least one of a dry etching process or a wet etching process, or a combination thereof. In some embodiments, the first etching process can be completed by using a dry etching process.

[0081] In some embodiments, the bottoms of the plurality of interconnected sub-recesses can be in a wavy connection state.

[0082] In this embodiment, in order to obtain the first recess and the second recess simultaneously in the same step, the operation of etching a plurality of sub-recesses in the peripheral region synchronously at adjacent positions is adopted while etching the first recess, and when the first recess is formed, the plurality of sub-recesses in the peripheral region are interconnected with each other, so that the second recess can be obtained simultaneously.

[0083] In some embodiments, the size of the sub-recess in the direction parallel to the surface of the substrate can be less than or equal to the size of the first recess. However, it is not limited thereto, and in some embodiments, the size of the sub-recess can also be greater than the size of the first recess, which can be selected flexibly according to actual conditions, and is not limited herein.

[0084] In the embodiments of the present disclosure, the trench formed in the peripheral region can effectively improve the performance of the structure (e.g., transistor structure) formed subsequently in the peripheral region. It can be understood that, compared with the structure in which the transistor disposed in the peripheral region is a planar transistor, the channel length of the transistor structure with the recess structure at the bottom can be effectively increased, thereby preventing the occurrence of short channel effect and significantly improving the performance of the transistor structure. In addition, since the trench formed at the bottom of the transistor structure in the peripheral region can significantly increase the channel length, the size of the gate structure covering the channel can also be increased accordingly. Therefore, compared with the planar transistor structure, the transistor structure with the recess structure at the bottom can have a larger channel length and gate length when occupying the same size of the substrate, thereby achieving better performance (e.g., smaller on-resistance, lower threshold voltage, and lower leakage current).

[0085] Meanwhile, when the semiconductor structure needs to be further improved in integration, the transistor structure with the recess structure at the bottom can not affect the normal performance of the transistor structure even if the size of the substrate is reduced to a certain extent, thereby facilitating the development of the semiconductor structure in the direction of improving the integration, while the performance is also taken into account.

[0086] Further, in the embodiments of the present disclosure, the second recess further comprises a plurality of sub-recesses, which, on the one hand, overcomes the disadvantage that the first recess and the second recess cannot be formed at the same time due to the large difference in size, and on the other hand, compared with the second recess without the plurality of sub-recesses, the second recess with the plurality of sub-recesses (the bottoms of the plurality of sub-recesses in communication with each other can be in a wave-shaped connection state) is also beneficial to further increase the area of the surface at the bottom position of the second recess, thereby improving the channel length and the gate length of the subsequently obtained structure to a greater extent, and further improving the performance of the transistor structure.

[0087] In addition, the plurality of sub-recesses further comply with the development of the semiconductor structure in the direction of improving the integration, while the performance is also taken into account.

[0088] It should be noted that, in the drawings of the embodiments of the present disclosure, only the case in which the second recess comprises two sub-recesses is schematically shown, and in actual operation, the number of sub-recesses is not limited to the number shown in the drawings. Optionally, in some embodiments, the number of sub-recesses can also be 3, 4, 5, 8, 10, dozens or even more. The number of sub-recesses can be selected according to actual conditions, and is not limited herein.

[0089] Next, step S103 is performed, as shown in FIG. 1C. Figure 7 and Figure 8As shown, a first semiconductor layer 141 is formed, which covers part of the first recess T1.

[0090] It can be understood that, in some embodiments, as shown in Figure 5 and Figure 6 As shown, after the first etching process is performed, before the first semiconductor layer 141 is formed, the preparation method further includes:

[0091] An insulating material layer 17a is formed, which covers the sidewalls and bottom of the first recess T1 and covers the surface of the second recess T2 and the substrate 10;

[0092] A second etching process is performed to remove the part of the insulating material layer 17a covering the bottom of the first recess T1, and remove the part of the insulating material layer 17a covering the bottom surface of the second recess T2 and the surface of the substrate 10, and the insulating material layer 17a remaining on the sidewall surface of the first recess T1 and the second recess T2 constitutes an insulating layer 17.

[0093] Here, the material of the insulating layer includes but is not limited to nitride, such as silicon nitride, etc.

[0094] It can be understood that, since the source region is also arranged between the plurality of first recesses, the subsequently formed bit line structure will include not only the part directly connected with the source region through the bit line plug, but also the part above the source region between the first recesses but not directly connected with the source region. When the sidewall of the first recess is covered with the insulating layer, a good electrical isolation effect can be achieved between the bit line structure and the source region located thereunder but not directly connected with the bit line structure in the region between the first recesses, preventing the occurrence of short circuit phenomenon. At the same time, when the sidewall of the first recess is covered with the insulating layer, the electrical isolation effect between the source regions located near the first recess can also be effectively improved. Therefore, the semiconductor structure provided by the embodiments of the present disclosure can have higher reliability.

[0095] Optionally, in some embodiments, the thickness of the insulating layer 17 ranges between 1 nm and 4 nm (including the end point value), such as 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, etc.

[0096] Continuing to refer to Figure 7 and Figure 8 As can be seen, in some embodiments, the formation of the first semiconductor layer 141 includes:

[0097] A first semiconductor material layer 141a is formed, which fills the first recess T1 and covers the surface of the second recess T2 and the substrate 10;

[0098] The etch-back process is performed to remove the portion of the first semiconductor material layer 141a covering the surface of the substrate 10 and the second recess T2, and to remove the portion of the first semiconductor material layer 141a located in the first recess T1 to form the first semiconductor layer 141, wherein the upper surface of the first semiconductor layer 141 is lower than the upper surface of the first recess T1.

[0099] Here, the material of the first semiconductor layer includes but is not limited to conductive material. In some embodiments, the material of the first semiconductor layer can be polysilicon.

[0100] In actual operation, the etch-back process can be implemented by dry etching process. However, it is not limited to this, in some other embodiments, the etch-back process can also be implemented by other conventional techniques, which are not limited here.

[0101] Then, step S104 is performed, as shown in FIG. 1C, the second dielectric layer 12 is formed on the first semiconductor layer 141, the second dielectric layer 12 fills the first recess T1 and covers at least the surface of the array region 21. Figure 9

[0102] Optionally, the material of at least part of the first dielectric layer 11 can be the same as the material of the second dielectric layer 12.

[0103] Here, the material of the second dielectric layer can be the same as the material of the second sub-layer. Optionally, in some embodiments, the material of the second dielectric layer includes but is not limited to silicon nitride, etc.

[0104] In this embodiment, since in the previous step, the first semiconductor layer only fills part of the recess, so that the surfaces of the first semiconductor layer and the first dielectric layer are in an uneven state, after the second dielectric layer is formed on the first semiconductor layer, the surface of the array region can be made to obtain a flat state, thereby providing favorable conditions for the array region to obtain a flat surface after the step of performing the planarization process.

[0105] In actual operation, the second dielectric layer can cover the surface of the peripheral region in addition to the surface of the array region. For example:

[0106] In some embodiments, as shown in FIG. 1C, the second dielectric layer 12 formed on the first semiconductor layer 141 includes: Figure 9

[0107] The second dielectric layer 12 is formed, the second dielectric layer 12 fills the portion of the first recess T1 not covered by the first semiconductor layer 141, and covers the surfaces of the array region 21, the second recess T2, and the peripheral region 22 located around the second recess T2.

[0108] ​​It can be understood that the second medium layer also covers the surface of the peripheral region, which can effectively reduce the height difference between the surface of the array region and the surface of the peripheral region, and provide good conditions for the subsequent planarization process.

[0109] Finally, step S105 is performed, as shown in Figure 10 The planarization process is performed to remove the second medium layer 12 and part of the first medium layer 11 and the first semiconductor layer 141, so that the surface of the remaining first semiconductor layer 141 is flush with the surface of the first medium layer 11.

[0110] In some embodiments, the planarization process includes:

[0111] The planarization process is performed to remove the second medium layer 12 located on the surface of the array region 21 and the surface of the peripheral region 22 around the second groove T2, and to remove part of the first medium layer 11 and part of the first semiconductor layer 141, so that the surface of the remaining first semiconductor layer 141 is flush with the surface of the first medium layer 11.

[0112] Here, in actual operation, the surface of the first semiconductor layer can be flush with the surface of the second sub-layer.

[0113] It can be understood that after the planarization process step is performed, the remaining first semiconductor layer can be used as a bit line plug of the semiconductor structure. At this time, since the first semiconductor layer serving as the bit line plug function and the first medium layer located around it have flush surfaces, the bit line material layer to be subsequently formed on the array region can also obtain a flat surface, which is beneficial to improve the flatness and uniformity between the bit line structures formed by etching the bit line material layer, and further to make the semiconductor structure also obtain higher stability and reliability.

[0114] In some embodiments, the planarization process includes a physical and mechanical polishing process.

[0115] Here, since the planarization process uses a physical and mechanical polishing process, the polishing selection ratio between materials is less involved, which is beneficial to obtain a better flat state between the first semiconductor layer and the first medium layer.

[0116] It can be understood that after the above steps are completed, some other operations can also be performed to obtain more structures. For example:

[0117] In some embodiments, as shown in Figure 11 After the planarization process is performed, the preparation method further includes:

[0118] A first mask layer M1 is formed, which covers the array region 21;

[0119] With the first mask layer M1 as a mask, the first dielectric layer 11 located in the peripheral region 22 and the insulating layer 17 and the second dielectric layer 12 covering the surface of the second trench T2 are removed to expose the second trench T2.

[0120] In some embodiments, as shown in Figure 12 、 Figure 13 and Figure 14 , after the second trench T2 is exposed, the preparation method further comprises:

[0121] forming a second mask layer M2 located in the peripheral region 22, the orthographic projection of the second mask layer M2 on the substrate 10 exposes the second trench T2;

[0122] performing an in-situ oxidation process on the active region 13 exposed by the second trench T2 to form an oxide layer 16 on the surface of the second trench T2;

[0123] removing the first mask layer M1 and the second mask layer M2.

[0124] In actual operation, the material of the first mask layer and the second mask layer can include but is not limited to photoresist and the like.

[0125] Optionally, in addition to using the in-situ oxidation process, the oxide layer 16 can also be formed by material deposition, which can be flexibly selected according to actual conditions and is not limited here.

[0126] In some embodiments, as shown in Figure 14 、 Figure 15 and Figure 16 , after the first mask layer M1 and the second mask layer M2 are removed, the preparation method further comprises:

[0127] forming a second semiconductor material layer 142a, the second semiconductor material layer 142a covering the surface of the array region 21, the oxide layer 16 and the peripheral region 22 located around the second trench T2;

[0128] performing a thinning process on the second semiconductor material layer 142a located on the surface of the array region 21 and the surface of the peripheral region 22 located around the second trench T2, and the remaining second semiconductor material layer 142a constitutes a second semiconductor layer 142; wherein the second semiconductor layer 142 located in the array region 21 has a flush surface;

[0129] forming a conductive material layer 15 covering the surface of the second semiconductor layer 142.

[0130] Here, the material of the second semiconductor material layer can be the same as or different from the material of the first semiconductor layer, which is not specifically limited here. Optionally, in some embodiments, the material of the second semiconductor material layer can include but is not limited to polysilicon and the like. The material constituting the conductive material layer can include but is not limited to a metal material, for example, tungsten and the like.

[0131] Optionally, continuing to refer to Figure 15 As shown in the figure, it can be seen that, in some embodiments, before the conductive material layer 15 is formed, the preparation method can further include:

[0132] The barrier layer 18 is formed to cover the surface of the second semiconductor layer 142.

[0133] Here, the barrier layer can be used as a diffusion barrier layer to prevent the metal material contained in the conductive material layer from diffusing downward, thereby improving the reliability of the finally obtained semiconductor structure.

[0134] Continuing to refer to Figure 16 It can be seen that, in some embodiments, after the conductive material layer 15 is formed, the preparation method can further include:

[0135] The cap material layer 19a is formed to cover the surface of the conductive material layer 15.

[0136] Here, the material forming the cap material layer includes an insulating material, for example, a nitride material and the like. Optionally, in some specific embodiments, the cap material layer can be silicon nitride. However, it is not limited thereto, and in actual applications, the cap material layer can also be other materials, which can be determined according to actual conditions, and is not specifically limited here.

[0137] It can be understood that, due to the surface of the first semiconductor layer and the first dielectric layer located in the array region being flush, the second semiconductor layer subsequently formed above the array region can also obtain a surface with higher flatness, which provides favorable conditions for the subsequently formed bit line structure to have higher surface flatness and better structural consistency, and helps the finally obtained semiconductor structure to have higher stability and reliability.

[0138] It can be understood that, in some embodiments, as Figure 17 shown, after the conductive material layer 15 is formed, the method further includes:

[0139] The third etching process is performed to remove part of the conductive material layer 15 and part of the second semiconductor layer 142, so as to form the bit line structure BL located in the array region 21 and the peripheral gate structure PG located in the peripheral region 22.

[0140] Continuing to refer to Figure 17Optionally, in some embodiments, before forming the bit line structure BL and the peripheral gate structure PG, the method further comprises:

[0141] performing a fourth etching process to remove part of the cap material layer 19a to form a cap layer 19 above the bit line structure BL and a cap layer 19 above the peripheral gate structure PG.

[0142] In this embodiment, the formation of the cap layer above the bit line structure and the peripheral gate structure helps to protect the bit line structure and the peripheral gate structure from being contaminated or damaged in subsequent processes, thereby facilitating the improvement of the performance of the finally formed semiconductor structure.

[0143] Optionally, after forming the peripheral gate structure, a source / drain region and the like can be further formed on both sides of the peripheral gate by a doping process and the like to finally obtain a transistor structure in the peripheral region.

[0144] In this embodiment, due to the foregoing reasons, the obtained bit line structure also has a higher surface flatness and better structural consistency, and when other operation steps are further included to obtain other structures, the good bit line structure provides favorable conditions for the execution of subsequent operation steps, which helps to obtain a semiconductor structure with better stability and reliability.

[0145] In addition, since the recess structure is formed below the peripheral gate structure, the performance of the transistor structure in the peripheral region can be effectively improved. Even in some embodiments in which the integration level needs to be improved, the transistor structure will not affect the normal performance even if it occupies a certain amount of substrate size. Therefore, the transistor structure in the peripheral region provided by the embodiments of the present disclosure can be applied to semiconductor structures with high integration requirements in addition to conventional applications.

[0146] It can be understood that, in some other embodiments, when the third etching process is performed after the formation of the conductive material layer, in addition to the above operations, the Figure 17 the first sub-layer of the insulating layer located on the side wall of the first recess and the second sub-layer of the substrate surface located between the plurality of bit line structures are removed at the same time, at this time, the obtained semiconductor structure can also have better stability and reliability, and a smaller weight can also be obtained.

[0147] The embodiments of the present disclosure also provide a semiconductor structure, as shown in Figure 17 The semiconductor structure comprises:

[0148] a substrate 10, the substrate 10 at least comprising an array region 21 and a peripheral region 22, and the array region 21 and the peripheral region 22 are both provided with an active region 13;

[0149] a plurality of first trenches T1 located in the array region 21 and exposing part of the active region 13, and at least one second trench T2 located in the peripheral region 22 and exposing part of the active region 13; wherein the second trench T2 comprises a plurality of sub-trenches 131;

[0150] a first semiconductor layer 141 filling the first trench T1;

[0151] a first dielectric layer 11 covering the surface of the substrate 10 between the first trenches T1 and having a surface level with the surface of the first semiconductor layer 141.

[0152] In some embodiments, the first and second trenches can be obtained in the same process step. It can be understood that, in order to obtain the first and second trenches synchronously in the same step, the plurality of sub-trenches in the peripheral region can be synchronously etched in adjacent positions at the same time when the first trench is formed, so that the plurality of sub-trenches in the peripheral region are interconnected when the first trench is formed, thereby synchronously obtaining the second trench.

[0153] In some embodiments, the size of the sub-trenches in the direction parallel to the surface of the substrate can be less than or equal to the size of the first trench. However, the size of the sub-trenches can also be greater than the size of the first trench in some embodiments, which can be flexibly selected according to actual conditions and is not limited herein.

[0154] In some embodiments, the bottoms of the plurality of interconnected sub-trenches can be in a wavy connection state.

[0155] In the embodiments of the present disclosure, the trenches formed in the peripheral region can effectively improve the performance of the structure (such as the transistor structure) subsequently formed in the peripheral region. It can be understood that, compared with the planar transistor structure in the conventional structure, the channel length of the transistor structure with the trench structure at the bottom can be effectively increased, thereby preventing the occurrence of the short channel effect and significantly improving the performance of the transistor structure. In addition, since the trench structure at the bottom of the transistor structure in the peripheral region can significantly increase the channel length, the size of the gate structure covering the channel can also be increased, so that, compared with the planar transistor structure, the transistor structure with the trench structure at the bottom can have a greater channel length and gate length when occupying the same size of the substrate, thereby obtaining better performance.

[0156] Meanwhile, when the semiconductor structure needs to be further improved in integration, the transistor structure provided with the groove structure at the bottom can not affect the normal performance of the transistor structure even if the transistor structure occupies a smaller size of the substrate, thereby facilitating the development of the semiconductor structure in the direction of improving the integration, while the performance is also taken into account.

[0157] Further, in the embodiment of the present disclosure, the second groove further comprises a plurality of sub-grooves, which, on the one hand, overcomes the shortcoming that the first groove and the second groove cannot be formed at the same time due to the too large size difference; on the other hand, compared with the second groove without the plurality of sub-grooves, the second groove further comprising the plurality of sub-grooves (the bottoms of the plurality of sub-grooves in communication with each other can be in a wavy connection state) is also conducive to further increasing the area of the surface at the bottom position of the second groove, so that the subsequent obtained structure can have a greater improvement in the channel length and the gate length, and further improves the performance of the transistor structure.

[0158] In addition, the plurality of sub-grooves further comply with the development of the semiconductor structure in the direction of improving the integration, while the performance is also taken into account.

[0159] It should be noted that in the drawings of the embodiment of the present disclosure, only the case that the second groove comprises two sub-grooves is schematically shown, and in actual operation, the number of sub-grooves is not limited to the number shown in the drawings. Optionally, in some embodiments, the number of sub-grooves can also be 3, 4, 5, 8, 10, dozens or even more, etc. The number of sub-grooves can be selected according to actual conditions, which is not limited here.

[0160] Continuing to refer to Figure 17 It can be seen that in some embodiments, the semiconductor structure further comprises an insulating layer 17 located at the sidewall of the first groove T1, and the first semiconductor layer 141 fills at least part of the cavity of the first groove T1 which is not covered by the insulating layer 17.

[0161] Here, the material of the insulating layer includes but is not limited to nitride, such as silicon nitride, etc.

[0162] In actual process, the first semiconductor layer can be used as a bit line plug of the semiconductor structure, and a bit line structure is further provided above the bit line plug, and the bit line structure can extend along a first direction parallel to the substrate plane.

[0163] It can be understood that, since the source region is also arranged between the plurality of first grooves, the bit line structure will include a part above the source region between the first grooves but not directly connected thereto in addition to the part directly connected to the source region through the bit line plug. When the sidewall of the first groove is covered with the insulating layer, a better electrical isolation effect can be achieved between the bit line structure and the source region below it but not directly in contact with it in the region between the first grooves, preventing the occurrence of short circuit phenomenon. At the same time, when the sidewall of the first groove is covered with the insulating layer, the electrical isolation effect between the source regions near the first groove can also be effectively improved. Therefore, the semiconductor structure provided by the embodiments of the present disclosure can have higher reliability.

[0164] Optionally, in some embodiments, the thickness of the insulating layer 17 ranges between 1 nm and 4 nm (including the end point value), for example, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, etc.

[0165] But not limited to this, it can be understood that, in some other embodiments, the semiconductor structure can also not be provided with Figure 17 The second sub-layer of the insulating layer on the sidewall of the first groove and the substrate surface between the plurality of bit line structures shown in the above embodiments, at this time, the semiconductor structure can also have better stability and reliability, and a smaller weight can also be obtained.

[0166] It can be understood that the semiconductor structure can be obtained by using the preparation method involved in any of the above embodiments.

[0167] It should be noted that the preparation method of the semiconductor device provided by the embodiments of the present disclosure can be applied to DRAM structures or other semiconductor devices, which are not limited here. The embodiments of the semiconductor device preparation method provided by the present disclosure belong to the same concept as the embodiments of the semiconductor device. The technical features in the technical solutions described in each embodiment can be combined arbitrarily without conflict.

[0168] The above is only a preferred embodiment of the present disclosure, and is not intended to limit the protection scope of the present disclosure. Any modification, equivalent replacement and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The preparation method comprises: providing a substrate, the substrate comprising at least an array region and a peripheral region, and an active region disposed on the array region and the peripheral region; forming a first dielectric layer on the substrate; performing a first etching process to remove part of the first dielectric layer and part of the substrate to form a plurality of first grooves in the array region and exposing part of the active region, and at least one second groove in the peripheral region and exposing part of the active region; forming a first semiconductor layer, the first semiconductor layer covering part of the first grooves; forming a second dielectric layer on the first semiconductor layer, the second dielectric layer filling the first grooves and covering at least the surface of the array region; performing a planarization process to remove the second dielectric layer and part of the first dielectric layer and the first semiconductor layer, so that the surface of the remaining first semiconductor layer is flush with the surface of the first dielectric layer.

2. The production method according to claim 1, characterized by, forming a first dielectric layer on the substrate, comprising: forming a first sub-layer, the first sub-layer covering the surface of the substrate; forming a second sub-layer, the second sub-layer covering the surface of the first sub-layer.

3. The preparation method according to claim 1, characterized in that, forming a plurality of first grooves in the array region and exposing part of the active region, and at least one second groove in the peripheral region and exposing part of the active region, comprising: performing a first etching process to remove part of the first dielectric layer and part of the substrate to form a plurality of the first grooves in the array region and exposing part of the active region, and form a plurality of sub-grooves in the peripheral region and exposing part of the active region and being interconnected, the plurality of sub-grooves constituting the second groove.

4. The method of claim 1, wherein, After performing the first etching process and before forming the first semiconductor layer, the preparation method further comprises: forming an insulating material layer, the insulating material layer covering the sidewall and bottom of the first grooves and covering the second groove and the surface of the substrate; performing a second etching process to remove part of the insulating material layer covering the bottom of the first grooves, and remove part of the insulating material layer covering the bottom surface of the second groove and the surface of the substrate, the insulating material layer remaining on the sidewall surface of the first grooves and the second grooves constituting an insulating layer.

5. The preparation method according to claim 1, characterized in that, forming the first semiconductor layer, comprising: forming a first semiconductor material layer, the first semiconductor material layer filling the first grooves and covering the second groove and the surface of the substrate; performing a back-etching process to remove part of the first semiconductor material layer covering the second groove and the surface of the substrate, and remove part of the first semiconductor material layer in the first grooves to form the first semiconductor layer, wherein the upper surface of the first semiconductor layer is lower than the upper surface of the first grooves.

6. The production method according to any one of claims 1 to 5, characterized by, forming the second dielectric layer on the first semiconductor layer, comprising: forming the second dielectric layer, the second dielectric layer filling the part of the first grooves not covered by the first semiconductor layer, and covering the surface of the array region, the second groove and the peripheral region around the second groove.

7. The production method according to claim 6, wherein performing the planarization process, comprising: A planarization process is performed to remove the second dielectric layer on the surface of the array region and on the surface of the peripheral region surrounding the second recess, and to remove part of the first dielectric layer and part of the first semiconductor layer, so that the surface of the remaining first semiconductor layer is flush with the surface of the first dielectric layer.

8. The production method according to claim 1 or 7, characterized by, The planarization process includes a physical and mechanical polishing process.

9. The preparation method according to claim 7, characterized in that, The material of at least part of the first dielectric layer is the same as the material of the second dielectric layer.

10. The method of claim 9, wherein, After the planarization process is performed, the preparation method further includes: forming a first mask layer covering the array region; with the first mask layer as a mask, removing the first dielectric layer on the peripheral region, and removing the insulating layer and the second dielectric layer covering the surface of the second recess, to expose the second recess.

11. The method of claim 10, wherein, After the second recess is exposed, the preparation method further includes: forming a second mask layer on the peripheral region, the orthographic projection of the second mask layer on the substrate exposing the second recess; performing an in-situ oxidation process on the active region exposed by the second recess, to form an oxide layer on the surface of the second recess; removing the first mask layer and the second mask layer.

12. The method of claim 11, wherein, After the first mask layer and the second mask layer are removed, the preparation method further includes: forming a second semiconductor material layer covering the array region, the oxide layer, and the surface of the peripheral region surrounding the second recess; performing a thinning process on the second semiconductor material layer on the surface of the array region and on the surface of the peripheral region surrounding the second recess, the remaining second semiconductor material layer constituting a second semiconductor layer; wherein the second semiconductor layer on the array region has a flush surface; forming a conductive material layer covering the surface of the second semiconductor layer.

13. The method of claim 12, wherein, After the conductive material layer is formed, the method further includes: performing a third etching process to remove part of the conductive material layer and part of the second semiconductor layer, to form a bit line structure on the array region and a peripheral gate structure on the peripheral region.

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