A memory layout optimization method and device

Abstract

The embodiment of the present application provides a memory arrangement optimization method and device for optimizing memory arrangement position and improving computing performance. Specifically, it includes: obtaining a memory arrangement request, the memory arrangement request includes the memory block size, start time and end time of each memory block in at least two memory blocks; determining a first arrangement order of the at least two memory blocks according to the memory block size, the start time and the end time; arranging the at least one memory block according to the first arrangement order.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory layout optimization method and device. Background Art

[0002] At present, artificial intelligence technology has entered the stage of all-round commercialization, and has had different degrees of impact on all parties involved in traditional industries, changing the ecology of various industries. Artificial intelligence relies on models and powerful computing power. Models are the core of artificial intelligence, and a huge amount of training is required to obtain the structure and parameters of the model. Powerful computing power is the key factor for the application of artificial intelligence, and the output results corresponding to the input information need to be calculated in a timely manner. The processing of calculations involves the input and output of data. The storage inside the computing chip is very expensive. It is necessary to use double data rate synchronous dynamic random-access memory (DDR SDRAM) to store data. When the corresponding data is processed, the data is read from the DDR memory into the chip, and then calculated. After the calculation is completed, the data is stored in the DDR memory or stored in the disk. In artificial intelligence, calculations are performed according to the granularity of the operator. When executing an operator, the input of the operator needs to be transferred to the fast buffer storage area (Cache). After the calculation is completed, the output of the operator needs to be written to the cache and then exported to the DDR memory. If the cache allocation location of the operator's input and output is unreasonable, data will need to be frequently exchanged between the cache and the DDR memory, resulting in an increase in the idle rate of the neural-network processing unit (NPU) or a longer model execution time, thus affecting the learning effect of deep learning.

[0003] Currently, memory size is usually standardized and reused. Figure 1 As shown in the figure, the size of memory block A is 10KB, the size of memory block B is 20KB, the size of memory block C is 20KB, the size of memory block D is 40KB, the size of memory block E is 40KB, the size of memory block G is 20KB, and the size of memory block F is 40KB. The time unit is 1. After traversal, there are three memory specifications, namely 10KB, 20KB, and 40KB. Memory of the same specification is reused as much as possible, and memory of different specifications is difficult to reuse. When memory of the same specification is not enough, new memory resources will be applied.

[0004] But from Figure 1 It can be seen from the example that there is a lot of memory waste. When the number of memory requirements increases and the specifications increase, the waste becomes more serious. Memory blocks of different specifications are difficult to reuse, and some memory is not fully reused, resulting in imperfect memory reuse and wasted memory space. Summary of the invention

[0005] The embodiments of the present application provide a memory arrangement optimization method and device for optimizing memory arrangement and improving computing performance.

[0006] In a first aspect, an embodiment of the present application provides a memory layout optimization method, specifically comprising: the memory optimization device obtains a memory layout request, the memory layout request including the memory block size, start time and end time of each memory block in at least two memory blocks; then determines a first layout order of each memory block in the at least two memory blocks according to the memory layout request; and finally arranges the at least two memory blocks according to the first layout order.

[0007] In this embodiment, the memory optimization device obtains the offset of the at least two memory blocks relative to the benchmark memory block after arranging the at least two memory blocks according to the first arrangement order. Finally, the memory optimization device stores data according to the offset of each memory block in the at least two memory blocks relative to the benchmark memory block.

[0008] In this embodiment, a memory arrangement request may correspond to the memory requirement of an artificial intelligence (AI) model, that is, a memory arrangement request includes multiple memory blocks corresponding to an AI model, which can effectively reduce information interaction and improve network resource utilization.

[0009] In the technical solution provided in this embodiment, the memory optimization device arranges multiple memory blocks according to preset rules and no longer standardizes and reuses them. That is, the data to be stored can be arranged in memory blocks corresponding to its own size requirements, and the memory blocks can be arranged and reused according to preset rules, thereby reducing the waste of memory resources.

[0010] Optionally, the memory optimization device determines the first arrangement order of the at least two memory blocks according to the memory block size, the start time and the end time as follows: the memory optimization device sorts the at least two memory blocks according to the memory block size, the start time and the end time according to a preset rule to obtain the first arrangement order, and the preset rule includes sorting the at least two memory blocks from large to small according to the life cycle (i.e., sorting in descending order according to the life cycle), wherein the life cycle is the time period between the start time and the end time. In this embodiment, sorting from large to small according to the life cycle can prioritize memory blocks with longer demand time, which can effectively reduce the difficulty of memory reuse in time.

[0011] Optionally, the preset rule also includes sorting the multiple memory blocks from large to small according to the memory block size (i.e., sorting them in descending order according to the memory block size) if there are multiple memory blocks with the same life cycle in the at least two memory blocks. In this way, the reuse of memory blocks in memory offset can be reduced while satisfying the premise of satisfying the reuse of memory blocks in time. At the same time, when the life cycle and memory block size are the same and there are no other constraints, the memory optimization device can arbitrarily determine the order of memory blocks.

[0012] Optionally, the memory arrangement request may also include a constraint condition, wherein the constraint condition is used to indicate a position constraint between the at least two memory blocks. The position constraint may be used to indicate the positional relationship between the at least two memory blocks, such as the at least two memory blocks need to be placed adjacently or spaced apart, etc. The position constraint may also include a continuity constraint, i.e., determining that at least two memory blocks need to be connected and placed in sequence. Assume that there is a continuity constraint between memory block A, memory block B, and memory block C, and the continuity constraint is used to limit the arrangement order of the three memory blocks to be memory block A before memory block B, and memory block B before memory block C.

[0013] Optionally, when the memory arrangement request includes a constraint condition, the memory optimization device may perform the following operations to determine the arrangement order of each of the at least two memory blocks:

[0014] The memory optimization device determines a first arrangement order of each memory block in the at least two memory blocks according to the memory arrangement request and preset rules and constraints, that is, the first arrangement order satisfies the constraints.

[0015] Among them, the specific operations of the memory optimization device for sorting according to the preset rules and the constraint conditions are as follows: the memory optimization device determines at least two associated memory blocks in the at least two memory blocks according to the constraint conditions; then adjusts the start time and end time of the at least two associated memory blocks to obtain multiple adjusted associated memory blocks as an overall memory block; determines the start time and end time of the overall memory block; finally, the memory optimization device sorts the overall memory block and other memory blocks in the at least two memory blocks according to the preset rules to obtain the first arrangement order.

[0016] In this embodiment, when there are constraints, the memory optimization device needs to arrange the memory blocks according to preset rules while satisfying the constraints, which can simultaneously achieve effective reuse of memory space and individual requirements, and more effectively realize dynamic adjustment of memory arrangement.

[0017] Optionally, the minimum start time among the multiple adjusted start times of the associated memory blocks is the start time of the overall memory block, and the maximum end time among the multiple adjusted end times of the associated memory blocks is the end time of the overall memory block.

[0018] Optionally, after the memory optimization device determines the arrangement of the at least two memory blocks according to the preset rule, the memory optimization device may continue to optimize the memory arrangement, and the specific operations are as follows:

[0019] The memory optimization device uses the maximum value of the memory space required by the at least two memory blocks according to the first arrangement order and obtains the peak memory; then determines the first memory block corresponding to the peak memory from the at least two memory blocks; then determines at least one first related memory block of the first memory block, wherein the life cycle of the at least one first related memory block overlaps with the life cycle of the first memory block; the memory optimization device then determines the target memory block from the at least one first related memory block, the target memory block is the memory block with the largest life cycle in the at least one first related memory block, and there is unoccupied memory space before the start offset of the target memory block; then the memory optimization device obtains the second related memory block of the target memory block, the memory offset of the second related memory is greater than or equal to the end offset of the target memory block, and the life cycle of the second related memory block overlaps with the life cycle of the target memory block; the memory optimization device sorts the second related memory block and the target memory block according to the life cycle from small to large to obtain a second arrangement order, and arranges the at least two memory blocks according to the second arrangement order. In this way, the memory that is not reused in the memory space can be further optimized, thereby reducing memory requirements.

[0020] The second aspect of the embodiment of the present application provides a memory optimization device, which has the function of implementing the behavior of the memory optimization device in the first aspect. The function can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0021] In a possible implementation, the device includes a unit or module for executing each step of the first aspect above. For example, the device includes: an acquisition module for acquiring a memory arrangement request, the memory arrangement request including the memory block size, start time and end time of at least two memory blocks; a processing module for determining a first arrangement order of the at least two memory blocks according to the memory arrangement request, and arranging the at least two memory blocks according to the first arrangement order.

[0022] Optionally, a storage module is also included to store the necessary program instructions and data of the memory optimization device.

[0023] In a possible implementation, the module includes: a processor and a transceiver, wherein the processor is configured to support the memory optimization device to perform the corresponding functions in the method provided in the first aspect. The transceiver is used to instruct the memory optimization device to send and receive information or instructions. Optionally, this module may also include a memory, which is coupled to the processor and stores the necessary program instructions and data for the memory optimization device.

[0024] In a possible implementation, when the memory optimization device is a chip, the chip includes: a processing module and a transceiver module, the transceiver module can be, for example, an input / output interface, a pin or a circuit on the chip, etc., to transmit a memory arrangement request to other chips or modules coupled to the chip or transmit a memory arrangement response to other chips or modules coupled to the chip; the processing module can be, for example, a processor, which is used to determine the first arrangement order of the at least two memory blocks according to the memory arrangement request, and arrange the at least two memory blocks according to the first arrangement order. The processing module can execute computer-executable instructions stored in the storage unit to support the memory optimization device to perform the method provided in the first aspect above. Optionally, the storage unit can be a storage unit in the chip, such as a register, a cache, etc., and the storage unit can also be a storage unit located outside the chip, such as a read-only memory (ROM) or other types of static storage modules that can store static information and instructions, a random access memory (RAM), etc.

[0025] The processors mentioned in any of the above may include one or more neural-network processing units (NPUs). They may also include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of programs of the spectrum resource reuse methods in the above aspects.

[0026] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer storage medium stores computer instructions, and the computer instructions are used to execute the method described in the first aspect above.

[0027] In a fourth aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer instructions to execute the method described in the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic diagram of an example of memory normalization reuse;

[0029] Figure 2 A hardware structure diagram of a memory optimization device;

[0030] Figure 3 A flowchart of memory writing and calling during operator calculation;

[0031] Figure 4 This is a schematic diagram of an exemplary relationship between a request module and a response module in a memory optimization device in an embodiment of the present application;

[0032] Figure 5 A schematic diagram of an embodiment of a memory arrangement optimization method in an embodiment of the present application;

[0033] Figure 6a This is a schematic diagram of an exemplary correspondence between a memory requirement identifier and a memory block in an embodiment of the present application;

[0034] Figure 6b This is another exemplary corresponding schematic diagram of the memory requirement identifier and the memory block in the embodiment of the present application;

[0035] Figure 7 A schematic diagram of adjusting the termination time of an associated memory block in an embodiment of the present application;

[0036] Figure 8 A schematic diagram of recalculating the life cycle of an associated memory block in an embodiment of the present application;

[0037] Fig. 9 A schematic diagram of an arrangement result of memory blocks in an embodiment of the present application;

[0038] Fig.10 A schematic diagram of another embodiment of the memory arrangement optimization method in the embodiment of the present application;

[0039] Fig.11 This is another schematic diagram of the arrangement result of the memory blocks in the embodiment of the present application;

[0040] Fig.12A schematic diagram of an embodiment of a memory optimization device in an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the present application more clear, the embodiments of the present application are described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. It is known to those skilled in the art that with the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0042] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described here can be implemented in an order other than the content illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or modules is not necessarily limited to those steps or modules clearly listed, but may include other steps or modules that are not clearly listed or inherent to these processes, methods, products or devices. The naming or numbering of steps in this application does not mean that the steps in the method flow must be executed in the time / logical sequence indicated by the naming or numbering. The process steps that have been named or numbered can change the execution order according to the technical purpose to be achieved, as long as the same or similar technical effects can be achieved. The division of units in this application is a logical division. There may be other division methods when it is implemented in actual applications. For example, multiple units can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection between units can be electrical or other similar forms, which are not limited in this application. In addition, the units or sub-units described as separate components may or may not be physically separated, may or may not be physical units, or may be distributed in multiple circuit units, and some or all of the units may be selected according to actual needs to achieve the purpose of the present application.

[0043] The technical solution provided by the embodiment of the present invention can be applied to Figure 2 In the memory optimization device 200 shown, Figure 2The memory optimization device 200 shown may include: a processor 202, a computer-readable storage medium / memory 203, a transceiver 204, an input device 205 and an output device 206, and a bus 201. Among them, the processor, the transceiver, the computer-readable storage medium, etc. are connected via a bus. The embodiment of the present application does not limit the specific connection medium between the above-mentioned components. It is understandable that the memory optimization device 200 may have more or fewer components than shown in the figure, may combine two or more components, or may have different component configurations. The various components shown in the figure can be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application-specific integrated circuits. The processor 202 involved in the above-mentioned memory optimization device 200 can be a neural network processing unit (NPU), and can also include a general-purpose processor, such as an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components or one or more integrated circuits for controlling the execution of programs of the above-mentioned spectrum resource reuse methods. The controller / processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of DSP and microprocessors, and the like. The processor usually performs logical and arithmetic operations based on program instructions stored in the memory. The bus 201 mentioned above may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 2It is represented by only one thick line, but it does not mean that there is only one bus or one type of bus. The computer-readable storage medium / memory 203 mentioned above may also store an operating system and other application programs. Specifically, the program may include a program code, and the program code includes computer operation instructions. More specifically, the above-mentioned memory may be a read-only memory (ROM), other types of static storage modules that can store static information and instructions, a random access memory (RAM), other types of dynamic storage modules that can store information and instructions, a disk storage, and the like. The memory 203 may be a combination of the above-mentioned storage types. And the above-mentioned computer-readable storage medium / memory may be in the processor, or may be outside the processor, or distributed on multiple entities including a processor or a processing circuit. The above-mentioned computer-readable storage medium / memory may be specifically embodied in a computer program product. For example, a computer program product may include a computer-readable medium in a packaging material. At the same time, the memory optimization device may be a computer or other terminal device that can run AI model calculations. And the specific process of calculating the AI ​​model may be as follows Figure 3 As shown, in artificial intelligence, it is the processor ( Figure 3(In the example of CPU or NPU, it is explained) and the calculation is performed according to the granularity of the operator. When executing an operator, the input information of the operator needs to be transferred from the DDR memory to the fast buffer storage area (Cache). After the calculation is completed, the output information of the operator needs to be written to the Cache, and then exported to the DDR memory, and finally stored in the hard disk. If the cache allocation position of the input and output of the operator is unreasonable, it is necessary to frequently exchange data between the Cache and the DDR memory, resulting in an increase in the NPU idle rate or a longer model execution time, thereby affecting the learning effect of deep learning. In order to achieve memory layout optimization and improve computing performance, an embodiment of the present application provides a memory layout optimization method, which is as follows: the memory optimization device 200 obtains a memory layout request, and the memory layout request includes a memory block size, a start time and an end time of each memory block in at least two memory blocks; the memory optimization device 200 determines the first arrangement order of the at least two memory blocks according to the memory block size, the start time and the end time; the memory optimization device 200 arranges the at least two memory blocks according to the first arrangement order. In this embodiment, the memory optimization function can be implemented by functional modules such as the request module and the response module in the memory optimization device. That is, the request module and the response module can be functional modules in the processor of the memory optimization device 200, and the memory optimization function in the embodiment of the present application is implemented by calling the instructions or codes stored in the memory of the memory optimization device 200. Among them, the request module and the response module can be different threads in the same computing device; or the request module and the response module are processes in different computing devices respectively, and their specific forms of expression can be as follows: Figure 4 shown.

[0044] For easier understanding, the terms in the embodiments of the present application are described below:

[0045] Memory block: A continuous memory space, the smallest unit of memory management.

[0046] Offset: The relative offset between multiple memory blocks.

[0047] Peak memory: The maximum value of the memory space required during the memory layout process.

[0048] Memory blocks related within a life cycle: memory blocks with overlapping life cycles.

[0049] In this embodiment, the memory arrangement optimization method in the embodiment of the present application is described with the request module and the response module as the execution body. For the specific embodiment, please refer to Figure 5 As shown:

[0050] 501. The request module sends a memory arrangement request to the response module, wherein the memory arrangement request includes a memory block size, a start time, and an end time of each memory block in at least two memory blocks.

[0051] In this embodiment, the start time and the end time can be absolute time, such as accurate to a few minutes and seconds, etc.; or, the start time and the end time can also use operators as timing units, such as one operator is counted as one time unit, in which case the start time can be marked as 1, and the end time can be marked as 4. The specific form of the memory arrangement request can be as shown in Table 1. The memory requirement identifier is used to identify the memory block, thereby avoiding a large amount of repeated content in the request. The start time is used to identify the start time when the memory block is used for calculation, the end time is used to identify the completion time when the memory block is used for calculation, and the memory block size is used to identify the memory space of the memory block. It can be understood that one memory block can correspond to one memory requirement identifier, or multiple memory blocks can correspond to one memory requirement identifier. Specifically, when there are constraints between at least two memory blocks, the at least two memory blocks can be identified by one memory requirement identifier. As shown in Table 1, the memory requirement identifier is used to identify the memory block. Figure 6a The following is the information carried by the memory arrangement request when there are no constraints. In this case, one memory requirement identifier corresponds to the information of one memory block. When there are constraints, the information carried by the memory arrangement request can be as follows: Figure 6b As shown, at this time, a memory requirement identifier corresponds to the information of multiple memory blocks (such as Figure 6b As shown, it can correspond to the information of three memory blocks).

[0052] Table 1

[0053]

[0054] In this embodiment, a memory arrangement request may correspond to the calculation of an AI model, that is, a memory arrangement request may be used to indicate an arrangement request for multiple memory blocks corresponding to a model. At the same time, the memory arrangement request may also include constraints between memory blocks. For example, if memory block A and memory block B need to be arranged together, or the output information of operator A needs to be used as the input information of operator B, then the memory occupied by the output information of operator A can be adjacent to the memory occupied by the output information of operator B.

[0055] 502. The response module determines a first arrangement order of the at least two memory blocks according to the memory arrangement request.

[0056] The response module obtains information of each memory block (ie, the size, start time, and end time of the memory block), and finally determines a first arrangement sequence of the at least one memory block according to the information of the memory block and a preset rule.

[0057] In this embodiment, the preset rule is to sort the life cycles of the memory blocks from large to small; if the life cycles are the same, the memory blocks are sorted from large to small according to their sizes. If the life cycles and memory block sizes are the same and there are no other constraints, the order of the memory blocks can be determined arbitrarily.

[0058] According to the above rules, assuming that there are no constraints between the memory blocks in Table 1, the final arrangement order can be shown in Table 2:

[0059] Table 2

[0060]

[0061] As can be seen from the above table, the memory block with memID 0 has a life cycle of 20, which is the longest among the above memory blocks. Therefore, the memory block with memID 0 is ranked first and is placed first. The memory blocks with memID 125 and memID 132 both have a life cycle of 7, which is the second longest. Therefore, these two memory blocks are arranged first. At the same time, since the memory size of the memory block with memID 125 is 1501888 and the memory size of the memory block with memID 132 is 700960, that is, the memory size of the memory block with memID 125 is larger than the memory size of the memory block with memID 132, the memory block with memID 125 is ranked second and the memory block with memID 132 is ranked third. When the other memory blocks have the same life cycle, they are arranged from large to small according to the memory block size. If there are at least two memory blocks with the same memory size and life cycle, and there are no other constraints, the at least two memory blocks can be arranged arbitrarily. It is understandable that when the memory arrangement request includes constraints, the response module needs to preprocess the memory blocks according to the constraints when sorting them, and sort them according to the constraints. The constraints are used to indicate the position constraints between at least two memory blocks. Among them, the position constraint can be used to represent the placement relationship of at least two memory blocks, such as the need for the at least two memory blocks to be placed adjacently or spaced apart, etc. The position constraint can also include continuity constraints, such as limiting that at least two memory blocks need to be placed consecutively. For example, memory block A is located before memory block B, and memory block B is located before memory block C. The preprocessing of memory blocks with constraints by the response module specifically includes the following aspects: 1. Adjusting the termination time of the memory blocks; 2. Adjusting the arrangement position of the memory blocks. An exemplary scheme is as follows Figure 7As shown in the figure, the output memory of operator A and the output memory of operator C are used as the input memory of operator B. Both are used as the input memory of operator B at the same time. In this way, the expiration time of the output memory of operator A needs to be extended to the expiration time of the output memory 1 of operator B. At the same time, operator B does not apply for output memory, and reuses the output memory of operator A and operator C as the input memory and output memory of operator B. Subsequent sorting by life cycle needs to be sorted according to the new life cycle.

[0062] At the same time, Figure 7 It can be seen that the output memory of operator A and the output memory of operator C are used as the input memory of operator B. The two need to be placed adjacently, and the output memory of operator A and the output memory of operator C are located before the output memory of operator B in time. In an exemplary solution, the information of each memory block in the memory demand request is shown in Table 3:

[0063] Table 3

[0064] life cycle Memory block size (in bytes) Memory requirement flag 4 536448 5 7 1501888 4 2 700960 3 3 2765984 1 20 5531936 2

[0065] The memory block with a memory requirement identifier of 1 needs to be arranged adjacent to the memory block with a memory requirement identifier of 2, so the final order of the memory blocks shown in Table 3 can be shown in Table 4:

[0066] Table 4

[0067]

[0068] In this exemplary solution, the memory block with a memory requirement identifier of 1 needs to be stored as a whole memory block with a memory requirement identifier of 2, and its life cycle needs to be recalculated. If the life cycle of the memory block with a memory requirement identifier of 1 overlaps with the life cycle of the memory block with a memory requirement identifier of 2, the minimum value among multiple start times is taken as the start time of the whole memory block, and the maximum value among multiple end times is taken as the end time of the whole memory block, and then the life cycle of the whole memory block is calculated. Specifically, it can be as follows Figure 8 As shown in the figure, the start time of the memory block corresponding to operator A is 0 and the end time is 4; the start time of the memory block corresponding to operator B is 2 and the end time is 8. If the memory block corresponding to operator A needs to be arranged adjacent to the memory block corresponding to operator B, the start time of the entire memory block corresponding to operator A and operator B should be 0 and the end time should be 8, and the life cycle of the entire memory block is 8.

[0069] 503. The response module arranges the at least two memory blocks according to the first arrangement sequence. After determining the first arrangement sequence according to a preset rule, the response module arranges the at least two memory blocks according to a non-overlapping rule. For example, if the first arrangement sequence determined by the response module for each memory block shown in Table 1 is shown in Table 2, then the response module arranges each memory block shown in Table 1 according to the arrangement sequence shown in Table 2, and the final arrangement result can be as follows: Fig. 9 shown.

[0070] The response module arranges the at least two memory blocks according to the non-overlapping rule according to the first arrangement order, and records the relative offsets between the memory blocks in the at least two memory blocks, thereby obtaining the first offset of each memory block in the at least two memory blocks. In this embodiment, the offset specifically indicates the relative offset between the at least two memory blocks. For example, according to the principle of occupied memory space and non-overlapping between memory blocks, it is determined that the offset of the first laid out memory block is 4 (that is, the first laid out memory block is offset by 4 relative to the laid out memory), and the offset of the second laid out memory block is 5 (the second laid out memory block is offset by 5 relative to the first laid out memory block).

[0071] Then the response module sends a first memory arrangement response to the request module, the first memory arrangement response including a first offset of each memory block in the at least two memory blocks. After receiving the first offset of each memory block in the at least two memory blocks, the request module stores the data into the corresponding memory block according to the first offset if data storage is required.

[0072] exist Fig. 9 In the arrangement result, further optimization can be performed. The specific process is as follows Fig.10 As shown:

[0073] 1001. The response module determines the peak memory and obtains the life cycle of the memory block corresponding to the peak memory.

[0074] After the at least two memory blocks are sorted according to the preset rules, the response module obtains the peak memory under the sorting, wherein the peak memory is the maximum value of the memory space required in the process of arranging the at least two memory blocks, and obtains the life cycle of the memory block corresponding to the peak memory. Fig. 9 As shown, the maximum value of the memory space required by the memory block is close to 16MB, and the memory block corresponding to the memory space close to 16MB is memory block 7, and the life cycle of memory block 7 is 1.

[0075] 1002. The response module determines at least one first related memory block of the memory block corresponding to the peak memory.

[0076] In this embodiment, the life cycle of the at least one first related memory block overlaps with the life cycle of the memory block corresponding to the peak memory. In this implementation, the overlap may include the existence of a contained relationship in the life cycle, or may refer to the existence of adjacent life cycles of two memory blocks. For example, if the end time of the first memory block is 8, and the start time of the second memory block is 8, then the life cycles of the first memory block and the second memory block also overlap. Fig. 9 As shown, the first related memory block includes memory block 4, memory block 5, and memory block 6.

[0077] 1003. The response module determines a target memory block from the at least one first related memory block, where the target memory block is a memory block with the longest life cycle among the at least one related memory block, and there is unoccupied memory space before the starting offset of the target memory block.

[0078] The starting offset of the target memory block is the starting offset of the target memory block relative to other memory blocks, which are also called reference memory blocks, for example, the memory block arranged in the first position. Specifically, the starting offset is the relative displacement relative to the starting offset position of the memory block arranged in the first position. Fig. 9 , the starting offset of the base memory block 1 is 0, the starting offset of the memory block 4 is 2, and the starting offset of the memory block 8 is 10.

[0079] The response module determines a target memory block from the at least one first related memory block, the target memory block being the largest memory block in the life cycle of the first related memory block, and the target memory block having a hole below the memory space (i.e., the starting offset of the target memory block) (i.e., there is an unoccupied memory space before the starting offset of the target memory block, such as Fig. 9 It is understandable that the target memory block may also satisfy the following conditions, such as the target memory block has no associated memory blocks, which is equivalent to the target memory block having no constrained adjacent memory blocks or memory blocks that need to be synchronously adjusted. Fig. 9 As shown, among memory blocks 4, 5, and 6, memory block 4 has the longest life cycle, and there is a hole below memory block 4 (that is, there is unoccupied memory space) and Fig. 9 There are no constraints between the memory blocks shown, that is, there are no memory blocks that must be placed adjacent to each other. In this case, the memory block 4 can be used as the target memory block.

[0080] 1004. The response module determines a second related memory block of the target memory block.

[0081] The response module selects a second related memory block whose offset is greater than or equal to the termination offset of the target memory block and whose life cycle overlaps. That is, the offset of the second related memory block needs to be after the termination offset of the target memory block, and the life cycle of the second related memory block needs to overlap with the life cycle of the target memory block. The termination offset of the target memory block is the termination offset of the target memory block relative to other memory blocks, which are also called reference memory blocks, for example, the memory blocks arranged in the first position. Specifically, the termination offset is a relative displacement relative to the starting offset position of the memory block arranged in the first position. Fig. 9 , the starting offset of the base memory block 1 is 0, the starting offset of the memory block 4 is 2, and its ending offset is 5, and the ending offset of the memory block 7 is 16. Fig. 9 As shown, memory block 16, memory block 5, memory block 6, memory block 8, memory block 7 and memory block 10 are second related memory blocks of the target memory block.

[0082] 1005. The response module arranges the second related memory block and the target memory block in ascending order according to life cycles to obtain a second arrangement order.

[0083] The response module sorts the second related memory block and the target memory block from small to large according to the life cycle to obtain an arrangement result between the second related memory and the target memory block, and updates the first arrangement order according to the arrangement result to obtain a second arrangement order of the at least two memory blocks. Fig. 9 For example, in the first arrangement order, the arrangement order of the target memory block and the second related memory block is the memory block 4, the memory block 5, the memory block 6, the memory block 7, the memory block 8, the memory block 10 and the memory block 16 (the memory block 4 is arranged first, then arranged in sequence, and the memory block 16 is arranged last). In the updated second arrangement order, the arrangement order of the target memory block and the second related memory block is the memory block 5, the memory block 6, the memory block 7, the memory block 8, the memory block 10, the memory block 16 and the memory block 4 (the memory block 5 is arranged first, then arranged in sequence, and the memory block 16 is arranged last). It can be understood that in the process of sorting the target memory block and the second related memory block in ascending order according to the life cycle, if the life cycle is the same, they can be arranged in descending order according to the memory block size. If the memory block size is the same, they can be sorted according to the constraints between the memory blocks. If there are no constraints between the memory blocks, the memory blocks can be sorted arbitrarily.

[0084] 1006. The response module arranges the at least two memory blocks according to the second arrangement order.

[0085] The response module re-arranges each memory block in sequence according to the second arrangement order, and ensures that the newly arranged memory blocks do not overlap with the already arranged memory blocks at the same time. According to this rule, Fig. 9 The result of the optimized memory layout can be shown as Fig.11 shown.

[0086] It is understandable that if the response module has the function of memory optimization, the response module can send two memory arrangement responses to the requester. Among them, the first memory arrangement request includes the offset of each memory block in the at least two memory blocks obtained by arranging the at least two memory blocks according to the first arrangement order; the second memory arrangement request includes the offset of each memory block in the at least two memory blocks obtained by arranging the at least two memory blocks according to the optimized second arrangement order, and indicates that the memory arrangement response sent for the second time is the offset finally executed. Optionally, the response module can also send a memory arrangement response to the request module once, and the memory arrangement response includes the offset of each memory block in the at least two memory blocks obtained by masking the at least two memory blocks according to the optimized second arrangement order. Finally, the requester can write the corresponding data according to the offset.

[0087] In this embodiment, the response module arranges multiple memory blocks according to rules and no longer standardizes and reuses them. That is, each data to be stored can correspond to a memory block according to its own size requirements, and memory arrangement and memory reuse are performed according to the memory block size, thereby reducing the waste of memory resources.

[0088] The above describes the memory arrangement optimization method in the embodiment of the present application. The following describes the memory optimization device in the embodiment of the present application.

[0089] Please refer to Fig.12 As shown, the memory optimization device 1200 in the embodiment of the present application includes: an acquisition module 1201, a processing module 1202 and a scheduling module 1203. The device 1200 can be used to perform the above Figures 5 to 11 The functions of the response module and the request module in any embodiment.

[0090] For example, the acquisition module 1201 can be used to execute step 501 in the above method embodiment. For example, the acquisition module 1201 receives a memory arrangement request sent by a request module, wherein the memory arrangement request includes the memory block size, start time and end time of at least two memory blocks.

[0091] For example, the processing module 1202 may be used to execute step 502 in the above method embodiment. For example, the processing module 1202 determines a first arrangement sequence of the at least two memory blocks according to the memory arrangement request.

[0092] For example, the scheduling module 1203 may be used to execute step 503 in the above method embodiment. For example, the scheduling module 1203 arranges the at least two memory blocks according to the first arrangement sequence.

[0093] Optionally, the device 1200 also includes a storage module, which is coupled to the processing module so that the processing module can execute the computer-executable instructions stored in the storage module to implement the functions of the request module or the response module in the above method embodiment, or to ensure the memory consistency of each computing resource. In an example, the storage module optionally included in the device 1200 can be a storage unit in the chip, such as a register, a cache, etc., and the storage module can also be a storage unit located outside the chip, such as a read-only memory (ROM) or other types of static storage modules that can store static information and instructions, a random access memory (RAM), etc.

[0094] It should be understood that the above Fig.12 The processes executed between the modules of the memory optimization device in the corresponding embodiment are similar to those in the above Figures 5 to 11 The processes executed by the response module and the request module in the corresponding method embodiment are similar, and will not be repeated here.

[0095] Alternatively, the embodiment of the present application also provides a general processing system, such as a chip, which includes: one or more microprocessors that provide processor functions; and an external memory that provides at least a portion of the storage medium, all of which are connected to other supporting circuits through an external bus architecture. When the instructions stored in the memory are executed by the processor, the processor executes the local operation module in Figures 5 to 11 Part or all of the steps in the memory layout optimization method in the described embodiments, and other processes used for the technology described in this application.

[0096] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0097] In the several embodiments provided in the present application, it should be understood that the disclosed systems, modules and methods can be implemented in other ways. For example, the module embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, modules or units, which can be electrical, mechanical or other forms.

[0098] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0099] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0100] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer module (which can be a personal computer, a server, or a network module, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program code.

[0101] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory layout optimization method, characterized in that: include: Obtain a memory arrangement request, wherein the memory arrangement request includes a memory block size, a start time and an end time of each memory block in at least two memory blocks; Determine a first arrangement order of the at least two memory blocks according to a preset rule, wherein the preset rule includes sorting the at least two memory blocks from large to small according to life cycles, wherein the life cycle is a time period between the start time and the end time, wherein the start time is used to identify a start time when the memory block is used for calculation, and the end time is used to identify a completion time when the memory block is used for calculation; The at least two memory blocks are arranged according to the first arrangement sequence.

2. The method according to claim 1, characterized in that: The preset rule also includes: if there are multiple memory blocks with the same life cycle, the multiple memory blocks are sorted from large to small according to the memory block sizes of the multiple memory blocks.

3. The method according to claim 1 or 2, characterized in that: The memory arrangement request includes a constraint condition, wherein the constraint condition includes a position constraint between the at least two memory blocks, and the position constraint is used to indicate a positional relationship between the at least two memory blocks; the first arrangement sequence satisfies the constraint condition.

4. The method according to claim 3, characterized in that The step of sorting the at least two memory blocks according to a preset rule to obtain the first arrangement order includes: Determining at least two associated memory blocks from among the at least two memory blocks according to the constraint condition; adjusting the start time and the end time of the at least two associated memory blocks to obtain a plurality of adjusted associated memory blocks as an overall memory block; Determine the start time and end time of the overall memory block; The overall memory block and other memory blocks in the at least two memory blocks are sorted according to the preset rule to obtain the first arrangement order.

5. The method according to claim 4, characterized in that The minimum start time among the adjusted start times of the associated memory blocks is the start time of the overall memory block, and the maximum end time among the adjusted end times of the associated memory blocks is the end time of the overall memory block.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: According to the first arrangement sequence, a maximum value of the memory space required by the at least two memory blocks is obtained as a peak memory; Determining a first memory block corresponding to the peak memory from the at least two memory blocks; Determining at least one first related memory block of the first memory block, wherein a life cycle of the at least one first related memory block overlaps with a life cycle of the first memory block; Determine a target memory block from the at least one first related memory block, the target memory block being a memory block with the longest life cycle among the at least one first related memory block, and there is unoccupied memory space before a starting offset of the target memory block, the starting offset being a starting offset of the target memory block relative to other memory blocks; Determine a second related memory block according to the target memory block, the second related memory block being a memory block whose start offset is greater than or equal to the end offset of the target memory block and has a life cycle overlap with the target memory block, the end offset being the end offset of the target memory block relative to other memory blocks; Arrange the target memory block and the second related memory block in ascending order according to their life cycles to obtain a second arrangement order; The at least two memory blocks are arranged according to the second arrangement sequence.

7. A memory optimization device, characterized in that: include: An acquisition module, used for acquiring a memory arrangement request, wherein the memory arrangement request includes a memory block size, a start time and an end time of each memory block in at least two memory blocks; a processing module, configured to determine a first arrangement order of the at least two memory blocks according to a preset rule, wherein the preset rule comprises sorting the at least two memory blocks from large to small according to life cycles, wherein the life cycle is a time period between the start time and the end time, wherein the start time is used to identify a start time when the memory block is used for calculation, and the end time is used to identify a completion time when the memory block is used for calculation; A scheduling module is used to arrange the at least one memory block according to the first arrangement sequence.

8. The device according to claim 7, characterized in that The preset rule also includes: if there are multiple memory blocks with the same life cycle, the multiple memory blocks are sorted from large to small according to the memory block sizes of the multiple memory blocks.

9. The device according to claim 7 or 8, characterized in that The memory arrangement request includes a constraint condition, wherein the constraint condition includes a position constraint between the at least two memory blocks, and the position constraint is used to indicate a positional relationship between the at least two memory blocks; the first arrangement sequence satisfies the constraint condition.

10. The device according to claim 9, characterized in that The processing module is specifically configured to determine at least two associated memory blocks from among the at least two memory blocks according to the constraint condition; adjusting the start time and the end time of the at least two associated memory blocks to obtain a plurality of adjusted associated memory blocks as an overall memory block; Determine the start time and end time of the overall memory block; The overall memory block and other memory blocks in the at least two memory blocks are sorted according to the preset rule to obtain the first arrangement order.

11. The device according to claim 10, characterized in that The minimum start time among the adjusted start times of the associated memory blocks is the start time of the overall memory block, and the maximum end time among the adjusted end times of the associated memory blocks is the end time of the overall memory block.

12. The device according to any one of claims 7 to 11, characterized in that The processing module is further used to obtain the maximum value of the memory space required by the at least two memory blocks according to the first arrangement sequence as the peak memory; Determining a first memory block corresponding to the peak memory from the at least two memory blocks; Determining at least one first related memory block of the first memory block, wherein a life cycle of the at least one first related memory block overlaps with a life cycle of the first memory block; Determine a target memory block from the at least one first related memory block, the target memory block being a memory block with the longest life cycle among the at least one first related memory block, and there is unoccupied memory space before a starting offset of the target memory block, the starting offset being a starting offset of the target memory block relative to other memory blocks; Determine a second related memory block according to the target memory block, the second related memory block being a memory block having a start offset greater than or equal to an end offset of the target memory block and having a life cycle overlap with the target memory block, the end offset being an end offset of the target memory block relative to other memory blocks; Arrange the target memory block and the second related memory block in ascending order according to their life cycles to obtain a second arrangement order; The scheduling module is further used to arrange the at least two memory blocks according to the second arrangement sequence.

13. A memory optimization device, comprising at least one processor and a memory, wherein the memory stores computer instructions, and the processor calls the computer instructions to execute the method described in any one of claims 1 to 6.

14. A computer-readable storage medium storing computer instructions for executing the method according to any one of claims 1 to 6.

15. A computer program product comprising instructions, which, when executed on a computer, cause the computer to perform the method according to any one of claims 1 to 6.

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