Resonant multilayer ceramic capacitor

Abstract

An improved multilayer ceramic capacitor and an electronic device including the multilayer ceramic capacitor are provided. The multilayer ceramic capacitor includes a first conductive plate electrically connected to a first external terminal and a second conductive plate electrically connected to a second external terminal. The first conductive plate and the second conductive plate form a capacitive coupling. A ceramic portion is located between the first conductive plate and the second conductive plate, wherein the ceramic portion includes a paraelectric ceramic dielectric. The multilayer ceramic capacitor has a rated DC voltage and a rated AC V PP , wherein the rated AC V PP is higher than the rated DC voltage.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to pending U.S. Provisional Application No. 63 / 076,444, filed on September 10, 2020, which is incorporated herein by reference. Technical Field

[0003] The present invention relates to an improved capacitor particularly suitable for high - voltage alternating current (AC) applications. More specifically, the present invention relates to a multilayer ceramic capacitor that can operate reliably at a peak - to - peak AC voltage higher than the DC voltage rating. Background Art

[0004] The development towards high - power circuits is an ongoing trend. Although not limited thereto, the increasing demand for electric vehicles has imposed a significant burden on developers of circuits and components used in the circuits. For the purposes of the present invention, the focus is on the need for high - voltage AC power supplies and the electronic capacitors used therein. Multilayer ceramic capacitors (MLCCs) have been very successfully used in high - voltage DC circuits, and they are now generally the technology of choice for such applications. The use of MLCCs in AC circuits presents significant problems, which limit their widespread use in high - voltage AC applications.

[0005] MLCCs with higher capacitance values absorb more current, and thus, the capacitor heats up more compared to an equivalent MLCC with lower capacitance. The current (I) is related to the voltage (V) and the impedance (Z c ) of the capacitor, as shown in Equation 1.

[0006] I = V / Z c Equation 1

[0007] The impedance (Z c ) of the capacitor is a reasonable approximation of the reactance (X c ) of the capacitor. Thus, the reactance can be roughly estimated based on the measurement frequency (f) and capacitance (C), as shown in Equation 2.

[0008]

[0009] Rearranging Equations 1 and 2 gives Equation 3.

[0010] I = V * 2 * π * f * C Equation 3

[0011] Based on the relationship in Equation 3, for a given voltage and frequency, increasing the capacitance will increase the current. Additionally, the actual power consumed is related to the current (I) and the equivalent series resistance (ESR) of the capacitor, as shown in Equation 4.

[0012] Actual power = 1 2 *ESR Equation 4

[0013] The ESR at a given frequency is the reactance of the capacitor (X c ) multiplied by the dissipation factor (DF f ) of the capacitor at that frequency, as shown in Equation 5.

[0014] ESR f = X c *DF f Equation 5

[0015] Therefore, the actual power consumed is proportional to the capacitance, as shown in Equation 6.

[0016] Actual power = V 2 *2*π*f*C*DF f Equation 6

[0017] Based on the above relationships, it is clear that as the current consumption increases (due to an increase in capacitance), the power consumed also increases.

[0018] In the case of MLCCs using C0G ceramics, the capacitance does not change with temperature, and therefore, the current remains relatively constant. Thus, when the component heats up, the temperature generated by the actual power dissipation must be removed from the MLCC, for example, through external conduction. This is a key design limitation that must be addressed.

[0019] In AC applications, to achieve reliable performance, it is important to minimize the heating due to ripple current. However, the complication is that the fact that the frequency has a significant impact must be taken into account in the design. At lower frequencies (typically 100 kHz or below), the performance of the MLCC is in the voltage-limited region, while at higher frequencies, its performance is in the current-limited region. In the current-limited region, based on the relationship in Equation 4, the current is limited by the subsequent heating of the component. This is shown in the Figure 1 figure.

[0020] Within the voltage-limited region, the peak-to-peak (V pp ) AC voltage should not exceed the DC voltage level to ensure reliable performance without overheating. MLCCs are typically rated by their DC voltage (V dc ), which is equivalent to the rated AC (V pp ). The root mean square (RMS) AC voltage (V rms ) is related to Vdc is related, and this relationship is given by Equation 7.

[0021]

[0022] Therefore, the progress of MLCCs expected for DC circuits and AC circuits has been developing in parallel because the relationship of the rated voltage has been considered to be correlated with the relationship of Equation 7. This has limited the use of MLCCs in high-voltage AC applications to those capacitors with a high rated DC voltage because, according to the prior art, the peak-to-peak voltage V PP should not exceed the rated DC voltage.

[0023] The present invention provides an MLCC having a rated peak-to-peak AC voltage that, based on the established relationship set forth in Equation 7, far exceeds what was expected in the prior art. Accordingly, the present invention provides an MLCC and a device using the MLCC that can withstand an AC voltage much higher than what was previously considered suitable. SUMMARY OF THE INVENTION

[0024] The present invention relates to an improved MLCC that is particularly suitable for high AC voltage applications.

[0025] More specifically, the present invention relates to an improved MLCC having a rated peak-to-peak AC voltage that is higher than the DC rated voltage, which is contrary to the generally accepted theory and practice in the art.

[0026] A particular feature of the improved MLCC is the ability to withstand a high AC voltage (e.g., 950 to 5700 V PP ) without a significant reduction in ESR.

[0027] Another particular feature of the improved MLCC is the ability to withstand high temperatures at high AC V PP without a reduction in ESR or loss of performance.

[0028] These and other embodiments to be achieved are provided in a multilayer ceramic capacitor that includes a first conductive plate electrically connected to a first external terminal; and a second conductive plate electrically connected to a second external terminal. The first conductive plate and the second conductive plate form a capacitive coupling. A ceramic portion is located between the first conductive plate and the second conductive plate, wherein the ceramic portion includes a paraelectric ceramic dielectric. The multilayer ceramic capacitor has a rated DC voltage and a rated AC voltage, wherein the rated AC V PP is higher than the rated DC voltage.

[0029] Another embodiment is provided in an electronic device including a first multilayer ceramic capacitor. The multilayer ceramic capacitor includes a first conductive plate electrically connected to a first external terminal; and a second conductive plate electrically connected to a second external terminal, wherein the first conductive plate and the second conductive plate form a capacitive coupling. A ceramic portion is located between the first conductive plate and the second conductive plate, wherein the ceramic portion includes a paraelectric ceramic dielectric. The multilayer ceramic capacitor has a rated DC voltage and a rated ACV PP , wherein the rated AC V PP is higher than the rated DC voltage.

[0030] Another embodiment is provided in a method of forming a multilayer ceramic capacitor, the method comprising:

[0031] forming a paraelectric dielectric ceramic including an oxide represented by General Formula A:

[0032] (Ca e Sr g ) j (Zr k Ti p ) q O 3

[0033] General Formula A

[0034] wherein:

[0035] e = 0.60 to 1.00; g = 0.00 to 0.40; k = 0.50 to 0.97; p = 0.03 to 0.50; and j / q = 0.99 to 1.01;

[0036] forming a ceramic slip including the dielectric ceramic;

[0037] forming a coating of the ceramic slip on a substrate;

[0038] printing a pattern of conductive ink on the coating to form a printed coating;

[0039] forming a laminate including the printed coating, wherein adjacent printed coatings are offset and alternating printed coatings are aligned;

[0040] forming a laminate of the laminate;

[0041] separating the laminate into green chips;

[0042] sintering the green chips, wherein the conductive ink forms a first conductive plate and a second conductive plate, and the ceramic slip forms a ceramic portion between the first conductive plate and the second conductive plate; and

[0043] sealing the sintered green chips.

[0044] Another embodiment is provided in a method of forming a multilayer ceramic capacitor, the method comprising:

[0045] Forming a paraelectric ceramic dielectric defined by the general formula B:

[0046] U a X b Y c Z d ((Ca 1-x-y Sr x M y ) m (Zr 1-u-v Ti u Hf v )O 3 ) 1-a-b-c-d

[0047] General formula B

[0048] Wherein:

[0049] M is at least one alkaline earth metal selected from Ba and Mg;

[0050] U comprises a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, Cr and Al;

[0051] X comprises at least one sintering aid, the sintering aid comprising a compound containing at least one element selected from Li, B and Si;

[0052] Y comprises a carbonate or oxide of at least one second transition metal selected from W, Ta and Mo;

[0053] Z comprises at least one rare earth element selected from Y, Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu;

[0054] 0 < a < 0.06: 0.0001 < b < 0.15; 0 < c ≤ 0.06; 0 < d < 0.06; 0 ≤ x ≤ 1; 0 ≤ y ≤ 1; 0 ≤ u ≤ 1; 0 ≤ v ≤ 0.2; and 0.98 ≤ m ≤ 1.02;

[0055] Forming a ceramic slurry comprising the paraelectric ceramic dielectric;

[0056] Forming a coating of the ceramic slurry on a substrate;

[0057] Printing a pattern of conductive ink on the coating to form a printed coating;

[0058] Form a laminate including printed coatings, wherein adjacent printed coatings are offset and alternating printed coatings are aligned;

[0059] Form a laminated product of the laminate;

[0060] Separate the laminated product into green chips;

[0061] Sinter the green chips, wherein the conductive ink forms a first conductive plate and a second conductive plate, and the ceramic paste forms a ceramic portion between the first conductive plate and the second conductive plate; and

[0062] Seal the sintered green chips. Description of the Drawings

[0063] Figure 1 Illustrates the variation of the MLCC capability limit according to frequency.

[0064] Figure 2 Illustrates the temperature coefficient of capacitance.

[0065] Figure 3 Shows a cross-sectional schematic view of an MLCC.

[0066] Figure 4 Shows a cross-sectional schematic view of an embodiment of the present invention.

[0067] Figure 5 Shows Figure 4 a part of

[0068] Figure 6 Shows a schematic view of an embodiment of the present invention.

[0069] Figure 7 Schematically shows a ripple current test circuit.

[0070] Figure 8 Illustrates an example of the prior art.

[0071] Figure 9 Illustrates an embodiment of the present invention.

[0072] Figure 10 Illustrates ripple current heating.

[0073] Figure 11 Illustrates a comparison between a control and an embodiment of the present invention.

[0074] Figure 12 Illustrates an example of the prior art.

[0075] Figure 13 Illustrates an embodiment of the present invention.

[0076] Figure 14 Illustrates an example of the prior art.

[0077] Figure 15 Illustrates an embodiment of the present invention.

[0078] Figure 16 Illustrates a comparison between an example of the prior art and an embodiment of the present invention.

[0079] Figure 17 Illustrates the test conditions.

[0080] Figure 18 Illustrates a comparison between an example of the prior art and an embodiment of the present invention.

[0081] Figure 19 Illustrates an example of the prior art.

[0082] Figure 20 Illustrates an embodiment of the present invention.

[0083] Figure 21 Illustrates an embodiment of the present invention.

[0084] Figure 22 Illustrates an example of the prior art.

[0085] Figure 23 Illustrates an embodiment of the present invention.

[0086] Figure 24 Is a flowchart of an embodiment of the present invention. Detailed implementation

[0087] The present invention relates to an improved MLCC, in which the peak-to-peak rated AC (V PP ) exceeds the rated DC voltage by at least 10%, more preferably at least 20%, which is contrary to the expectations in the art and contradicts the generally accepted theoretical model. More specifically, the present invention provides an MLCC having a voltage-enhanced U2J (VEU2J) paraelectric ceramic dielectric.

[0088] A particular feature of the present invention is the ability to provide an MLCC that is particularly suitable for use as a high AC V PP resonant capacitor. These MLCCs are made of paraelectric VEU2J ceramics, which can achieve reliable performance at higher AC V PP compared to current MLCCs with comparable rated DC voltages, as demonstrated by the relatively low surface temperature under the application of high AC V PP for a long time. Their stability is enhanced, in part due to the negative capacitance coefficient above 25°C and the stable ESR with respect to high AC V PP and temperature. These MLCCs utilizing VEU2J dielectrics, at high AC V PPUnder operation, it is very effective to evenly distribute the temperature throughout the multi-capacitor array. If the temperature of a single capacitor increases, the capacitance of that capacitor will decrease, thereby reducing the current according to Equation 3. As the current decreases, the temperature also decreases, thus compensating for any manufacturing differences in the component itself.

[0089] As described above, in the case of capacitors made of C0G ceramics, the capacitance does not change significantly with temperature. Therefore, the current remains relatively constant. Conventionally, for C0G capacitors, in the temperature range of -55°C to +125°C, the capacitance change is + / -30 PPM / °C relative to the value at 25°C. When the capacitor heats up, the temperature generated by actual power heat dissipation must be removed from the MLCC through external conduction or the like. In contrast, as Figure 2 shown, for capacitors including VEU2J ceramics, the capacitance decreases as the temperature increases. Therefore, when the component heats up, the capacitor absorbs less current.

[0090] More specifically, the present application provides a multi-layer ceramic capacitor device formed by a plurality of laminated ceramic layers and a plurality of internal electrode layers, wherein the ceramic layers and the internal electrode layers are alternately laminated. The ceramic layers are made of a disclosed dielectric composition, and the internal electrode layers are made of a conductive paste mainly containing base metals (such as Ni, etc.). After co-firing under a low oxygen partial pressure, the resulting multi-layer ceramic capacitor can have a capacitance temperature coefficient of ±1000 ppm / °C in the temperature range of -55°C to 150°C.

[0091] The capacitance of VEU2J decreases as the temperature increases, resulting in a slower increase in temperature over time, even when the AC voltage and current increase. To evaluate the reliability of the MLCC under AC voltage conditions, the degree of heating by the AC ripple current is defined based on the risk of failure when the surface temperature is higher than the ambient temperature. For the present invention, a temperature increase of ≤25°C above the ambient temperature is considered a low risk, a temperature increase of ≥25°C to ≤50°C above the ambient temperature is considered a medium risk, depending on the specific application, and a temperature increase of ≥50°C above the ambient temperature is considered to have an increased risk of thermal runaway and overvoltage failure.

[0092] The rated DC voltage is the maximum DC voltage at which the capacitor can store and operate reliably under this bias voltage. Although the rated DC voltage and the rated AC V PP are considered to be related by Equation 7, in the capacitors of the present invention, the rated AC V PP and the rated DC voltage are not related. In the present invention, according to Equation 7, the rated AC V PPA base rated DC voltage higher than expected. The rated DC voltage is typically determined by taking a sacrificial capacitor equivalent to the test capacitor and subjecting the sacrificial capacitor to an increasing DC voltage until breakdown is achieved (the voltage at which breakdown occurs is referred to as the breakdown voltage). For the purposes of the present invention, the rated DC voltage is defined as 60% of the average breakdown voltage to allow for manufacturing and testing variations. Thus, for the purposes of the present invention, the peak-to-peak value of the rated AC voltage is higher than 60% of the DC breakdown voltage of an equivalent component.

[0093] The present invention will be described with reference to the accompanying drawings, which form an essential, non-limiting part of the present invention. In the respective drawings, like elements will be numbered correspondingly.

[0094] Reference will be made to Figure 3 illustrate an embodiment of the present invention, in which a multilayer ceramic capacitor is shown in a cross-sectional side view. A first conductive plate 3 serves as an electrode and is electrically connected to a first external terminal 9. A second conductive plate 5 serves as an electrode and is electrically connected to a second external terminal 7. The first conductive plate and the second conductive plate have opposite polarities and form an electrical coupling. The electrodes are separated or spaced apart by a VEU2J dielectric 11. An optional non-preferred resin 12 encapsulates a portion of the capacitor in a manner known in the art.

[0095] Reference will be made to Figure 4 illustrate an embodiment of the present invention. Figure 4 A portion of the capacitor is enlarged to Figure 5 In Figure 4 , a double-printed capacitor 20 is schematically shown in a sectional view. First conductive plates 22 and 22' are printed on both sides in close proximity and terminate at a first external terminal 28 and thus have the same polarity. The double-printed conductive plates are separated by a VEU2J dielectric 26. Second conductive plates 24 and 24' are also printed on both sides in close proximity and terminate at a second external terminal 30 and thus have the same polarity. The VEU2J dielectric 26 is located between adjacent conductive plates of opposite polarities, for example, 22 and 24 or 22' and 24'. The spacing ( Figure 5 D1) between conductive plates of opposite polarities is at least five times the spacing ( Figure 5 D2) between conductive plates of the same polarity. More preferably, the spacing between conductive plates of opposite polarities is at least seven times the spacing distance between conductive plates of the same polarity.

[0096] The preparation of laminated ceramic capacitors is well documented, and the present invention does not make any significant changes to the manufacturing method relative to the standard procedures known in the art.

[0097] Reference will be made to Figure 24 illustrate a method for forming an MLCC, which is shown by a flowchart in this figure. Refer to Figure 24, at 60, preferably by the solid-state synthesis method well-known in the art, a dielectric ceramic is formed from the dielectric described herein. At 62, a ceramic slurry is formed, wherein the ceramic slurry contains the dielectric ceramic. The ceramic slurry is a formable material. The ceramic slurry typically contains an organic carrier, etc., to allow the ceramic slurry to be coated onto a substrate. At 64, the ceramic slurry coating is formed on the substrate. There is no particular limitation on the substrate because it will not become part of the final product. Polyethylene terephthalate (PET) is widely used in the art due to reasons such as cost and availability, and is suitable for demonstrating the present invention. There is no particular limitation on the method of forming the coating except that preferably those methods suitable for forming a coating with a uniform thickness are used. The doctor blade method is widely used and suitable for demonstrating the present invention. At 66, the ceramic slurry is dried. At 68, an internal electrode is formed by printing an electrode pattern of conductive ink onto the dried ceramic slurry. The conductive ink preferably includes base metals, preferably nickel or nickel alloys. At 70, a stack is formed, wherein the stack includes a ceramic precursor layer without printing to form a dielectric ceramic layer capacitively coupled to the outside. Then, the layers including the printed electrode patterns are sequentially laminated, wherein adjacent layers are offset so that the alternating printed electrode patterns are aligned. An additional layer without printing is applied to form a dielectric ceramic opposite capacitively coupled to the outside. At 72, the layered structure is pressed and heated to form a laminate. At 74, the laminate is cut into green chips. At 76, the green chips are sintered and capped in a manner known in the art to form a capacitor.

[0098] The conductor for forming the internal electrode layer is preferably a base metal. Typical base metals are nickel and nickel alloys. The preferred nickel alloy is an alloy of nickel and at least one element selected from Mn, Cr, Co, and Al, and more preferably such nickel alloy contains at least 95 wt% nickel. Nickel and nickel alloys may contain up to about 0.1 wt% of phosphorus and other trace components. Other conductors that can be used as internal electrodes, such as copper, precious metals, or their alloys, and the particularly preferred precious metals are selected from palladium and silver. It should be understood that for internal electrodes containing copper or precious metals, lower temperature firing is preferred.

[0099] The voltage-enhanced U2J (VEU2J) ceramic is based on a calcium zirconate structure and further includes an additive that enhances the ability of a capacitor including the VEU2J ceramic to withstand an AC V of at least 950 V PP , up to 5700 V PP of rated AC V PP of high AC V PP while having a rated DC voltage lower than the AC V PP .

[0100] The VEU2J ceramic comprises a paraelectric ceramic dielectric having a negative capacitance coefficient above 25 °C. More preferably, the VEU2J ceramic comprises at least 95 mol% of a paraelectric ceramic dielectric having a negative capacitance coefficient above 25 °C. The paraelectric ceramic dielectric of the VEU2J dielectric is a strontium calcium zirconium titanate ceramic having the general formula A:

[0101] (Ca e Sr g ) j (Zr k Ti p ) q O 3

[0102] General formula A

[0103] Where:

[0104] e = 0.60 to 1.00;

[0105] g = 0.00 to 0.40;

[0106] k = 0.50 to 0.97;

[0107] p = 0.03 to 0.50; and

[0108] j / q = 0.99 to 1.01.

[0109] In general formula A, the VEU2J main component preferably comprises at least 90 mol% of the dielectric of general formula A, to which a minor constituent is added. In general formula A, Ca or Zr may be replaced by Ba or Mg. In general formula A, Zr or Ti may be replaced by Hf. The minor constituent may include a secondary component, which includes Zn, Cu, Ni, Co, Fe, Mn, Cr, Al, Li, B, Si, W, Ta, Mo, Y, Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Yu. Preferably, the minimum amount of these minor components is 0.5 mol%.

[0110] More specifically, the VEU2J ceramic comprises an oxide represented by the general formula B:

[0111] U a X b Y c Z d ((Ca 1-x-y Sr x M y )m(Zr 1-u-v Ti u Hf v )O3 ) 1-a-b-c-d

[0112] General formula B

[0113] Wherein:

[0114] M is at least one alkaline earth metal selected from Ba and Mg;

[0115] U comprises a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, Cr and Al;

[0116] X comprises at least one sintering aid, which sintering aid comprises a compound containing at least one element selected from Li, B and Si;

[0117] Y comprises a carbonate or oxide of at least one second transition metal selected from W, Ta and Mo;

[0118] Z comprises at least one rare earth element selected from Y, Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu;

[0119] 0 < a < 0.06; 0.0001 < b < 0.15; 0 < c ≤ 0.06; 0 < d < 0.06; 0 ≤ x ≤ 1; 0 ≤ y ≤ 1; 0 ≤ u ≤ 1; 0 ≤ v ≤ 0.2; and 0.98 ≤ m ≤ 1.02.

[0120] Even more specifically, the VEU2J ceramic comprises an oxide represented by general formula B, and the general formula B is selected from formula I, formula II, formula III, formula IV, formula V, formula VI and formula VII,

[0121] In formula I:

[0122] M is at least one alkaline earth metal selected from Ba and Mg;

[0123] U comprises a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, Cr and Al;

[0124] X comprises at least one sintering aid, which sintering aid comprises a compound containing at least one element selected from Li, B and Si;

[0125] Y comprises a carbonate or oxide of at least one second transition metal selected from W, Ta and Mo; 0 < a < 0.06; 0.0001 < b < 0.15; 0 < c ≤ 0.06; d = 0; 0 ≤ x ≤ 1; 0 ≤ y ≤ 1; 0 ≤ u < 0.8; 0 ≤ v ≤ 0.2; and 0.98 ≤ m ≤ 1.02;

[0126] In formula II:

[0127] M is Ba;

[0128] U comprises a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, and Cr;

[0129] X comprises at least one sintering aid, which comprises a compound containing at least one element selected from Li, B, and Si;

[0130] Z comprises at least one rare earth element selected from Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu;

[0131] 0 < a < 0.06; 0.0001 < b < 0.15; c = 0; 0 < d < 0.06; 0 ≤ x ≤ 1; 0 ≤ y ≤ 1; 0.03 < u ≤ 1; 0 ≤ v ≤ 0.2; and 0.98 ≤ m ≤ 1.02;

[0132] In formula III:

[0133] M is Ba;

[0134] U comprises a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, and Cr;

[0135] X comprises at least one sintering aid, which comprises a compound containing at least one element selected from Li, B, and Si;

[0136] Z comprises at least one rare earth element selected from Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu;

[0137] 0 < a < 0.06; 0.0001 < b < 0.15; c = 0; 0 < d < 0.02; 0 ≤ x ≤ 1; 0 ≤ y ≤ 1; 0 ≤ u ≤ 1; 0 ≤ v ≤ 0.2; and 0.98 ≤ m ≤ 1.02;

[0138] In formula IV:

[0139] M is Ba;

[0140] U comprises a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, and Cr;

[0141] X comprises at least one sintering aid, which comprises a compound containing at least one element selected from Li, B, and Si;

[0142] Z comprises at least one rare earth element selected from Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Ho, Er, Tm, Yb, and Lu;

[0143] 0 < a < 0.06; 0.0001 < b < 0.15; c = 0; 0 < d < 0.06; 0 ≤ x ≤ 1; 0 ≤ y ≤ 1; 0 ≤ u ≤ 1; 0 ≤ v ≤ 0.2; and 0.98 ≤ m ≤ 1.02;

[0144] In formula V:

[0145] M is at least one alkaline earth metal selected from Ba and Mg;

[0146] U comprises a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, Cr, and Al;

[0147] X comprises at least one sintering aid, and the sintering aid comprises a compound containing at least one element selected from Li, B, and Si;

[0148] Z comprises at least one rare earth element selected from Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu;

[0149] 0 < a < 0.06; 0.0001 < b < 0.15; c = 0; 0 < d < 0.06; 0 ≤ x ≤ 1; 0 ≤ y ≤ 1; 0.1 < u < 0.55; 0 ≤ v ≤ 0.2; and 0.98 ≤ m ≤ 1.02;

[0150] In formula VI:

[0151] M is at least one alkaline earth metal selected from Ba and Mg;

[0152] U comprises a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, Cr, and Al;

[0153] X comprises at least one sintering aid, and the sintering aid comprises a compound containing at least one element selected from Li, B, and Si;

[0154] Z comprises at least one rare earth element selected from Y, Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu;

[0155] 0 < a < 0.06; 0.0001 < b < 0.15; c = 0; 0.015 < d < 0.06; 0 ≤ x ≤ 1; 0 ≤ y ≤ 1; 0.1 < u < 0.55; 0 ≤ v ≤ 0.2; 0.98 ≤ m ≤ 1.02; and

[0156] In Formula VII:

[0157] M is at least one alkaline earth metal selected from Ba and Mg;

[0158] U comprises a carbonate or an oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, Cr, and Al;

[0159] X comprises at least one sintering aid, and the sintering aid comprises a compound containing at least one element selected from Li, B, and Si;

[0160] Y comprises a carbonate or an oxide of at least one second transition metal selected from W, Ta, and Mo;

[0161] Z comprises at least one rare earth element selected from Y, Sc, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu;

[0162] 0 < a < 0.06; 0.0001 < b < 0.15; 0 < c ≤ 0.06; 0 < d < 0.06; 0 ≤ x ≤ 1; 0 ≤ y ≤ 1; 0.1 < u < 0.8; 0 ≤ v ≤ 0.2; and 0.98 ≤ m ≤ 1.02.

[0163] A particular advantage of the present invention is that when measured at a frequency such as 50 kHz, or when measured at a frequency from 10 kHz to not exceeding 1 MHz, more preferably when measured at a frequency from 20 kHz to not exceeding 200 kHz, at high voltage or high temperature, the ESR does not decrease. A decrease in ESR can lead to an increase in local heating, which will further degrade the capacitor. By minimizing or eliminating the decrease in ESR, the capacitor remains stable after many cycles of high AC V PP or after being at high AC V for a long time. The decrease in ESR caused by the dielectric is most easily observed at lower frequencies (which is the main component of ESR). PP

[0164] A particular advantage of the present invention is the ability to improve the thermal dissipation management of electronic devices. The capacitors of the present invention having different capacitances can be combined in electrical parallel. As shown by the relationship in Equation 6, the capacitor having a higher capacitance will consume the most actual power. Therefore, the capacitor having a higher capacitance can be physically positioned to improve thermal dissipation.

[0165] In addition to the ESR stability, a further advantage of the present invention is shown in Figure 6 wherein the electronic device 40 is shown in a partially cutaway schematic view. In Figure 6 ​In this case, the electronic device includes two capacitors, C1 and C2, connected in electrical parallel. Based on the relationship in Equation 3, if the temperature of C1 increases, the capacitance decreases as the current decreases due to the negative thermal coefficient of capacitance of the VEU2J dielectric, which results in a decrease in the temperature of C1. Thus, C1 self-corrects for the temperature rise. Unfortunately, the decrease in current in C1 causes an increase in current in C2. The heat dissipation component D1 located near C2 dissipates the heat from C2, which allows the combination of C1 and C2 to handle more current without heat accumulation. As will be appreciated, the heat dissipation component can be strategically located near various capacitors, particularly capacitors connected in electrical parallel, to increase the ability of the capacitor combination to handle more current. In this document, the heat dissipation component is not particularly limited to passive devices (e.g., heat sinks) or active devices (e.g., moving the flowing dielectric or devices providing physical cooling), and is suitable for demonstrating the present invention.

[0166] Embodiment

[0167] To evaluate the comparative ripple current heating, the capacitors under test are mounted on a similar test specimen, and the top surface temperature is measured. The test setup is schematically shown in Figure 7 In Figure 7 the test setup 50 includes a sine wave generator 52, a power amplifier 54, a coil autotransformer 56, and an impedance matching unductance coil 58, all in the circuit schematically shown with the device under test (DUT).

[0168] The test instrument design is based on the principle of inductor-capacitor resonance. The device under test (DUT) is selected, and the inductance is matched to ensure that the resonant frequency of the component is suitable for the test conditions. Under excitation, the device temperature is taken from the top of the DUT, which is the highest temperature point. The ambient temperature is also continuously measured as a function of time. The difference between the device temperature and the ambient temperature is reported.

[0169] Measurements of the effective series resistance (ESR) and impedance (Z) are obtained on a Keysight E4990A impedance analyzer with a custom fixture. The custom fixture is used to mitigate the electromagnetic coupling between the voltage and current connections used to measure the DUT. The electromagnetic coupling is mitigated by making the current and voltage traces of the DUT perpendicular to each other as they approach the DUT.

[0170] This decoupling is particularly necessary when measuring Class 1 components made of paraelectric dielectrics to more accurately characterize their very low ESR values. The custom fixture also allows the component to be soldered to the test fixture to reduce contact resistance and simulate the way it is actually used. Traces are routed from the DUT pads on the top side to vias connected to the back of the fixture, and on the back of the fixture, they are terminated to MMCX connectors. Four short cables are used to connect the MMCX connectors on the back of the fixture to BNC connectors on the front of the fixture. The measurement cables should be as short as possible to reduce any potential phase errors and increase the bandwidth of the setup.

[0171] Four separate fixtures are used during the measurement, three for compensation and one for the DUT. Open, short, and load fixtures are used to compensate for the parasitic residuals from the wires and fixtures used to measure the DUT. Open compensation uses the fixture as it is, without soldering the DUT or any other component to the pads. Short compensation uses a copper shorting block that is approximately the same size as a typical DUT soldered to the fixture pads. Load compensation uses a 50 Ω resistor soldered to the fixture pads to create a stable impedance over all measurement frequencies.

[0172] The fixture can be placed in an oven for measuring ESR at high temperatures. The same fixture and setup are used, except for the measurement cables used to connect the fixture and the analyzer. A 1-meter long high-temperature cable is used so that the fixture can be placed in the Sun system chamber. Compensation is done at room temperature (usually 25 °C). Then, the chamber is set to the desired test temperature, and the DUT is soaked for 10 minutes. Once the temperature of the DUT reaches a steady state, the ESR of the DUT is measured, and the temperature is adjusted to the next temperature point. This process is repeated until the temperature rating of the DUT is reached. Compensation can be re-verified at each measurement temperature as needed.

[0173] Figure 8 and Figure 9 respectively show the front and back ripple current ESR measurements of a single printed C0G (6A rms 750V rms ) and a double printed VEU2J (10A rms 1250V rms ).

[0174] Power curve fitting as shown in Equations 8 and 9 is used to predict the expected temperature rise at a distant time, where A and B are summarized in the tables for all embodiments. If the temperature rise increases very little with time, the fitting weakens.

[0175] Temperature = A * Time B Equation 8

[0176]

[0177] A series of MLCCs were fabricated using C0G (as a control) and the VEU2J dielectric described herein. Under different conditions, the ripple current tests were carried out for comparison using the above test fixture. A summary of the MLCCs tested is provided in Table 1.

[0178] Table 1:

[0179]

[0180] A comparison example of the ripple current test is described as follows.

[0181] Embodiment 1

[0182] A series of EIA case size 3640 15 nF MLCCs with a rated DC voltage of 2000 V were fabricated using the C0G and VEU2J dielectrics in Table 1. As dc shown, at various currents and temperatures, the ripple current heating of these MLCCs was measured at 85 kHz. The electrical properties of these MLCCs are shown in Table 2. Figure 10

[0183] Table 2:

[0184]

[0185]

[0186] These electrical characteristics are typical for MLCCs with a rated DC voltage of 2000 V dc . In Table 2, the average breakdown voltage of the VEU2J capacitors is slightly higher than that of the C0G capacitors, but the minimum breakdown voltage is very close. The average 3σ of C0G is 3718 V compared to 3751 V for VEU2J.

[0187] In both cases, C0G and U2J can be rated at 2000 V dc to achieve an AC rating of 707 V rms based on the expected relationship of Equation 7. However, when an AC voltage was applied to each MLCC, contrary to the theoretical expectation, the VEU2J MLCC did not exhibit the expected self-heating at these and higher voltages, see Figure 10 . It is important to note that in the case of C0G, applying 6 A rms 750 V rms would result in the temperature reaching 25 °C above ambient temperature after approximately 24 hours. According to Equation 7, this AC voltage level is slightly higher than 707 V rmsLimit. Although there are fewer electrodes than in C0G, the single - printed version of this VEU2J component does not heat up much at 8.4 A rms and 980 V rms The smaller number of electrodes inhibits the conduction of heat from the center of the MLCC. In the case of this C0G MLCC, if the AC voltage is increased to 8 A rms and 1000 V rms , the MLCC will quickly heat up above the high - risk temperature range, and at 10 A rms and 1250 V rms , it will reach the MLCC breakdown point and the capacitor will break down.

[0188] This indicates that the VEU2J dielectric has unexpected benefits in terms of ripple - current handling. By doubling the print to increase the number of electrodes in the VEU2J MLCC to match the C0G capacitor, the performance will be further improved. The double - printed VEU2J MLCC remains at 25 °C after 24 hours at 10 A rms and 1250 V rms (1.77 times higher than the recommended AC voltage limit based on Equation 7). In addition, although the temperature of the VEU2J MLCC rises rapidly at these high AC voltages, the temperature still remains stable over time. This stability with temperature can only be partially explained by the aforementioned differences in capacitance with temperature. Since the actual power consumed is proportional to the ESR, as shown in Equation 4, the ESR and impedance are measured before and after exposure to ripple current. For the post - exposure components, the C0G samples have been exposed to 6 A rms at 750 V rms , while the VEU2J samples have been exposed to 10 A rms and 1250 V rms .

[0189] Although the VEU2J samples were tested at much higher ripple currents, the post - test ESR only shows a small change, while the post - test ESR of the C0G samples is significantly higher. Exposure to high ripple currents results in an increased ESR, which causes the observed temperature rise.

[0190] Embodiment 2

[0191] A series of 21015 nF MLCCs with a rated DC voltage of 1000 V dc in EIA case size 1 are fabricated using C0G and VEU2J dielectrics. At 100 kHz, the ripple - current heating of these MLCCs is measured using the aforementioned test method, and the results are as shown in Figure 11 .

[0192] Under the same conditions, the VEU2J MLCC remains within the safe range of ripple current heating, while the C0G MLCC quickly heats up to more than 50°C above ambient. This AC voltage is much higher than the 353V expected from Equation 7. rms , but the VEU2J MLCC does not exhibit significant ripple current heating.

[0193] To further understand these differences, impedance and ESR measurements were made over a wide frequency range on the MLCCs before exposure to this high AC voltage, and the results were compared to the MLCCs after exposure. Measurements were also made at elevated temperatures using the test methods described above.

[0194] The ESR results obtained for 15nF C0G and VEU2J MLCC at ambient temperature are shown below: Figure 12 and 13 as shown in .

[0195] Exposure to high AC voltage does not significantly affect the impedance value, while in the case of C0G capacitors, the ESR after exposure can be 10 times or more than an order of magnitude higher than the ESR before exposure at frequencies below 1MHz. In the case of VEU2J capacitors, the ESR remains very close in the MLCC after exposure, increasing by less than a factor of two at any frequency. This is critical for ripple current heating because the actual power dissipated is proportional to the ESR as shown in Equation 4. Pre-exposure (initial) and post-exposure measurements up to 100°C were also performed. Figure 14 and 15 These embodiments are shown separately for measurements over a wide frequency range.

[0196] At higher temperatures, there is little difference in the ESR data before (initial) and after exposure for the VEU2J capacitor. Figure 16 This can be seen more clearly by extracting the ESR data measured at 100kHz and different temperatures as shown in Figure 1.

[0197] At 100kHz, the ESR of the exposed VEU2J capacitors barely changes with increasing temperature, while the ESR of the exposed C0G capacitors increases more than five times at 100°C compared to the pre-tested parts.

[0198] Embodiment 3

[0199] Use C0G and VEU2J capacitors to create a series with 630V DC The EIA case size 120610nF MLCCs are rated for DC voltage. The ripple current heating of these MLCCs was measured at 85kHz using the test method described previously. In this case, the heating of the part is similar to Figure 17 shown.

[0200] Although the ripple current heating appears similar, the rate of increase in temperature over time for the VEU2J capacitor is slower, so the component does not reach 25 °C as quickly as the C0G capacitor.

[0201] Embodiment 4

[0202] A series of EIA case size 1210 33 nF MLCCs with a rated DC voltage of 630 V DC were manufactured using C0G and VEU2J dielectrics. The ripple current heating of these MLCCs was measured at 50 kHz at an ambient temperature of 85 °C, and the results are as Figure 18 shown.

[0203] At this elevated temperature environment of 85 °C, the ripple current heating of the VEU2J is much less than that of the equivalent C0G MLCC. The ESR of these components before (initial) and after the ripple current is as Figure 19 and 20 shown.

[0204] The ESR results before (initial) and after the ripple current measured at 50 kHz at different temperatures are reported in Table 3.

[0205] Table 3:

[0206]

[0207]

[0208] As shown in Table 3, the ESR of the C0G samples increased by more than 23% at all temperatures and more than 50% at 25 °C and 85 °C. The ESR of the VEU2J capacitor increased by less than 2%.

[0209] To understand the difference in the heating rate between the C0G and VEU2J MLCCs over all times to the temperatures of 25 °C and 50 °C using the power curve fitting described above, the test conditions for Examples 1, 2, 3, and 4 are summarized in Table 4, and the results are summarized in Table 5. To achieve a better curve fit in both cases, the surface temperatures recorded in the first 5 hours were not considered significant.

[0210] Table 4:

[0211]

[0212] Table 5:

[0213]

[0214]

[0215] The surface temperature data for the first 5 hours is not applicable to these cases.

[0216] In Example 1, after 24 hours at 10A rms 1250V rms (1.77 times higher than the AC voltage limit based on Equation 7), the VEU2J dual - printed MLCC remained at 25°C. Additionally, although the temperature of the VEU2J MLCC increased rapidly under these high AC voltages, the temperature remained stable over time. Temperature stability under applied AC voltage is crucial for long - term reliability. Compared to C0G, even though the test voltage increased, the predicted times for the VEU2J to reach the critical temperatures of 25°C and 50°C were still much higher.

[0217] Compared to a C0G MLCC with the same nominal capacitance, the VEU2J MLCC of Example 2 experienced much less heat generation, and thus had better reliability under AC voltage at this frequency. In the case of Example 3, even when the surface heating of the C0G and VEU2J MLCCs appeared similar, curve fitting showed that the VEU2J surface temperature did not increase rapidly over time, and thus it took longer to reach the critical temperature.

[0218] Furthermore, in an array of two or more VEU2J capacitors electrically paralleled in the same circuit, the MLCC with a higher capacitance value will have a higher proportion of the current, as shown in Equation 3, but as this heating occurs the capacitance will decrease, and thus the current will be more evenly distributed between the two MLCCs. This helps to more evenly distribute the current between capacitor arrays, even when these capacitors are arranged in series in a matrix.

[0219] Embodiment 5

[0220] A series of EIA case size 1210 33nF MLCCs rated at 630V DC, manufactured using C0G and VEU2J dielectrics, were mounted on a test board. With and without a 472.5V DC bias voltage applied at 25°C, the ripple - current heating of the two types of dielectrics was measured at 100 kHz. The temperature rise as a function of time was measured, as DC shown. Figure 21 shown.

[0221] As the test continued, the C0G MLCC developed a short - circuit failure. The same C0G MLCC was exposed for a shorter time of 1.5 hours under the same conditions and with a DC bias voltage applied at an ambient temperature of 25°C to allow evaluation of the ESR change. After being exposed to this ripple current and bias for 1.5 hours, the ESR of the C0G before (initial) and after the ripple current was compared, as Figure 22As shown. As shown in other embodiments exposed to pure AC voltage, even when a DC bias voltage is applied, the ESR increases significantly. The ripple current test of the VEU2J MLCC with the bias voltage applied continued for 66 hours, but no further increase in temperature was detected. The ESR before (initial) and after the ripple current of these VEU2J MLCCs is as Figure 23 shown. No increase in ESR was detected in the VEU2J MLCC despite long-term exposure.

[0222] These results indicate that even when a DC bias voltage is applied in addition to the AC ripple voltage, the temperature rise of the VEU2J is less than that of the C0G.

[0223] The present invention has been described with reference to preferred embodiments, but is not limited thereto. Other embodiments and improvements can be implemented, which are not specifically described herein, but fall within the scope of the present invention more specifically set forth in the appended claims.

Claims

1. A multilayer ceramic capacitor, comprising: a first conductive plate and a second conductive plate, the first conductive plate being electrically connected to a first external terminal, the second conductive plate being electrically connected to a second external terminal, wherein the first conductive plate and the second conductive plate form a capacitive coupling; and a ceramic portion located between the first conductive plate and the second conductive plate, wherein the ceramic portion comprises a paraelectric ceramic dielectric; The multilayer ceramic capacitor has a rated DC voltage and a rated AC V PP , where the rated AC V PP Higher than the rated DC voltage; wherein the paraelectric ceramic dielectric comprises an oxide defined by General Formula A: (Ca e Sr g ) j (Zr k Ti p ) q O 3 General Formula A wherein: e = 0.60 to 1.00; g = 0.00 to 0.40; k = 0.50 to 0.97; p = 0.03 to 0.50; and j / q = 0.99 to 1.01; or the paraelectric ceramic dielectric is defined by General Formula B: U a X b Y c Z d ((Ca 1-x-y Sr x M y ) m (Zr 1-u-v Ti u Hf v )O 3 ) 1-a-b-c-d General Formula B wherein: M is at least one alkaline earth metal selected from Ba and Mg; U comprises a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, Cr, and Al; X comprises at least one sintering aid, the sintering aid comprising a compound containing at least one element selected from Li, B, and Si; Y comprises a carbonate or oxide of at least one second transition metal selected from W, Ta, and Mo; Z comprises at least one rare earth element selected from Y, Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu; 0<a<0.06； 0.0001<b<0.15； 0<c≤0.06； 0<d<0.06； 0≤x≤1； 0≤y≤1； 0≤u≤1； 0 ≤ v ≤ 0.2; and 0.98≤m≤1.02。 2. The multilayer ceramic capacitor according to claim 1, wherein the rated AC V PP is 950V PP to 5700V PP .

3. The multilayer ceramic capacitor according to claim 1, wherein at least 90 mol% of the ceramic portion is the paraelectric ceramic dielectric defined by General Formula A.

4. The multilayer ceramic capacitor according to claim 1, wherein Ca or Zr is replaced by Ba or Mg.

5. The multilayer ceramic capacitor according to claim 1, wherein Zr or Ti is replaced by Hf.

6. The multilayer ceramic capacitor according to claim 1, wherein the paraelectric ceramic dielectric further comprises a secondary component, the secondary component comprising at least one element selected from Zn, Cu, Ni, Co, Fe, Mn, Cr, Al, Li, B, Si, W, Ta, Mo, Y, Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Yu.

7. The multilayer ceramic capacitor according to claim 6, wherein the paraelectric ceramic dielectric comprises at least 0.5 mol% of the secondary component.

8. The multilayer ceramic capacitor according to claim 1, wherein the paraelectric ceramic dielectric is selected from Formula I, Formula II, Formula III, Formula IV, Formula V, Formula VI, and Formula VII, In Formula I: M is at least one alkaline earth metal selected from Ba and Mg; U comprises a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, Cr, and Al; X comprises at least one sintering aid, the sintering aid comprising a compound containing at least one element selected from Li, B, and Si; Y comprises at least one carbonate or oxide of a second transition metal selected from W, Ta, and Mo; 0<a<0.06； 0.0001<b<0.15； 0<c≤0.06； d＝0； 0≤x≤1； 0≤y≤1； 0≤u<0.8； 0 ≤ v ≤ 0.2; and 0.98≤m≤1.02； In Formula II: M is Ba; U comprises at least one carbonate or oxide of a first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, and Cr; X comprises at least one sintering aid, and the sintering aid comprises a compound containing at least one element selected from Li, B, and Si; Z comprises at least one rare earth element selected from Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu; 0<a<0.06； 0.0001<b<0.15； c＝0； 0<d<0.06； 0≤x≤1； 0≤y≤1； 0.03<u≤1； 0 ≤ v ≤ 0.2; and 0.98≤m≤1.02； In Formula III: M is Ba; U comprises at least one carbonate or oxide of a first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, and Cr; X comprises at least one sintering aid, and the sintering aid comprises a compound containing at least one element selected from Li, B, and Si; Z comprises at least one rare earth element selected from Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu; 0<a<0.06； 0.0001<b<0.15； c＝0； 0<d<0.02； 0≤x≤1； 0≤y≤1； 0≤u≤1； 0 ≤ v ≤ 0.2; and 0.98≤m≤1.02； In Formula IV: M is Ba; U comprises at least one carbonate or oxide of a first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, and Cr; X comprises at least one sintering aid, and the sintering aid comprises a compound containing at least one element selected from Li, B, and Si; Z comprises at least one rare earth element selected from Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Ho, Er, Tm, Yb, and Lu; 0<a<0.06； 0.0001<b<0.15； c＝0； 0<d<0.06； 0≤x≤1； 0≤y≤1； 0≤u≤1； 0 ≤ v ≤ 0.2; and 0.98≤m≤1.02； In Formula V: M is at least one alkaline earth metal selected from Ba and Mg; U comprises at least one carbonate or oxide of a first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, Cr, and Al; X comprises at least one sintering aid, and the sintering aid comprises a compound containing at least one element selected from Li, B, and Si; Z comprises at least one rare earth element selected from Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu; 0<a<0.06； 0.0001<b<0.15； c＝0； 0<d<0.06； 0≤x≤1； 0≤y≤1； 0.1<u<0.55 0 ≤ v ≤ 0.2; and 0.98≤m≤1.02； In Formula VI: M is at least one alkaline earth metal selected from Ba and Mg; U comprises at least one carbonate or oxide of a first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, Cr, and Al; X comprises at least one sintering aid, and the sintering aid comprises a compound containing at least one element selected from Li, B, and Si; Z comprises at least one rare earth element selected from Y, Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu; 0<a<0.06； 0.0001<b<0.15； c＝0； 0.015<d<0.06； 0≤x≤1； 0≤y≤1； 0.1<u<0.55； 0 ≤ v ≤ 0.2; and 0.98 ≤ m ≤ 1.02; and In Formula VII: M is at least one alkaline earth metal selected from Ba and Mg; U comprises a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, Cr, and Al; X comprises at least one sintering aid, the sintering aid comprising a compound containing at least one element selected from Li, B, and Si; Y comprises a carbonate or oxide of at least one second transition metal selected from W, Ta, and Mo; Z comprises at least one rare earth element selected from Y, Sc, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu; 0<a<0.06； 0.0001<b<0.15； 0<c≤0.06； 0<d<0.06； 0≤x≤1； 0≤y≤1； 0.1<u<0.8； 0 ≤ v ≤ 0.2; and 0.98≤m≤1.02。 9. The multilayer ceramic capacitor according to claim 1, wherein: M is at least one alkaline earth metal selected from Ba and Mg; U comprises a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, Cr, and Al; X comprises at least one sintering aid, the sintering aid comprising a compound containing at least one element selected from Li, B, and Si; Y comprises a carbonate or oxide of at least one second transition metal selected from W, Ta, and Mo; 0<a<0.06； 0.0001<b<0.15； 0<c≤0.06； d＝0； 0≤x≤1； 0≤y≤1； 0≤u<0.8； 0 ≤ v ≤ 0.2; and 0.98≤m≤1.02。 10. The multilayer ceramic capacitor according to claim 9, wherein U is Mn.

11. The multilayer ceramic capacitor according to claim 9, wherein X is Si.

12. The multilayer ceramic capacitor according to claim 9, wherein Y is W.

13. The multilayer ceramic capacitor according to claim 1, wherein: M is Ba; U comprises a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, and Cr; X comprises at least one sintering aid, the sintering aid comprising a compound containing at least one element selected from Li, B, and Si; Z comprises at least one rare earth element selected from Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu; 0<a<0.06； 0.0001<b<0.15； c＝0； 0<d<0.06； 0≤x≤1； 0≤y≤1； 0.03<u≤1； 0 ≤ v ≤ 0.2; and 0.98≤m≤1.02。 14. The multilayer ceramic capacitor according to claim 13, wherein M is Ba.

15. The multilayer ceramic capacitor according to claim 13, wherein U is Mn.

16. The multilayer ceramic capacitor according to claim 13, wherein X is Si.

17. The multilayer ceramic capacitor according to claim 13, wherein Z is selected from Ce, Eu, Gd, Tb, and Dy.

18. The multilayer ceramic capacitor according to claim 1, wherein: M is Ba; U comprises a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, and Cr; X comprises at least one sintering aid, the sintering aid comprising a compound containing at least one element selected from Li, B, and Si; Z comprises at least one rare earth element selected from Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu; 0<a<0.06； 0.0001<b<0.15； c＝0； 0<d<0.02； 0≤x≤1； 0≤y≤1； 0≤u≤1； 0 ≤ v ≤ 0.2; and 0.98≤m≤1.02。 19. The multilayer ceramic capacitor according to claim 18, wherein M is Ba.

20. The multilayer ceramic capacitor according to claim 18, wherein U is Mn.

21. The multilayer ceramic capacitor according to claim 18, wherein X is Si.

22. The multilayer ceramic capacitor according to claim 18, wherein Z is selected from Pr, Eu, Gd, Tb, and Dy.

23. The multilayer ceramic capacitor according to claim 1, wherein: M is Ba; U comprises a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, and Cr; X comprises at least one sintering aid, the sintering aid comprising a compound containing at least one element selected from Li, B, and Si; Z comprises at least one rare earth element selected from Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Ho, Er, Tm, Yb, and Lu; 0<a<0.06； 0.0001<b<0.15； c＝0； 0<d<0.06； 0≤x≤1； 0≤y≤1； 0≤u≤1； 0 ≤ v ≤ 0.2; and 0.98≤m≤1.02。 24. The multilayer ceramic capacitor according to claim 23, wherein M is Ba.

25. The multilayer ceramic capacitor according to claim 23, wherein U is Mn.

26. The multilayer ceramic capacitor according to claim 23, wherein X is Si.

27. The multilayer ceramic capacitor according to claim 23, wherein Z is selected from Nd, Eu, Gd, and Tb.

28. The multilayer ceramic capacitor according to claim 1, wherein: M is at least one alkaline earth metal selected from Ba and Mg; U comprises a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, Cr, and Al; X comprises at least one sintering aid, the sintering aid comprising a compound containing at least one element selected from Li, B, and Si; Z comprises at least one rare earth element selected from Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu; 0<a<0.06； 0.0001<b<0.15； c＝0； 0<d<0.06； 0≤x≤1； 0≤y≤1； 0.1<u<0.55； 0 ≤ v ≤ 0.2; and 0.98≤m≤1.02。 29. The multilayer ceramic capacitor according to claim 28, wherein M is Ba.

30. The multilayer ceramic capacitor according to claim 28, wherein U is Mn.

31. The multilayer ceramic capacitor according to claim 28, wherein X is Si.

32. The multilayer ceramic capacitor according to claim 28, wherein Z is selected from Eu, Gd, Tb, and Dy.

33. The multilayer ceramic capacitor according to claim 1, wherein: M is at least one alkaline earth metal selected from Ba and Mg; U comprises a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, Cr, and Al; X comprises at least one sintering aid, the sintering aid comprising a compound containing at least one element selected from Li, B, and Si; Z comprises at least one rare earth element selected from Y, Sc, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu; 0<a<0.06； 0.0001<b<0.15； c＝0； 0.015<d<0.06； 0≤x≤1； 0≤y≤1； 0.1<u<0.55； 0 ≤ v ≤ 0.2; and 0.98≤m≤1.02。 34. The multilayer ceramic capacitor according to claim 33, wherein M is Ba.

35. The multilayer ceramic capacitor according to claim 33, wherein U is Mn.

36. The multilayer ceramic capacitor according to claim 33, wherein X is Si.

37. The multilayer ceramic capacitor according to claim 33, wherein Z is selected from Y, Eu, Gd, Tb, and Dy.

38. The multilayer ceramic capacitor according to claim 1, wherein: M is at least one alkaline earth metal selected from Ba and Mg; U includes a carbonate or oxide of at least one first transition metal selected from Zn, Cu, Ni, Co, Fe, Mn, Cr, and Al; X includes at least one sintering aid, and the sintering aid includes a compound containing at least one element selected from Li, B, and Si; Y includes a carbonate or oxide of at least one second transition metal selected from W, Ta, and Mo; Z includes at least one rare earth element selected from Y, Sc, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu; 0<a<0.06； 0.0001<b<0.15； 0<c≤0.06； 0<d<0.06； 0≤x≤1； 0≤y≤1； 0.1<u<0.8； 0 ≤ v ≤ 0.2; and 0.98≤m≤1.02。 39. The multilayer ceramic capacitor according to claim 38, wherein M is Ba.

40. The multilayer ceramic capacitor according to claim 38, wherein U is Mn.

41. The multilayer ceramic capacitor according to claim 38, wherein X is Si.

42. The multilayer ceramic capacitor according to claim 38, wherein Y is W.

43. The multilayer ceramic capacitor according to claim 38, wherein Z is Y.

44. The multilayer ceramic capacitor according to claim 1, wherein the multilayer ceramic capacitor has a capacitance temperature characteristic within ±1000 ppm / °C in a temperature range from -55°C to 150°C.

45. The multilayer ceramic capacitor according to claim 1, wherein the paraelectric ceramic dielectric has a negative capacitance coefficient above 25°C.

46. The multilayer ceramic capacitor according to claim 1, wherein the capacitor has a first ESR measured at 50 kHz before being exposed to an AC V higher than the rated DC voltage, and a second ESR measured at 50 kHz after being exposed to the AC V, where the second ESR is not more than 20% higher than the first ESR. PP Before, it has a first ESR measured at 50 kHz, and after being exposed to the AC V PP it has a second ESR measured at 50 kHz, where the second ESR is not more than 20% higher than the first ESR.

47. The multilayer ceramic capacitor according to claim 46, wherein the exposure to the AC V PP is carried out at a temperature higher than 25 °C.

48. The multilayer ceramic capacitor according to claim 47, wherein the exposure to the AC V PP is performed at a temperature higher than 50°C.

49. The multilayer ceramic capacitor according to claim 48, wherein the exposure to the AC V PP is carried out at a temperature of up to 100 °C.

50. The multilayer ceramic capacitor according to claim 46, wherein the second ESR is not more than 10% higher than the first ESR.

51. The multilayer ceramic capacitor according to claim 1, wherein the capacitor has a first ESR measured at 10 Hz to not more than 1 MHz before being exposed to an alternating current V higher than the rated direct current voltage, and a second ESR measured at 10 Hz to not more than 1 MHz after being exposed to the alternating current V, wherein the second ESR is not more than 20% higher than the first ESR. PP Before, it has a first ESR measured at 10 Hz to not more than 1 MHz, and after being exposed to the alternating current V PP Afterwards, it has a second ESR measured at 10 Hz to not more than 1 MHz, wherein the second ESR is not more than 20% higher than the first ESR.

52. The multilayer ceramic capacitor according to claim 51, wherein the second ESR is measured at a frequency of at least 20 kHz to not more than 200 kHz.

53. The multilayer ceramic capacitor according to claim 1, wherein the capacitor has a surface temperature, and after being exposed to an alternating current V higher than the rated DC voltage PP for 24 hours, the surface temperature does not exceed 25 °C. PP ​ 54. The multilayer ceramic capacitor according to claim 53, wherein after being exposed to the AC V PP for at least 35,000 hours, the surface temperature does not exceed 25 °C.

55. The multilayer ceramic capacitor according to claim 54, wherein after being exposed to the AC V PP for at least 500,000 hours, the surface temperature does not exceed 25 °C.

56. The multilayer ceramic capacitor according to claim 55, wherein the surface temperature does not exceed 25 °C after being exposed to the AC V PP for at least 2,000,000 hours.

57. The multilayer ceramic capacitor according to claim 1, wherein the first conductive plate is a first double-printed conductive plate.

58. The multilayer ceramic capacitor according to claim 57, further comprising a paraelectric ceramic dielectric between the first double-printed conductive plates.

59. The multilayer ceramic capacitor according to claim 58, wherein the first conductive plate and the second conductive plate are spaced apart by a first distance, and the first double-printed conductive plates are spaced apart by a second distance, and wherein the first distance is greater than the second distance.

60. The multilayer ceramic capacitor according to claim 59, wherein the first distance is at least twice the second distance.

61. The multilayer ceramic capacitor according to claim 1, wherein at least one of the first conductive plate or the second conductive plate includes a base metal.

62. The multilayer ceramic capacitor according to claim 61, wherein the base metal is nickel.

63. The multilayer ceramic capacitor according to claim 62, wherein the rated DC voltage is 60% of the average breakdown voltage.

64. An electronic device, comprising: a first multilayer ceramic capacitor, the multilayer ceramic capacitor being defined by the multilayer ceramic capacitor according to any one of claims 1-63.

65. The electronic device according to claim 64, further comprising a second multilayer ceramic capacitor, wherein the first multilayer ceramic capacitor and the second multilayer ceramic capacitor are electrically connected in parallel.

66. The electronic device according to claim 65, wherein the capacitance of the first multilayer ceramic capacitor is higher than that of the second multilayer ceramic capacitor.

67. The electronic device according to claim 66, wherein the electronic device further comprises a heat dissipation element.

68. The electronic device according to claim 67, wherein the heat dissipation element is closer to the first multilayer ceramic capacitor than the second multilayer ceramic capacitor.

69. The electronic device according to claim 64, further comprising a second multilayer ceramic capacitor, wherein the first multilayer ceramic capacitor and the second multilayer ceramic capacitor are electrically connected in series.

70. The electronic device according to claim 69, wherein the capacitance of the first multilayer ceramic capacitor is higher than that of the second multilayer ceramic capacitor.

71. The electronic device according to claim 70, wherein the electronic device further comprises a heat dissipation element.

72. The electronic device according to claim 71, wherein the heat dissipation element is closer to the first multilayer ceramic capacitor than the second multilayer ceramic capacitor.

73. The electronic device according to claim 64, wherein the rated alternating current V PP is 950V PP to 5700V PP .

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