Chip and manufacturing method thereof, and electronic device

Abstract

The present application provides a chip and a manufacturing method thereof, and an electronic device, which relates to the field of chip technology and can reduce the influence of external stress on the semiconductor device inside the chip. The chip substrate, device layer, cap, and side wall; wherein the device layer is provided with a semiconductor device, and the device layer is provided with an isolation groove on the surface of the side away from the substrate and around the semiconductor device; the cap is arranged opposite to the device layer, and the cap is located on the side of the device layer away from the substrate; the side wall is arranged between the cap and the device layer, and the side wall is arranged around the semiconductor device, and the isolation groove is located on the inner side of the side wall.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a chip and a manufacturing method thereof, and an electronic device. Background Art

[0002] In chip packaging technology, the surface of semiconductor devices is covered with epoxy mold compound (EMC) to protect the chip from or reduce the impact of the external environment (including physical and chemical impacts) and provide a good working condition for it so that the chip has stable and normal functions.

[0003] Since the plastic encapsulation material is in direct contact with the surface of the semiconductor device, and the plastic encapsulation material will shrink during the curing process, compressive stress will be generated on the surface of the semiconductor device. In addition, during the operation of the semiconductor device, due to the different thermal expansion coefficients of the device itself and the plastic encapsulation material and changes in ambient temperature and other factors, the plastic encapsulation material will also generate thermal stress on the surface of the semiconductor device. These external stresses may affect the performance of the semiconductor device and even cause the device to fail. Summary of the invention

[0004] The embodiments of the present application provide a chip and a method for manufacturing the same, and an electronic device, which can reduce the impact of external stress on semiconductor devices inside the chip.

[0005] The present application provides a chip, comprising: a substrate, a device layer, a cap, and a side wall; wherein a semiconductor device is arranged in the device layer, and an isolation groove is arranged on a surface of the device layer on a side away from the substrate and around the semiconductor device; the cap is arranged opposite to the device layer, and the cap is located on a side of the device layer away from the substrate; the side wall is arranged between the cap and the device layer, and the side wall is arranged around the semiconductor device, and the isolation groove is located on the inner side of the side wall.

[0006] The chip provided in the embodiment of the present application, on the one hand, by arranging the semiconductor device in the cavity area formed by the cap and the sidewall, the surface of the semiconductor device is isolated from the external environment, thereby preventing external stress from directly acting on the surface of the semiconductor device; on the other hand, in the cavity area formed by the cap and the sidewall, by arranging an isolation groove in the area between the semiconductor device and the sidewall on the device layer, the stress transmission path from the outside of the cavity to the semiconductor device is cut off, thereby preventing external stress from being transmitted to the semiconductor device; thereby reducing the influence of external stress on the semiconductor device.

[0007] In some possible implementations, the semiconductor device includes one or more of a piezoelectric device, a piezoresistive device, and a capacitive sensor; based on the sensitivity of the piezoelectric device, the piezoresistive device, and the capacitive sensor to stress, an isolation groove is provided around the semiconductor device to reduce the influence of external stress on the semiconductor device, thereby effectively ensuring the performance and normal operation of the semiconductor device.

[0008] In some possible implementations, the isolation trench includes an annular groove arranged around the semiconductor device, so as to cut off the transmission path of the external stress to the semiconductor device to the greatest extent, thereby effectively reducing the impact of the external stress on the semiconductor device.

[0009] In some possible implementations, the isolation trench includes a plurality of grooves dispersedly arranged around the semiconductor device; effective support is provided in the connection area between two adjacent isolation trenches to ensure that the isolation trench cuts off the transmission path of external stress to the semiconductor device while ensuring that the chip has reliable connection strength (i.e., reliability) at the isolation trench position.

[0010] In some possible implementations, the width of the isolation trench is greater than or equal to 0.1 μm, so as to prevent the isolation trench from being deformed due to stress along the trench width, resulting in squeeze contact between the two trench walls, thereby failing to effectively block the conduction of external stress to the semiconductor device.

[0011] In some possible implementations, the bottom of the isolation trench is located in the substrate to ensure that the isolation trench effectively blocks external stress.

[0012] In some possible implementations, the semiconductor device includes an electrode; the chip is provided with a via on a side of the electrode facing away from the cap; the substrate is provided with a connecting portion on a side facing away from the cap, and the connecting portion is connected to the electrode through the via. In this case, since the chip is usually covered with a plastic encapsulation material on the upper surface of the cap when it is packaged, and the plastic encapsulation material is not covered on the lower surface of the substrate, compared with setting the connecting portion on the upper surface of the cap, by setting the connecting portion on the lower surface of the substrate, it is possible to effectively avoid the stress (such as thermal stress, curing shrinkage stress, etc.) generated by the plastic encapsulation material from being transmitted to the surface of the semiconductor device through the connecting portion.

[0013] The present application also provides a chip manufacturing method including:

[0014] A device layer including semiconductor devices is formed on the substrate.

[0015] An isolation trench is formed on the surface of the device layer around the semiconductor device.

[0016] The cap is covered on the device layer through the side wall; wherein the side wall is arranged around the semiconductor device, and the isolation groove is located on the inner side of the side wall.

[0017] The chip manufacturing method provided in the embodiment of the present application is prepared by making an isolation groove around the semiconductor device in the device layer, and forming side walls and a cap on the device layer on the outside of the semiconductor device and the isolation groove, and placing the semiconductor device and the isolation groove in the cavity formed by the side walls and the cap; in this case, the cavity formed by the side walls and the cap can isolate the surface of the semiconductor device from the external environment, thereby avoiding external stress directly acting on the surface of the semiconductor device; the isolation groove can cut off the stress transmission path from the outside of the cavity to the semiconductor device, thereby preventing external stress from being transmitted to the semiconductor device; thereby reducing the influence of external stress on the semiconductor device.

[0018] In some possible implementations, the chip manufacturing method further includes: forming a via hole on the surface of the substrate on the side away from the cap, corresponding to the position of the electrode in the semiconductor device, and forming a connection portion connected to the electrode through the via hole. Since the chip is usually covered with a plastic encapsulation material on the upper surface of the cap and not on the lower surface of the substrate when it is packaged, compared with setting the connection portion on the upper surface of the cap, by forming a connection portion connected to the electrode of the semiconductor device on the surface of the substrate on the side away from the cap, it is avoided that the stress generated by the plastic encapsulation material (such as thermal stress, curing shrinkage stress, etc.) is transmitted to the surface of the semiconductor device through the connection portion.

[0019] In some possible implementations, covering the cap onto the device layer via the sidewall includes: forming a sidewall surrounding the semiconductor device on the outer side of the isolation trench on a surface of the device layer facing away from the substrate; and covering the cap onto the sidewall.

[0020] An embodiment of the present application also provides an electronic device, including a printed circuit board and a chip provided in any of the possible implementation methods described above; the chip is connected to the printed circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of a cross-sectional structure of a chip provided in an embodiment of the present application;

[0022] Figure 2 A top view of a chip provided in an embodiment of the present application;

[0023] Figure 3 A top view of a chip provided in an embodiment of the present application;

[0024] Figure 4 A top view of a chip provided in an embodiment of the present application;

[0025] Figure 5 A top view of a chip provided in an embodiment of the present application;

[0026] Figure 6 A top view of a chip provided in an embodiment of the present application;

[0027] Figure 7 A schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0028] Figure 8a A schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0029] Figure 8b A schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0030] Fig. 9 A top view or bottom view of a chip provided in an embodiment of the present application;

[0031] Fig.10 A flow chart of a chip manufacturing method provided in an embodiment of the present application;

[0032] Fig.11 A schematic diagram of a chip manufacturing process provided in an embodiment of the present application;

[0033] Fig.12 A schematic diagram of a chip manufacturing process provided in an embodiment of the present application;

[0034] Fig.13 A schematic diagram of a chip manufacturing process provided in an embodiment of the present application;

[0035] Fig.14 A schematic diagram of a chip manufacturing process provided in an embodiment of the present application;

[0036] Fig.15 A schematic diagram of a chip manufacturing process provided in an embodiment of the present application;

[0037] Fig.16 A schematic diagram of the structure of a chip manufacturing process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of this application clearer, the technical solution in this application will be clearly described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0039] The terms "first", "second", etc. in the specification embodiments, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. "Connected", "connected" and similar words are used to express the intercommunication or interaction between different components, which may include direct connection or indirect connection through other components. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for description and clarification relative to, and they can change accordingly according to the changes in the orientation of the components in the drawings.

[0040] Some embodiments of the present application provide an electronic device, which includes a chip and other electronic devices connected to the chip, such as a printed circuit board (PCB), etc. A semiconductor device is disposed inside the chip.

[0041] The present application does not impose any restrictions on the specific configuration of the semiconductor device in the above-mentioned chip, as long as it meets the working requirements of the electronic device; illustratively, the semiconductor device may include: processor logic circuit, storage circuit, capacitive sensor, piezoelectric device, piezoresistive device, etc.

[0042] The embodiments of the present application do not impose any special restrictions on the specific form of the above-mentioned electronic device; for example, the electronic device can be an electronic product such as a mobile phone, a tablet computer, a notebook, a car computer, a smart watch, a smart bracelet, etc.

[0043] The electronic device provided by the embodiment of the present application, by setting the device layer surface of the semiconductor device inside the chip, setting an isolation trench around the semiconductor device, and cutting off the transmission path between the external stress and the semiconductor device through the isolation trench, thereby reducing the influence of the external stress on the semiconductor device; especially for stress-sensitive semiconductor devices, by setting the isolation trench around the semiconductor device, the external stress on the semiconductor device is reduced, and the normal operation of the electronic device is effectively guaranteed. Schematically, when the chip is encapsulated with a plastic encapsulation material, the plastic encapsulation material generates compressive stress during the curing process; and the thermal expansion coefficients of the semiconductor device inside the chip and the plastic encapsulation material outside are different, and thermal stress will also be generated when the ambient temperature changes; the chip of the present application can block these stresses from being transmitted from the outside to the internal semiconductor device surface by setting the isolation trench, thereby achieving the purpose of protecting the semiconductor device, and then ensuring the normal operation of the electronic device.

[0044] The specific configuration structure of the chip used in the electronic device according to the embodiment of the present application is described below.

[0045] Some embodiments of the present application provide a chip, such as Figure 1 (Sectional view) and Figure 2 As shown in FIG. 1 (a top view of a part of the device), the chip includes a substrate 10 and a device layer 1 arranged on the substrate 10 ; wherein a semiconductor device 20 is arranged in the device layer 1 .

[0046] Illustratively, the substrate 10 may be a glass sheet (ie, a glass substrate), a silicon sheet (ie, a Si sheet, a Si wafer), or other sheets formed of materials having similar functions and compatible with wafer-level packaging processes.

[0047] Schematically, the device layer 1 generally includes a plurality of patterned film layers such as a metal layer, a semiconductor layer, and a dielectric layer, and the semiconductor device 20 is formed by the plurality of patterned film layers.

[0048] As shown, the semiconductor device 20 can be a semiconductor device that is more sensitive to stress; for example, the semiconductor device can be a piezoelectric device such as a surface acoustic wave device (SAW) and a bulk acoustic wave device (BAW), or a piezoresistive device such as a piezoresistive accelerometer, or a capacitive sensor device such as a capacitive accelerometer.

[0049] Illustratively, the semiconductor device 20 may include electrodes (such as E1 and E2, but not limited thereto) to connect to external devices (such as chips, PCBs, etc.) through the electrodes, thereby achieving interconnection and communication between the chip and the external devices.

[0050] In addition, if Figure 1 and Figure 2 As shown, in the chip, an isolation groove C is provided around the semiconductor device 20 on the upper surface of the device layer 1 (i.e., the surface facing away from the substrate 10). The isolation groove C cuts off the stress transmission path from the outside of the chip to the semiconductor device 20, thereby isolating the external stress and reducing the influence of the external stress on the semiconductor device 20.

[0051] The present application does not impose too many restrictions on the specific arrangement of the isolation trench C, as long as the isolation trench C is arranged along the four sides of the semiconductor device 20 .

[0052] As shown, in some possible implementations, in order to cut off the transmission path of the external stress to the semiconductor device 20 to the greatest extent, the influence of the external stress on the semiconductor device is effectively reduced; Figure 2 As shown, the isolation groove C can be an annular groove arranged around the semiconductor device 20. Schematically, the opening of the annular groove can be a circular ring, a rectangular ring, etc., which is not limited in the present application and can be set as needed in practice; for example, the shape of the isolation groove C can be adaptively set according to the outer contour shape of the semiconductor device 20.

[0053] As shown, in some possible implementations, in order to ensure that the chip has reliable connection strength (ie, reliability) at the isolation groove C while cutting off the transmission path of the external stress to the semiconductor device 20 through the isolation groove C; Figure 3 , Figure 4 As shown, the isolation groove C can be a plurality of grooves arranged at intervals around the semiconductor device 20, and the reliability of the chip is ensured by the connection area between two adjacent isolation grooves C. The present application does not limit the specific shape of the plurality of grooves arranged in a dispersed manner; for example, the groove can be a strip groove arranged along the outer contour of the semiconductor device 20 (such as Figure 3 ), or a circular groove (such as Figure 4 , that is, a round hole), etc., which can be set as needed in practice.

[0054] As shown, in some possible implementations, the isolation trench C may include a groove disposed in a portion of a side region of the semiconductor device 20; for example, Figure 5 , Figure 6 As shown, the isolation trench C may include grooves disposed on two opposite sides of the semiconductor device 20 ; for another example, the isolation trench C may only include a groove disposed on a certain side (such as the left side or the right side) of the semiconductor device 20 .

[0055] In addition, in order to prevent the isolation groove C from being deformed due to stress along the groove width direction, resulting in the two groove walls being squeezed and contacted, thereby failing to effectively prevent the external stress from being transmitted to the semiconductor device 20, in some possible implementations, reference is made to Figure 2 As shown, the width w of the isolation groove C can be set to be greater than or equal to 0.1 μm; for example, the width w of the isolation groove C can be set to 10 μm, 20 μm, 50 μm, etc.; to ensure that the transmission path of the external stress to the semiconductor device 20 can be effectively cut off through the isolation groove C. It should be noted here that the width of the isolation groove C refers to the distance between the edge of the isolation groove C close to the semiconductor device 20 and the side away from the semiconductor device 20.

[0056] It can be understood here that the larger the width of the isolation groove C, the better the isolation effect against stress. However, considering the small size requirement of the chip, in order to avoid increasing the chip size, in some possible implementation methods, the width w of the isolation groove C can be set to be less than or equal to 100μm.

[0057] It can also be understood that the greater the depth of the isolation groove C, the better the stress isolation effect. The present application does not limit the depth of the isolation groove C. Under the condition of ensuring that the chip has a reliable connection strength (i.e., reliability) at the position of the isolation groove C, the depth of the isolation groove C can be increased as much as possible according to the type and specification of the chip. In some possible implementation methods, for example, Figure 1 As shown, the depth of the isolation trench C may extend into the substrate 10 , that is, the bottom of the isolation trench C is located in the substrate 10 .

[0058] On this basis, if Figure 1 As shown, the chip further includes: a cap 3 arranged opposite to the device layer 1, and the device layer 1 and the cap 3 are supported and connected by a side wall 2; wherein, reference Figure 2 As shown, the sidewall 2 is arranged around the semiconductor device 20, and the isolation groove C is located on the inner side of the sidewall 2 (that is, the isolation groove C is located in the area between the semiconductor device 20 and the sidewall 2). In this case, a cavity is formed between the cap 3 and the sidewall 2, and the semiconductor device 20 is located in the cavity area; that is, the upper surface of the semiconductor device 20 is isolated from the outside world by the cap 3 and the sidewall 2, thereby avoiding direct contact between the plastic encapsulation material and the upper surface of the semiconductor device during subsequent packaging, and reducing the impact of external stress on the semiconductor device.

[0059] For the side wall 2 and the cap 3:

[0060] In some possible implementations, refer to Figure 1As shown, the side wall 2 and the cap 3 can be two independent components; schematically, the side wall 2 and the cap 3 can be made of different materials and manufactured through different processes when manufacturing the chip; for example, the side wall 2 can be made of polymer, and the cap 3 can be made of glass wafers, silicon wafers or other thin films formed of materials with similar functions and compatible with wafer-level packaging processes.

[0061] In some possible implementations, refer to Figure 7 As shown, the sidewall 2 and the cap 3 may also be a connected integral structure; for example, when manufacturing a chip, the sidewall 2 and the cap 3 may be manufactured by processing the same thin sheet (such as a silicon wafer).

[0062] Regarding the relevant manufacturing conditions of the sidewall 2 and the cap 3 , reference may be made to the subsequent chip manufacturing method embodiments, which will not be described in detail here.

[0063] In summary, the chip provided in the embodiment of the present application, on the one hand, by arranging the semiconductor device 20 to be located in the cavity area formed by the cap 3 and the side wall 2, the surface of the semiconductor device 20 is isolated from the external environment, thereby preventing external stress from directly acting on the surface of the semiconductor device 20; on the other hand, in the cavity area formed by the cap 3 and the side wall 2, an isolation groove C is arranged in the area between the semiconductor device 20 and the side wall 3 on the device layer 1, thereby cutting off the stress transmission path from the outside of the chip to the semiconductor device, thereby preventing external stress from being transmitted to the semiconductor device; thereby reducing the influence of external stress on the semiconductor device.

[0064] In addition, in order to ensure that the semiconductor device 20 in the chip can be electrically connected to external devices (such as chips, PCBs, etc.) to achieve interconnection communication; the chip can be capped on the upper surface of the cover 3 (that is, the surface facing away from the substrate 10, such as Figure 8a ), or, on the lower surface of the substrate 10 (i.e., the surface away from the cap 3, such as Figure 8b ), setting a connection part P (pad); connecting the connection part P to the electrodes (E1, E2) of the semiconductor device 20 located inside the chip, transmitting electrical signals to the electrodes (E1, E2) of the semiconductor device 20 through the connection part P, and realizing the interconnection communication of the chips. In some possible implementation methods, such as Figure 8a and Fig. 9As shown in (top view of the chip), a support column Z can be set between the electrodes (E1, E2) of the semiconductor device 20 and the cap 3, and the support column Z and the cap 3 are provided with vias at the positions corresponding to the electrodes (E1, E2), and the connecting portion P located on the upper surface of the cap 3 is connected to the upper surface of the electrode (E1, E2) through the via; it can be understood here that the connecting portion P includes a portion located on the upper surface of the cap 3 and a portion extending into the via; of course, the portion of the connecting portion P located on the upper surface of the cap 3 and the portion extending into the via can be manufactured by the same manufacturing process, or can be manufactured twice separately, and the present application does not impose any restrictions on this.

[0065] As shown, in some possible implementations, the support column Z and the side wall 2 located between the cap 3 and the device layer 1 can be manufactured and processed by the same film layer, that is, the support column Z and the side wall 2 are set in the same layer and material to simplify the process and reduce the manufacturing cost.

[0066] In some possible implementations, such as Figure 8b and Fig. 9 As shown in (bottom view of the chip), a via can be provided below the electrode (E1, E2) of the semiconductor device 20 (i.e., on the side away from the cap 3), and a connecting portion P located on the lower surface of the substrate 10 is connected to the lower surface of the electrode (E1, E2) through the via; it can be understood here that the connecting portion P includes a portion located on the lower surface of the substrate 10 and a portion extending into the via; of course, the portion of the connecting portion P located on the lower surface of the substrate and the portion extending into the via can be manufactured by the same manufacturing process, or can be manufactured twice separately, and the present application does not impose any restrictions on this.

[0067] It can be understood here that when the chip is packaged, the upper surface of the cap 3 is usually covered with plastic packaging material, while the lower surface of the substrate 10 is not covered with plastic packaging material. In this case, compared with setting the connecting part P on the upper surface of the cap 3, by setting the connecting part P on the lower surface of the substrate 10, it is possible to effectively avoid the stress generated by the plastic packaging material (such as thermal stress, curing shrinkage stress, etc.) from being transmitted to the surface of the semiconductor device 20 through the connecting part P.

[0068] In addition, in order to verify that the stress on the surface of the semiconductor device 20 can be effectively reduced by setting the isolation groove C and the cap 3, the present application has carried out actual simulation of the stress changes on the surface of the semiconductor device 20 with three different settings at the same ambient temperature (105°C); wherein the three different forms of semiconductor devices 20 are: a semiconductor device 20 without the isolation groove C and the cap 3, a semiconductor device 20 without the isolation groove C but with the cap 3, and a semiconductor device 20 with the isolation groove C and the cap 3; the simulation results are as follows:

[0069] (1) For the semiconductor device 20 without the isolation groove C and the cap 3, the relative displacement at the midpoint of the surface is 1.13 nm, and the surface stress is 60.3 MPa.

[0070] (2) For the semiconductor device 20 that is not provided with the isolation groove C but is provided with the cap 3, the relative displacement at the midpoint of the surface is 0.97 nm and the surface stress is 39.99 MPa.

[0071] (3) For the semiconductor device 20 provided with the isolation groove C (45 μm) and the cap 3, the relative displacement at the midpoint of the surface is 0.71 nm, and the surface stress is 15.87 MPa.

[0072] By comparing (1), (2), and (3), it can be seen that the relative displacement of the surface of the semiconductor device 20 provided with the isolation groove C (groove depth of 45 μm) and the cap 3 in (3) is the smallest, and the surface stress is also the smallest, that is, the stress on the surface of the semiconductor device 20 is effectively reduced by the provision of the isolation groove C and the cap 3. In addition, by comparing (1) and (2), it can be seen that the provision of the cap 3 can reduce the stress on the surface of the semiconductor device 20; by comparing (2) and (3), it can be seen that the provision of the isolation groove C can reduce the stress on the surface of the semiconductor device 20.

[0073] Some embodiments of the present application provide a method for manufacturing a chip, such as Fig.10 The manufacturing method shown includes:

[0074] Step 01: Reference Fig.11 As shown, a device layer 1 including a semiconductor device 20 is formed on a substrate 10 .

[0075] Illustratively, the above step 01 may include manufacturing a device layer 1 of multiple patterned film layers on a substrate 10 (such as a Si substrate); wherein semiconductor devices 20 are formed in the multiple patterned film layers; and the semiconductor device 20 includes electrodes (such as E1 and E2).

[0076] Step 02: Reference Fig.12 As shown, an isolation trench C is formed on the surface of the device layer 1 and around the semiconductor device 20 .

[0077] Indicatively, the above step 02 may include: referring to Fig.12 As shown, a reactive ion etching (RIE) process is used to form an isolation trench C around the semiconductor device 20; wherein the width of the isolation trench C may be 10 μm, and the depth may extend into the substrate 10, for example, the trench depth may be 50 μm.

[0078] For other related settings of the isolation groove C, please refer to the corresponding parts in the aforementioned chip embodiment, which will not be repeated here.

[0079] Step 03: Reference Fig.13 Medium (d) or Fig.14 As shown in (d), the cap 3 is covered on the device layer 1 through the side wall 2; wherein the side wall 2 is arranged around the semiconductor device 20, and the isolation groove C is located on the inner side of the side wall 2; that is, the isolation groove C is located between the semiconductor device 20 and the side wall 2.

[0080] For illustration, two specific manufacturing methods are provided below for covering the cap 3 on the device layer 1 through the sidewall 2 in the above step 03, but the present application is not limited thereto.

[0081] Production method 1, the above step 03 may include:

[0082] Step 3a, reference Fig.13 As shown in (b), a sidewall 2 is formed on the surface of the device layer 1 outside the isolation trench C and surrounding the semiconductor device 20 .

[0083] Illustratively, step 3a may include: referring to Fig.13 As shown in (a), a polymer (such as DF3570 type negative photoresist) can be used to form an organic film layer A on the surface of the device layer 1; then a photolithography process (including but not limited to exposure, development, curing and other processes) is used to pattern the organic film layer A to form a side wall 2 (refer to Fig.13 (as shown in (b)).

[0084] Step 3b. Reference Fig.13 As shown in (c), the cap 3 is covered on the side wall 2.

[0085] Schematically, step 3b may include: covering the silicon wafer (ie, 3) with the surface of the sidewall 2, and bonding the silicon wafer (3) to the sidewall 2. Then, referring to Fig.13 As shown in (d), the lower surface of the Si substrate (10) and the upper surface of the silicon wafer (3) are polished and thinned using a chemical mechanical polishing (CMP) process.

[0086] Production method 2, the above step 03 may include:

[0087] Step 3c, Reference Fig.14 As shown in (a) and (b), a substrate S is provided, and a groove R is formed on the surface of the substrate S to form an integrated structure of the side wall 2 and the cap 3; wherein the bottom of the groove R serves as the cap, and the side wall of the groove R serves as the side wall 2.

[0088] Illustratively, step 3c may include: providing a Si substrate (S), and forming a groove R on the surface of the Si substrate (S) by an etching process to form a sidewall 2 and a cap 3 of an integrated structure.

[0089] Step 3d, Reference Fig.14 As shown in (c), the integrated structure of the sidewall 2 and the cap 3 (ie, the Si substrate after etching) is covered with the device layer 1 via the sidewall 2.

[0090] Indicative, reference Fig.14 As shown in (c) and (d), the etched Si substrate (i.e., the integrated structure of the side wall 2 and the cap 3) is bonded to the device layer 1 through the side wall 2, and then a chemical mechanical polishing process can be used to polish and thin the lower surface of the substrate 10 and the upper surface of the cap 3.

[0091] In addition, after the cap 3 is covered with the device layer 1, in order to ensure that the electrodes (E1, E2) in the semiconductor device 20 can be normally connected to the external device for interconnection communication, after the aforementioned step 03, the chip manufacturing method may further include: forming a connection portion P connected to the electrodes (E1, E2) on the lower surface of the substrate 10 or the upper surface of the cap 3, referring to Figure 8a and Figure 8b ; The following is a schematic description of the production of the connecting portion P.

[0092] For example, in some possible implementations, after the aforementioned step 03, the chip manufacturing method may further include: referring to Fig.15 As shown in (a) and (b), a via V is formed on the surface of the substrate 10 on the side away from the cap 3 at the position corresponding to the electrode (E1, E2) in the semiconductor device 20 to expose the electrode (E1, E2); then, a connecting portion P connected to the electrode (E1, E2) through the via V is formed on the surface of the substrate 10 on the side away from the cap 3; that is, the connecting portion P extends from the surface of the substrate 10 to the via V area and contacts the electrode.

[0093] Schematically, an etching process can be used to form a via V on the surface of the substrate 10 facing away from the cap, corresponding to the position of the electrode (E1, E2) in the semiconductor device 20, and then a coating, etching and other processes can be used to form a connecting portion P connected to the electrode through the via V.

[0094] For example, in some possible implementations, reference Fig.16 As shown, in the aforementioned step 3a, while forming the sidewall 2, a support column Z with a via V can be formed on the upper surface of the electrode (E1, E2); and after forming the cap 3 in step 03, refer to Figure 8aAs shown, a new via hole that penetrates the via hole in the support column Z (that is, a via hole is formed above the electrode) can be formed on the cap 3 to expose the electrode (E1, E2); then, a connecting portion P is formed on the surface of the cap 3, and the connecting portion P is connected to the electrode (E1, E2) through the via hole located above the electrode (E1, E2); that is, the formed connecting portion P extends from the surface of the cap 3 to the via hole area and contacts the electrode.

[0095] The chip manufacturing method provided in the embodiment of the present application is used for preparation, by making an isolation groove C around the semiconductor device 20 in the device layer 1, and forming a side wall 2 and a cap 3 on the upper side of the device layer 1 and on the outer side of the semiconductor device 20 and the isolation groove C, the semiconductor device 20 and the isolation groove C are placed in the cavity formed by the side wall 2 and the cap 3; in this case, the cavity formed by the side wall and the cap can isolate the surface of the semiconductor device from the external environment, thereby avoiding external stress directly acting on the surface of the semiconductor device; the isolation groove can cut off the stress transmission path from the outside of the cavity to the semiconductor device, thereby preventing external stress from being transmitted to the semiconductor device; thereby reducing the influence of external stress on the semiconductor device.

[0096] Regarding other relevant contents in the above-mentioned chip manufacturing method embodiment, such as the formation and size of the isolation groove C, etc., the corresponding parts in the above-mentioned chip structure embodiment can be referred to, and no further details will be given here; regarding the relevant structures in the above-mentioned chip structure embodiment, they can be manufactured correspondingly with reference to the above-mentioned chip manufacturing method embodiment, or they can be manufactured by making appropriate adjustments in combination with relevant technologies, and this application does not impose any restrictions on this.

[0097] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip, characterized in that: include: A substrate, and a device layer disposed on the substrate; the device layer includes a semiconductor device, and an isolation groove is disposed on a surface of the device layer on a side away from the substrate and around the semiconductor device; A cap; the cap is located on a side of the device layer facing away from the substrate; A sidewall is disposed between the cap and the device layer; the sidewall is disposed around the semiconductor device, and the isolation groove is located on the inner side of the sidewall; The bottom of the isolation trench is located in the substrate, and the semiconductor device is a surface acoustic wave device.

2. The chip according to claim 1, characterized in that: The isolation trench includes an annular groove arranged around the semiconductor device.

3. The chip according to claim 1, characterized in that: The isolation trench includes a plurality of grooves dispersedly arranged around the semiconductor device.

4. The chip according to claim 1, characterized in that: The width of the isolation groove is greater than or equal to 0.1 μm.

5. The chip according to any one of claims 1 to 4, characterized in that: The semiconductor device comprises an electrode; The chip is provided with a via on a side of the electrode away from the cap; The substrate is provided with a connecting portion on a side away from the cap, and the connecting portion is connected to the electrode through the via hole.

6. A method for manufacturing a chip, characterized in that: include: forming a device layer including a semiconductor device on a substrate; wherein the semiconductor device is a surface acoustic wave device; An isolation trench is formed on the surface of the device layer and around the semiconductor device, wherein the bottom of the isolation trench extends into the substrate; The cap is covered on the device layer through the sidewall; wherein the sidewall is arranged around the semiconductor device, and the isolation groove is located on the inner side of the sidewall.

7. The method for manufacturing a chip according to claim 6, characterized in that: The chip manufacturing method further includes: A via hole is formed on a surface of the substrate facing away from the cap, corresponding to the position of the electrode in the semiconductor device, and a connection portion connected to the electrode through the via hole is formed.

8. The method for manufacturing a chip according to claim 6 or 7, characterized in that: The step of covering the cap onto the device layer through the sidewalls comprises: A sidewall is formed on the surface of the device layer facing away from the substrate and surrounding the semiconductor device, and located outside the isolation trench; The cap is closed onto the side wall.

9. An electronic device, characterized in that: It comprises a printed circuit board and a chip as claimed in any one of claims 1 to 5; the chip is connected to the printed circuit board.

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