Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a plurality of array distributed sub-pixels, a pixel driving circuit of a plurality of sub-pixels forms M pixel rows and N pixel columns; the display substrate further comprises a first initialization signal line and a second initialization signal line extending along a first direction; the pixel driving circuit comprises a plurality of transistors and a light emitting device, the plurality of transistors comprising a driving transistor; the light emitting device comprises a first electrode; wherein the first initialization signal line is respectively electrically connected with the mth row of sub-pixels, and is configured to transmit a first initialization signal to the control electrode of the mth row of pixel driving transistors; the second initialization signal line is respectively electrically connected with the m-1th row of sub-pixels, and is configured to transmit a second initialization signal to the first electrode of the light emitting device of the m-1th row of sub-pixels, m is a positive integer greater than or equal to 1 and less than or equal to M; the first initialization signal is different from the second initialization signal.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices, possessing advantages such as self-illumination, wide viewing angles, high contrast, low power consumption, extremely high response speed, thinness, and flexibility. With the continuous development of display technology, flexible display devices using OLEDs or QLEDs as light-emitting devices and employing thin-film transistors (TFTs) for signal control have become the mainstream products in the current display field. The ever-increasing demand for image quality also presents new challenges to the development of current OLED and QLED technologies. Summary of the Invention

[0003] In one aspect, embodiments of this disclosure provide a display substrate, comprising:

[0004] Substrate;

[0005] Multiple arrayed sub-pixels, at least one of the sub-pixels including a pixel driving circuit and a light-emitting device, the multiple sub-pixels forming an M-row * N-column array, where M and N are positive integers greater than or equal to 1; the pixel driving circuit includes multiple transistors, the multiple transistors including driving transistors; the light-emitting device includes a first electrode;

[0006] The substrate further includes: a first initialization signal line and a second initialization signal line; the first initialization signal line and the second initialization signal line extend along a first direction, the first direction being the extension direction of the sub-pixel row;

[0007] Wherein, the first initialization signal line is electrically connected to the m-th row of sub-pixels and is configured to transmit the first initialization signal to the control electrode of the driving transistor of the m-th row of sub-pixels; the second initialization signal line is electrically connected to the (m-1)-th row of sub-pixels and is configured to transmit the second initialization signal to the first electrode of the light-emitting device of the (m-1)-th row of sub-pixels.

[0008] In the second direction, the projection of the first initialization signal line on the substrate is located on the side of the projection of the second initialization signal line on the substrate away from the projection of the (m-1)th row of sub-pixels on the substrate. The second direction is the extension direction of the sub-pixel column, and m is a positive integer greater than or equal to 1 and less than or equal to M.

[0009] The first initialization signal is different from the second initialization signal.

[0010] Optionally, the first initialization signal line and the second initialization signal line are located between the driving transistors of two adjacent rows of sub-pixels, and are located on the same side of the driving transistors in either row in the second direction.

[0011] Optionally, in the second direction, the width of the first initialization signal line is different from the width of the second initialization signal line.

[0012] Optionally, in the second direction, the width of the second initialization signal line is greater than the width of the first initialization signal line.

[0013] Optionally, in the second direction, the width of the second initialization signal line is 1.3 to 2.4 times the width of the first initialization signal line.

[0014] Optionally, the display substrate further includes: a reset signal line extending along the first direction for transmitting a reset signal to the pixel driving circuit;

[0015] The plurality of transistors further includes: a first reset transistor and a second reset transistor;

[0016] The first reset transistor is configured to transmit a first initialization signal on the first initialization signal line to the control electrode of the driving transistor of the m-th row sub-pixel under the control of the reset signal; the second reset transistor is configured to transmit a second initialization signal on the second initialization signal line to the first electrode of the light-emitting device of the (m-1)-th row sub-pixel under the control of the reset signal.

[0017] Optionally, in the second direction, the reset signal line, the second initialization signal line, and the first initialization signal line are arranged sequentially along a direction away from the m-th row sub-pixel driving transistor.

[0018] Optionally, in a direction perpendicular to the display substrate, the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially disposed on the substrate.

[0019] The semiconductor layer includes the active layer of the plurality of transistors, the active layer including the channel region and source / drain region of the transistor; the first conductive layer includes the reset signal line and the control electrode of the transistor; the second conductive layer includes the first initialization signal line and the second initialization signal line; the third conductive layer includes the first power supply line; and the fourth conductive layer includes the second power supply line and the data signal line.

[0020] Optionally, the display substrate further includes a third initialization signal line extending along the second direction, wherein the third initialization signal line is disposed on a different layer from the first initialization signal line, and the third initialization signal line is electrically connected to the first initialization signal line or the second initialization signal line.

[0021] Optionally, the third conductive layer may further include the third initialization signal line.

[0022] Optionally, the third initialization signal line is electrically connected to the first initialization signal line and is distributed in a mesh pattern.

[0023] Optionally, at least one column of sub-pixels is provided between adjacent third initialization signal lines.

[0024] Optionally, at least two of the first power lines are provided between adjacent third initialization signal lines.

[0025] Optionally, the plurality of sub-pixels includes a red sub-pixel that emits red light, a blue sub-pixel that emits blue light, and a green sub-pixel that emits green light; the plurality of pixel columns include a red-blue pixel column and a green pixel column; the red-blue pixel column includes red and blue sub-pixels alternately arranged in the second direction; the green pixel column includes green sub-pixels arranged sequentially along the second direction; and the third initialization signal line is located in the red-blue pixel column.

[0026] Optionally, the shape of the third initialization signal line electrically connected to the red and blue pixel column in the nth column is the same as the shape of the third initialization signal line electrically connected to the red and blue pixel column in the (n+1)th column, where n is a positive integer greater than or equal to 1 and less than or equal to N.

[0027] Optionally, the third initialization signal line includes a first extension, a second extension, and a third extension connected sequentially along the second direction. The first extension extends along the second direction and is electrically connected to the first initialization signal line via a via. The extension direction of the third extension is different from that of the first extension, and the second extension is used to connect the first extension and the third extension, with the extension direction of the second extension deviating from the second direction.

[0028] Optionally, the projection of the first extension on the substrate overlaps with the projections of the reset signal line, the first initialization signal line, and the second initialization signal line on the substrate.

[0029] Optionally, the first extension is connected to the first electrode of the first transistor via a via.

[0030] Optional,

[0031] The second extension forms an angle greater than 90° and less than 180° with the first extension;

[0032] The third extension forms an angle greater than 90° and less than 180° with the second extension;

[0033] Optionally, the plurality of transistors further includes: a second transistor, wherein the first terminal of the second transistor is electrically connected to the second terminal of the driving transistor, and the second terminal of the second transistor is electrically connected to the control terminal of the driving transistor;

[0034] The second conductive layer further includes a shielding portion electrically connected to the first power line, wherein the projection of the shielding portion on the substrate covers at least a portion of the source / drain region of the second transistor and is located between the projections of the data signal line on the substrate and the projections of the adjacent data signal lines on the substrate.

[0035] Optionally, the third conductive layer further includes a fourth connecting portion and a fifth connecting portion, and the fourth conductive layer further includes a seventh connecting portion, which is electrically connected to the fourth and fifth connecting portions. The fourth connecting portion and the fifth connecting portion have different shapes.

[0036] In another aspect, embodiments of this disclosure also provide a display device including a display substrate as described in any of the preceding embodiments.

[0037] The display substrate and display device described in this disclosure reset the gate of the driving transistor in the m-th row of sub-pixels using a first initialization signal line, and reset the first electrode of the light-emitting element in the (m-1)-th row of sub-pixels using a second initialization signal line. The first and second initialization signals are different, allowing for better reset of the gate of the driving transistor and the first electrode of the light-emitting element. This ensures that the OLED display substrate has lower brightness and improved display uniformity in black conditions. Furthermore, this disclosure also provides a display substrate and display device with third initialization signal lines distributed in a specific pixel column. The third initialization signal lines are electrically connected to the first or second initialization signal lines in a mesh pattern, which significantly reduces the impedance of the initialization signal lines and improves image quality. Attached Figure Description

[0038] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0039] Figure 1a This is a schematic diagram of the planar structure of a display substrate according to an embodiment of the present disclosure;

[0040] Figure 1b This is a schematic diagram of the planar structure of another display substrate in an embodiment of this disclosure;

[0041] Figure 2 This is a schematic diagram of a cross-sectional structure of a display substrate;

[0042] Figure 3 This is a schematic diagram of the pixel driving circuit in an exemplary embodiment of a display panel disclosed herein;

[0043] Figure 4 for Figure 3 A possible timing diagram of a pixel driving circuit driving method;

[0044] Figure 5 This is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0045] Figure 6a for Figure 5 A schematic diagram of the semiconductor layer structure of the display substrate;

[0046] Figure 6b for Figure 5 An enlarged view of the semiconductor layer structure within a sub-pixel region;

[0047] Figure 7 for Figure 5 A schematic diagram of the structure of the first conductive layer of the display substrate;

[0048] Figure 8 for Figure 5 A schematic diagram of the structure of the second conductive layer of the display substrate;

[0049] Figure 9 for Figure 5 A schematic diagram of the structure of the third conductive layer of the display substrate;

[0050] Figure 10 for Figure 5 A schematic diagram of the structure of the fourth conductive layer of the display substrate;

[0051] Figure 11 This is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0052] Figure 12a for Figure 11 A schematic diagram of the structure of the third conductive layer of the display substrate;

[0053] Figure 12b for Figure 11 An enlarged view of the structure of the third conductive layer within a sub-pixel region;

[0054] Figure 13 for Figure 11 A schematic diagram showing the connection between the first initialization signal line and the third initialization signal line in the display substrate;

[0055] Figure 14 for Figure 5 , Figure 11 A schematic diagram of the stacked structure of the semiconductor layer and the first conductive layer of the display substrate;

[0056] Figure 15 for Figure 11 Schematic diagram of the stacked structure of the middle structure and the fifth conductive layer;

[0057] Figure 16 for Figure 15 A schematic diagram of the fifth conductive layer structure of the display substrate;

[0058] Figure 17 for Figure 15 A schematic diagram of the cross-sectional structure of line A-A';

[0059] Figure 18 for Figure 15 A schematic diagram of the cross-sectional structure of B-B';

[0060] Figure 19a , Figure 19b , Figure 19c for Figure 11 A schematic diagram of the wiring structure in the central and surrounding areas.

[0061] Explanation of reference numerals in the attached figures:

[0062] 11—First active layer; 12—Second active layer; 13—Third active layer;

[0063] 14—Fourth active layer; 15—Fifth active layer; 16—Sixth active layer;

[0064] 17—Seventh active layer;

[0065] 21—Reset signal line; 22—First scan signal line; 221—First protrusion;

[0066] 23—Light emission control signal line; 24—First electrode plate; 31—First initialization signal line;

[0067] 32—Second initialization signal line; 33—Shielding part; 34—First conductive part;

[0068] 341—First through-hole; 41—Third initialization signal line; 42—First power supply line;

[0069] 43—First connecting part; 44—Second connecting part; 45—Third connecting part

[0070] 46—Fourth connecting part; 47—Fifth connecting part; 411—First extension part;

[0071] 412—Second extension; 413—Third extension; 414—Fourth extension;

[0072] 415—Fifth extension; 416—Sixth extension; 421—Seventh extension;

[0073] 51—Data signal line; 52—Second power supply line; 53—Flat section;

[0074] 531—First color flat area; 532—Second color flat area; 533—Third color flat area;

[0075] 54—Sixth connecting part; 55—Seventh connecting part; 56—Eighth connecting part;

[0076] 61—First electrode; 61a—Main body; 61b—Auxiliary part;

[0077] 71—First insulating layer; 72—Second insulating layer; 73—Third insulating layer;

[0078] 73—Third insulating layer; 74—Fourth insulating layer; 75—Fifth insulating layer;

[0079] 711—First via; 8—Pixel definition layer; 81—First opening;

[0080] 91—Light-emitting layer; 91—Second electrode; 001—Substrate;

[0081] 102—Driver circuit layer; 103—Light-emitting structure layer; 104—Encapsulation layer;

[0082] 401—First encapsulation layer; 402—Second encapsulation layer; 403—Third encapsulation layer. Detailed Implementation

[0083] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will now be clearly and completely described with reference to the accompanying drawings. The embodiments described below are some, but not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments described in this disclosure without creative effort are within the scope of protection of this disclosure.

[0084] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains. The ordinal numbers such as “first,” “second,” and “third” used in this specification are provided to avoid confusion of constituent elements and not to limit their quantity.

[0085] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0086] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0087] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0088] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0089] In this specification, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions. The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures; the figures described in this disclosure are merely schematic diagrams.

[0090] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0091] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0092] In this specification, shapes such as triangles, rectangles, trapezoids, pentagons, or hexagons refer to shapes that approximate triangles, rectangles, trapezoids, pentagons, or hexagons within the range of process and measurement errors. In actual process, these may include deformations such as chamfers, curved edges, rounded corners, and concave or convex shapes that occur within the tolerance range.

[0093] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0094] Figure 1a This is a schematic diagram of a planar structure of a display substrate according to an embodiment of the present disclosure. Figure 1aAs shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first-color sub-pixel P1 emitting a first-color light, a second-color sub-pixel P2 emitting a second-color light, and two third-color sub-pixels P3 emitting a third-color light. Each of the four sub-pixels may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in each sub-pixel is connected to a scan signal line, a data signal line, and a light-emitting control signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting control signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is connected to the pixel driving circuit of its respective sub-pixel, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel.

[0095] In an exemplary embodiment, the first color sub-pixel P1 can be a red sub-pixel (R) emitting red light, and the pixel driving circuit of sub-pixel P1 is electrically connected to the first electrode of the light-emitting device emitting red light. The second color sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the pixel driving circuit of sub-pixel P2 is electrically connected to the first electrode of the light-emitting device emitting blue light. The third sub-pixel P3 can be a green sub-pixel (G) emitting green light, and the pixel driving circuit of sub-pixel P3 is electrically connected to the first electrode of the light-emitting device emitting green light. In an exemplary embodiment, the shape of the first electrode of the sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal. The first electrodes of the four sub-pixels can be arranged in a square to form a GGRB pixel arrangement, such as... Figure 1a As shown; alternatively, a diamond arrangement can be used to form an RGBG pixel layout, such as... Figure 1b As shown. In an exemplary embodiment, the four sub-pixels can be arranged in a horizontal or vertical manner. In an exemplary embodiment, a pixel unit can include three sub-pixels, and the first electrodes of the three sub-pixels can be arranged in a horizontal, vertical, or triangular manner. This disclosure does not limit the specific arrangement.

[0096] In an exemplary embodiment, the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and a storage capacitor constituting a pixel driving circuit. The pixel driving circuit may be a 2T1C, 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure, where T represents a thin-film transistor and C represents a storage capacitor. Figure 2 The structure of a pixel driving circuit is illustrated using only one driving transistor 210 and one storage capacitor 211 as an example.

[0097] like Figure 2As shown, the display substrate has a substrate 001, which can be either a flexible or rigid substrate. The light-emitting structure layer 103 of each sub-pixel can include multiple film layers, including a first electrode 301, a pixel definition layer 8, a light-emitting layer 303, and a second electrode 304. The first electrode 301 is connected to the drain electrode of the driving transistor 210 through a via. The organic light-emitting layer 303 is connected to the first electrode 301, and the second electrode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of a corresponding color under the drive of the first electrode 301 and the second electrode 304. The encapsulation layer 104 can include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403. The first and third encapsulation layers 401 and 403 can be made of inorganic materials, while the second encapsulation layer 402 can be made of organic materials. The second encapsulation layer 402 is disposed between the first and third encapsulation layers 401 and 403 to prevent external moisture from entering the light-emitting structure layer 103.

[0098] In an exemplary embodiment, the organic light-emitting layer 303 may include a stacked Hole Injection Layer (HIL), Hole Transport Layer (HTL), Electron Block Layer (EBL), Emitting Layer (EML), Hole Block Layer (HBL), Electron Transport Layer (ETL), and Electron Injection Layer (EIL). In this exemplary embodiment, the Hole Injection Layer of all sub-pixels may be a common layer connected together, the Electron Injection Layer of all sub-pixels may be a common layer connected together, the Hole Transport Layer of all sub-pixels may be a common layer connected together, the Hole Block Layer of all sub-pixels may be a common layer connected together, and the Emitting Layer and Electron Block Layer of all sub-pixels may have a small overlap or may be isolated.

[0099] In an exemplary embodiment Figure 3 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. (Example) Figure 3As shown, the pixel driving circuit may include seven transistors: a first reset transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a second reset transistor T7, and a storage capacitor C. The node connected to the gate of the driving transistor is the first node N1, the node connecting the first terminal of the driving transistor T3 to the fourth transistor T4 is the second node N2, and the connection between the second transistor T2 and the driving transistor T3 is the third node N3.

[0100] In this configuration, the first terminal of the first reset transistor T1 is connected to the first initialization signal terminal INIT1, the control terminal of the first transistor is connected to the first reset signal terminal Re1, and the second terminal of the first reset transistor T1 is connected to the first node N1. When the on-level scanning signal is applied to the first reset signal terminal Re1, the first reset transistor T1 transmits the first initialization signal to the control terminal of the driving transistor T3 to initialize the voltage of the control terminal of the driving transistor T3.

[0101] The control electrode of the second transistor T2 is connected to the first scan signal terminal S1, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3. When the on-level scan signal is applied to the first scan signal line terminal S1, the second transistor T2 connects the control electrode of the driving transistor T3 to the second electrode.

[0102] The control electrode of driving transistor T3 is connected to the first node N1, which means the control electrode of driving transistor T3 is connected to the second plate of storage capacitor C. The first electrode of driving transistor T3 is connected to the second node N2, and the second electrode of driving transistor T3 is connected to the third node N3. Driving transistor T3 determines the driving current value flowing between the first power supply signal terminal VDD and the second power supply signal terminal VSS based on the potential difference between its control electrode and its first electrode, thereby driving the light-emitting device to emit light.

[0103] The first terminal of the fourth transistor T4 is connected to the data signal terminal DATA, the second terminal of the fourth transistor T4 is connected to the second terminal of the driving transistor T3, and the control terminal of the fourth transistor T4 is connected to the first scan signal terminal S1. When the on-level scan signal is applied to the first scan signal terminal S1, the fourth transistor T4 is configured to input the data voltage provided by the data signal terminal DATA into the pixel driving circuit.

[0104] The control electrode of the fifth transistor T5 is connected to the light-emitting signal control terminal EM, the first electrode of the fifth transistor T5 is connected to the first power supply signal terminal VDD, and the second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, i.e., the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor is connected to the light-emitting signal control terminal EM, the first electrode of the sixth transistor is connected to the second electrode of the driving transistor T3, the second electrode of the sixth transistor is connected to the first electrode of the light-emitting device, and the first electrode of the sixth transistor T6 is connected to the third node N3. When a conduction-level light-emitting signal is applied to the light-emitting signal terminal EM, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply signal terminal VDD and the second power supply signal terminal VSS, causing the light-emitting device to emit light.

[0105] The control terminal of the second reset transistor T7 is connected to the second reset signal terminal Re2, the first terminal of the second reset transistor T7 is connected to the second initialization signal terminal INIT2, and the second terminal of the second reset transistor T7 is connected to the first electrode of the light-emitting device. When a conduction level scan signal is applied to the second reset signal terminal Re2, the second reset transistor T7 transmits the second initialization signal to the first electrode of the light-emitting device, so as to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0106] The storage capacitor C has a first plate and a second plate. The first plate is connected to the first power supply signal terminal VDD, and the second plate is connected to the first node N1. That is, the second plate of the storage capacitor C is connected to the control electrode of the driving transistor T3.

[0107] In an exemplary embodiment, the light-emitting device may be an OLED, including a first electrode (anode), an organic light-emitting layer and a second electrode (cathode) stacked together, or it may be a QLED, including a first electrode (anode), a quantum dot light-emitting layer and a second electrode (cathode) stacked together.

[0108] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power signal terminal VSS, where the signal of the second power signal terminal VSS is a low-level signal, and the signal of the first power signal terminal VDD is a continuously high-level signal. For the m-th display row, the second reset signal terminal Re2 is Re(m), and the first reset signal terminal Re1 is Re(m-1). The first reset signal terminal Re1 of this display row and the second reset signal terminal Re2 in the pixel driving circuit of the previous display row can be the same signal, which can reduce the signal lines of the display panel and achieve a narrow bezel of the display panel.

[0109] In an exemplary embodiment, the seven transistors in the pixel circuit can be either P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 can include both P-type and N-type transistors.

[0110] In an exemplary embodiment, the transistors in the pixel circuit can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OPTs offer advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate forms a Low Temperature Polysilicon+Oxide (LTPO) display substrate, which leverages the advantages of both technologies to achieve low-frequency driving, reduce power consumption, and improve display quality.

[0111] Figure 4 for Figure 3 A timing diagram of one driving method for pixel driving circuits. The following is a summary of the process. Figure 4 The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. Here, Re1 represents the timing of the first reset signal terminal, Re2 represents the timing of the second reset signal terminal, S1 represents the timing of the first scan signal terminal, EM represents the timing of the light emission control signal terminal, DATA represents the timing of the data signal terminal, and all seven transistors are P-type transistors.

[0112] In an exemplary embodiment, taking OLED as an example, the operation of the pixel driving circuit may include:

[0113] The first stage, t1, is called the reset stage. The first reset signal terminal Re1 outputs a low-level signal, turning on the first reset transistor T1. The first initialization signal terminal INIT1 inputs an initial signal to the first node N1 and initializes the storage capacitor C, clearing the original data voltage in the storage capacitor. The second reset signal terminal Re2, the first scan signal terminal S1, and the light emission signal control terminal EM output high-level signals, turning off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the second reset transistor T7. During this stage, the OLED does not emit light.

[0114] The second stage, t2, is called the data writing stage or threshold compensation stage. The first scan signal terminal S1 outputs a low-level signal, turning on the fourth transistor T4, the second transistor T2, and the second reset transistor T7. Simultaneously, the data signal terminal DATA outputs a drive signal to write data voltage to the first node N1. At this time, the second transistor T2 turns on, causing the drive transistor T3 to be in a diode-connected state. The data voltage is supplied to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data signal terminal DATA and the threshold voltage of the drive transistor T3 is charged into the storage capacitor C. The voltage on the second plate of the storage capacitor C (second node N2) is Vdata - |Vth|, where Vdata is the data voltage output by the data signal line DATA, and Vth is the threshold voltage of the drive transistor T3.

[0115] The second reset transistor T7 is turned on, providing the second initialization voltage of the second initialization signal terminal INIT2 to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light. The first reset signal line Re1 outputs a high-level signal, turning off the first transistor T1. The light emission control signal terminal EM outputs a high-level signal, turning off the fifth transistor T5 and the sixth transistor T6.

[0116] The third stage, t3, is called the light-emitting stage. The light-emitting control signal terminal EM outputs a low-level signal, while the first reset signal terminal Re1, the second reset signal terminal Re2, and the first scan signal terminal S1 output high-level signals. The low-level signal at the light-emitting control signal terminal EM turns on the fifth transistor T5 and the sixth transistor T6. The first power supply voltage output from the first power supply signal terminal VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, driving transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0117] During the pixel driving circuit operation, the driving current flowing through the driving transistor T3 is determined by the voltage difference between its control electrode and its first electrode. Since the voltage at the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0118] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vdata+|Vth|)] 2 =K*[(Vdd-Vdata)] 2

[0119] Where I is the driving current flowing through the driving transistor T3, which is also the driving current driving the OLED; K is a constant; Vgs is the voltage difference between the control electrode and the first electrode of the driving transistor T3; Vth is the threshold voltage of the driving transistor T3; Vdata is the data voltage output from the data signal terminal DATA; and Vdd is the first power supply voltage output from the first power supply signal terminal VDD. This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0120] The pixel driving circuit can provide a first initialization signal to the first node N1 through the first initialization signal terminal INIT1, and provide a second initialization signal to the first electrode of the light-emitting device through the second initialization signal terminal INIT2.

[0121] Specifically, in an exemplary embodiment, this disclosure provides a display substrate, including:

[0122] Substrate;

[0123] Multiple arrayed sub-pixels, at least one of the sub-pixels including a pixel driving circuit and a light-emitting device, the multiple sub-pixels forming an M-row * N-column array, where M and N are positive integers greater than or equal to 1; the pixel driving circuit includes multiple transistors, the multiple transistors including driving transistors; the light-emitting device includes a first electrode;

[0124] The substrate further includes: a first initialization signal line and a second initialization signal line; the first initialization signal line and the second initialization signal line extend along a first direction, the first direction being the extension direction of the sub-pixel row;

[0125] Wherein, the first initialization signal line is electrically connected to the m-th row of sub-pixels and is configured to transmit the first initialization signal to the control electrode of the driving transistor of the m-th row of sub-pixels; the second initialization signal line is electrically connected to the (m-1)-th row of sub-pixels and is configured to transmit the second initialization signal to the first electrode of the light-emitting device of the (m-1)-th row of sub-pixels.

[0126] In the second direction, the projection of the first initialization signal line on the substrate is located on the side of the projection of the second initialization signal line on the substrate away from the projection of the (m-1)th row of sub-pixels on the substrate. The second direction is the extension direction of the sub-pixel column, and m is a positive integer greater than or equal to 1 and less than or equal to M.

[0127] The first initialization signal is different from the second initialization signal.

[0128] Specifically, such as Figure 5 As shown, the display substrate includes a substrate. Figure 5The diagram shows the specific structure of the display substrate in this embodiment: In a plane parallel to the display substrate, the display substrate may include a plurality of arrayed sub-pixels, at least one of which includes a pixel driving circuit. The plurality of pixel driving circuits form M pixel rows along a first direction and N pixel columns along a second direction. M and N are both positive integers greater than or equal to 1. The first direction and the second direction intersect. Furthermore, the first direction and the second direction may be perpendicular.

[0129] like Figure 5 As shown, the pixel driving circuit may include multiple transistors and light-emitting devices. The pixel driving circuit can adjust the driving current flowing through the driving transistors to drive the light-emitting devices to emit light.

[0130] Please continue to refer to this. Figure 5 The display substrate also includes a first initialization signal line 31 and a second initialization signal line 32. Both the first initialization signal line 31 and the second initialization signal line 32 are signal lines extending along a first direction from the main body portion. In this disclosure, A extending along the B direction means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along the B direction, and the length of the main part extending along the B direction is greater than the length of the secondary part extending along other directions. The first initialization signal line 31 can provide a first initialization signal Vinit1 to the first initialization signal terminal INIT1 in the pixel driving circuit, and the second initialization signal line 32 can provide a second initialization signal Vinit2 to the second initialization signal terminal INIT2 in the pixel driving circuit.

[0131] Please continue to refer to Figure 5 Taking the m-th row of pixels as an example, the first initialization signal line 31 is electrically connected to each sub-pixel in the m-th row. The first initialization signal line 31 is configured to transmit the first initialization signal Vinit1 transmitted thereon to the control electrode of the driving transistor of the m-th row of pixels, i.e., the gate electrode of the driving transistor, to reset it. The second initialization signal line 32 is electrically connected to each sub-pixel in the (m-1)-th row. The second initialization signal line 32 is configured to transmit the second initialization signal Vinit2 transmitted thereon to the first electrode of the light-emitting device of the (m-1)-th row of sub-pixels. For example, the first electrode can be the anode, thereby completing the reset of the anode of the light-emitting device. In the second direction, the projection of the first initialization signal Vinit1 on the substrate is located on the side of the projection of the second initialization signal line Vinit2 on the substrate away from the (m-1)-th row of pixels. Here, m is a positive integer greater than or equal to 1 and less than or equal to M.

[0132] In this design, the first initialization signal Vinit1 and the second initialization signal Vinit2 may not be equal. Therefore, the pixel driving circuit can provide different initialization signals to the first node N1 and the first electrode of the light-emitting device according to actual needs. For example, setting the effective voltage level of the first initialization signal to -3V and the effective voltage level of the second initialization signal to -4V can ensure that the display screen has low brightness in black, improving the image display effect. In another possible implementation, the first initialization signal line 31 and the second initialization signal line 32 are located between the driving transistors of two adjacent rows of sub-pixels, and are located on the same side of the driving transistors of any row in the second direction. Figure 5 As shown, in the column direction, the first initialization signal line 31 and the second initialization signal line 32 are located between the driving transistors of the m-th row pixel and the driving transistors of the (m-1)-th row pixel, and are located on the same side of both rows. Positioning the first initialization signal line 31 and the second initialization signal line 32 between adjacent rows of sub-pixels allows for a shorter reset path when resetting the first node N1 of the m-th row pixel and the first electrode of the light-emitting device of the (m-1)-th row pixel, enabling faster and more complete resets. Simultaneously, this arrangement helps to better utilize the space of the display substrate, resulting in a more rational pixel arrangement, smaller footprint, and easier achievement of high-resolution displays.

[0133] In another possible implementation, the width of the first initialization signal line 31 in the second direction is different from the width of the second initialization signal line 32 in the second direction. It should be noted that the "width in the second direction" refers to the width of the main portion of the two signal lines extending along the first direction in the second direction. The second direction is also the extension direction of the pixel column. The sheet resistance value of a signal line has a negative correlation with its width; that is, the larger the line width, the smaller the sheet resistance. Setting one of the two signal lines to a wider line width can effectively reduce the overall sheet resistance of the two signal lines. Simultaneously, setting one of them to a wider line width also helps to fully utilize the space of the display substrate while reducing resistance, thereby improving the display effect. Specifically, in one possible implementation, the width of the second initialization signal line 32 in the second direction can be greater than the width of the first initialization signal line in the second direction. Furthermore, in one possible implementation, the width of the second initialization signal line 32 is 1.3 to 2.4 times the width of the first initialization signal line 31.

[0134] In another possible implementation, please continue to refer to Figure 5The display substrate also includes a reset signal line 21 extending along a first direction, and multiple transistors including a first reset transistor T1 and a second reset transistor T7. Taking the m-th row sub-pixel as an example: the reset signal line 21 is used to provide a first reset signal to the first reset signal terminal Re1 of the m-th row sub-pixel driving circuit, and simultaneously, the reset signal line 21 is used to provide a second reset signal to the second reset signal terminal Re2 of the (m-1)-th row sub-pixel driving circuit. At this time, the first reset signal Re1 of the m-th row and the second reset signal Re2 of the (m-1)-th row are the same signal. Specifically, taking a P-type transistor as an example, when the first reset signal Re1 is a low-level signal, the first reset transistor T1 of the m-th row pixel circuit is turned on, and the first initialization signal Vinit1 can be written to the control electrode of the driving transistor T3 of the m-th row sub-pixel via the first reset transistor T1; the second reset transistor T7 is turned on when the second reset signal is a low-level signal, and the second initialization signal Vinit2 can be written to the first electrode of the (m-1)-th row sub-pixel via the second reset transistor T7.

[0135] In the example implementation, please continue to refer to Figure 5 In the second direction, the reset signal line 21, the first initialization signal line 31, and the second initialization signal line 32 are arranged sequentially along the direction away from the driving transistor of the m-th row sub-pixel.

[0136] In an exemplary implementation, such as Figures 6a-10 As shown, in a plane perpendicular to the display substrate, the display substrate may include a semiconductor layer 1, a first conductive layer 2, a second conductive layer 3, a third conductive layer 4, and a fourth conductive layer 5 sequentially disposed on the substrate. The semiconductor layer 1 includes an active layer of multiple transistors, and the active layer includes a channel region and a source / drain region of the transistors. The first conductive layer 2 includes a reset signal line 21 and a control electrode of the transistor. The second conductive layer 3 includes a first initialization signal line 31 and a second initialization signal line 32. The third conductive layer 4 includes a first power line 42, a first electrode and a second electrode of the transistor. The fourth conductive layer 5 includes a second power line 52 and a data signal line 51.

[0137] In another possible implementation, please refer to Figure 11 The display substrate also includes a third initialization signal line 41 extending along the second direction, which is disposed on a different layer from the first initialization signal line 31. Figure 11 The semiconductor layer, first metal layer, second metal layer, fourth metal layer, etc. in the illustrated embodiment can all be referred to as such. Figure 6a , Figure 7 , Figure 8 , Figure 10The settings are detailed here. In this disclosure, "A and B are set in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is its dimension in the direction perpendicular to the display substrate. The third initialization signal line 41 is electrically connected to one of the first initialization signal line 31 and the second initialization signal line 32. For details, please refer to... Figure 12a and Figure 12b The third initialization signal line 41 can be located in the third conductive layer 4; in another possible implementation, please refer to Figure 11 The third initialization signal line 41 can be electrically connected to the first initialization signal line 31.

[0138] By placing the third initialization signal line 41 on a different layer than the first initialization signal line 31 and the second initialization signal line 32, and electrically connecting it to one of them, the initialization signals Vinit1 or Vinit2 can be transmitted in different directions on different layers. This helps reduce the voltage drop during initialization signal transmission and improves the uniformity of the displayed image. Specifically, the third initialization signal line 41 can be connected to the first initialization signal line 31 via a via.

[0139] Furthermore, in another possible implementation, the third initialization signal line 41 and the first initialization signal line 31 are connected via vias to form a mesh distribution structure, such as... Figure 13 As shown, the use of a mesh distribution structure can significantly reduce the voltage drop during the transmission of the first initialization signal Vinit1, and can more significantly improve the uniformity of the image.

[0140] In another possible implementation, please refer to [link / reference]. Figure 11 At least one column of sub-pixels is set between two adjacent third initialization signals 41. That is, for a total of M rows and N columns of sub-pixels, the third initialization signal lines 41 are only set in odd-numbered columns, such as the first column, the third column, the fifth column, and so on. Of course, the third initialization signal lines 41 can also be set only in even-numbered columns, such as the second column, the fourth column, the sixth column, and so on. Setting the third initialization signal lines 41 in alternating columns helps to increase the distance between two adjacent signal lines, reduce parasitic capacitance, and improve the display quality.

[0141] In another possible implementation, please refer to [link / reference]. Figure 11At least two first power lines 42 are provided between two adjacent initialization signal lines 41. For example, two first power lines 42 with constant voltage can be provided between two adjacent third initialization signal lines 41, and the first power lines 42 provide a first power supply voltage Vdd to the first power supply signal terminal VDD of the pixel driving circuit. This arrangement helps to maximize the use of the substrate space, achieve a tight arrangement of pixels, and at the same time prevent crosstalk between adjacent third initialization signal lines 41, thereby improving the display quality.

[0142] In one possible implementation, the shapes of two adjacent third initialization signal lines may be the same or different. The phrase "A and B have the same shape" as used in this disclosure means that, within a reasonable error range or process deviation, the shapes of A and B are approximately the same.

[0143] In one possible implementation, the plurality of transistors includes a first reset transistor T1, a second transistor T2, a drive transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a second reset transistor T7.

[0144] like Figure 6a and Figure 6b The semiconductor layer 1 shown includes: a first active layer 11 of the first transistor T1 to a seventh active layer 17 of the second reset transistor. The active layer of each transistor includes a source / drain region and a channel region. The source / drain region of each transistor includes a first region and a second region. The channel region of each transistor is located between the first and second regions of the transistor. Specifically, as... Figure 6bAs shown, the first active layer 11 includes the channel region 111 of the first transistor T1, the first region 112, and the second region 113. The first active layer 12 includes the channel region 121 of the second transistor T2, the first region 122, and the second region 123. The third active layer 13 includes the channel region 131 of the driving transistor T3, the first region 132, and the second region 133. The fourth active layer 14 includes the channel region 141 of the fourth transistor T4, the first region 142, and the second region 143. The fifth active layer 15 includes the channel region 151 of the fifth transistor T5, the first region 152, and the second region 153. The sixth active layer 16 includes the channel region 161 of the sixth transistor T6, the first region 162, and the second region 163. The seventh active layer 17 includes the channel region 171 of the seventh transistor T7, the first region 172, and the second region 173. Among them, the first region 112 of the first active layer 11 is separately provided. The second region 113 of the first active layer 11 simultaneously serves as the first region 122 of the second active layer 12. The first region 132 of the third active layer 13 simultaneously serves as the second region 143 of the fourth active layer 14 and the second region 153 of the fifth active layer 15. The second region 133 of the third active layer 13 simultaneously serves as the second region 123 of the second active layer 12 and the first region 162 of the sixth active layer 16. The second region 163 of the sixth active layer 16 simultaneously serves as the first region 172 of the seventh active layer 17. In an exemplary embodiment, the first region 142 of the fourth active layer 14, the first region 152 of the fifth active layer 15, and the second region 173 of the seventh active layer are separately provided.

[0145] In the m - 1th pixel row, the first active layer 11, the second active layer 12, and the fourth active layer 14 are located on the side of the third active layer 13 of this pixel driving circuit away from the mth pixel row. The first active layer 11 is located on the side of the second active layer 12 and the fourth active layer 14 away from the third active layer 13. In the m - 1th pixel row, the fifth active layer 15, the sixth active layer, and the seventh active layer 17 are located on the side of the third active layer 13 close to the mth pixel row.

[0146] Among them, exemplarily: the first active layer 11 may present an "n" shape and be a double - gate structure including two channel regions; the second active layer 12 may be a "7" shape and be a double - gate structure including two channel regions; the third active layer 13 may be a "ji" shape or an "I" shape. The shapes of each active layer can be selected according to process requirements, and the present disclosure does not limit this.

[0147] As Figure 7 shown, the first conductive layer 2 includes a reset signal line 21, a first scan signal line 22, a light - emitting signal control line 23, and the first electrode plate 24 of the storage capacitor C. The first conductive layer 2 can be referred to as the first gate metal layer (Gate1 layer).

[0148] The reset signal line 21, which provides the first reset signal to the pixel driving circuit of the (m-1)th row, and the first scan signal line 22, which provides the first scan signal, are located on the side of the first electrode plate 24 of this pixel row away from the sub-pixel of the mth row. The first scan signal line 22 is located on the side of the reset signal line 21, which provides the first reset signal to this pixel row, away from the first electrode plate 24. The light emission control signal line 23 can be located on the side of the first electrode plate 24 of this pixel row closer to the pixel of the mth row.

[0149] Figure 14 The diagram shows a stacked structure of semiconductor layer 1 and first conductive layer 2. The area on the first conductive layer 2 that overlaps with the semiconductor layer 1 projected onto the substrate can serve as the control electrode of each transistor. Specifically, a portion of the structure of the reset signal line 21 can be used to form the control electrode (gate) of the first reset transistor T1 and the second reset transistor T7. For the reset signal line 21 that provides the first reset signal to the m-th row of pixels, a portion of its structure can constitute the control electrode of the first reset transistor T1 in the current row of pixels and the control electrode of the second reset transistor T7 in the (m-1)-th row. A portion of the structure of the first scan signal line 22 can be used to form the control electrode (gate) of the second transistor T2 and the fourth transistor T4. The first scan signal line 22 includes a first protrusion 221, which includes the control electrode of the second transistor T2. The light emission control signal line 23 can provide a light emission control signal to the light emission control signal terminal EM of the pixel circuit. A portion of the structure of the light emission control signal line 23 can be used to form the control electrode (gate) of the fifth transistor T5 and the sixth transistor T6. The first electrode plate 24 can simultaneously serve as the control electrode (gate) of the driving transistor T3. The first electrode plate 24 can be a rounded rectangle, and its projection on the substrate overlaps with the projection of the driving transistor T3 on the substrate.

[0150] Specifically, the substrate fabrication process may include: depositing a semiconductor layer 1 on the substrate and patterning the semiconductor layer 1 to form the active layers of each transistor; depositing an insulating thin film on the semiconductor layer 1, and then depositing a first conductive layer 2 on the insulating thin film, and patterning the first conductive layer 2 to form a reset signal line 21, a first scan signal line 22, a light emission control signal line EM, and a first electrode 24; and performing a conductor treatment on the semiconductor layer 1, where the area blocked by the first conductive layer 2 forms the channel region of T1T7, and the unblocked first conductive layer 1 is conductor-treated, that is, the source and drain regions of T1 to T7 are all conductor-treated.

[0151] like Figure 8 As shown, the second conductive layer 3 includes: a first initialization signal line 31, a second initialization signal line 32, a shielding portion 33, a first conductive portion 34, and a second electrode plate including a storage capacitor C. A first through-hole 341 is provided on the first conductive portion 34. Please refer to... Figure 4 and Figure 11 In one possible implementation, the projection of the second initialization signal line 32 onto the substrate overlaps with the projection of at least a portion of the source and drain regions of the first transistor T1 onto the substrate. Specifically, when the first transistor T1 is a dual-gate transistor, the second initialization signal line 32 blocks the conductive portion between the two dual gates of the first transistor T1 to prevent the conductive portion between the dual gates from being affected by other parts of the pixel driving circuit, thereby improving the display effect.

[0152] like Figure 12a and Figure 12b As shown, the third conductive layer 4 may include: a third initialization signal line 41, a first power line 42, a first connection portion 43, a second connection portion 44, a third connection portion 45, a fourth connection portion 46, and a fifth connection portion 47; the third initialization signal line 41 includes a first extension portion 411, a second extension portion 412, and a third extension portion 413 connected sequentially along a second direction. The first extension portion 411 extends along the second direction and is electrically connected to the first initialization signal line 411 through a via. The extension direction of the third extension portion 413 is different from the extension direction of the first extension portion 411. The second extension portion 412 is used to connect the first extension portion 411 and the third extension portion 413. The extension direction of the second extension portion 412 deviates from the second direction.

[0153] Please continue to refer to this. Figure 12a and Figure 12b In some possible embodiments, the first extension 411 extends along the second direction, and the second extension 412 is connected to the first extension 411, having an included angle α1, where 90° < α1 < 180°, for example, it can be 130° to 135°; the third extension 413 is connected to the second extension 412, having an included angle α2, where 90° < α2 < 180°, for example, it can be 125° to 135°.

[0154] For some possible implementations, please refer to [link / reference]. Figure 12a and Figure 12b The third initialization signal line may further include a fourth extension 414, a fifth extension 415, and a sixth extension 416; wherein the fourth extension 414 is connected to the third extension 413, and the connection position can be a chamfered or rounded structure, and the fourth extension 414 extends along a first direction; the fifth extension 415 is connected to the fourth extension 414, having an included angle α3, and 90°<α3<180°, for example, it can be 125° to 135°. The sixth extension 416 is connected to the fifth extension 415, and the sixth extension 416 extends along a second direction, and the fifth extension 415 and the sixth extension 416 have an included angle α4, and 90°<α4<180°, for example, it can be 125° to 135°.

[0155] It should be noted that the included angles of the various extensions mentioned above refer to the included angles between the line segments containing the various extensions. Those skilled in the art will understand that, in actual manufacturing processes, the edges of the various extensions may not be as... Figure 12a and Figure 12b The shapes presented are all regular straight lines, but they can be wavy, curved, or other irregular edge shapes that are allowed within the range of process error. Therefore, it can also be understood that the above included angles can actually have a certain degree of deviation (e.g., ±10°).

[0156] Please refer to Figures 12a-12b The projection of the first extension 413 onto the substrate overlaps with the projections of the reset signal line 21, the first initialization signal line 31, and the second initialization signal line 32 onto the substrate. The first extension 413 is also electrically connected to the first region of the first transistor T1 via a via. That is, the first extension 413 can transmit the first initialization signal Vinit1 by connecting to the first initialization signal line 31, which is used to form a mesh structure and reduce the transmission voltage drop. At the same time, the first extension 413 can transmit the first initialization signal Vinit1 to the first region of the first transistor T1, thereby resetting the first plate 24 of the storage capacitor C and the control electrode of the driving transistor.

[0157] Please refer to Figure 11 and Figures 12a-12b The projections of the second extension 412 onto the substrate overlap with the projections of the first protrusion 221 and the shielding portion 33 onto the substrate. The second extension 412 forms an angle α1 with the first extension 411. Properly setting this angle allows for better avoidance of pixel circuitry, minimizing parasitic capacitance while maximizing the use of substrate space. Along the first direction, the projection of the third extension 413 onto the substrate is located on the side where the projection of the driving transistor T3 onto the substrate is furthest from the projection of the first power line 42 onto the substrate.

[0158] Please continue to refer to Figure 11 and Figures 12a-12b The second connection part 44 is connected to the second initialization signal line 32 through a via and to the first region of the second reset transistor T7, so as to transmit the second initialization number Vinit2 to the first electrode of the light-emitting device and reset it; the first end of the third connection part 45 is connected to the control electrode of the driving transistor T3 through a via, and the second end is connected to the first region of the second transistor T2 through a via.

[0159] Please continue to refer to Figures 12a-12bThe first power line 42 may include multiple seventh extensions 421. Each seventh extension 421 may include a portion bent along a first direction. The width of the seventh extension 421 in the first direction is greater than the width of other parts of the first power line 42 in the first direction. The seventh extension 421 is electrically connected to the first region and the first conductive portion 43 of the fifth transistor T5 to transmit the Vdd signal to the first conductive portion 421, providing a first power supply voltage signal to the second plate of the storage capacitor and the driving transistor. At the same time, the first conductive portion 43 can be transversely connected through the seventh extensions 421 in the first direction to reduce the voltage drop of the first power supply voltage transmission and improve the display effect.

[0160] like Figure 10 As shown, the fourth conductive layer 5 includes a data signal line 51, a second power supply line 52, a sixth connection portion 54, a seventh connection portion 55, an eighth connection portion 56, and a flattening portion 53. The flattening portion 53 further includes a first color flattening portion 531, a second color flattening portion 532, and a third color flattening portion 533. The data signal line 51 is used to transmit a data voltage signal Vdata to the data signal terminal DATA of the pixel driving circuit. The data signal line 51 is connected to the first connection portion 43 via the sixth connection portion 54, and the first connection portion 43 is connected to the first region 142 of the fourth transistor T4.

[0161] In one possible implementation, please refer to Figure 11 and Figures 12a-12b The shielding portion 33 is connected to the first power line 42 via a via, and its projection on the substrate covers the source and drain regions of the second transistor T2. Furthermore, the projection of the shielding portion 33 on the substrate does not overlap with the projection of the data signal line 51 on the substrate. That is, the shielding portion 33 shields the conductive region of the second transistor T2. Further, when the second transistor T2 has a dual-gate structure, the projection of the shielding portion 33 on the substrate covers the projection of the conductive portion between the dual gates of the second transistor T2 onto the substrate. Under the coupling of other conductive structures, the potential of the conductive portion is prone to change, which can cause leakage to the source or drain of the second transistor T2. Therefore, when the shielding portion 33 has a Vdd voltage, it helps to prevent the conductive portion from floating, thus playing a certain role in voltage stabilization and improving the image quality. At the same time, the projection of the shielding portion 33 on the substrate does not overlap with the projection of the data signal line 51 on the substrate, reducing the parasitic capacitance between the data signal line 51 and the shielding portion 33. Meanwhile, the shielding portion 33 plays a role in voltage stabilization, which can prevent the influence of pixel data voltage changes in adjacent columns on sub-pixels and improve the image quality.

[0162] The second power line 52 is electrically connected to the first power line 42 via the eighth connecting part 56 and the seventh extension part 421. Specifically, this connection can be achieved through a via. That is, the second power line 52 and the first power line 51 are connected in parallel, which can significantly reduce the voltage drop of the Vdd signal during transmission and improve the display effect.

[0163] In one possible implementation, the projection of the second power line 52 onto the substrate at least partially overlaps with that of the first power line 42. Furthermore, the width of the second power line 52 in the first direction is smaller than the width of the seventh extension 421 in the first direction.

[0164] The seventh connecting part 55 is connected to the fourth connecting part 46 and the fifth connecting part 47 via vias. The fourth connecting part 46 and the fifth connecting part 47 are connected to the second region of the sixth transistor T6 via vias. The shapes of the fourth connecting part 46 and the fifth connecting part 47 may be different, for example, Figures 12a-12b As shown, the fifth connecting portion 47 is longer than the fourth connecting portion 46 in the second direction. In one possible embodiment, the fourth connecting portion 46 and the first initialization signal line 41 are disposed in the same pixel column. Of course, the shapes of the fourth connecting portion 46 and the fifth connecting portion 47 can also be the same.

[0165] Please continue to refer to this. Figure 10 The fourth conductive layer also includes a flat portion 53, which is connected to the second power line 52. That is, the potential of the flat portion 53 is a Vdd signal. The connection between the flat portion 53 and the second power line 52 can reduce the resistance of the second power line, reduce the voltage drop of the second power signal line 52 from the first end to the second end, reduce signal transmission loss, and improve the display effect.

[0166] Please refer to Figure 15 In one possible implementation, the projection of the flat portion 53 onto the substrate at least partially overlaps with the projection of the first electrode of the light-emitting device onto the substrate. The first electrode can be an anode, and the flat portion 53 can be used to improve the flatness of the first electrode, improve color shift, and enhance the display effect. Further, in other possible implementations, the projection of the first electrode of the light-emitting device onto the substrate completely covers the projection of the flat portion 53 onto the substrate. In this disclosure, "the projection of A completely covers B" means that the outline of the projection of B in a certain plane is completely located inside the outline of the projection of A in the same plane.

[0167] Please continue to refer to this. Figure 10 In one possible implementation, the shapes of the flat portions 53 of the sub-pixels emitting different colors of light may be different, for example, they may include a first color flat portion 531, a second color flat portion 532, and a third color flat portion 533. Of course, the shapes of the flat portions 53 may also be the same.

[0168] Please refer to Figure 10 In one possible implementation, the area of ​​the first color flat portion 531 is larger than the area of ​​the second color flat portion 532 and the area of ​​the third color flat portion 533.

[0169] In one possible implementation, please refer to Figure 1a and Figure 1b The multiple sub-pixels include a first color sub-pixel P1, a second color sub-pixel P2, and a third color sub-pixel P3 that emit different colors of light. The first color sub-pixel P1 can be a red sub-pixel (R) that emits red light, and the pixel driving circuit of sub-pixel P1 is electrically connected to the first electrode of the light-emitting device that emits red light. The second color sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the pixel driving circuit of sub-pixel P2 is electrically connected to the first electrode of the light-emitting device that emits blue light. The third sub-pixel P3 can be a green sub-pixel (G) that emits green light, and the pixel driving circuit of sub-pixel P3 is electrically connected to the first electrode of the light-emitting device that emits green light.

[0170] Please continue to refer to Figure 1a and Figure 1b The multiple sub-pixels P include red sub-pixels R that emit red light, blue sub-pixels G that emit blue light, and green sub-pixels B that emit green light, arranged in multiple pixel rows and multiple pixel columns. The multiple pixel columns include red-blue pixel column RB and green pixel column GG. The red-blue pixel column RB includes red sub-pixels R and blue sub-pixels B alternately arranged along a second direction. The green pixel column GG includes green sub-pixels G arranged sequentially along the second direction.

[0171] In one possible implementation, the third initialization signal line 41 is only provided in the red-blue pixel column RB. In another possible implementation, the third initialization signal line 41 is only provided in the green-green sub-pixel column GG. In yet another possible implementation, the third initialization signal line 41 may be provided in both the red-blue pixel column RB and the green pixel column GG.

[0172] In one possible implementation, the shape of the third initialization signal line 31 located in the nth column of red and blue pixels RB can be the same as the shape of the third initialization signal line 31 located in the (n+1)th column, where n is a positive integer greater than or equal to 1 and less than or equal to N.

[0173] In one possible implementation, the display substrate further includes a fifth conductive layer 6, such as... Figure 16 As shown, the fifth conductive layer 6 includes a first electrode 61 for each sub-pixel. Specifically, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are respectively provided with a first electrode 611, a second electrode 612, and a third electrode 613.

[0174] like Figure 17 As shown, the display substrate also includes a first insulating layer 7, and a third conductive layer 5 is located on the side of the first insulating layer 7 facing the substrate. The first insulating layer 7 includes a first via 711, which exposes the first connection portion 46 and the first connection portion 47.

[0175] The first electrode 61 includes a main portion 61a and an auxiliary portion 61b. The auxiliary portion 61b is electrically connected to the third conductive layer 4 through a first via 711. In this embodiment, the main portion 61a and the auxiliary portion 61b in the same sub-pixel are an integral structure and can be formed simultaneously using a single patterning process.

[0176] like Figure 18 As shown, the display substrate also includes a pixel defining layer 8, a light-emitting layer 91 located on the side of the fifth conductive layer 6 facing away from the substrate, and a cathode 92 located on the side of the light-emitting layer 91 facing away from the fifth conductive layer 6. The pixel defining layer has an opening 81 that exposes at least a portion of the main body portion of the first electrode. The light-emitting layer 81 is located within the opening 81 and in contact with the area of ​​the main body portion exposed by the opening. The area where the light-emitting layer is located within the opening can be used for light emission, thereby defining an effective light-emitting area EA through the opening. In other words, the portion of the opening of the pixel defining layer 8 that overlaps with the main body portion 61a of the first electrode 61 is the effective light-emitting area EA of each sub-pixel. Specifically, as... Figure 18 As shown, in one possible implementation, the area where the opening of the pixel definition layer 8 in the second color sub-pixel P2 overlaps with the main body of the first electrode 612 is the effective light-emitting area EA2 of the second color sub-pixel P2. Similarly, the area where the opening of the pixel definition layer 8 in the first color sub-pixel P1 overlaps with the main body 611a of the first electrode 611 is the effective light-emitting area EA1 of the first color sub-pixel P1, and the area where the opening of the pixel definition layer 8 in the third color sub-pixel P3 overlaps with the main body of the first electrode 613 is the effective light-emitting area EA3 of the third color sub-pixel P3.

[0177] In one possible implementation, the flat portion 53 is located on the side of the first electrode 61 closest to the substrate. For example... Figure 15 and Figure 16 As shown, the shape of the first color flat portion 531 is basically the same as the shape of the main body portion 611a of the first electrode 611 of the first color sub-pixel, the shape of the second color flat portion 532 is basically the same as the shape of the main body portion 612a of the first electrode 612 of the second color sub-pixel, and the shape of the third color flat portion 533 is basically the same as the shape of the main body portion 613a of the first electrode 613 of the third color sub-pixel.

[0178] In this disclosure, "A and B have substantially the same shape" means that A and B have the same outline shape and the area difference between A and B does not exceed ±1%.

[0179] In other words, the shape of each flat part corresponds one-to-one with the shape of each first electrode above it, which helps to make each part of each first electrode uniform and flat, eliminates asymmetry, and thus improves or even eliminates color deviation.

[0180] In one possible implementation, the areas of the main body portions of the first electrode of different color sub-pixels may be different. For example, the area of ​​the main body portion 611a of the first electrode of the first color sub-pixel may be larger than the area of ​​the main body portion 612a of the first electrode of the second color sub-pixel and the area of ​​the third color sub-pixel 613a. Of course, the areas of the main body portions of each color may also be the same, or the size may be set as needed. This disclosure does not limit this.

[0181] like Figure 15 and Figure 16 As shown, the main body portion 61a of the first electrode 61 can be octagonal in shape, and correspondingly, the shape of each flat portion 53 can also be approximately octagonal. The first color flat portion 531 includes a first recess 5311, which is used to avoid the through-hole electrically connecting the eighth connecting portion 56 and the seventh extension portion 421; the third color flat portion 533 includes a second recess 5331, which is used to avoid the through-hole electrically connecting the seventh connecting portion 55 and the fifth connecting portion 47; in other possible embodiments, the shape of the main body portion 61a can be hexagonal, rectangular, or other shapes, and this disclosure does not limit this.

[0182] In one possible implementation, the projection of the flat portion 53 of each sub-pixel onto the substrate at least partially overlaps with the projection of the first electrode 61 of the corresponding sub-pixel onto the substrate. Specifically, the projection of the first color flat portion 531 onto the substrate at least partially overlaps with the projection of the first electrode 611 of the first color sub-pixel onto the substrate; the projection of the second color flat portion 532 onto the substrate at least partially overlaps with the projection of the first electrode 612 of the second color sub-pixel onto the substrate; and the projection of the third color flat portion 533 onto the substrate at least partially overlaps with the projection of the first electrode 613 of the third color sub-pixel onto the substrate. That is, each first electrode of a different color sub-pixel has a flat portion on the side closest to the substrate, which enables the first electrode of each sub-pixel to be flat, reducing color shift and improving the uniformity of the displayed image.

[0183] Furthermore, in one possible implementation, the projection of the first electrode 611 of the first color sub-pixel onto the substrate completely covers the projection of the first color flattening portion 531 onto the substrate; the projection of the first electrode 612 of the second color sub-pixel onto the substrate completely covers the projection of the second color flattening portion 532 onto the substrate; and the projection of the first electrode 613 of the third color sub-pixel onto the substrate completely covers the projection of the third color flattening portion 533 onto the substrate. Typically, the signal lines such as the first power line 42 and the second power line 52, fabricated by the third conductive layer 4 and the fourth conductive layer 5 located on the side of the first electrode closer to the display substrate, have a relatively large thickness in the direction perpendicular to the substrate. The insulating layer above the signal lines cannot achieve complete planarization, resulting in an uneven light-emitting layer above the planarization layer. This leads to asymmetrical protrusions in the first electrode 61 and the light-emitting layer above it, causing color shift when viewed from the left and right sides of the display substrate at the same angle as the display substrate. By setting a flat portion below the first electrode of different sub-pixels, and the flat portion being completely located inside the projection of the first electrode, the corresponding position of the first electrode of each sub-pixel can be flattened, further improving color shift.

[0184] In one possible implementation, the projection of the flat portion 53 onto the substrate overlaps with the projection of the first power line 41 onto the substrate. Specifically, in the embodiment shown in this disclosure, the projection of the flat portion 53 onto the substrate at least partially overlaps with the seventh extension 421 of the first power line 42. This arrangement helps to reduce the voltage drop of the first power supply voltage transmitted on the signal line and improves the uniformity of the displayed image.

[0185] Please refer to Figure 1a and Figure 15 In one possible implementation, the first color sub-pixel can be a red sub-pixel R that emits red light, and the second color sub-pixel can be a blue sub-pixel G that emits blue light. Correspondingly, the first color flat portion 531 and the second color flat portion 532 at least partially overlap with the seventh extension portion 421.

[0186] Please continue to refer to this. Figure 15 In one possible implementation, the first color sub-pixel can be a red sub-pixel R that emits red light, and the second color sub-pixel can be a blue sub-pixel B that emits blue light. In this case, the projections of the first color flat portion 531 and the second color flat portion 532 on the substrate overlap at least partially with the projection of the control electrode 24 of the driving transistor T3 on the substrate, which can stabilize the potential of the first node N1.

[0187] Please continue to refer to this. Figure 15In one possible implementation, the third color sub-pixel can be a green sub-pixel G that emits green light. In this case, the projection of the third color flattening portion 533 onto the substrate at least partially overlaps with the projection of the source / drain region and / or channel region of the first transistor T1 onto the substrate. Specifically, when the first reset transistor T1 is a dual-gate transistor, the third color flattening portion 533 blocks the conductive portion between the dual gates of the first reset transistor T1, which can reduce leakage current. In another possible implementation, the first reset transistor T1 can also be an oxide transistor (IGZO). In this case, the third color flattening portion 533 blocks the oxide transistor T1, which can further prevent the influence of light on the transistor performance.

[0188] Please continue to refer to this. Figure 1a and Figure 15 In one possible implementation, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel emit red light, blue light, and green light, respectively. Multiple red sub-pixels R and blue sub-pixels B are alternately arranged along a second direction to form an RB pixel column, and multiple green sub-pixels G are alternately arranged along the second direction to form a green pixel column GG. The red and blue pixel columns RB and the green pixel column GG are alternately arranged along a first direction. The projection of the auxiliary portion 611b of the first electrode of the red sub-pixel R onto the substrate at least partially overlaps with the projection of the source / drain region of the second transistor T2 of the adjacent green sub-pixel G onto the substrate. When the second transistor T2 has a dual-gate structure, this overlap is located in the conductive region between the dual gates, thereby reducing leakage current in the second transistor T2 and improving the uniformity of the displayed image. Similarly, the projection of the auxiliary portion of the first electrode of the blue sub-pixel G onto the substrate at least partially overlaps with the projection of the source / drain region of the second transistor T2 of the adjacent green sub-pixel G onto the substrate. The principle and technical effect are the same, and will not be repeated here.

[0189] In one possible implementation, the display substrate may further include a light-shielding layer (not shown in the figure). The light-shielding layer may be located between the substrate and the semiconductor layer 1. The projection of the light-shielding layer on the substrate covers at least the projection of the active region of one of the multiple transistors on the substrate. For example, the projection of the light-shielding layer on the substrate may cover the projection of the channel region of the driving transistor T3 on the substrate. This is used to block external light and shield external interference, avoid affecting the performance of the active layers of each transistor, and improve the display effect.

[0190] Furthermore, in one possible implementation, the light-shielding layer can be a semiconductor material (a-Si) or a metallic material (Mo). The light-shielding layer can be electrically connected to a constant potential to prevent it from being in a floating state, thus providing better anti-interference for the channel region of the active layer. Specifically, the light-shielding layer can be electrically connected to the first power line 41, or to the first initialization signal line 31 or the second initialization signal line 32.

[0191] In another possible implementation, the light-shielding layer may include only the first connecting structure extending along the first direction, or only the second connecting structure extending along the second direction, or both the first connecting structure extending along the first direction and the second connecting structure extending along the second direction.

[0192] The first and second connection structures can each be connected in a mesh configuration with their electrically connected structures to significantly reduce loading. For example, the first connection structure can be electrically connected to the first power line 41 and form a mesh configuration. Alternatively, the first connection structure can be electrically connected to the third initialization signal line 41 and form a mesh configuration. Another example is that the second connection structure can be electrically connected to either the first initialization signal line 31 or the second initialization signal line 32 and form a mesh configuration. Yet another example is that the second connection structure can be connected in parallel with the third initialization signal line 41, and the second connection structure can be located only in the red-blue pixel column, only in the green-green pixel column, or simultaneously in both the red-blue and green-green pixel columns. Furthermore, the first and second connection structures can be connected in a mesh configuration, meaning the light-shielding layer itself can be mesh-like.

[0193] like Figure 1a and Figure 19a As shown, the display substrate includes a display area AA and a peripheral area NA located outside the display area. The peripheral area NA may include a left bezel area NA-L, a right bezel area NA-R, a top bezel area NA-U, and a bottom bezel area NA-D. In one possible embodiment, a first initialization signal line bus 31' and a second initialization signal line bus 32' extending along a second direction are provided in the left bezel area NA-L and the right bezel area NA-R, respectively. Multiple first initialization signal lines 31 are electrically connected to the first initialization signal line bus 31', and multiple second initialization signal lines 32 are electrically connected to the second initialization signal line bus 32'. Simultaneously, a third initialization signal line bus 41' extending along a first direction may be provided in the top bezel area NA-U and / or the bottom bezel area NA-D, and electrically connected to multiple third initialization signal lines 41. Each initialization signal line bus provides an initialization signal for the corresponding initialization signal line.

[0194] In another possible implementation, such as Figure 19bAs shown, the left frame area NA-L and the right frame area NA-R are each provided with a first initialization signal line bus 31' and a second initialization signal line bus 32' extending along the second direction. Multiple first initialization signal lines 31 are electrically connected to the first initialization signal line bus 31', and multiple second initialization signal lines 32 are electrically connected to the second initialization signal line bus 32'.

[0195] In another possible implementation, such as Figure 19c As shown, a bus 41' extending along the first direction can be provided in the upper frame area NA-U and / or the lower frame area NA-D, which is electrically connected to multiple third initialization signal lines 41 to provide corresponding initialization signals for the third initialization signal lines.

[0196] In possible implementations, the first initialization signal bus 31', the second initialization signal bus 32', and the third initialization signal bus 41' can be located in the same film layer, such as all of them being located in the third conductive layer 4 or all of them being located in the fourth conductive layer 5; of course, they can also be located in different film layers. For example, the first initialization signal bus 31' can be located in the third conductive layer 4, and the second initialization signal bus 32' and the third initialization signal bus 41' can be located in the fourth conductive layer 5. Of course, the design can be customized according to specific needs, and this disclosure does not limit this.

[0197] This disclosure also provides a display device, which includes the aforementioned display panel. The display device can be a mobile phone, tablet computer, or other display device.

[0198] This disclosure also provides a method for manufacturing a display substrate, comprising at least the following steps:

[0199] S1: A semiconductor layer 1 is deposited on a substrate, and the semiconductor layer 1 is patterned to form the active layers of each transistor; the first active layer 11 to the seventh active layer 17 are an integral structure interconnected with each other.

[0200] S2: A second insulating layer 72 is deposited on semiconductor layer 1, and then a first conductive layer 2 is deposited on the second insulating layer 12. The first conductive layer 2 is patterned to form a reset signal line 21, a first scan signal line 22, a light emission control signal line EM, and a first electrode 24; as shown. Figure 7 As shown, the first metal layer can also be called the gate metal layer (Gate1 layer).

[0201] S3: Conducting a conductive process on semiconductor layer 1, such as ion implantation, etc. The area shielded by the first conductive layer 2 forms the channel region of the first reset transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the second reset transistor T7. The unshielded semiconductor layer 1 is conductive, that is, the source and drain regions of the seven transistors T1 to T7 are all conductive.

[0202] S4: A third insulating layer 73 is deposited on the first conductive layer 2, and a second conductive layer 3 is deposited and patterned on the insulating layer. The second conductive layer 3 includes a first initialization signal line 31, a second initialization signal line 32, a shielding portion 33, and a first conductive portion 34. The second conductive layer can also be a second gate metal layer (Gate2 layer).

[0203] S5: Deposit a third insulating layer 74 on the second conductive layer 3, deposit a third conductive layer 4 on top of the third insulating layer and pattern it, the third conductive layer includes at least a third initialization signal line 41, a first power line 42, a first connection portion 43, a second connection portion 44, a third connection portion 45, a fourth connection portion 46 and a fifth connection portion 47.

[0204] S6: A first insulating layer 71 is deposited above the third conductive layer 4, and a fourth conductive layer 5 is deposited and patterned on the first insulating layer 71. The fourth conductive layer 5 includes at least a data signal line 51, a second power line 52, and a flat portion 53.

[0205] S7: A fourth insulating layer 75 is deposited on the fourth conductive layer 5, and a fifth conductive layer 6 is deposited and patterned above the fourth insulating layer 75 to form the first electrode pattern of the sub-pixel.

[0206] Subsequent fabrication processes may include: forming an organic light-emitting layer using inkjet printing or vapor deposition; connecting the organic light-emitting layer to a first electrode through an opening in a pixel definition layer; forming a second electrode on the organic light-emitting layer; and connecting the second electrode to the organic light-emitting layer. An encapsulation layer is then formed, which may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is positioned between the first and third encapsulation layers to prevent external moisture from intruding into the light-emitting structure.

[0207] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz, while the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0208] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They may be single-layer, multi-layer, or composite layers. The first insulating layer is called a buffer layer, used to improve the substrate's resistance to water and oxygen. The second and third insulating layers are called gate insulating (GI) layers, and the fourth insulating layer is called an interlayer insulating (ILD) layer. The active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc. This disclosure applies to transistors manufactured using oxide, silicon, or organic technologies. The first and fourth insulating layers can be made of organic materials, such as resin. The fifth conductive layer can be a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a multilayer composite structure, such as ITO / Ag / ITO. The pixel definition layer can be made of polyimide, acrylic, or polyethylene terephthalate. The cathode can be any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals.

[0209] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0210] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure shall still be defined by the appended claims.

Claims

1. A display substrate, comprising: Substrate; Multiple sub-pixels distributed in an array, at least one of the sub-pixels including a pixel driving circuit and a light-emitting device, the multiple sub-pixels forming M rows An array of N columns, where M and N are positive integers greater than or equal to 1; The pixel driving circuit includes a plurality of transistors, the plurality of transistors including a driving transistor; The light-emitting device includes a first electrode; The substrate further includes: a first initialization signal line and a second initialization signal line; the first initialization signal line and the second initialization signal line extend along a first direction, the first direction being the extension direction of the sub-pixel row; Wherein, the first initialization signal line is electrically connected to the m-th row of sub-pixels and is configured to transmit the first initialization signal to the control electrode of the driving transistor of the m-th row of sub-pixels; the second initialization signal line is electrically connected to the (m-1)-th row of sub-pixels and is configured to transmit the second initialization signal to the first electrode of the light-emitting device of the (m-1)-th row of sub-pixels. In the second direction, the projection of the first initialization signal line on the substrate is located on the side of the projection of the second initialization signal line on the substrate away from the projection of the (m-1)th row of sub-pixels on the substrate. The second direction is the extension direction of the sub-pixel column, and m is a positive integer greater than or equal to 1 and less than or equal to M. The first initialization signal is different from the second initialization signal; In the second direction, the width of the first initialization signal line is different from the width of the second initialization signal line.

2. The display substrate according to claim 1, wherein, The first initialization signal line and the second initialization signal line are located between the driving transistors of two adjacent rows of sub-pixels, and are located on the same side of the driving transistors in either row in the second direction.

3. The display substrate according to claim 2, wherein, In the second direction, the width of the second initialization signal line is greater than the width of the first initialization signal line.

4. The display substrate according to claim 3, wherein, In the second direction, the width of the second initialization signal line is 1.3 to 2.4 times the width of the first initialization signal line.

5. The display substrate according to any one of claims 1 to 4, wherein, The display substrate further includes: a reset signal line, which extends along the first direction and is used to transmit a reset signal to the pixel driving circuit; The plurality of transistors further includes: a first reset transistor and a second reset transistor; The first reset transistor is configured to transmit a first initialization signal on the first initialization signal line to the control electrode of the driving transistor of the m-th row sub-pixel under the control of the reset signal; the second reset transistor is configured to transmit a second initialization signal on the second initialization signal line to the first electrode of the light-emitting device of the (m-1)-th row sub-pixel under the control of the reset signal.

6. The display substrate according to claim 5, wherein, In the second direction, the reset signal line, the second initialization signal line, and the first initialization signal line are arranged sequentially along a direction away from the m-th row sub-pixel driving transistor.

7. The display substrate according to claim 6, wherein, In a direction perpendicular to the display substrate, the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially disposed on the substrate. The semiconductor layer includes the active layer of the plurality of transistors, the active layer including the channel region and source / drain region of the transistor; the first conductive layer includes the reset signal line and the control electrode of the transistor; the second conductive layer includes the first initialization signal line and the second initialization signal line; the third conductive layer includes the first power supply line; and the fourth conductive layer includes the second power supply line and the data signal line.

8. The display substrate according to claim 7, wherein, The display substrate further includes a third initialization signal line extending along the second direction, wherein the third initialization signal line is disposed on a different layer from the first initialization signal line, and the third initialization signal line is electrically connected to the first initialization signal line or the second initialization signal line.

9. The display substrate according to claim 8, wherein, The third conductive layer also includes the third initialization signal line.

10. The display substrate according to claim 8, wherein, The third initialization signal line is electrically connected to the first initialization signal line and is distributed in a mesh pattern.

11. The display substrate according to claim 10, wherein, At least one column of sub-pixels is provided between adjacent third initialization signal lines.

12. The display substrate according to claim 11, wherein, At least two first power lines are provided between adjacent third initialization signal lines.

13. The display substrate according to claim 10, wherein, The plurality of sub-pixels includes a red sub-pixel that emits red light, a blue sub-pixel that emits blue light, and a green sub-pixel that emits green light; the plurality of sub-pixel columns include a red-blue pixel column and a green pixel column; the red-blue pixel column includes red and blue sub-pixels alternately arranged in the second direction; the green pixel column includes green sub-pixels arranged sequentially along the second direction; the third initialization signal line is located in the red-blue pixel column.

14. The display substrate according to claim 13, wherein, The shape of the third initialization signal line electrically connected to the red and blue pixel column in column n is the same as the shape of the third initialization signal line electrically connected to the red and blue pixel column in column n+1, where n is a positive integer greater than or equal to 1 and less than or equal to N.

15. The display substrate according to claim 14, wherein, The third initialization signal line includes a first extension, a second extension, and a third extension connected sequentially along the second direction; the first extension extends along the second direction and is electrically connected to the first initialization signal line through a via; the extension direction of the third extension is different from the extension direction of the first extension, and the second extension is used to connect the first extension and the third extension, and the extension direction of the second extension deviates from the second direction.

16. The display substrate according to claim 15, wherein, The projection of the first extension on the substrate has an overlapping area with the projections of the reset signal line, the first initialization signal line, and the second initialization signal line on the substrate.

17. The display substrate according to claim 16, wherein, The first extension is connected to the first electrode of the first reset transistor via a via.

18. The display substrate according to claim 15, wherein, The second extension forms an angle greater than 90° and less than 180° with the first extension; The third extension is at an angle greater than 90° and less than 180° to the second extension.

19. The display substrate according to claim 7, wherein the plurality of transistors further comprises: The second transistor has a first terminal electrically connected to the second terminal of the driving transistor, and the second terminal of the second transistor is electrically connected to the control terminal of the driving transistor. The second conductive layer further includes a shielding portion electrically connected to the first power line, wherein the projection of the shielding portion on the substrate covers at least a portion of the source / drain region of the second transistor and is located between the projections of the data signal line on the substrate and the projections of the adjacent data signal lines on the substrate.

20. The display substrate according to claim 7, wherein, The third conductive layer further includes a fourth connecting portion and a fifth connecting portion, and the fourth conductive layer further includes a seventh connecting portion, which is electrically connected to the fourth connecting portion and the fifth connecting portion; the fourth connecting portion and the fifth connecting portion have different shapes.

21. A display device comprising a display substrate as described in any one of claims 1-20.

Images