Single pulse avalanche breakdown energy test method and test circuit

Abstract

The present invention provides a single-pulse avalanche breakdown energy testing method and testing circuit. Under the condition of ensuring the original testing process in the prior art, after the single-pulse driving circuit turns off the output of the single-pulse signal, the DC power supply is controlled to be turned off after a preset time delay relative to the turn-off moment of the single-pulse signal, that is, after the avalanche test is completed, the DC power supply is controlled to charge the energy storage circuit (such as an inductor) for a preset time and then turned off, thereby ensuring that the energy stored in the energy storage circuit is sufficient to reach the avalanche point of the device under test, so that the real avalanche value of the device under test can be measured, and the size of the front burn point of the device under test can be reduced, and the problem of metal melting on the back of the device under test can be solved. The present invention is easy to implement and has low implementation cost.

Description

Technical Field

[0001] The invention relates to the technical field of single pulse avalanche breakdown energy testing, and in particular to a single pulse avalanche breakdown energy testing method and a testing circuit. Background Art

[0002] After semiconductor devices (such as MOS tubes, etc.) are manufactured, their parameters will be tested. Abnormal device parameters correspond to abnormal device structure or process, so the test results are an important reference for improving device structure and process. In the process of testing semiconductor devices, an important test item is the EAS (single pulse avalanche breakdown energy) test of the device. The EAS (single pulse avalanche breakdown energy) test of the device calibrates the level of reverse avalanche breakdown energy that the device can safely absorb.

[0003] However, the existing single pulse avalanche breakdown energy test method and test circuit have problems such as being unable to measure the true avalanche value of the device under test or causing the back metal of the device under test to melt and thus damage the test machine during the avalanche test. Summary of the invention

[0004] The object of the present invention is to provide a single pulse avalanche breakdown energy testing method and testing circuit, which can not only ensure that the testing energy is sufficient to reach the avalanche point of the device under test, but also improve the damage problem on the front and back sides of the device under test.

[0005] To achieve the above object, the present invention provides a single pulse avalanche breakdown energy testing method, which comprises:

[0006] First, the device under test is connected to a corresponding test circuit, wherein the test circuit has an energy storage circuit, a DC power supply, and a single pulse drive circuit, wherein the single pulse drive circuit is coupled to a control terminal of the device under test;

[0007] Before the test, the single pulse driving circuit outputs a single pulse signal to control the device under test to be turned on, and the DC power supply charges the energy storage circuit until the current flowing through the device under test reaches a set value;

[0008] Next, the single-pulse driving circuit turns off the output of the single-pulse signal to turn off the device under test. The energy stored in the energy storage circuit is released through the device under test, and an avalanche test is performed on the device under test. The DC power supply is turned off after a preset time delay relative to the turn-off moment of the single-pulse signal.

[0009] Optionally, the preset time is achieved through software control.

[0010] Optionally, the preset time is 1 to 3 times the avalanche failure time of the device under test.

[0011] Optionally, the device under test is an IGBT device, and the preset time is 1 μs to 3 μs.

[0012] Optionally, the energy storage circuit includes an inductor.

[0013] Based on the same inventive concept, the present invention also provides a test circuit for implementing the single-pulse avalanche breakdown energy test method as described in the present invention, wherein the test circuit comprises an inductor, a DC power supply and a single-pulse drive circuit, wherein the inductor, the DC power supply and the corresponding device under test are connected in series in sequence, and the single-pulse drive circuit is coupled to the control end of the device under test and controls the conduction of the device under test by outputting a single-pulse signal.

[0014] Optionally, the test circuit further includes a current limiting impedance, and the current limiting impedance is connected in series between the control terminal of the device under test and the single-pulse drive circuit.

[0015] Optionally, the test circuit further includes a diode, a cathode of the diode is coupled to a connection node between the inductor and the DC power supply, and an anode of the diode is grounded.

[0016] Optionally, the test circuit also includes a power switch coupled to the DC power supply, and the power switch is turned on when the DC power supply charges the energy storage circuit, and is turned off after a preset time delay relative to the turn-off moment of the single pulse signal to turn off the charging of the energy storage circuit by the DC power supply.

[0017] Optionally, the test circuit further comprises a controller coupled to a control terminal of the power switch, for generating a corresponding control signal after a preset time delay relative to a turn-off moment of the single pulse signal, so as to control the power switch to turn off.

[0018] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0019] 1. While ensuring the original test process in the prior art, after the avalanche test is completed, the DC power supply is controlled to continue charging the energy storage circuit (such as an inductor) for a preset time (such as 2.5μs) and then shut down, ensuring that the energy stored in the energy storage circuit (such as an inductor) is sufficient to reach the avalanche point of the device under test, thereby being able to measure the true avalanche value of the device under test while reducing the size of the burn point on the front side of the device under test and solving the problem of metal melting on the back side of the device under test.

[0020] 2. It can combine the advantages of two testing methods in the prior art, while avoiding the defects of the two testing methods in the prior art, and is easy to implement and has low implementation cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0022] Figure 1 It is a structural schematic diagram of an existing EAS test circuit.

[0023] Figure 2 It is an application Figure 1 The test circuit shown is a curve diagram of a method for performing single pulse avalanche breakdown energy testing.

[0024] Figure 3 It is an application Figure 1 The test circuit shown is a curve diagram of another method for performing single pulse avalanche breakdown energy testing.

[0025] Figure 4 yes Figure 3 Schematic diagram of the defects produced by the method shown.

[0026] Figure 5 It is a schematic diagram of the structure of a test circuit according to a specific embodiment of the present invention.

[0027] Figure 6 It is a curve diagram of a single pulse avalanche breakdown energy testing method according to a specific embodiment of the present invention.

[0028] Figure 7 It is a schematic diagram of the results of the single pulse avalanche breakdown energy testing method according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0029] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0030] Existing EAS test circuits such as Figure 1 As shown, it includes a DC power supply VDD, an inductor L, a power switch MOS_SW, a diode D0, a single pulse drive circuit VG, a current limiting impedance RG, a device under test DUT and a current sensor ID. The positive electrode of the DC power supply VDD is connected to one end of the inductor L through the power switch MOS_SW. The other end of the inductor L is connected to the drain D of the device under test DUT through the current sensor ID; the gate G of the device under test DUT is connected to one end of the single pulse drive circuit VG through the current limiting impedance RG, and the single pulse drive circuit VG controls the on-off between the source S and the drain D of the device under test DUT by outputting a corresponding single pulse. The source S of the device under test DUT, the other end of the single pulse drive circuit VG, the anode of the diode D0 and the negative electrode of the DC power supply VDD are all grounded. The cathode of the diode D0 is connected to the connection node of the inductor L and the power switch MOS_SW, so as to maintain the current in the loop in parallel with the device under test DUT.

[0031] Please refer to Figure 2 , the traditional method of single pulse avalanche breakdown energy test using the above test circuit is:

[0032] Before the test, the device under test (DUT) is in the off state, the power switch MOS_SW is turned on, and the drain-source voltage V DS Equal to the voltage of the DC power supply VDD, there is no energy stored in the inductor L.

[0033] Then, a single pulse signal is output through the single pulse drive circuit VG, the device under test DUT is turned on, and the DC power supply VDD charges the inductor L until the current I detected by the current sensor ID reaches D Reach the set value.

[0034] After that, the single pulse signal output by the single pulse drive circuit VG is disconnected, and the current I D The energy stored in the inductor L will be released through the device under test DUT, and the avalanche test of the device under test DUT will begin. Specifically, when the voltage across the device under test DUT reaches its breakdown voltage BV, the device under test DUT undergoes avalanche breakdown, and the current I D Until the energy stored in the inductor L is completely released, I D After decreasing to 0, the device under test DUT is turned off, and the drain-source voltage V DS It is equal to the voltage of the DC power supply VDD again. During this process, the energy borne by the device under test DUT is EAS.

[0035] The main problem with the above test method is that during the test, the energy stored in the inductor L is E = 1 / 2*L*I Dmax 2 , which is not enough to reach the avalanche point of the device under test DUT, resulting in the inability to measure the true avalanche value of the device under test DUT.

[0036] To solve the above problems, please refer to Figure 3 The prior art provides another method for single pulse avalanche breakdown energy testing using the above test circuit, specifically: when the inductor L is charged to a current I D When the set value is reached, the single pulse signal output by the single pulse drive circuit VG is disconnected, but the power switch MOS_SW is kept closed, so that the DC power supply VDD continues to charge the inductor L, and the device under test DUT undergoes an avalanche test. At this time, the avalanche energy is E=EAS=1 / 2*L*I Dmax 2 *BV / (BV-VDD), this mode is defined as VDD ON mode.

[0037] The main problem with the above test method using VDD ON mode is: Figure 4 After the avalanche test is completed, the DC power supply VDD is still powered on. If the die of the device under test DUT is broken down during the avalanche test, the continuous power supply of the DC power supply VDD will cause the damage size on the front side of the die of the device under test DUT to increase, and at the same time cause the metal on the back side of the die of the device under test DUT to melt, thereby damaging the test machine and the wafer where the device under test is located.

[0038] Based on this, the present invention provides a single pulse avalanche breakdown energy test method and test circuit, which can control the DC power supply VDD to charge the energy storage circuit (such as inductor L, etc.) for a preset time (such as 2.5μs) after the avalanche test is completed while ensuring the original test process in the prior art, to ensure that the energy stored in the energy storage circuit is sufficient to reach the avalanche point of the device under test DUT, and then turn off the DC power supply VDD to reduce the size of the front burn point of the device under test DUT, while solving the problem of metal melting on the back of the device under test DUT. Obviously, the technical solution of the present invention can combine the advantages of the above two test methods, while avoiding the defects of the above two test methods, and is easy to implement and has low implementation cost.

[0039] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0040] Please refer to Figure 5 and Figure 6 An embodiment of the present invention provides a single pulse avalanche breakdown energy testing method and a testing circuit for implementing the single pulse avalanche breakdown energy testing method as described in the present invention.

[0041] The test circuit is as follows Figure 5 As shown, there is an energy storage circuit (for example, including an inductor L), a DC power supply VDD, a single pulse drive circuit VG, a power switch MOS_SW, a diode D0, a current limiting impedance RG and a current sensor ID. The positive electrode of the DC power supply VDD is connected to one end of the energy storage circuit (i.e., one end of the inductor L) through the power switch MOS_SW. The other end of the energy storage circuit (i.e., the other end of the inductor L) is connected to the drain D of the device under test DUT through the current sensor ID; the gate G of the device under test DUT is connected to one end of the single pulse drive circuit VG through the current limiting impedance RG, and the single pulse drive circuit VG controls the on-off between the source S and the drain D of the device under test DUT by outputting a corresponding single pulse signal. The source S of the device under test DUT, the other end of the single pulse drive circuit VG, the anode of the diode D0 and the negative electrode of the DC power supply VDD are all grounded. The cathode of the diode D0 is connected to the connection node of the inductor L and the power switch MOS_SW, so as to maintain the current in the loop in parallel with the device under test DUT.

[0042] In this embodiment, the power switch MOS_SW is turned on when the DC power supply VDD charges the energy storage circuit, and is turned off after a preset time t0 is delayed relative to the turn-off moment of the single pulse signal output by the single pulse drive circuit VG, so as to turn off the charging of the energy storage circuit by the DC power supply VDD. The power switch MOS_SW can be a MOS transistor, but in other embodiments of the present invention, the power switch MOS_SW can also be replaced by any suitable switch element or switch circuit such as a triode as long as the controllable switch function can be realized by software, and there is no limitation on this.

[0043] Optionally, the test circuit also includes a controller (not shown), which is a software controller or a controller combining software and hardware, which is coupled to the control end of the power switch MOS_SW, and is used to generate a corresponding control signal after a preset time t0 is delayed relative to the turn-off moment of the single pulse signal of the single pulse drive circuit VG, so as to control the power switch MOS_SW to turn off, thereby turning off the charging of the energy storage circuit by the DC power supply VDD.

[0044] The single pulse avalanche breakdown energy testing method provided in this embodiment includes the following steps:

[0045] First, connect the device under test (DUT) to Figure 5 In the test circuit shown, the device under test (DUT) is in the off state.

[0046] Before the test, the power switch MOS_SW is turned on, the drain-source voltage VDS of the device under test DUT is equal to the voltage of the DC power supply VDD, and there is no energy stored in the inductor L. At this time, the single-pulse drive circuit VG outputs a single-pulse signal (not shown) to control the device under test DUT to turn on, and the DC power supply VDD supplies the energy storage circuit (i.e. Figure 5 The inductor L in the circuit is charged until the current I flowing through the device under test DUT D Reach the set value.

[0047] Then, the single pulse driving circuit VG turns off the output of the single pulse signal to turn off the device under test DUT, and the energy storage circuit (i.e. Figure 5 The energy stored in the inductor L) is released through the device under test DUT, and the device under test DUT is subjected to an avalanche test. During this process, the DC power supply VDD is turned off after a preset time t0 relative to the turn-off time of the single pulse signal. Figure 6 and Figure 7 As shown, the energy storage circuit (i.e. Figure 5The energy stored in the inductor L) is sufficient to reach the avalanche point of the device under test DUT, so that the true avalanche value of the device under test DUT can be measured, and the size of the burn point on the front of the device under test DUT can be reduced, and the problem of metal melting on the back of the device under test DUT can be solved. Specifically, when the voltage across the device under test DUT reaches its breakdown voltage BV, the device under test DUT undergoes avalanche breakdown, and the current I D Until the energy stored in the inductor L is completely released, I D After decreasing to 0, the device under test DUT is turned off, and the drain-source voltage VDS of the device under test DUT is equal to the voltage of the DC power supply VDD again. In this process, the energy borne by the device under test DUT is EAS.

[0048] Among them, when the single-pulse driving circuit VG can turn off the output of the single-pulse signal, the delayed output of the control signal for turning off the power switch MOS_SW can be controlled by software. When the control signal is output after a preset time t0, the power switch MOS_SW can be turned off, thereby making the DC power supply VDD be turned off by a preset time t0 relative to the turn-off moment of the single-pulse signal, that is, the cancellation of the DC power supply VDD is delayed by the preset time t0 relative to the cancellation of the single-pulse signal.

[0049] It should be understood that the preset time t0 is closely related to the avalanche failure duration of the device under test DUT. Figure 5 The inductor L in the tank circuit is charged enough so that Figure 5 The energy stored in the inductor L) is sufficient to reach the avalanche point of the device under test DUT, and the preset time t0 is set as small as possible, thereby minimizing the size of the burn point on the front side of the device under test DUT as much as possible and avoiding the problem of metal melting on the back side of the device under test DUT as much as possible.

[0050] Usually, the avalanche failure time is very short, so the preset time t0 can be set to 1 to 3 times the avalanche failure time of the device under test DUT. As an example, the device under test DUT is an IGBT device, and its avalanche failure time is basically around 1μs, so the preset time can be set to be around 1μs to 3μs, for example, exactly equal to 2.5μs.

[0051] In addition, it should be understood that, in the present embodiment, the reason why the preset time t0 required for software control is adopted so that the DC power supply VDD is turned off after the preset time t0 relative to the turn-off moment of the single pulse signal is delayed is because: on the one hand, the avalanche test time of the device under test DUT (i.e., the avalanche failure duration) is generally very short, and the required preset time t0 (for example, about 2.5μs) will also be very short. The current hardware delay circuit technology is difficult to achieve such a short delay effect, and the power switch MOS_SW cannot be turned off at such a fast speed; on the other hand, even if there is technology that can achieve the delay of the preset time t0 by adding an additional hardware delay circuit, during the avalanche test, the added hardware delay circuit will also introduce more stray inductance, affecting the accuracy of the avalanche test.

[0052] In summary, the single pulse avalanche breakdown energy test method and test circuit of the present invention are easy to implement and have low cost. After the avalanche test is completed, the DC power supply is controlled to continue charging the energy storage circuit (such as an inductor) for a preset time (such as 2.5 μs) while ensuring the original test process in the prior art, and then the DC power supply is turned off to ensure that the energy stored in the energy storage circuit (such as an inductor) is sufficient to reach the avalanche point of the device under test, thereby being able to measure the true avalanche value of the device under test, while also being able to reduce the size of the front burn point of the device under test and solve the problem of metal melting on the back of the device under test. Therefore, the technical solution of the present invention combines the advantages of the two test methods in the prior art while avoiding the defects of the two test methods in the prior art.

[0053] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A single pulse avalanche breakdown energy test method, It is characterized in that include: First, the device under test is connected to a corresponding test circuit, wherein the test circuit has an energy storage circuit, a DC power supply, and a single pulse drive circuit, wherein the single pulse drive circuit is coupled to a control terminal of the device under test; Before the test, the single pulse driving circuit outputs a single pulse signal to control the device under test to be turned on, and the DC power supply charges the energy storage circuit until the current flowing through the device under test reaches a set value; Next, the single-pulse driving circuit turns off the output of the single-pulse signal to turn off the device under test. The energy stored in the energy storage circuit is released through the device under test, and an avalanche test is performed on the device under test. The DC power supply is turned off after a preset time delay relative to the turn-off moment of the single-pulse signal.

2. The single pulse avalanche breakdown energy testing method according to claim 1, It is characterized in that The preset time is realized through software control.

3. The single pulse avalanche breakdown energy testing method according to claim 1, It is characterized in that The preset time is 1 to 3 times the avalanche failure time of the device under test.

4. The single pulse avalanche breakdown energy testing method as claimed in claim 3, It is characterized in that The device under test is an IGBT device, and the preset time is 1 μs to 3 μs.

5. The single pulse avalanche breakdown energy testing method according to any one of claims 1 to 4, It is characterized in that The energy storage circuit includes an inductor.

6. A test circuit for implementing the single pulse avalanche breakdown energy test method according to any one of claims 1 to 5, It is characterized in that The test circuit has an inductor, a DC power supply and a single-pulse drive circuit. The inductor, the DC power supply and the corresponding device under test are connected in series in sequence. The single-pulse drive circuit is coupled to the control end of the device under test and controls the conduction of the device under test by outputting a single-pulse signal.

7. The test circuit as claimed in claim 6, It is characterized in that The test circuit further comprises a current limiting impedance, which is connected in series between the control terminal of the device under test and the single pulse driving circuit.

8. The test circuit as claimed in claim 6, It is characterized in that The test circuit further includes a diode, a cathode of the diode is coupled to a connection node between the inductor and the DC power supply, and an anode of the diode is grounded.

9. The test circuit as claimed in claim 6, It is characterized in that The test circuit also includes a power switch coupled to the DC power supply, and the power switch is turned on when the DC power supply charges the energy storage circuit, and is turned off after a preset time delay relative to the turn-off moment of the single pulse signal to turn off the DC power supply charging the energy storage circuit.

10. The test circuit as claimed in claim 9, It is characterized in that The test circuit further includes a controller coupled to a control terminal of the power switch, and configured to generate a corresponding control signal after a preset time delay relative to a turn-off moment of the single pulse signal, so as to control the power switch to turn off.

Images