A pole-pole tracking frequency compensation circuit for an LDO

Abstract

A pole-pole tracking frequency compensation circuit for an LDO, belonging to the field of semiconductor integrated circuits. It includes a current sampling unit circuit, a buffer stage unit circuit, a feedback unit circuit, a loop compensation unit circuit, and a current mirror circuit. Taking the output pole POUT as the main pole of the LDO and the power transistor input pole Pe as the secondary main pole, by inserting the circuit of the present invention between the error amplifier and the power transistor in the traditional LDO structure as a buffer stage, using the current sampling circuit to sample the output current, making the power transistor input pole Pe associated with the load current, and following the output pole to move in the same direction within the load current change range, forming a pole-pole tracking effect, so as to achieve the purpose of maintaining the stability of the feedback loop. At the same time, a feedback circuit is added to control the positional relationship between the two poles so that the power transistor input pole Pe is always outside the unity gain bandwidth. Thus, the primary and secondary relationships between the power transistor input pole and the output pole and the positional relationship between the two are solved, realizing the stability of the LDO under large load currents. It is widely applied to the field of LDOs with large load currents.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuits, and more particularly to the field of low dropout voltage power integrated circuits. Specifically, it relates to a pole-pole tracking frequency compensation circuit for an LDO. Background Art

[0002] The LDO (Low Dropout Linear Regulator), as an important part of the power management module, is widely used in various systems such as data acquisition, battery-powered, low-power, and industrial control to provide a stable and reliable power environment. Whether its output voltage is stable and not interfered by power supply and load mutations directly determines the overall performance of the system.

[0003] The LDO is essentially a stable negative feedback system. Ensuring the stability of the LDO loop feedback is the most basic requirement in circuit design. With the continuous development of system devices, the required output current of the LDO is getting larger and larger. This makes the load current move within a large range during operation, and the output pole POUT will also move within a large frequency range. This will greatly increase the difficulty of frequency compensation. Improper handling may even cause the instability of the entire system. There are two low-frequency poles in the LDO that affect the loop stability, namely the power transistor input pole Pe at the output end of the error amplifier and the output pole POUT. On the one hand, due to the increasing load current, a larger size of the power transistor is required, and the larger parasitic capacitance will push the power transistor input pole Pe to a lower frequency, making it difficult to compensate; on the other hand, the position of the output pole will change within a large frequency range with the change of the load current. As Figure 1 shown, the structural block diagram of the traditional LDO consists of a bandgap reference, an error amplifier, a resistor voltage division network, and a power transistor. In this circuit, at least two low-frequency poles will affect the stability of the entire feedback loop, one output pole POUT and one power transistor input pole Pe. How to handle the primary-secondary relationship and the position relationship of these two low-frequency poles is the key to ensuring the stability of the LDO loop. Especially in the high-current scenario, the load current will move within a large range, and the output pole POUT will also move within a large frequency range. Frequency compensation becomes very difficult or even impossible to compensate, severely restricting the output current of the LDO. In previous designs, by inserting a buffer stage between the error amplifier and the power transistor, the power transistor input pole is pushed to a higher frequency to achieve the compensation effect. However, as the load current continues to increase, such a buffer stage is obviously no longer applicable. Therefore, restricted by frequency compensation, it is very difficult to increase the load current in the traditional-structured LDO.

[0004] Therefore, the problem of how to handle the primary-secondary relationship between the power transistor input pole and the output pole and their positions, and ensure the stability of the loop within a large load current range is the focus of LDO design.

[0005] In view of this, the present invention is hereby proposed. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to solve the problem that it is difficult for the prior art to perform frequency compensation to improve the stability of the LDO under a large load current.

[0007] The concept of the present invention is: taking the output pole POUT as the main pole of the LDO, taking the input pole Pe of the power transistor as the secondary main pole, and inserting a pole-pole tracking frequency compensation circuit between the error amplifier and the power transistor in the traditional LDO structure as a buffer stage. As Figure 2 shown, the insertion position of the circuit of the present invention in the traditional LDO structure is respectively connected to the output end of the error amplifier and the input end of the power transistor as a buffer stage, which plays a role in making the input pole Pe of the power transistor follow the output pole POUT and move in the same direction within the load current change range. Different from the traditional buffer stage, the buffer stage proposed by the present invention uses a current sampling circuit to sample the output current, so that the input pole Pe of the power transistor is associated with the load current, and follows the output pole along the same direction within the load current change range, forming a pole-pole tracking effect, so as to achieve the purpose of maintaining the stability of the feedback loop. At the same time, a feedback circuit is added to control the position relationship between the two poles so that the input pole Pe of the power transistor is always outside the unity gain bandwidth, thus solving the primary-secondary relationship between the input pole and the output pole of the power transistor and the position relationship between the two.

[0008] For this reason, the present invention provides a pole-pole tracking frequency compensation circuit for an LDO, and the principle block diagram is as Figures 3-4 shown.

[0009] It includes: a buffer stage unit circuit, a feedback unit circuit, a current mirror circuit, a current sampling unit circuit, and a loop compensation unit circuit.

[0010] The input end of the buffer stage unit circuit is connected to the output end of the previous-stage error amplifier, and the output end is connected to the input end of the subsequent-stage power amplifier. The buffer stage unit circuit is used to generate an output pole that follows the change of the load current, realize the input pole-output pole tracking frequency compensation of the power transistor, and is connected to the input end of the power amplifier.

[0011] The input end of the feedback unit circuit is connected to the input end of the subsequent-stage power amplifier, and the output end is connected to the load end of the buffer stage unit circuit. The feedback unit circuit includes a current amplifier, which is used to compensate the current of the buffer stage unit circuit and realize the adjustment of the output pole of the buffer stage unit circuit.

[0012] The output terminal of the current mirror circuit is connected to the load terminal of the buffer stage unit circuit. The current mirror circuit is used to copy the sampling current of the current sampling unit circuit and provide a variable load for the buffer stage unit circuit.

[0013] The input terminal of the current sampling unit circuit is connected to the input terminal of the subsequent power amplifier, and the output terminal is connected to the output terminal of the buffer stage unit circuit and the constant current load terminal of the current mirror circuit. The current sampling unit circuit is used to sample the power amplifier current of the LDO in proportion;

[0014] The input terminal of the loop compensation unit circuit is connected to the input terminal of the subsequent power amplifier, and the output terminal is connected to the load terminal of the buffer stage unit circuit. The loop compensation unit circuit is used to perform frequency compensation on the loop formed by the buffer stage unit circuit and the feedback unit circuit.

[0015] The compensation algorithm of the pole-pole tracking frequency compensation circuit for LDO is as follows:

[0016] Taking the output pole POUT as the main pole of the LDO and the input pole Pe of the power transistor as the secondary main pole, by inserting the circuit of the present invention between the error amplifier and the power transistor in the traditional LDO structure as a buffer stage, and using the current sampling circuit to sample the output current, the input pole Pe of the power transistor is associated with the load current and moves in the same direction as the output pole within the load current change range, forming a pole-pole tracking effect, so as to achieve the purpose of maintaining the stability of the feedback loop. At the same time, a feedback circuit is added to control the position relationship between the two poles so that the input pole Pe of the power transistor is always outside the unity gain bandwidth. Thus, the primary and secondary relationship between the input pole and the output pole of the power transistor and the position relationship between the two are solved, and the stability of the LDO under large load currents is achieved. It is widely used in the frequency compensation design of LDOs with large load currents, improving the frequency stability of LDOs and simplifying the design cost.

[0017] The beneficial effects of the present invention are:

[0018] 1. Simple structure: It can be realized only by a simple current mirror, source follower and current amplifier. The design structure is simple, easy to implement, and occupies a small area.

[0019] 2. Improved stability: The primary and secondary relationship between the input pole and the output pole of the power transistor and the position relationship between the two are reasonably allocated, and the output pole can follow the input pole of the power transistor within a large current range, that is, pole-pole tracking, improving the loop stability.

[0020] The pole-pole tracking frequency compensation circuit for LDO of the present invention is widely used in the field of LDOs with large load currents. Description of the Drawings

[0021] Figure 1 It is a schematic diagram of the existing LDO structure.

[0022] Figure 2 It is a schematic diagram of the position of the circuit of the present invention in the block diagram of the existing LDO structure.

[0023] Figure 3 It is a schematic block diagram of the circuit principle of the present invention.

[0024] Figure 4 It is a schematic diagram of the circuit principle of the present invention.

[0025] Figure 5 It is a schematic diagram of the characteristic effects of the main pole and the secondary pole of the LDO under no load and heavy load after inserting the circuit of the present invention.

[0026] Figure 6 It is a schematic diagram of the characteristic effects of the gain curve and the phase curve of the LDO under no load and heavy load after inserting the circuit of the present invention. Detailed implementation manners

[0027] As Figures 4-6 shown, the pole-pole tracking frequency compensation circuit for an LDO is implemented as follows:

[0028] It includes PNP transistors Q1 and Q2 of the same type, NPN transistors Q3 and Q4 of the same type, PNP transistor Q5, current sources I1 and I2, current amplifier A1, resistor R1, and capacitor C1.

[0029] The buffer stage unit circuit includes a source follower composed of PNP transistor Q5 and a current source load I2 with variable current.

[0030] The feedback unit circuit includes current amplifier A1.

[0031] The current mirror circuit includes two NPN transistors Q3 and Q4 of the same type and current source I1.

[0032] The current sampling unit circuit includes two PNP transistors Q1 and Q2 of the same type.

[0033] The loop compensation unit circuit includes resistor R1 and capacitor C1, which are connected in series to form a Miller compensation circuit with zero adjustment.

[0034] The base of the PNP transistor Q5 serves as the input terminal of the pole-pole tracking frequency compensation circuit for the LDO, and is connected to the output terminal of the error amplifier of the conventional LDO structure. The emitter of the PNP transistor Q5 serves as the output terminal of the pole-pole tracking frequency compensation circuit for the LDO, and is connected to the input terminal of the power transistor Q6 of the conventional LDO structure; the base and collector of the same type of PNP transistor Q1 are short-circuited and connected to the base of the power transistor Q6, and the base of the same type of PNP transistor Q1 is connected to the base of the same type of PNP transistor Q2; the PNP transistor Q5 of the buffer stage unit circuit is connected to the base of the power transistor Q6 and the current source I2; the base and collector of the same type of NPN transistor Q3 are short-circuited and connected to the base of the same type of NPN transistor Q4, the current source I2, and the collector of the PNP transistor Q2. The collector of the same type of NPN transistor Q4 is connected to the collector of the NPN transistor Q5 of the buffer stage unit circuit, the input terminal of the current amplifier A1, and the capacitor C1 of the loop compensation unit circuit; the output terminal of the current amplifier A1 is connected to the input terminal of the power transistor Q6, and the loop compensation unit circuit includes a resistor R1 and a capacitor C1 connected in series, and the resistor R1 is connected to the input terminal of the power transistor Q6.

[0035] As Figure 4 shown, it is the pole-pole tracking circuit proposed by the present invention. As described above, the LDO has two low-frequency poles, one output pole POUT:

[0036]

[0037] where COUT is the load capacitor and ROUT is the load. In the high-current scenario, the load current moves within a large range, causing the output resistance ROUT to change significantly, resulting in POUT moving within a large frequency range;

[0038] Another pole Pe at the input of the power transistor:

[0039]

[0040] Among them, ROUT-EA is the output resistance of the error amplifier, and Ce is the parasitic capacitance of the power transistor. On the one hand, the output accuracy requirement of the LDO is continuously increasing, and the error amplifier improves the gain by increasing the output resistance ROUT-EA. On the other hand, as the output current increases, the power transistor size increases, resulting in an increase in the parasitic capacitance Ce. These two reasons make the input pole of the power transistor at a lower frequency and difficult to compensate in the high-current scenario. Based on the current problems, in the circuit of the present invention, the output pole POUT is set as the main pole, and the input pole Pe of the power transistor is set as the secondary pole, making the input pole Pe of the power transistor associated with the load current, moving in the same direction as the output pole within the load current change range, forming a pole-pole tracking effect, and always being outside 2.2 times the unity gain bandwidth.

[0041] In Figure 4 , the PNP transistor Q1 proportionally replicates and transmits the output current to the same type of PNP transistor Q2, and uses the current mirror Q3, Q4 to take the replicated current as the variable load of the source follower Q5. When the output current increases, the changing current △IOUT is transmitted through the current path of Q1→Q2→Q3→Q4→Q5, changing the load current of Q5, and further changing the output impedance of Q5; at the same time, a current amplifier A1 with a gain of A is added between the collector and emitter of Q5 as a feedback circuit to adjust the position of the input pole Pe of the power transistor. When designing, the current of the current source I2 is designed to be greater than the current of the current source I1. During operation, the excess current flows into the current amplifier A1, is amplified by A1 and fed back to the emitter of Q5, greatly increasing the current of the output stage and further reducing the output impedance. After calculation, the output resistance of Q5 at this time can be obtained:

[0042]

[0043] Among them, A is the gain of the current amplifier A1, gm is the transconductance of the transistor, and substituting it into the expression of the input pole Pe of the power transistor:

[0044]

[0045] Among them, VT is the thermal voltage constant, and α, β are the current replication coefficients. Due to the addition of the feedback circuit, it can be seen from the expression of the pole Pe that by changing the gain A of the current amplifier A1, the positional relationship between the two poles can be controlled, so that the input pole Pe of the power transistor is always outside the unity gain bandwidth, ensuring the stability of the loop. From the expression of the output pole POUT:

[0046]

[0047] It is obtained that:

[0048] P e ∝POUT。

[0049] As Figure 5 shown, it is a schematic diagram of the main pole and the secondary pole of the LDO inserted into the circuit of the present invention under no load and heavy load. It can be seen that during the process of the load converting from no load to heavy load, as the load current increases,

[0050] the input pole Pe of the power transistor follows the output pole POUT and moves in the same direction, forming a pole-pole tracking effect, achieving the circuit design goal.

[0051] As Figure 6 shown, it is a schematic diagram of the gain curve and the phase curve of the LDO inserted into the circuit of the present invention under no load and heavy load. It can be seen that during the process of the load converting from no load to heavy load, as the load current increases, the input pole Pe of the power transistor follows the output pole POUT and moves in the same direction, and is always outside the unity gain bandwidth, and the system always remains stable.

[0052] Finally, it should be noted that the above embodiments are only examples given for clear illustration. The present invention includes but is not limited to the above embodiments, and it is not necessary and impossible to enumerate all implementation manners here. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. All implementation manners that meet the requirements of the present invention fall within the protection scope of the present invention.

Claims

1. A pole-pole tracking frequency compensation circuit for an LDO, characterized in that: It includes a buffer stage unit circuit, a feedback unit circuit, a current mirror circuit, a current sampling unit circuit and a loop compensation unit circuit; The input end of the buffer stage unit circuit is connected to the output end of the previous-stage error amplifier, and the output end is connected to the input end of the subsequent-stage power amplifier, generating an output pole that follows the change of the load current to compensate the tracking frequency of the input pole - output pole of the power transistor; The input end of the feedback unit circuit is connected to the input end of the subsequent-stage power amplifier, and the output end is connected to the load end of the buffer stage unit circuit. The feedback unit circuit includes a current amplifier to compensate the current of the buffer stage unit circuit and adjust the output pole of the buffer stage unit circuit; The output end of the current mirror circuit is connected to the load end of the buffer stage unit circuit to copy the sampling current of the current sampling unit circuit and provide a variable load for the buffer stage unit circuit; The input end of the current sampling unit circuit is connected to the input end of the subsequent-stage power amplifier, and the output end is connected to the output end of the buffer stage unit circuit and the constant-current load end of the current mirror circuit to sample the power amplifier current of the LDO in proportion; The input end of the loop compensation unit circuit is connected to the input end of the subsequent-stage power amplifier, and the output end is connected to the load end of the buffer stage unit circuit to perform frequency compensation on the loop formed by the buffer stage unit circuit and the feedback unit circuit; The frequency compensation circuit includes: PNP transistors Q1 and Q2 of the same type, NPN transistors Q3 and Q4 of the same type, PNP transistor Q5, current sources I1 and I2, current amplifier A1, resistor R1, and capacitor C1; The buffer stage unit circuit includes a source follower composed of PNP transistor Q5 and a current source load I2 with variable current; The feedback unit circuit includes current amplifier A1; The current mirror circuit includes two NPN transistors Q3 and Q4 of the same type and current source I1; The current sampling unit circuit includes two PNP transistors Q1 and Q2 of the same type; The loop compensation unit circuit includes resistor R1 and capacitor C1, which are connected in series to form a Miller compensation circuit with zero adjustment; The base of Q5 is connected to the output end of the error amplifier of the LDO. The emitter of Q5 is connected to the negative pole of current source I2, the base of Q1, the collector of Q1, the base of Q2, one end of R1, the output end of A1, and the base of Q6. The collector of Q5 is connected to the collector of Q4, the input end of A1, and one end of C1; the other end of C1 is connected to the other end of R1; the emitter of Q4 is connected to the emitter of Q3, the base of Q4 is connected to the base of Q3, the collector of Q3, the collector of Q2, and the negative pole of current source I1; the positive pole of current source I1 is connected to the emitter of Q2, the positive pole of current source I2, the emitter of Q1, and the emitter of Q6.

2. The pole-pole tracking frequency compensation circuit for an LDO according to claim 1, characterized in that: The main pole and the secondary pole are outside 2.2 times the unity gain bandwidth.

3. The compensation algorithm of the pole-pole tracking frequency compensation circuit for an LDO according to claim 1, characterized in that: The output pole POUT is used as the main pole of the LDO, and the input pole Pe of the power transistor is used as the secondary main pole; Insert the circuit described in claim 1 between the error amplifier and the power transistor in the LDO structure as a buffer stage; The output current is sampled by the current sampling circuit, so that the input pole Pe of the power transistor is associated with the load current and moves in the same direction along with the output pole within the load current variation range, forming a pole-pole tracking effect, thereby achieving the purpose of maintaining the stability of the feedback loop; A feedback circuit is added to control the positional relationship between the two poles, so that the input pole Pe of the power transistor is always outside the unity gain bandwidth.

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