Data processing method, device, electronic device and storage medium

Abstract

The present application provides a data processing method, device, electronic device and storage medium, the method comprising: after a first data link completes data transmission, determining whether there is a first memory space allocated for the first data link in the cache; if so, updating the traffic information of the first data link stored in the first memory space to the traffic information after the first data link completes data transmission. In the present application, memory space is allocated for the data link in advance in the cache of the FPGA chip. After the data link completes data transmission, if the data link has memory space in the cache, the data link directly accesses the cache and updates the traffic information of this data transmission to the cache, reducing the number of times the data link accesses the DDR, saving the bandwidth of the DDR, and thus improving the data transmission speed of the FPGA chip.

Description

Technical Field

[0001] The present application relates to the field of chip data processing, and more specifically, to a data processing method, device, electronic device, and storage medium. Background Art

[0002] With the rapid development of FPGA chips, users are increasingly demanding higher data transmission speeds. During data transmission, both the data link and the CPU (Central Processing Unit) frequently access DDR (Double Data Rate Synchronous Dynamic Random Access Memory). However, due to the limited bandwidth of DDR, it is difficult to support the bandwidth requirements of high-speed data transmission, thus limiting the data transmission speed of FPGA chips. Summary of the Invention

[0003] The purpose of the embodiments of the present application is to provide a data processing method, device, electronic device and storage medium to alleviate the problem of insufficient DDR bandwidth in FPGA chips and improve the data transmission speed of FPGA chips.

[0004] In a first aspect, the present application provides a data processing method, which is applied to an FPGA chip, wherein the FPGA chip includes a cache and a data path, and the cache is connected to the data path. The method includes: when a first data link completes data transmission, determining whether there is a first memory space allocated for the first data link in the cache, wherein the first data link is a transmission link in the data path, and the first memory space is used to store traffic information of the first data link; if so, updating the traffic information of the first data link stored in the first memory space to the traffic information after the first data link completes data transmission.

[0005] In this implementation, memory space is pre-allocated for the data link in the FPGA chip's cache. After the data link completes data transmission, if the cache already has memory space for the data link, the data link directly accesses the cache and updates the traffic information for this data transmission. This reduces the number of DDR accesses required by the data link, conserving DDR bandwidth and improving the data transmission speed of the FPGA chip.

[0006] In an optional embodiment, before determining whether there is a first memory space allocated for the first data link in the cache, the method includes: generating a first ID for the first data link when establishing the first data link; and allocating a memory space in the cache as the first memory space according to the first ID.

[0007] In the above implementation process, a unique ID is assigned to each data link. The read and write addresses of each data link in the cache are the corresponding IDs, thereby ensuring that the read and write addresses of each data link in the cache do not conflict.

[0008] In an optional embodiment, the FPGA chip also includes a double-rate synchronous dynamic random access memory. Before determining whether there is a first memory space allocated for the first data link in the cache, the method includes: generating a first ID for the first data link when establishing the first data link; and allocating a memory space in the cache or the double-rate synchronous dynamic random access memory as the first memory space based on the first ID.

[0009] In the above implementation process, considering that the number of data links in the FPGA may be large, in order to balance resource utilization and data transmission efficiency, the memory space corresponding to some data links is set in the cache, and the memory space corresponding to the remaining data links is set in the DDR.

[0010] In an optional embodiment, the cache includes multiple memory spaces, each memory space corresponds to the ID of a data link, and the address of each memory space is the first N bit value of the ID of the data link corresponding to the memory space. The method of allocating a memory space in the cache or the double-rate synchronous dynamic random access memory as the first memory space based on the first ID includes: when there is no memory space in the cache whose address is the same as the first N bit value of the first ID, allocating a memory space in the cache as the first memory space; when there is a memory space in the cache whose address is the same as the first N bit value of the first ID and the ID of the data link corresponding to the memory space is different from the first ID, allocating a memory space in the double-rate synchronous dynamic random access memory as the first memory space.

[0011] In the above implementation, when allocating memory space, the first N bits of the first ID are used to determine whether there is free memory space in the cache. If so, a memory space is allocated in the cache as the first memory space. If not, a memory space is allocated in the DDR as the first memory space. This approach effectively avoids memory space conflicts.

[0012] In an optional embodiment, the cache includes multiple memory spaces, each memory space corresponds to the ID of a data link, and the address of each memory space is the first N bit value of the ID of the data link corresponding to the memory space. The method of allocating a memory space in the cache or the double-rate synchronous dynamic random access memory as the first memory space based on the first ID includes: when there is no memory space in the cache whose address is the same as the first N bit value of the first ID, allocating a memory space in the cache as the first memory space; when there is a memory space in the cache whose address is the same as the first N bit value of the first ID and the ID of the data link corresponding to the memory space is different from the first ID, allocating a second memory space in the double-rate synchronous dynamic random access memory to store the traffic data of the data link corresponding to the memory space, and using the memory space in the cache as the first memory space.

[0013] In the above implementation process, when allocating memory space, when a memory space conflict occurs, a second memory space is allocated in the double-rate synchronous dynamic random access memory to store the traffic data originally stored in the cache, and then the memory space in the cache is allocated to the first data link, thereby effectively avoiding memory space conflicts.

[0014] In an optional embodiment, the method also includes: obtaining current traffic information stored in a first memory space corresponding to the first data link; if the current traffic information stored in the first memory space is the same as the traffic information corresponding to the first data link pre-saved in the CPU, closing the first data link and clearing the first memory space corresponding to the first data link; if the current traffic information stored in the first memory space is different from the traffic information corresponding to the first data link pre-saved in the CPU, updating the traffic information corresponding to the first data link pre-saved in the CPU to the current traffic information stored in the first memory space.

[0015] In the above implementation process, the above method is used to realize dynamic monitoring of the data link, maintain the data link in a working state, and close the data link that has not sent data for a long time.

[0016] In an optional implementation, the traffic information of the first data link includes packet statistics information and byte statistics information.

[0017] In a second aspect, the present application provides a data processing device, which is configured on an FPGA chip, wherein the FPGA chip includes a cache and a data path, and the cache is connected to the data path. The device includes: a judgment module, which is used to judge whether there is a first memory space allocated for the first data link in the cache after the first data link completes data transmission, wherein the first data link is a transmission link in the data path, and the first memory space is used to store traffic information of the first data link; an update module, which is used to update the traffic information of the first data link stored in the first memory space to the traffic information after the first data link completes data transmission when there is a first memory space allocated for the first data link in the cache.

[0018] In an optional embodiment, the device further includes an allocation module, configured to generate a first ID for the first data link when the first data link is established; and allocate a memory space in the cache as the first memory space according to the first ID.

[0019] In an optional embodiment, the FPGA chip also includes a double-rate synchronous dynamic random access memory, and the allocation module is used to generate a first ID for the first data link when establishing the first data link; and allocate a memory space in the cache or the double-rate synchronous dynamic random access memory as the first memory space according to the first ID.

[0020] In an optional embodiment, the cache includes multiple memory spaces, each memory space corresponds to the ID of a data link, and the address of each memory space is the first N bit value of the ID of the data link corresponding to the memory space. The allocation module is specifically used to allocate a memory space in the cache as the first memory space when there is no memory space in the cache whose address is the same as the first N bit value of the first ID; when there is a memory space in the cache whose address is the same as the first N bit value of the first ID and the ID of the data link corresponding to the memory space is different from the first ID, allocate a memory space in the double-rate synchronous dynamic random access memory as the first memory space.

[0021] In an optional embodiment, the cache includes multiple memory spaces, each memory space corresponds to the ID of a data link, and the address of each memory space is the first N bit value of the ID of the data link corresponding to the memory space. The allocation module is specifically used to allocate a memory space in the cache as the first memory space when there is no memory space in the cache whose address is the same as the first N bit value of the first ID; when there is a memory space in the cache whose address is the same as the first N bit value of the first ID and the ID of the data link corresponding to the memory space is different from the first ID, allocate a second memory space in the double-rate synchronous dynamic random access memory to store the traffic data of the data link corresponding to the memory space, and use the memory space in the cache as the first memory space.

[0022] In an optional embodiment, the device also includes a data link control module for obtaining current traffic information stored in a first memory space corresponding to the first data link; if the current traffic information stored in the first memory space is the same as the traffic information corresponding to the first data link pre-saved in the CPU, the first data link is closed and the first memory space corresponding to the first data link is cleared; if the current traffic information stored in the first memory space is different from the traffic information corresponding to the first data link pre-saved in the CPU, the traffic information corresponding to the first data link pre-saved in the CPU is updated to the current traffic information stored in the first memory space.

[0023] In an optional implementation, the traffic information of the first data link includes packet statistics information and byte statistics information.

[0024] In a third aspect, the present application provides an electronic device comprising: a processor, a memory and a bus; the processor and the memory communicate with each other through the bus; the memory stores program instructions that can be executed by the processor, and the processor calls the program instructions to execute a method as described in any of the foregoing embodiments.

[0025] In a fourth aspect, the present application provides a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are read and executed by a computer, the method as described in any one of the aforementioned embodiments is executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0027] Figure 1 A flowchart of a data processing method provided in an embodiment of the present application;

[0028] Figure 2 A data interaction diagram of an FPGA chip provided in an embodiment of the present application;

[0029] Figure 3 A structural block diagram of a data processing device provided in an embodiment of the present application;

[0030] Figure 4 This is a schematic structural diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0032] The embodiments of the present application provide a data processing method, device, electronic device, and storage medium to alleviate the problem of insufficient DDR bandwidth in FPGA chips and improve the data transmission speed of FPGA chips.

[0033] The following is an introduction to the data processing method provided in this application.

[0034] See also Figure 1 , Figure 1 This is a flowchart of a data processing method provided in an embodiment of the present application. The data processing method is applied to an FPGA chip. The FPGA chip includes a cache and a data path. The cache is connected to the data path. The data processing method may include the following contents:

[0035] Step 101: After the first data link completes data transmission, it is determined whether there is a first memory space allocated for the first data link in the cache.

[0036] Step 102: If it exists, the flow information of the first data link stored in the first memory space is updated to the flow information after the first data link completes data transmission.

[0037] To facilitate understanding of this solution, we first introduce the working mode between the CPU, DDR, and data link in the current FPGA chip.

[0038] During FPGA operation, multiple data links are generated for data transmission. When a data link is established, an address request is sent to the CPU. After receiving the address, the CPU allocates a memory address in the DDR for the data link and records the corresponding relationship between the memory address and the data link.

[0039] After a data link is established, when data is transmitted on a data link, the traffic information (such as data length, byte count, etc.) of this data transmission will be written back to the DDR, which will save this traffic information. And while the data link connection is maintained, as the data link continues to transmit data, the traffic information will be updated in real time.

[0040] During this process, the data link frequently accesses the DDR and updates traffic information. However, the bandwidth of DDR is relatively limited and cannot support the bandwidth requirements of high-speed data transmission, thus limiting the data transmission speed of the FPGA chip.

[0041] To address the above-mentioned problem, an embodiment of the present application provides a data processing method. When a first data link completes data transmission, a determination is made as to whether a first memory space allocated for the first data link exists in a cache. If the first memory space exists in the cache, the flow information of the first data link stored in the first memory space is updated to the flow information after the first data link completes data transmission.

[0042] Specifically, if Figure 2 As shown in the figure, the CPU pre-allocates memory space for the data link in the FPGA chip's cache. After the data link completes data transmission, if the data link has memory space in the cache, the data link directly accesses the cache and updates the traffic information of this data transmission. This reduces the number of times the data link accesses the DDR, saves DDR bandwidth, and thus improves the data transmission speed of the FPGA chip.

[0043] Data link traffic information can be packet statistics, byte statistics, or both, and this application does not specifically limit this. Packet statistics represent the number of data packets sent after a data link transmission. Byte statistics represent the number of bytes sent after a data link transmission.

[0044] The above steps 101-102 are the interaction process between the first data link and the cache during data transmission on the data link. When establishing the first data link, the CPU will allocate a first memory space for the data link. The following describes how to allocate the first memory space.

[0045] As an optional implementation, before step 101, the data processing method provided in the embodiment of the present application further includes:

[0046] A1: When the first data link is established, a first ID is generated for the first data link.

[0047] A2: Allocate a memory space in the cache according to the first ID as the first memory space.

[0048] In the embodiment of the present application, when the first data link is established, an address request is sent to the CPU. After receiving the address request sent by the first data link, the CPU first generates a unique ID (i.e., a first ID) for the first data link. The first ID is a unique identifier of the first data link in the FPGA chip. Then, based on the first ID, a memory space is allocated in the cache as the first memory space.

[0049] Specifically, the first ID can be a 32-bit value, which is used as the read and write address of the first memory space. It is understood that the CPU assigns a unique 32-bit ID to each data link. The read and write address of each data link in the cache is the corresponding 32-bit ID, thereby ensuring that the read and write addresses of each data link in the cache do not conflict.

[0050] As an optional implementation, before step 101, the data processing method provided in the embodiment of the present application further includes:

[0051] B1: When the first data link is established, a first ID is generated for the first data link.

[0052] B2: Allocate a memory space in the cache or the DDR SDRAM according to the first ID as the first memory space.

[0053] In the embodiment of the present application, step B1 is implemented in the same manner as the aforementioned step A1, and will not be described here in detail to keep the description concise.

[0054] After the CPU assigns the first ID to the first data link, considering that the number of data links in the FPGA may be large, in order to balance resource utilization and data transmission efficiency, the memory space corresponding to some data links is set in the cache, and the memory space corresponding to the remaining data links is set in the DDR.

[0055] In some implementations, memory space is preferentially allocated in the cache for the data link. Specifically, a first threshold is set. When the amount of memory space in the cache is less than the first threshold, a memory space is allocated in the cache as the first memory space. When the amount of memory space in the cache is greater than the first threshold, a memory space is allocated in the DDR as the first memory space.

[0056] In other implementations, it is determined to allocate a memory space in the cache or in the DDR as the first memory space according to bit information in the first ID corresponding to the first data link.

[0057] As an optional implementation, the above step B1 may include the following steps:

[0058] C1: When there is no memory space in the cache whose address is identical to the first N bits of the first ID, a memory space is allocated in the cache as the first memory space.

[0059] C2: When there is a memory space in the cache whose address is the same as the first N bits of the first ID and the ID of the data link corresponding to the memory space is different from the first ID, a memory space is allocated in the double data rate synchronous dynamic random access memory as the first memory space.

[0060] In the embodiment of the present application, the cache provides 2N memory spaces for storing the traffic information of each data link. The address of each memory space is the same as the first N bits of the ID of the corresponding data link.

[0061] For example, if the data link ID is a 32-bit number and N is set to 8, the cache provides 256 memory spaces for storing traffic information for each data link. Assume that the first 8 bits of a data link ID are 00000001, and the address of the cache memory space for this data link is 00000001. For another data link ID, if the first 8 bits are 00000011, the address of the cache memory space for this data link is 00000011.

[0062] When there are a large number of data links, the first N bits of two data links may be the same. Therefore, when the CPU allocates memory space for the first data link based on the first ID corresponding to the first data link, it first determines whether there is a memory space in the cache whose address has the same first N bit values ​​as the first N bit values ​​of the first ID. If there is no memory space in the cache whose address has the same first N bit values ​​as the first N bit values ​​of the first ID, it means that the memory space corresponding to the first N bit values ​​of the first ID in the cache has not been allocated to other data links. Therefore, the memory space corresponding to the first N bit values ​​of the first ID is allocated to the first data link.

[0063] If the first N bit values ​​of the address of a memory space in the cache are the same as the first N bit values ​​of the first ID, it means that the memory space corresponding to the first N bit values ​​of the first ID in the cache has been allocated to other data links (for the convenience of subsequent explanation, this data link is referred to as the second data link). According to the above introduction, the first N bit values ​​of the second ID corresponding to the second data link are the same as the first N bit values ​​of the second ID corresponding to the first data link, and the first N bit values ​​of the two data links will point to the same memory space. If this memory space is used as the first memory space of the first data link, after the first data link transmits data, the flow information of the second data link in this memory space will be updated to the flow information of the first data link, resulting in data errors. Therefore, in order to avoid memory space conflicts, this memory space is still used as the memory space of the second data link, and a memory space is allocated in the DDR as the first memory space.

[0064] In the embodiment of the present application, when allocating memory space, a determination is made based on the first N bits of the first ID to determine whether there is free memory space in the cache. If so, a memory space is allocated in the cache as the first memory space. If not, a memory space is allocated in the DDR as the first memory space. This approach effectively avoids memory space conflicts.

[0065] As another optional implementation, the above step B1 may include the following steps:

[0066] D1: when there is no memory space in the cache whose address is the same as the first N bits of the first ID, allocate a memory space in the cache as the first memory space;

[0067] D2: When there is a memory space in the cache whose address is the same as the first N bits of the first ID and the ID of the data link corresponding to the memory space is different from the first ID, a second memory space is allocated in the double-rate synchronous dynamic random access memory to store the traffic data of the data link corresponding to the memory space, and the memory space in the cache is used as the first memory space.

[0068] In the embodiment of the present application, similar to the aforementioned steps C1 and C2, the cache provides 2N memory spaces for storing the traffic information of each data link. The address of each memory space is the same as the first N bits of the ID of the corresponding data link.

[0069] When allocating memory space to the first data link based on the first ID corresponding to the first data link, the CPU first determines whether there is a memory space in the cache whose address has the same first N bit values ​​as the first N bit values ​​of the first ID. If there is no memory space in the cache whose address has the same first N bit values ​​as the first N bit values ​​of the first ID, it indicates that the memory space corresponding to the first N bit values ​​of the first ID in the cache has not been allocated to another data link. Therefore, the memory space corresponding to the first N bit values ​​of the first ID is allocated to the first data link.

[0070] If the first N bits of the address of a memory space in the cache are the same as the first N bits of the first ID, it means that the memory space corresponding to the first N bits of the first ID in the cache has been allocated to another data link (for the convenience of subsequent explanation, this data link is referred to as the second data link). To avoid memory space conflicts, a second memory space is allocated in the DDR and the traffic information of the second data link is stored in the second memory space. The memory space corresponding to the first N bits of the first ID in the cache is then used as the memory space of the first data link (i.e., the first memory space).

[0071] In an embodiment of the present application, when allocating memory space, when a memory space conflict occurs, a second memory space is allocated in the double-rate synchronous dynamic random access memory to store the traffic data originally stored in the cache, and then the memory space in the cache is allocated to the first data link.

[0072] Furthermore, the data processing method provided in the embodiment of the present application also includes:

[0073] E1: Acquire current traffic information stored in a first memory space corresponding to a first data link.

[0074] E2: If the current flow information stored in the first memory space is identical to the flow information corresponding to the first data link pre-stored in the CPU, close the first data link and clear the first memory space corresponding to the first data link.

[0075] E3: If the current flow information stored in the first memory space is different from the flow information corresponding to the first data link pre-stored in the CPU, the flow information corresponding to the first data link pre-stored in the CPU is updated to the current flow information stored in the first memory space.

[0076] In the embodiment of this application, Figure 2 As shown, after the CPU allocates memory for each data link, in order to determine whether to maintain the connection of each data link, it sends a read request (corresponding to Figure 2req1 in), prepare to obtain the flow information of each data, and compare the flow information read twice before and after. When sending a read request, the ID corresponding to the data link (corresponding to Figure 2 After receiving the read request, the DDR determines the memory address corresponding to the ID of the read request, obtains the traffic information from the memory address, and sends it to the CPU.

[0077] If the traffic information is stored in the cache, DDR sends a read request to the cache (corresponding to Figure 2 req2), obtain the corresponding traffic information from the cache and send it to the CPU; if the traffic information is stored in the DDR, the DDR directly sends the corresponding traffic information to the CPU.

[0078] If the traffic information read twice changes, the data link is considered to be still transmitting data, so the data link is maintained and the previously saved traffic information corresponding to the data link is updated with the newly obtained traffic information. Otherwise, if the traffic information read twice does not change, the data link is considered to have stopped working and a command is issued to shut down the data link.

[0079] In the embodiment of the present application, the above-mentioned method is used to realize dynamic monitoring of the data link, maintain the data link in a working state, and close the data link that has not sent data for a long time.

[0080] Based on the same inventive concept, the present application also provides a data processing device. Figure 3 , Figure 3 This is a structural block diagram of a data processing device provided in an embodiment of the present application. The data processing device 300 is configured on an FPGA chip. The FPGA chip includes a cache and a data path. The cache is connected to the data path. The data processing device 300 may include:

[0081] a determination module 301 configured to determine, after a first data link completes data transmission, whether there is a first memory space allocated for the first data link in the cache, wherein the first data link is a transmission link in the data path, and the first memory space is used to store traffic information of the first data link;

[0082] The updating module 302 is configured to update the flow information of the first data link stored in the first memory space to the flow information after the first data link completes data transmission when there is a first memory space allocated for the first data link in the cache.

[0083] In an optional embodiment, the device further includes an allocation module, configured to generate a first ID for the first data link when the first data link is established; and allocate a memory space in the cache as the first memory space according to the first ID.

[0084] In an optional embodiment, the FPGA chip also includes a double-rate synchronous dynamic random access memory, and the allocation module is used to generate a first ID for the first data link when establishing the first data link; and allocate a memory space in the cache or the double-rate synchronous dynamic random access memory as the first memory space according to the first ID.

[0085] In an optional embodiment, the cache includes multiple memory spaces, each memory space corresponds to the ID of a data link, and the address of each memory space is the first N bit value of the ID of the data link corresponding to the memory space. The allocation module is specifically used to allocate a memory space in the cache as the first memory space when there is no memory space in the cache whose address is the same as the first N bit value of the first ID; when there is a memory space in the cache whose address is the same as the first N bit value of the first ID and the ID of the data link corresponding to the memory space is different from the first ID, allocate a memory space in the double-rate synchronous dynamic random access memory as the first memory space.

[0086] In an optional embodiment, the cache includes multiple memory spaces, each memory space corresponds to the ID of a data link, and the address of each memory space is the first N bit value of the ID of the data link corresponding to the memory space. The allocation module is specifically used to allocate a memory space in the cache as the first memory space when there is no memory space in the cache whose address is the same as the first N bit value of the first ID; when there is a memory space in the cache whose address is the same as the first N bit value of the first ID and the ID of the data link corresponding to the memory space is different from the first ID, allocate a second memory space in the double-rate synchronous dynamic random access memory to store the traffic data of the data link corresponding to the memory space, and use the memory space in the cache as the first memory space.

[0087] In an optional embodiment, the device also includes a data link control module for obtaining current traffic information stored in a first memory space corresponding to the first data link; if the current traffic information stored in the first memory space is the same as the traffic information corresponding to the first data link pre-saved in the CPU, the first data link is closed and the first memory space corresponding to the first data link is cleared; if the current traffic information stored in the first memory space is different from the traffic information corresponding to the first data link pre-saved in the CPU, the traffic information corresponding to the first data link pre-saved in the CPU is updated to the current traffic information stored in the first memory space.

[0088] In an optional implementation, the traffic information of the first data link includes packet statistics information and byte statistics information.

[0089] See also Figure 4 , Figure 4 This is a schematic diagram of the structure of an electronic device 400 according to an embodiment of the present application. The electronic device 400 includes: at least one processor 401, at least one communication interface 402, at least one memory 403, and at least one bus 404. The bus 404 is used to realize direct connection and communication between these components, the communication interface 402 is used to communicate signaling or data with other node devices, and the memory 403 stores machine-readable instructions executable by the processor 401. When the electronic device 400 is running, the processor 401 communicates with the memory 403 via the bus 404, and the computer-readable instructions are called by the processor 401 to execute the data processing method described above.

[0090] The processor 401 can be an integrated circuit chip with signal processing capabilities. The above-mentioned processor 401 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0091] The memory 403 may include but is not limited to random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0092] In addition, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a computer, the steps of the data processing method in the above embodiment are executed.

[0093] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interface, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0094] In addition, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0095] Furthermore, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0096] It should be noted that if the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0097] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0098] The above description is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, various modifications and variations of the present application are possible. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A data processing method, characterized in that: The method is applied to an FPGA chip, the FPGA chip including a cache, a data path, and a double-rate synchronous dynamic random access memory. The cache includes multiple memory spaces, each memory space corresponds to an ID of a data link, and the address of each memory space is the first N bits of the ID of the data link corresponding to the memory space. The cache is connected to the data path. The method includes: When establishing a first data link, generating a first ID for the first data link, wherein the first data link is a transmission link in the data path; Allocating a memory space in the cache or the double rate synchronous dynamic random access memory as a first memory space according to the first ID, wherein the first memory space is used to store traffic information of the first data link; After the first data link completes data transmission, determining whether the first memory space allocated for the first data link exists in the cache; If so, updating the flow information of the first data link stored in the first memory space to the flow information after the first data link completes data transmission; The allocating a memory space in the cache or the DDR DRAM as the first memory space according to the first ID includes: When there is no memory space in the cache whose address is the same as the first N bits of the first ID, allocating a memory space in the cache as the first memory space; When there is a memory space in the cache whose address is the same as the first N bit values ​​of the first ID and the ID of the data link corresponding to the memory space is different from the first ID, a memory space is allocated in the double-speed synchronous dynamic random access memory as the first memory space, or a second memory space is allocated in the double-speed synchronous dynamic random access memory to store the traffic data of the data link corresponding to the memory space, and the memory space in the cache is used as the first memory space.

2. The method according to claim 1, characterized in that The method further comprises: Obtaining current traffic information stored in a first memory space corresponding to the first data link; If the current traffic information stored in the first memory space is identical to the traffic information corresponding to the first data link pre-stored in the CPU, closing the first data link and clearing the first memory space corresponding to the first data link; If the current flow information stored in the first memory space is different from the flow information corresponding to the first data link pre-stored in the CPU, the flow information corresponding to the first data link pre-stored in the CPU is updated to the current flow information stored in the first memory space.

3. The method according to any one of claims 1-2, characterized in that The traffic information of the first data link includes packet statistics information and byte statistics information.

4. A data processing device, characterized in that: The device is configured on an FPGA chip, the FPGA chip including a cache, a data path, and a double-rate synchronous dynamic random access memory. The cache includes multiple memory spaces, each memory space corresponds to an ID of a data link, and the address of each memory space is the first N bits of the ID of the data link corresponding to the memory space. The cache is connected to the data path. The device includes: an allocation module, configured to generate a first ID for a first data link when establishing the first data link, wherein the first data link is a transmission link in the data path; allocate a memory space in the cache or the double data rate synchronous dynamic random access memory as a first memory space according to the first ID, wherein the first memory space is used to store traffic information of the first data link; a determination module, configured to determine whether the first memory space allocated for the first data link exists in the cache after the first data link completes data transmission; an updating module, configured to update the flow information of the first data link stored in the first memory space to the flow information after the first data link completes data transmission, when a first memory space allocated for the first data link exists in the cache; Among them, the allocation module is specifically used to allocate a memory space in the cache as the first memory space when there is no memory space in the cache whose address is the same as the first N bit values ​​of the first ID; when there is a memory space in the cache whose address is the same as the first N bit values ​​of the first ID and the ID of the data link corresponding to the memory space is different from the first ID, allocate a memory space in the double-rate synchronous dynamic random access memory as the first memory space, or allocate a second memory space in the double-rate synchronous dynamic random access memory to store the traffic data of the data link corresponding to the memory space, and use the memory space in the cache as the first memory space.

5. An electronic device, characterized in that: include: processor, memory, and bus; The processor and the memory communicate with each other via the bus; The memory stores program instructions that can be executed by the processor, and the processor can execute the method according to any one of claims 1 to 3 by calling the program instructions.

6. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer program instructions, and when the computer program instructions are read and executed by a computer, the method according to any one of claims 1 to 3 is executed.

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