Write-back clear command used to perform scans and reads in a memory device

Abstract

This application relates to a write-back clear command for performing scans and reads in a memory device. One method includes: receiving a write-back clear command from a processing device by control logic of the memory device; in response to the write-back clear command, causing a page buffer to perform a dual-gated read operation on a first memory cell configured as a single-level cell, the dual-gated read operation including soft gating at a first threshold voltage and hard gating at a second threshold voltage, the first threshold voltage and the second threshold voltage being sensed between threshold voltage distributions of the first memory cell; causing the page buffer to determine the number of bit values ​​detected within a threshold voltage range between the first and second threshold voltages within the threshold voltage distribution; and in response to the number of bit values ​​not satisfying a threshold criterion, causing data in the first memory cell to be written back to a second memory cell configured as a higher-level cell without intervention from the processing device.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to write-back clear commands for performing scans and reads in a memory device. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. These memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] One embodiment of this disclosure provides a memory device comprising: one or more memory cell arrays including first memory cells configured as single-level cell memory and second memory cells configured as higher-level cell memory; one or more page buffers coupled to the one or more memory cell arrays; and control logic operably coupled to the one or more page buffers, the control logic performing operations including: receiving a write-back clear command from a processing device, the write-back clear command identifying a plurality of the first memory cells; and, in response to the write-back clear command, causing a page buffer among the one or more page buffers to access the plurality of the first memory cells. The unit performs a dual-gated read operation, the dual-gated read operation comprising soft gating at a first threshold voltage and hard gating at a second threshold voltage, the first threshold voltage and the second threshold voltage being sensed approximately between the threshold voltage distributions of the plurality of first memory cells; such that the page buffer determines the number of bit values ​​detected within the threshold voltage distribution in the threshold voltage range between the first threshold voltage and the second threshold voltage; and in response to the number of bit values ​​not satisfying a threshold criterion, such that data in the plurality of first memory cells is written back to the plurality of second memory cells without intervention from the processing device.

[0004] Another embodiment of this disclosure provides a method comprising: receiving a write-back clear command from a processing device by control logic of a memory device, the memory device including a first memory cell configured as a single-level cell memory and a second memory cell configured as a higher-level cell memory, wherein the write-back clear command identifies a plurality of the first memory cells; the control logic causing a page buffer to perform a dual-gated read operation on the plurality of first memory cells in response to the write-back clear command, the dual-gated read operation including soft gating at a first threshold voltage and hard gating at a second threshold voltage, the first threshold voltage and the second threshold voltage being sensed approximately between threshold voltage distributions of the plurality of first memory cells; the control logic causing the page buffer to determine a number of bit values ​​detected within a threshold voltage range between the first threshold voltage and the second threshold voltage within the threshold voltage distribution; and in response to the number of bit values ​​not satisfying a threshold criterion, causing data in the plurality of first memory cells to be written back to the plurality of second memory cells without intervention from the processing device.

[0005] Another embodiment of this disclosure provides a system comprising: a memory device including: one or more memory cell arrays comprising first memory cells configured as single-level cell memory and second memory cells configured as higher-level cell memory; and control logic operatively coupled to one or more page buffers of the one or more memory cell arrays; and processing means operatively coupled to the memory device, the processing means being configured to perform operations including: generating a write-back clear command identifying a plurality of the first memory cells, the plurality of first memory cells storing data to be copied to a plurality of second memory cells; the write-back clear command including a voltage range between threshold distributions sensed by the page buffers between hard and soft strobing; and transmitting the write-back clear command to the control logic for execution by the control logic before the control logic executes writing the data back to the plurality of second memory cells. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of some embodiments thereof.

[0007] Figure 1A This describes an instance computing system including a memory subsystem according to some embodiments.

[0008] Figure 1B This is a block diagram of a memory device communicating with a memory subsystem controller according to an embodiment.

[0009] Figures 2A to 2B For reference purposes based on embodiments Figure 1B A schematic diagram of a portion of the memory cell array in the described type of memory.

[0010] Figure 3A This is a block diagram of a memory subsystem for generating and processing write-back clear commands according to at least some embodiments.

[0011] Figure 3B This is a circuit diagram of a page buffer for a memory subsystem according to at least some embodiments.

[0012] Figure 4A A diagram illustrating a dual-gated read operation within a valley line of a single-level cell (SLC) with write-back clearing according to at least one embodiment.

[0013] Figure 4B This is a diagram illustrating a dual-gated read operation within a valley line of an SLC memory cell that has not been cleared by write-back, according to at least one embodiment.

[0014] Figure 5 This is a flowchart of a method for generating a write-back clear command and reacting to the result of a write-back clear, according to at least some embodiments.

[0015] Figure 6 This is a flowchart of a method for executing a write-back clear command and performing a write-back when the write-back clear command passes, according to at least one embodiment.

[0016] Figure 7 This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0017] Embodiments of this disclosure relate to a write-back clear command for performing scans and reads in a memory device. In some memory devices (e.g., NAND memory devices), each memory device includes one or more arrays of memory cells. The one or more arrays of memory cells may include: a first memory cell configured as a single-level cell (SLC) memory, which stores one bit per cell; and a second memory cell configured as a higher-level cell (HLC) memory, which stores more than one bit per cell. For example, an HLC memory may include multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and / or five-level cell (PLC), each of which stores multiple bits of each cell as logical states depending on a threshold voltage stored in each cell. Memory cells of the memory device may be grouped into pages, where a page may refer to a logical cell of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0018] In these memory devices, the memory subsystem controller controls write-back and / or internal data movement (IDM) processes (collectively referred to herein as "write-back"), in which data is copied from SLC memory to HLC memory. This write-back process is also known as folding or compressing data from SLC memory into HLC memory, since multiple bits of SLC data can be stored within a single cell of HLC memory. The memory subsystem controller can control the execution of write-back within the memory device, for example, to convert SLC data into high-density data and thereby free up additional memory array space for more data. In some cases, SLC memory is used as SLC cache memory, where data stored in SLC cache memory is copied to HLC data, as the memory device is freed from other programming, reading, and erasing operations to achieve this.

[0019] In these memory devices, because errors in SLC data are amplified and largely uncorrectable after being written back to HLC memory, the memory subsystem controller takes steps to ensure that the SLC data is sufficiently error-free, for example, the write-back read bit error rate (RBER) is less than a specific High Reliability Error Threshold (HRER) specification. To achieve this, the controller performs an SLC data scan by reading the SLC data, decoding the SLC data according to an Error Correction Code (ECC) algorithm, and performing error checks on the SLC data. Since errors can sometimes originate from defects in individual pillars, channels, and / or word lines, each word line is scanned, for example, instead of selectively checking data associated only with certain word lines. This means that a large amount of SLC data is read and error-checked before the controller can proceed to guide the memory device to perform a write-back.

[0020] In these memory devices, if certain errors are detected and are correctable, the controller can correct the errors and re-encode the SLC data before programming the SLC data into the HLC memory. However, if the detected errors are uncorrectable, the controller performs a refresh of the SLC data before re-encoding the SLC data and programming it into the HLC memory. Because HLC memory is becoming increasingly prevalent, and SLC memory is often used as a cache to maintain high performance, write-back processes are frequently performed, resulting in significant performance penalties for these memory devices in terms of latency (e.g., when scanning and reading SLC data to clear the SLC data to be written back to the HLC memory) and data bus congestion.

[0021] The aspects of this disclosure address the above and other deficiencies by employing a memory subsystem controller (e.g., a processing device) with a write-back clear command. The write-back clear command, also referred to herein as a Unit Soft Bit Read (SBSBR) command, directs the memory device to perform an initial health check of SLC data. If the SLC data passes, the memory device automatically performs a write-back without further intervention from the memory subsystem controller. For example, the memory device's local media controller (e.g., control logic) may act on a write-back clear command received from the processing device. In one embodiment, when executing the write-back clear command, the control logic causes the page buffer to perform a dual-gated read operation on the target SLC memory cell. In at least some embodiments, the dual-gated read operation includes a soft gating at a first threshold voltage and a hard gating at a second threshold voltage, performed serially. The first and second threshold voltages can be sensed approximately between threshold voltage distributions of a first set of SLC memory cells. In other words, the first and second threshold voltages are oriented to fall within a valley identified between the threshold voltage distributions.

[0022] In at least these embodiments, the control logic further causes the page buffer to determine the number of bit values ​​detected within a threshold voltage range between a first threshold voltage and a second threshold voltage, within the threshold voltage distribution. The more bit values ​​detected in the first memory cells within the threshold voltage range, the higher the probability that the RBER will be high for a set of first memory cells. Therefore, in response to a number of bit values ​​not meeting the threshold criterion, the control logic may further cause to perform a write-back of data from a set of first memory cells to a set of second memory cells (e.g., HLC memory cells) without intervention from the processing device. For example, the threshold criterion may be a value corresponding to a specific HRER, which, if met, indicates an RBER that is too high to pass the initial health check. This specific HRER may be slightly lower than the previously mentioned specific HRER to carefully clear errors in the SLC data without full error checking. Therefore, if the threshold criterion is met, the control logic does not perform a data write-back, and the memory subsystem controller may perform further error checking.

[0023] In these embodiments, the control logic may further cause the page buffer to store a pass indicator value or a fail indicator value in a status register depending on whether the number of bit values ​​meets a threshold criterion. The status register is accessible to a processing device, which can therefore know the health status of the SLC data before deciding how to proceed with writing back the SLC data to a set of second memory cells. In response to detecting, for example, a pass indicator value in the status register, the processing device may take no further action, thereby enabling the memory device to perform data write-back on multiple second memory cells. In response to detecting a fail indicator value in the status register, the processing device may retrieve health data from a set of latches in the memory device and determine, based on the health data, whether to perform error correction or block refresh on a set of first memory cells, for example, depending on how many bit values ​​are detected within a threshold voltage range across a threshold voltage distribution.

[0024] Therefore, the advantages of the systems and methods implemented according to some embodiments of this disclosure include, but are not limited to, reduced complexity and improved performance in clearing SLC data stored in SLC memory cells to be written back to HLC memory cells. This performance improvement includes reduced latency, particularly when the processing device does not need to take further action before performing a write-back, and less congestion on the data bus (e.g., Open NAND Flash Interface (ONFI) bus) between the memory subsystem controller and the memory device when reading and error checking of SLC data is avoided. Furthermore, dual-strobe read operations incur less read time (tR) overhead, as will be explained. Other advantages will be apparent to those skilled in the art of folding data into memory devices, which will be discussed below.

[0025] Figure 1A This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or combinations of such media or memory devices. The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules.

[0026] Memory device 130 may be a non-volatile memory device. An example of a non-volatile memory device is a NAND memory device. A non-volatile memory device is a package of one or more dies. Each die may contain one or more planes. Planes may be grouped into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory units (“units”). The unit is an electronic circuit for storing information. Depending on the unit type, a unit may store one or more bits of binary information and has various logic states related to the number of bits stored. Logic states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of such values.

[0027] Memory device 130 may consist of bits arranged in a two-dimensional or three-dimensional grid, also referred to as a memory array. Memory cells are etched onto a silicon wafer in the form of column (hereinafter also referred to as bit lines) and row (hereinafter also referred to as word lines) arrays. A word line may refer to one or more rows of memory cells of the memory device, which are used in conjunction with one or more bit lines to generate the address of each of the memory cells. The intersection of a bit line and a word line constitutes the address of the memory cell.

[0028] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0029] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0030] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1A This describes an example of a host system 120 coupled to a memory subsystem 110. The host system 120 can provide data for storage at the memory subsystem 110 and can request retrieval of data from the memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, and magnetic connections.

[0031] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 to, for example, write data to memory subsystem 110 and read data from memory subsystem 110.

[0032] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1AThe memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0033] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0034] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint ("3D crosspoint") memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory cells can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. Furthermore, in contrast to many flash-based memories, crosspoint non-volatile memories can perform in-place write operations, where non-volatile memory cells can be programmed without prior erasing. NAND flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0035] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0036] While a 3D cross-point array of non-volatile memory cells and a non-volatile memory component of NAND flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0037] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0038] The memory subsystem controller 115 may include a processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0039] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1A The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0040] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may also include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0041] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0042] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0043] In some embodiments, controller 115 (e.g., processing means) includes an error correction code (ECC) encoder / decoder 111. The ECC encoder / decoder 111 can perform ECC encoding on data written to memory device 130 and ECC decoding on data read from memory device 130. ECC decoding can be performed to decode ECC codewords to correct errors in the original read data, and in many cases, also to report the number of bit errors in the original read data. Memory subsystem controller 115 may also include processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. Local memory 119 may also buffer data used by the executed instructions.

[0044] In at least some embodiments, the controller 115 further includes a memory interface component 113 capable of handling interactions between the controller 115 and a memory device (e.g., memory device 130) of the memory subsystem 110. For example, the memory interface component 113 may generate a write-back clear command and transmit the command to the memory device 130, retrieve pass and fail indicator values ​​from the memory device, and retrieve health status data, using the health status data to determine whether to perform error correction or refresh the SLC data stored in a set of SLC memory cells before performing a write-back on the SLC data. In some embodiments, these aspects of the memory interface 113 may be partially or entirely included within the functionality of the host system 120.

[0045] In various embodiments, memory device 130 further includes one or more page buffers 152, which provide circuitry for programming data into and reading data from memory cells of memory device 130. Local media controller 135 may further include program manager 136, which is implemented using firmware, hardware, or a combination of firmware and hardware. In one embodiment, program manager 136 receives a write-back clear command from memory interface 113. Program manager 136 may execute the write-back clear command to determine whether to continue writing data back from SLC memory cells to HLC memory cells without further intervention from controller 115, or whether to wait for controller 115 to determine whether to perform error correction or refresh the data stored in the SLC memory cells before performing the write-back operation. In some embodiments, program manager 136 is part of host system 110, an application, or an operating system. Further details regarding the operation of program manager 136 are described below.

[0046] Figure 1B For example, the present memory subsystem according to the embodiment (e.g., Figure 1AA simplified block diagram of a first device in the form of a memory device 130 communicating with a second device in the form of a memory subsystem controller 115 (of memory subsystem 110). Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0047] Memory device 130 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1B (Not shown in the text) can be programmed to be one of at least two target data states.

[0048] Row decoding circuitry 108 and column decoding circuitry 111 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 112 to manage inputs of commands, addresses, and data to memory device 130, as well as outputs of data and status information from memory device 130. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 111 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and local media controller 135 to latch incoming commands.

[0049] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 104 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 104. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 111 to control them in response to addresses. As discussed, the local media controller 135 may also include a program manager 136.

[0050] The local media controller 135 also communicates with cache register 118 and data register 121. Cache register 118 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 104 is busy writing or reading other data. During a programming operation (e.g., a write operation), data can be transferred from cache register 118 to data register 121 for transfer to memory cell array 104; then, new data can be latched from I / O control circuitry 112 into cache register 118. During a read operation, data can be transferred from cache register 118 to I / O control circuitry 112 for output to memory subsystem controller 115; then, new data can be transferred from data register 121 to cache register 118. Cache register 118 and / or data register 121 may form page buffers (e.g., at least a portion thereof) in one or more page buffers 152 of memory device 130. Each page buffer may further include a sensing device, such as a sensing amplifier, to sense the data status of the memory cells in the memory cell array 104, for example, by sensing the status of the data lines connected to the memory cells. Status register 122 may communicate with I / O control circuitry 112 and local memory controller 135 to latch status information for output to memory subsystem controller 115.

[0051] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 132. For example, control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received further via control link 132. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 134, and outputs data to memory subsystem controller 115 via I / O bus 134.

[0052] For example, commands can be received via the input / output (I / O) pins [7:0] of the I / O bus 134 at I / O control circuitry system 112, and then written to command register 124. Addresses can be received via the input / output (I / O) pins [7:0] of the I / O bus 134 at I / O control circuitry system 112, and then written to address register 114. Data can be received via the input / output (I / O) pins [7:0] for 8-bit devices or the input / output (I / O) pins [15:0] for 16-bit devices at I / O control circuitry system 112, and then written to cache register 118. Data can then be written to data register 121 for programming memory cell array 104.

[0053] In this embodiment, the cache register 118 may be omitted, and data may be written directly to the data register 121. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to the memory device 130 via an external device (e.g., the memory subsystem controller 115).

[0054] Those skilled in the art will understand that additional circuitry and signals can be provided and the process has been simplified. Figure 1B The memory device 130. It should be understood that, reference Figure 1B The functionality of the various block components described may not necessarily be separate from different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1B The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1B The functionality of a single block component. Additionally, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0055] Figures 2A to 2B This is a schematic diagram of a portion of a memory cell array 200A, such as a NAND memory array, which may be used, for example, as part of a memory cell array 104 in accordance with the embodiment reference. Figure 1B The memory array 200A contains, for example, word lines 2020 to 2020. N Access lines and, for example, bit lines 2040 to 204 MThe data cable. Word line 202 can be connected in a many-to-one relationship to data cables not in... Figure 2A The global access lines (e.g., global word lines) shown in the diagram. In some embodiments, the memory array 200A may be formed over a semiconductor, which may be conductively doped to have a certain conductivity type, such as having p-type conductivity to form a p-well, or having n-type conductivity to form an n-well, for example.

[0056] The memory array 200A can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a string of memory cells (e.g., non-volatile memory cells) connected in series, such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Each bit line 204 and NAND string 206 may be associated with a sub-block in a set of sub-blocks of memory array 200A. Memory cell 208 may represent a non-volatile memory cell for storing data. The memory cell 208 of each NAND string 206 may be connected in series between a select gate 210 (e.g., a field-effect transistor) and a select gate 212 (e.g., a field-effect transistor), the select gate 210 being, for example, select gates 2100 to 210. M One of them (for example, it may be a source-select transistor, often referred to as a select-gate-source), and the select gate 212 is, for example, select gate 2120 to 212. M One of them (for example, it could be a drain-select transistor, often referred to as a select-gate drain). Select gate 2100 to 210 M They can be commonly connected to select line 214, such as source select line (SGS), and select gates 2120 to 212. M They can be connected together to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent a plurality of select gates connected in series, wherein each select gate connected in series is configured to receive the same or independent control signal.

[0057] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0058] The drain of each select gate 212 can be connected to a bit line 204 corresponding to the NAND string 206. For example, the drain of select gate 2120 can be connected to a bit line 2040 corresponding to the NAND string 2060. The source of each select gate 212 can be connected to a memory cell 208 corresponding to the NAND string 206. N For example, the source of the select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0059] Figure 2A The memory array 200A can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a generally parallel plane. Alternatively, Figure 2A The memory array 200A in the memory array can be a three-dimensional memory array, for example, in which the NAND string 206 can extend substantially perpendicular to the plane containing the common source 216 and substantially perpendicular to the plane containing the bit line 204, and the plane containing the bit line 204 can be substantially parallel to the plane containing the common source 216.

[0060] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, etc.) that determines the data state of the memory cell (e.g., by changing a threshold voltage) and a control gate 236, such as... Figure 2A As shown in the diagram. The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The memory cell 208 connects its control gate 236 to (and in some cases, forms) a word line 202.

[0061] A column of memory cells 208 may be a NAND string 206 or several NAND strings 206 selectively connected to a given word line 204. A row of memory cells 208 may consist of memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may contain, but does not need to contain, all memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 typically contains memory cells 208 that are commonly connected to a given word line 202 every other one. For example, those commonly connected to word line 202... N Furthermore, memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while those commonly connected to word line 202 N Furthermore, memory cells 208 selectively connected to odd bit lines 204 (e.g., bit lines 2041, 2043, 2045, etc.) can be another physical page of memory cell 208 (e.g., odd memory cell).

[0062] Despite Figure 2A Although bit lines 2043 to 2045 are not explicitly depicted in the figure, it is evident from the figure that bit lines 204 of the memory cell array 200A can be consecutively numbered from bit line 2040 to bit line 204. M Other groups of memory cells 208 commonly connected to a given word line 202 may also define physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given word line may be considered physical pages of the memory cells. A portion of a physical page of a memory cell (in some embodiments, it may still be an entire row) that is read during a single read operation or programmed during a single programming operation (e.g., the upper or lower page of the memory cell) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to word lines 2020 to 202. N All memory cells (e.g., all NAND strings 206 sharing a common word line 202). Unless explicitly distinguished, references to memory cell pages herein refer to the memory cells of the logical pages of the memory cells. This is despite the discussion of NAND flash memory. Figure 2A Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS, phase-change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0063] Figure 2B For reference only Figure 1BAnother schematic diagram of a portion of a memory cell array 200B in a memory of the described type, for example as part of a memory cell array 104. Figure 2B Elements with the same number in the text correspond to elements such as those related to... Figure 2A The description provided. Figure 2B Further details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may incorporate a vertical structure that may contain semiconductor pillars, a portion of which may serve as channel regions for the memory cells of NAND strings 206. Each of the NAND strings 206 may be selectively connected to bit lines 2040 to 204 via a select transistor 212 (e.g., a drain select transistor, often referred to as a select gate drain). M And selectively connected to a common source 216 via a selection transistor 210 (e.g., which may be a source selection transistor, commonly referred to as a select gate source). Multiple NAND strings 206 can be selectively connected to the same bit line 204. A subset of NAND strings 206 can be connected via bias selection lines 2150 to 215. K Each word line 202 is connected to its corresponding bit line 204 to selectively activate a specific selection transistor 212 located between the NAND string 206 and the bit line 204. Selection transistors 210 can be activated by biasing selection line 214. Each word line 202 can be connected to multiple rows of memory cells in the memory array 200B. Multiple rows of memory cells interconnected by specific sub-lines 202 can be collectively referred to as a layer.

[0064] Figure 3A This is a block diagram of a memory subsystem 300 that implements the generation and processing of write-back clear commands according to at least some embodiments. In some embodiments, the memory device 130 is operatively coupled to a memory interface 113. In one embodiment, the memory device 130 includes a program manager 136, one or more page buffers 152, and a memory array 350, which is... Figures 2A to 2B An example of a parallel-plane memory cell array is illustrated herein. Memory array 350 may include memory cell arrays formed at the intersections of word lines and bit lines, as shown in the reference. Figures 2A to 2B As explained. In these embodiments, each page buffer of one or more page buffers 152 includes a latch (at least a first latch and a second latch) and a status register 344. The status register 344 may also be located outside one or more page buffers 152 within the memory device 130.

[0065] In various embodiments, memory cells are grouped into blocks, and the blocks are further grouped into block stripes across a plane. In one embodiment, there may be a first portion 351 of the blocks of memory array 350 configured as SLC memory, and a second portion 354 of the blocks of memory array 350 configured as HLC memory. In another embodiment, the first portion 351 is a first memory array and the second portion 354 is a second memory array. In these embodiments, the HLC memory may comprise blocks configured as one or more of MLC memory, TLC memory, QLC memory, PLC memory, or other types of memory. Furthermore, in at least some embodiments, the SLC memory is treated as a cache memory of the HLC memory.

[0066] In some memory devices, memory cells can experience high raw bit error rate (RBER) events due to large temperature variations between program-erase cycles (PEC) and when a memory cell is programmed and when it is read, where the total tail of the threshold voltage distribution can cause the valley lines to at least partially contract. This at least partial contraction of the valley lines between the threshold voltage distributions occurs when SLC data is placed in the final bit-per-cell (PBC) configuration, for example, for writing back from SLC memory to HLC memory (see, for example...). Figure 4B Too many High Reliability Errors (HRERs) have been generated. These errors can be inherently caused by high cycling, high temperature differences, and / or high interference workloads, and are becoming increasingly important to correct as SLC endurance requirements increase and valley shrinkage and / or high RBER events become more dominant in these higher cycles. These errors can also manifest externally as pin, channel, or word line defects. The memory subsystem 300 (specifically the memory interface 113) scans for these potential errors to determine when it is time to deregister, refurbish, etc. However, maintaining dedicated management reads for all SLC blocks is impractical due to firmware complexity and quality of service reasons (e.g., the performance impact of calibration overhead within the memory device 130).

[0067] Furthermore, existing practice of scanning SLC data before performing a write-back involves performing a hard gating, generally in the middle of a valley between two threshold voltage distributions, as a standard read operation to return a dataset (e.g., one or more bits of data) from the threshold voltage distributions. The reliability of this standard read is checked by employing a separate pair of soft gating, with one soft gating on each side of the hard gating to determine which bits are low or high confidence. The soft gating can then establish an XOR of information within the valley to determine which bits are low or high confidence. For example, the information obtained from the soft gating can be used to determine whether to perform error correction or refresh the SLC data via a log-likelihood ratio (LLR) operator, which serves as part of the error correction operation. Thus, the LLR will return a low or high reliability binary. However, these scans are performed across the entire block of memory cells because any word line can be defective. Furthermore, each read checked by controller 115 requires two reads, a hard gating, and a pair of soft gating in these memory devices. This existing practice is inefficient, incurring considerable overhead when performing two separate reads, and thus increasing memory access latency, thereby reducing the quality of service.

[0068] In the various solution-based embodiments discussed herein, the memory interface 113 (e.g., a processing device) employs a write-back clear command, also referred to herein as a Unit Soft Bit Read (SBSBR) command. This write-back clear command can be formatted differently, for example, by adding a prefix or suffix to an existing programming command or by generating a completely different programming command. In these embodiments, the write-back clear command directs the memory device 130 to perform an initial health check of the SLC data. If the SLC data passes, the memory device automatically writes back the SLC data without further intervention from the memory subsystem controller (e.g., performing a full scan or error correction). For example, the program manager 136 (e.g., control logic) of the memory device 130 may act on a write-back clear command received from the memory interface 113.

[0069] In these embodiments, when executing a write-back clear or SBSBR command, the program manager 136 causes one or more page buffers 152 to perform a dual-strobe read operation on a target SLC memory cell, which may comprise a block, multiple blocks, and / or stripes of memory cells. Figure 4A This is a diagram illustrating a dual-gated read operation within a valley line of an SLC memory cell by write-back clearing according to at least one embodiment. Figure 4BThis diagram illustrates a dual-gated read operation within a valley of an SLC memory cell that has not passed write-back clear, according to at least one embodiment. In at least some embodiments, the dual-gated read operation includes a soft gating 401 at a first threshold voltage (first) and a hard gating 403 at a second threshold voltage (second), the first and second threshold voltages being sensed approximately between threshold voltage distributions of a set of first memory cells (e.g., SLC memory cells). In other words, the first and second threshold voltages are oriented to fall within a valley identified between the threshold voltage distributions. In these embodiments, the hard gating and soft gating are executed serially as a single enhanced read operation in response to a single write-back clear command.

[0070] In some embodiments, the threshold voltage range between the first threshold voltage and the second threshold voltage is a predetermined voltage range adopted in response to each write-clear command. In at least some embodiments, the page buffer aims the hard gate 403 at the lower tail of the highest threshold voltage distribution 95 in the threshold voltage distribution, and aims the soft gate 401 at the upper tail of the lowest threshold voltage distribution 95 in the threshold voltage distribution. In other embodiments, the page buffer aims the hard gate 403 at the upper tail of the lowest threshold voltage distribution 90, and aims the soft gate 401 at the lower tail of the highest threshold voltage distribution, which is consistent with... Figures 4A to 4B The situation described in the text is the opposite.

[0071] In at least these embodiments, the program manager 136 further causes the page buffer to determine the number of bit values ​​detected within the threshold voltage range between the first and second threshold voltages, within threshold voltage distributions 90 and 95. The more bit values ​​detected within the threshold voltage range stored in the first memory cell, the higher the likelihood that the RBER will become too high. Figure 4A As can be seen, there is no single bit between the first and second threshold voltages, which means the write-back clear command will pass. In contrast, Figure 4B This indicates that many single-bit values ​​will be detected between the first threshold voltage and the second threshold voltage, such as causing the write-back clear command to fail.

[0072] In at least some embodiments, in response to the number of bits not meeting a threshold criterion, program manager 136 further causes data to be written back from a first set of memory cells to a second set of memory cells (e.g., HLC memory cells) without intervention from the processing device. For example, the threshold criterion could be a value corresponding to a specific HRER, which, if met, indicates that the RBER is too high to pass the initial health check. This specific HRER could be slightly lower than the previously mentioned specific HRER to carefully clear errors in the SLC data without full error checking. Therefore, if the threshold criterion is met, the control logic does not perform data write-back, and the memory subsystem controller can perform further error checking.

[0073] In these embodiments, depending on whether the number of bit values ​​meets a threshold criterion, the program manager 136 further causes the page buffer to store either a pass indicator value or a fail indicator value in a status register 344. The status register 344 is accessible to a processing device, which can therefore know the health status of the SLC data before deciding how to proceed with writing back the SLC data to a set of second memory cells. In response to detecting, for example, a pass indicator value in the status register 344, the memory interface 113 (e.g., of the controller 115) may take no further action, thereby enabling the memory device 130 to perform a write-back of the data to the set of second memory cells. In response to detecting a fail indicator value in the status register 344, the memory interface 113 may retrieve health data from a set of latches 342 of the memory device and determine, based on the health data, whether to perform error correction or block refresh on the set of first memory cells, for example, depending on how many bit values ​​are detected within the threshold voltage range between threshold voltage distributions.

[0074] Figure 3BThis is a circuit diagram of a page buffer 352 of a memory subsystem 300 according to at least some embodiments. In some embodiments, the page buffer 352 of one or more page buffers 152 includes, for example, a first latch 342A to store each threshold voltage stored in a memory cell detected as having a threshold voltage within a threshold voltage range. In these embodiments, the page buffer 352 further includes a second latch 342B to store a second threshold voltage and an XOR gate 360 ​​(or XOR logic) receiving the output as input from the first latch 342A and the second latch 342B. The page buffer 352 may further include a counter 368 to count the number of bit values ​​detected by the XOR gate 360. Thus, a bit value is detected only when a particular threshold voltage in the threshold voltage range is one and the second threshold voltage is zero. A hard probe may be directed at the end of the tail of the threshold voltage distribution such that the second threshold voltage should generally be zero. In this way, the page buffer 352 can be stepped by counting the bit values ​​stored in memory cells within the threshold voltage range between threshold voltage distributions.

[0075] Figure 5 This is a flowchart of a method 500 for generating a write-back clear command and reacting to the result of a write-back clear, according to at least some embodiments. Method 500 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1A The process is executed via the memory interface 113 of the controller 115 (e.g., a processing device). Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0076] At operation 505, a write-back clear command is generated. More specifically, the processing logic generates a write-back clear command that identifies a first set of memory cells storing data to be copied to a second set of memory cells.

[0077] At operation 510, a voltage range is specified. More specifically, the processing logic within the write-back clear command includes a voltage range sensed by the page buffer between threshold distributions of a set of first memory cells, used between hard and soft strobing.

[0078] At operation 520, a write-back clear command is transmitted. More specifically, before the control logic performs a write-back of data on a set of second memory cells, the processing logic transmits the write-back clear command to the control logic (e.g., the local media controller 135) for execution by the control logic.

[0079] At operation 525, a pass / fail determination is made. More specifically, the processing logic checks the pass or fail indicator value in the status register of the memory device as a result of a write-back clear command that has been executed by the memory device.

[0080] At operation 530, the write-back is allowed to continue. More specifically, in response to the detection of a passing indicator value, the processing logic takes no further action, thereby enabling the memory device to perform a write-back of data to a second set of memory cells.

[0081] At operation 535, an additional health check is performed. More specifically, in response to detecting a non-pass indicator value, the processing logic retrieves health data from a set of latches in the memory device.

[0082] At operation 540, a choice is made between error correction and data refresh. More specifically, the processing logic determines, based on health data, whether to perform error correction or block refresh on a first set of memory cells.

[0083] Figure 6 This is a flowchart of a method 600 for executing a write-back clear command and performing a write-back upon the passage of the write-back clear command, according to at least one embodiment. Method 600 may be executed by processing logic that may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 600 is performed by… Figures 1A to 1B The local media controller 135 executes the process, for example, the control logic of the program manager 136 of the memory device 130. The memory device 130 includes a first memory cell configured as a single-level cell memory and a second memory cell configured as a higher-level cell memory. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0084] At operation 605, a write-back clear command is received. More specifically, the processing logic receives a write-back clear command from the processing device, the write-back clear command identifying a first set of memory cells as the target of the write-back clear command.

[0085] At operation 610, a dual-strobe read operation is initiated. More specifically, the processing logic, in response to a write-back clear command, causes the page buffer to perform a dual-strobe read operation on a set of first memory cells. The dual-strobe read operation includes soft strobing at a first threshold voltage and hard strobing at a second threshold voltage, the first and second threshold voltages being sensed to be approximately within the threshold voltage distribution of the set of first memory cells.

[0086] At operation 615, the number of bit values ​​is determined. More specifically, the processing logic causes the page buffer to determine the number of bit values ​​detected within the threshold voltage range between the first and second threshold voltages, within the threshold voltage distribution.

[0087] At operation 620, a single-bit value is checked against a threshold. More specifically, the processing logic determines whether the number of single-bit values ​​meets a threshold criterion. For example, the threshold criterion could be a value corresponding to a specific HRER, which, if met, indicates that the RBER is too high to pass the initial health check. This specific HRER could be slightly lower than the previously mentioned specific HRER to carefully remove errors from the SLC data without a full error check.

[0088] At operation 625, the write-back continues without processing intervention. More specifically, in response to the number of bits not meeting a threshold criterion, the control logic causes data in a first set of memory cells to be written back to a second set of memory cells without intervention from the processing device.

[0089] At operation 630, the indicator value is stored. More specifically, the processing device causes the page buffer to store the indicator value in a status register accessible by the processing device.

[0090] At operation 635, the write-back is not performed. More specifically, in response to the number of bits satisfying the threshold criterion, the processing logic does not perform a data write-back.

[0091] At operation 640, the fail indicator value is stored. More specifically, the processing device causes the page buffer to store the fail indicator value in a status register accessible by the processing device.

[0092] Figure 7An example machine illustrating computer system 700 is described, within which a set of instructions is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1A The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A The memory subsystem 110), or may be used to perform controller operations (e.g., to execute an operating system, thereby executing commands corresponding to...). Figure 1A (Operation of the memory subsystem controller 115). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a client-server network environment.

[0093] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions that will take a specified action by said machine. Furthermore, although a single machine is described, it should be understood that the term "machine" also includes any collection of machines that individually or collectively execute a set (or more) of instructions to perform any one or more of the methods discussed herein.

[0094] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 710 (e.g., flash memory, static random access memory (SRAM)), and a data storage system 718, which communicate with each other via a bus 730.

[0095] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 728 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 712 for communication via network 720.

[0096] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) on which one or more sets of instructions 728 or software embodying any one or more of the methods or functions described herein are stored. The data storage system 718 may further include the previously discussed local media controller 135 and page buffers 152 or 352. The instructions 728 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, which also constitute the machine-readable storage medium. The machine-readable storage medium 724, the data storage system 718, and / or main memory 704 may correspond to... Figure 1A The memory subsystem 110.

[0097] In one embodiment, instruction 726 includes instructions for implementing a controller (e.g., Figures 1A to 1B The local media controller 135) contains functional instructions, such as a program manager 136, which may be included in various embodiments. Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiments, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0098] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. The algorithms described herein generally refer to a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical control over a physical quantity. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for general reasons, it has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0099] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system, or other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0100] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for a desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0101] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods. Structures for various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0102] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0103] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made to the invention without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A memory device comprising: An array of one or more memory cells, comprising a first memory cell configured as a single-level cell memory and a second memory cell configured as a higher-level cell memory; One or more page buffers coupled to the one or more memory cell arrays; and Control logic, which is coupled to the one or more page buffers in an operational manner, performs operations including the following: The processing device receives a write-back clear command, the write-back clear command identifying a plurality of the first memory cells; In response to the write-back clear command, one or more page buffers perform a dual-gated read operation on the plurality of first memory cells, the dual-gated read operation including soft gating at a first threshold voltage and hard gating at a second threshold voltage, the first threshold voltage and the second threshold voltage being sensed between the threshold voltage distributions of the plurality of first memory cells; This allows the page buffer to determine the number of bit values ​​detected within the threshold voltage range between the first threshold voltage and the second threshold voltage, within the threshold voltage distribution; and In response to the number of a single value not satisfying the threshold criterion, the data in the plurality of first memory cells is written back to the plurality of second memory cells without intervention from the processing device.

2. The memory device of claim 1, wherein the threshold voltage range includes a predetermined voltage range used in response to each write-clear command.

3. The memory device of claim 1, wherein the write-back clear command includes a unit soft bit read SBSBR command.

4. The memory device of claim 1, wherein causing the page buffer to perform the dual-strobe read operation comprises causing the page buffer to perform the following operations: The hard gate is aimed at the lower tail of the highest value in the threshold voltage distribution; and The soft gate is aimed at the upper tail of the lowest of the threshold voltage distributions.

5. The memory device of claim 1, wherein causing the page buffer to perform the dual-strobe read operation comprises causing the page buffer to perform the following operations: The hard gate is aimed at the upper tail of the lowest value in the threshold voltage distribution; and The soft gate is aimed at the lower tail of the highest value in the threshold voltage distribution.

6. The memory device of claim 1, wherein the page buffer comprises: A first latch is used to store each threshold voltage stored in the memory cell, the memory cell being detected as having a threshold voltage within the threshold voltage range; A second latch is used to store the second threshold voltage; and An XOR gate that receives the outputs of the first latch and the second latch as inputs.

7. The memory device of claim 1, wherein the operation further comprises causing the page buffer to store an indicator value in a status register accessible by the processing device.

8. The memory device of claim 1, wherein the operation further comprises responding to the number of bits satisfying a threshold criterion: The write-back of the data is not performed; and This causes the page buffer to store the indicator value in a status register that can be accessed by the processing device.

9. A method comprising: The control logic of the memory device receives a write-back clear command from the processing device, the memory device including a first memory cell configured as a single-level cell memory and a second memory cell configured as a higher-level cell memory, wherein the write-back clear command identifies a plurality of the first memory cells; The control logic, in response to the write-back clear command, causes the page buffer to perform a dual-gated read operation on the plurality of first memory cells. The dual-gated read operation includes soft gating at a first threshold voltage and hard gating at a second threshold voltage, wherein the first threshold voltage and the second threshold voltage are sensed between the threshold voltage distributions of the plurality of first memory cells. The control logic causes the page buffer to determine the number of bit values ​​detected within the threshold voltage range between the first threshold voltage and the second threshold voltage, within the threshold voltage distribution; and In response to the number of a single value not satisfying the threshold criterion, the data in the plurality of first memory cells is written back to the plurality of second memory cells without intervention from the processing device.

10. The method of claim 9, wherein the threshold voltage range includes a predetermined voltage range adopted in response to each write-clear command.

11. The method of claim 9, wherein the write-back clear command comprises a unit soft bit read SBSBR command.

12. The method of claim 9, wherein causing the page buffer to perform the dual-strobe read operation comprises causing the page buffer to perform the following operations: The hard gate is aimed at the lower tail of the highest value in the threshold voltage distribution; and The soft gate is aimed at the upper tail of the lowest of the threshold voltage distributions.

13. The method of claim 9, wherein causing the page buffer to perform the dual-strobe read operation comprises causing the page buffer to perform the following operations: The hard gate is aimed at the upper tail of the lowest value in the threshold voltage distribution; and The soft gate is aimed at the lower tail of the highest value in the threshold voltage distribution.

14. The method of claim 9, wherein causing the page buffer to determine the number of bit values ​​comprises: Each threshold voltage stored in the memory cell that is detected as having a threshold voltage within the threshold voltage range is stored in the first latch; The second threshold voltage is stored in the second latch; and This allows the XOR gate to operate on the outputs of the first latch and the second latch.

15. The method of claim 9, further comprising causing the page buffer to store an indicator value in a status register accessible by the processing device.

16. The method of claim 9, further comprising responding to the number of a single value satisfying a threshold criterion: The write-back of the data is not performed; and This causes the page buffer to store the indicator value in a status register that can be accessed by the processing device.

17. A system comprising: A memory device comprising: One or more memory cell arrays, comprising a first memory cell configured as a single-level cell memory and a second memory cell configured as a higher-level cell memory; and Control logic, which is operatively coupled to one or more page buffers of the one or more memory cell arrays; and A processing device operatively coupled to the memory device, the processing device being configured to perform operations including: A write-back clear command is generated to identify a plurality of the first memory cells, the plurality of first memory cells storing data to be copied to a plurality of second memory cells; The write-back clear command includes a voltage range between the threshold distributions of the plurality of first memory cells sensed by the page buffer, used between hard and soft gating; and Before the control logic executes the write-back clear command to write the data back to the plurality of second memory cells, the write-back clear command is transmitted to the control logic for execution by the control logic.

18. The system of claim 17, wherein the write-back clear command includes a unit soft bit read SBSBR command.

19. The system of claim 17, wherein the operation further comprises: The status register of the memory device detects the result of the write-back clear command via an indicator value. and No further action is taken to enable the memory device to perform the write-back of the data to the plurality of second memory cells.

20. The system of claim 17, wherein the operation further comprises: The status register of the memory device detects a non-pass indicator value as the result of the write-back clear command; Retrieve health data from a set of latches in the memory device; and Based on the health data, it is determined whether to perform error correction or block refresh on the plurality of first memory cells.

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