A test method for effectively distinguishing true and false data retention failures of flash memory

Abstract

The present invention discloses a test method for effectively distinguishing true and false data retention failure of a flash memory, comprising: S1, writing data: selecting a flash memory unit to write target data; S2, selecting a flash memory chip, reading data stored in each flash memory unit, comparing a read current representing the stored data with a standard current to obtain read data, comparing the read data with the written target data, and classifying the flash memory chip to be tested according to the comparison result; S3, clamping the standard current to perform a second inspection on the product to be confirmed, comparing the read current with two clamping thresholds and reclassifying the products into a first category of products to be confirmed and a second category of products to be confirmed; S4, performing simulated aging on the first category of products to be confirmed and the second category of products to be confirmed; S5, after the aging treatment, performing a third inspection: again reading the data stored in each flash memory unit of the flash memory chip, and again comparing it with the written data to determine good products, ordinary defective products, and data retention defective products.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a testing method for effectively distinguishing true and false data retention (DR) failures of flash memory. Background Art

[0002] With the continuous advancement of electronic technology, embedded systems are increasingly being used in electronic products such as control, consumer, and communications, and embedded technology is becoming increasingly integrated into people's lives. Flash memory devices are a type of non-volatile solid-state memory. They are fully non-volatile, providing reliable data protection against power failures. They can also be written online and have fast access speeds, making them highly reliable and high-density solid-state storage devices. Currently, various types of Flash memory have gradually become the most important storage devices in embedded systems. However, flash memory devices also have inherent limitations. First, programmed flash memory cells must be erased before they can be reprogrammed, and flash memory cells have a limited lifespan; that is, they can only be erased a limited number of times before failing. For example, a NAND flash memory cell typically has a maximum erase cycle of one million. Consequently, due to its "erase before write" nature, flash memory access speeds are slow, and repeated erase operations can damage the flash memory cells. Therefore, ensuring data reliability during access (i.e., data retention) is a crucial task for storage device manufacturers. The most important consideration is that during the data access process, the integrity of the data may be affected by the flash memory device itself or external factors.

[0003] However, some data retention (DR) failures (bin-outs) during chip probe (CP) testing of flash memory products are caused by weak programming or erase. In such cases, the die actually meet shipping standards. However, some customers lock the test circuit (program) after testing (blowing confidentiality bits such as fuses or OTP single-write bits), making analysis or retesting impossible. In the event of a dispute, the wafer batch faces the risk of being scrapped due to the inability to re-evaluate.

[0004] like Figure 1As shown in the figure, the vertical axis represents the percentage distribution of the read current Ir1 for a memory cell reading 1, and the horizontal axis represents the read current Ir1 for a read of 1 (M1). The dashed line on the left side of the figure represents the standard current for determining a "1," which is the second set threshold (the standard current for reading a 0 is the first set threshold), and is shown as 20uA. The lower left side of the histogram represents the tail bits. A similar distribution is observed for reading a "0" (M0), with memory cells whose read current Ir0 exceeds the first set threshold being considered tail bits. Some tail bits on weakly erased wafers may barely pass the read current test (M0 and M1) but may exhibit data retention failures (DR bins) during the second / third probe tests (CP2 / CP3). However, the root cause of these failures is due to weak erase mode or weak write mode, and does not involve DR issues.

[0005] like Figure 2a Figure 2 shows a schematic diagram of the data retention check (DR) process for a conventional split-gate flash memory. Multiple probe tests are performed during split-gate flash memory testing. The first probe test, CP1, includes many tests, including a flash memory chip open / short test, a program test, an erase test, a data crosstalk test, a checkboard test, and a data retention (DR) test. The data retention (DR) test runs through the three tests of CP1, CP2, and CP3.

[0006] First, during the first probe test (CP1), the data writing operation is performed, that is, each storage block of the flash memory chip is scanned in units of blocks, and data is written to each storage block. Then, each storage block of the flash memory chip is scanned in units of blocks, and the data in each storage block is read for the first time. The data read in each block is compared with the data written before to find the bad sectors in each block; then the first baking (Bake1) is performed, and the flash memory chip is baked at high temperature in a nitrogen environment for 3 days or 2 days to accelerate the aging simulation to simulate the condition of the flash memory chip after being used for a period of time. Usually, the baking Flash memory chips are baked at 250 degrees Celsius for three days. After baking, a second probe test (CP2) is performed. When testing data retention (DR), each storage block of the flash memory chip is scanned in units of blocks. The data previously written to the flash memory chip is read first to check whether the data is still correct after simulated aging. This is the data retention test of the second probe test (CP2). Of course, the aged chip will also be further tested for reading, writing, and erasing. After the second probe test (CP2), a second bake (Bake2) is performed; then a third probe test CP3 is performed.

[0007] As can be seen, in the normal test process (Normal Flow), in addition to the first probe test CP1, there are also the first bake (Bake1), the second probe test (CP2), the second bake (Bake12), and the third probe test CP3. Data retention issues (DR issues) will appear during the second probe test (CP2). Once an abnormality occurs, it can be studied and remedied.

[0008] In order to improve the efficiency of probe test (CP test) and save test time and cost, Figure 2bAs shown in the customer request process (TTR Customer Request), some products skip the data retention DR test (Skip CP2) during the second probe test (CP2), meaning only a single bake and DR test (Skip Bake1). Sometimes, the second probe test CP2 may not even be performed at all (Skip CP2). For example, some flash memory customers, for confidentiality reasons, lock the die after the CP3 test. This results in a high rate of data retention DR failures after CP3, making it impossible to analyze the wafer and determine if they are genuine data retention failures, leading to direct wafer rejection. This situation requires early warning or early detection. This is because the post-erase current of some bits in some chips is slightly above the threshold. After aging, the read current will be slightly below the threshold, thus identifying the chip as a data retention failure. When a wafer exhibits weak erase behavior, and a high proportion of such chips make up the total number of chips on the wafer, a high data retention failure rate will also be observed. According to industry practice, wafers with high data retention failure rates are scrapped entirely. However, analysis revealed that weakly erased chips do not actually have data retention issues. Summary of the Invention

[0009] In order to overcome the deficiencies of the above-mentioned prior art, the purpose of the present invention is to provide a test method for effectively distinguishing true and false data retention failures in flash memory, so as to improve the test efficiency and yield of wafers.

[0010] To achieve the above and other purposes, the present invention provides a method for effectively distinguishing true from false data retention failure in a flash memory, comprising the following steps:

[0011] Step S1, writing data: selecting a flash memory unit of the flash memory chip to write target data;

[0012] Step S2, first inspection: select a flash memory chip, read the data stored in each flash memory cell, compare the read current representing the stored data with the standard current to obtain read data, compare the read data with the written data, and classify the flash memory chips under test based on the comparison results. Those that fail the test are classified as ordinary defective products, and those that pass the test are classified as pending products.

[0013] Step S3: Perform a second check on the pending products from step S2 using the clamping standard current. Two clamping thresholds are generated for the read current by adding two first-level clamping test items. A second read operation is performed on the flash memory chip to be tested from the pending products to obtain the read current. The read current is compared with the two clamping thresholds and the chips are classified again. Based on the classification results, the number of chips on the wafer is statistically classified. Those that pass are defined as first-class pending products, and those that fail are defined as second-class pending products. The fail bit addresses of the second-class pending products are recorded.

[0014] Step S4, simulated aging: the first category of products to be confirmed and the second category of products to be confirmed are simultaneously placed in a simulated environment for simulated aging, simulating the condition of the flash memory chip after a period of use;

[0015] Step S5, performing a third inspection after the aging process: reading the data stored in each flash memory unit of the flash memory chip again, and comparing it with the written data again to determine good products, ordinary defective products, and data retention defective products.

[0016] Optionally, in step S2, the flash memory chips to be tested are classified according to the comparison results, and flash memory chips that do not meet the standards and flash memory chips that meet the standards are found and marked as common defective products and products to be confirmed, respectively.

[0017] Optionally, step S3 further includes:

[0018] Step S300 , selecting a flash memory chip in the product to be confirmed, reading data stored in each flash memory cell, and obtaining a read current representing the stored data;

[0019] Step S301 : adding two first-level clamping test items to generate a first clamping threshold and a second clamping threshold.

[0020] Step S302: Compare the obtained readout current representing the stored data with the first clamping threshold and the second clamping threshold, mark the failure status accordingly based on the comparison result, and classify the products into the first category of pending confirmation and the second category of pending confirmation, and record the failure bit address of the products in the second category of pending confirmation;

[0021] Optionally, the clamping one gear refers to increasing or decreasing the comparison threshold of the read current by a set ratio to make the read current determination more stringent, and the range of the set ratio is 5% to 15%.

[0022] Optionally, in step S301, when the judgment is "0", the read current is required to be less than a first set threshold, and the first set threshold is lowered by the first set ratio by clamping the first gear setting ratio as the first clamping threshold; when the judgment is "1", the read current is required to be greater than a second set threshold, and the second set threshold is increased by the second set ratio by clamping the first gear setting ratio as the second clamping threshold.

[0023] Optionally, in step S4, the flash memory chip is placed in a simulation environment for processing to simulate the condition of the flash memory chip after being used for a period of time.

[0024] Optionally, in step S5, the chips that pass the third inspection are marked as good products. For the chips that fail the third inspection, it is necessary to determine whether the marked data they carry is the first category of pending confirmation products or the second category of pending confirmation products. If the marked data they carry is the first category of pending confirmation products, they are defined as data-retained defective products. If the marked data they carry is the second category of pending confirmation products and the failure address is within the failure bit address range recorded in step S3, they are defined as ordinary defective products. Otherwise, they are defined as data-retained defective products.

[0025] Compared with the prior art, the present invention provides a test method for effectively distinguishing true and false data retention failures of flash memory by adding two clamping-one-level test items during the first inspection, and selecting the flash memory unit again for a read operation to obtain a read current. The corresponding flash memory unit is given a failure warning based on the read current and the two clamping thresholds, and the failure is recorded but not counted as a bad chip. The good products, ordinary defective products and data retention defective products are distinguished during the third inspection. If the proportion of data retention defective items in the data retention test to the entire wafer is too high, the high proportion of data retention defective products indicates that the entire wafer has a greater risk, and the wafer needs to be further analyzed and disposed of. After processing, there will be no weakly erased or weakly written chips in the data retention defective products, thereby achieving the purpose of improving the test efficiency and yield of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 The distribution diagram of the memory cell read 1 current Ir1;

[0027] Figure 2a Test normal flow chart for existing flash memory;

[0028] Figure 2b Test flow chart for current customer requirements;

[0029] Figure 3 It is a test flow chart of the present invention;

[0030] Figure 4 The present invention is a flowchart of the steps of a test method for effectively distinguishing true and false data retention failure in flash memory. DETAILED DESCRIPTION

[0031] The following describes the embodiments of the present invention using specific examples and accompanying drawings. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through other different specific examples, and the details in this specification may be modified and altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] Figure 3 This is a flow chart of the steps of a test method for effectively distinguishing true and false data retention failure in a flash memory according to the present invention. Figure 3 As shown, the present invention provides a test method for effectively distinguishing true and false data retention failure in a flash memory, comprising the following steps:

[0033] Step S1, writing data, i.e. writing data during the first probe test CP1: selecting the flash memory cell of the flash memory chip to write the target data (including 0 and 1). Specifically, writing data to each storage cell of the flash memory chip, and the data is stored in the corresponding address;

[0034] Step S2, the first inspection, that is, the first inspection during the first probe test CP1: select a flash memory chip, read the data stored in each flash memory unit, compare the read current representing the stored data with the standard current (first standard current, second standard current) and digitize it to obtain the read data, compare the read data with the written target data, and classify the flash memory chips to be tested according to the comparison results, find out the flash memory chips that do not meet the standards (NG1), and set a mark according to the "ordinary defective product" classification, and continue testing the ones that pass the standard and are marked as pending confirmation products (OK1).

[0035] For example, if the read current of the flash memory cell with the information "0" written is less than the first standard current (the first set threshold), the read data is considered to be "0". At this time, the read data is consistent with the written information "0", and the flash memory cell is considered to be a flash memory cell that meets the standards (this test passes, Pass), that is, the product to be confirmed (OK1). Similarly, if the read current of the flash memory cell with the information "1" written is greater than the second standard current (the second set threshold), the read data is considered to be "1". At this time, the read data is consistent with the written information "1", and the flash memory cell is considered to be a flash memory cell that meets the standards (this test passes, Pass). , Pass), that is, the product to be confirmed (OK1); on the contrary, if the read current of the flash memory cell with the information "0" written is greater than the first standard current, at this time, the read data is different from the written information "0", and the flash memory cell is considered to be a flash memory cell that does not meet the standards (this test fails, Fail), that is, a common defective product (NG1). Similarly, if the read current of the flash memory cell with the information "1" written is less than the second standard current, the read data is different from the written information "1", and at this time, the flash memory cell is considered to be a flash memory cell that does not meet the standards (this test fails, Fail), that is, a common defective product (NG1).

[0036] In step S3, the products to be confirmed in step S2 are checked a second time using the clamping standard current. Two clamping thresholds are generated for the current during readout by adding two clamping-level test items. A second read operation is performed on the flash memory chip to be tested from the products to be confirmed, obtaining the readout current. The readout current is compared with the two clamping thresholds and classified into two categories: products that meet the clamping standard (OK2, the first category of products to be confirmed, i.e., product 1) and products that do not meet the clamping standard (NG2, the second category of products to be confirmed, i.e., product 2). The bit address of the failed chip is also recorded.

[0037] Specifically, step S3 further includes:

[0038] Step S300 , selecting a flash memory chip, reading data stored in each flash memory cell, and obtaining a read current representing the stored data.

[0039] Step S301 : adding two first-level clamping test items to generate a first clamping threshold and a second clamping threshold (clamping standard).

[0040] Typically, in flash memory products, each storage bit has two states, 0 or 1. After programming, the read current is compared with the set threshold to determine whether it is correct. For example, when writing data 0, if the read current is less than the first set threshold, such as 5uA, it is judged as 0 (correct). For writing data 1, the read current must be greater than the second set threshold, such as 20uA, to be judged as 1 (correct). Otherwise, it is considered a write failure.

[0041] In the present invention, the so-called tightening one gear refers to raising or lowering the comparison threshold of the read current by a set ratio, so as to make the determination of the read current more stringent. In a specific embodiment of the present invention, the set ratio ranges from 5% to 15%.

[0042] Specifically, assuming that a first set ratio for the first clamping level setting for reading a "0" is determined to be 10%, this ratio is determined based on the flash memory situation. To determine a "0," the read current must be less than a first set threshold. The present invention reduces the first set threshold by the first set ratio, for example, from 5 uA to 5*(1-10%)=4.5 uA, to serve as the first clamping threshold. This means that memory cells with a read current less than the first clamping threshold are marked as pass, and otherwise as fail. To determine a "1," the read current must be greater than a second set threshold. assuming that a second set ratio for the first clamping level setting for reading a "1" is determined to be 5%, the present invention increases the second set threshold by the second set ratio, for example, from 20 uA to 20*(1+5%)=21 uA, to serve as the second clamping threshold. This means that memory cells with a read current greater than the second clamping threshold are marked as pass, and otherwise as fail.

[0043] In step S302, the read current representing the stored data is compared with the first clamping threshold and the second clamping threshold. The failure is marked accordingly based on the comparison result, and the failure is divided into the first category of unconfirmed products and the second category of unconfirmed products, i.e., unconfirmed product 1 and unconfirmed product 2. At the same time, the bit address of the chip failure is recorded.

[0044] Specifically, the read current is further inspected, and this time the inspection uses stricter standards. The present invention adds two clamping test items to record failures but not count them as bad dies or defective products. That is, the judgment of 0 and 1 is strictly clamped, for example, 10% and 5% respectively. After clamping, the bare dies judged as passed (OK2, the first category of pending confirmation) and failed (NG2, the second category of pending confirmation) are marked. For example, the marks are A failure warning (binA, read 0 failure warning) and B failure warning (binB, read 1 failure warning). Of course, other failure warning numbers can also be used. The principle is that they do not conflict with the established failure warning numbers. These failed bare dies are not counted as bad dies or defective products and will continue to undergo subsequent screening tests.

[0045] In a specific embodiment of the present invention, an example of tightening the threshold by one level is as follows:

[0046] Program: M0, when reading "0", if it is less than the threshold current, it is judged as "0". The first set threshold is 5uA. When the first clamping threshold current changes from 5 to 4.5 (decreases when clamping, such as by 10%), that is, when the read current of the selected flash memory cell is greater than 4.5uA (the first clamping threshold), the corresponding die position is marked as binA;

[0047] Erase: M1, when reading "1", if it is greater than the threshold current, it is judged as "1". The second set threshold is 20uA. When the second clamping threshold current changes from 20 to 21 (it increases when clamping, such as by 5%), that is, when the read current is less than 21uA (the second clamping threshold), the corresponding die position is marked as binB.

[0048] Step S4, normal simulated aging test: The flash memory chips of the first category of products to be confirmed and the second category of products to be confirmed with the target data previously written therein are placed in a simulated environment for processing, such as baking the flash memory chips under high temperature and pressure, to simulate the condition of the flash memory chips after a period of use (for example, simulating the condition of the flash memory chips reaching their 10-year service life).

[0049] Step S5, after the simulated aging treatment in step S4, the third readout test (CP3) is performed, and the chips that meet the standards (OK3, OK4) are marked as "good products", and the chips that do not meet the standards (NG3, NG4) need to be judged by the marking data they carry. The chip with the marking data of the unconfirmed product 1 (NG3) is a "data-retained defective product", and the chip with the marking data of the unconfirmed product 2 (NG4), if all the NG4 failure addresses are included in the failure address list when it is judged as the unconfirmed product 2 (NG2), it is listed as an "ordinary defective product", otherwise it is also listed as a data-retained defective product.

[0050] When all chips on a wafer have been tested, it is necessary to check the proportion of chips defined as data retention defectives to all chips on the wafer. If the proportion exceeds a certain level, the wafer may have data retention reliability issues and may require further analysis and clarification.

[0051] For example, a die-to-die correlation analysis is performed to check whether the die with data retention DR failure is the die marked as failure warning binA / B in step S3, so that appropriate measures can be taken, such as placing the wafer in a simulated environment and performing high-temperature pressurized epitaxial baking (extension bake) on the flash memory chip to check whether further failure processing is needed to improve the yield. This measure does not fall within the scope of the present invention.

[0052] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any skilled artisan may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the appended claims.

Claims

1. A method for effectively distinguishing true from false data retention failure in flash memory, comprising the following steps: Step S1, writing data: selecting a flash memory unit of the flash memory chip to write target data; Step S2, first inspection: select a flash memory chip, read the data stored in each flash memory cell, compare the read current representing the stored data with the standard current to obtain the read data, compare the read data with the written target data, and classify the flash memory chips under test based on the comparison results. Those that fail the test are classified as ordinary defective products, and those that pass the test are classified as pending products. Step S3: Perform a second check on the pending products from step S2 using the clamping standard current. Two clamping thresholds are generated for the read current by adding two first-level clamping test items. A second read operation is performed on the flash memory chip to be tested from the pending products to obtain the read current. The read current is compared with the two clamping thresholds and the chips are classified again. Based on the classification results, the number of chips on the wafer is statistically classified. Those that pass are defined as first-class pending products, and those that fail are defined as second-class pending products. The fail bit addresses of the second-class pending products are recorded. Step S4, simulated aging: the first category of products to be confirmed and the second category of products to be confirmed are simultaneously placed in a simulated environment for simulated aging, simulating the condition of the flash memory chip after a period of use; Step S5, performing a third inspection after the aging process: reading the data stored in each flash memory unit of the flash memory chip again, and comparing it with the written data again to determine good products, ordinary defective products, and data retention defective products.

2. A test method for effectively distinguishing true from false data retention failure in flash memory according to claim 1, characterized in that: In step S2, the flash memory chips to be tested are classified according to the comparison results, and flash memory chips that do not meet the standards and flash memory chips that meet the standards are found and marked as ordinary defective products and pending confirmation products respectively.

3. A test method for effectively distinguishing true from false data retention failure in flash memory as claimed in claim 2, characterized in that: Step S3 further comprises: Step S300 , selecting a flash memory chip in the product to be confirmed, reading data stored in each flash memory cell, and obtaining a read current representing the stored data; Step S301, adding two first-level clamping test items to generate a first clamping threshold and a second clamping threshold; Step S302 , compare the obtained readout current representing the stored data with the first clamping threshold and the second clamping threshold, mark the failure status accordingly based on the comparison result, divide the products into the first category to be confirmed and the second category to be confirmed, and record the failure bit address of the products in the second category to be confirmed.

4. A test method for effectively distinguishing true from false data retention failure in a flash memory as claimed in claim 3, characterized in that: The tightening by one gear refers to raising or lowering the comparison threshold of the read current by a set ratio, so as to make the determination of the read current more stringent, and the range of the set ratio is 5% to 15%.

5. A test method for effectively distinguishing true from false data retention failure in a flash memory as claimed in claim 4, characterized in that: In step S301, when the judgment is "0", the read current is required to be less than a first set threshold, and the first set threshold is lowered by a first set ratio by tightening the ratio by one level to serve as the first clamping threshold. When the judgment is "1", the read current is required to be greater than a second set threshold, and the second set threshold is raised by a second set ratio by tightening the ratio by one level to serve as the second clamping threshold.

6. A test method for effectively distinguishing true from false data retention failure in a flash memory as claimed in claim 5, characterized in that: In step S4, the flash memory chip to which data has been written is placed in a simulation environment for processing to simulate the condition of the flash memory chip after being used for a period of time.

7. A method for effectively distinguishing true from false data retention failure in a flash memory according to claim 6, characterized in that: In step S5, the chips that pass the third inspection are marked as good products. For the chips that fail the third inspection, it is necessary to determine whether the marked data they carry is the first category of pending confirmation products or the second category of pending confirmation products. If the marked data they carry is the first category of pending confirmation products, they are defined as data-retained defective products. If the marked data they carry is the second category of pending confirmation products and the address is within the failure bit address range recorded in step S3, they are defined as ordinary defective products. Otherwise, they are defined as data-retained defective products.

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