A method of generating test vectors for testing a memory

Abstract

The application provides a method for generating a test vector for testing a memory, wherein the method comprises generating a table, the table comprising a functional area in column form and a cycle period in row form, the functional area comprising an assignment area, an operation change area and a cycle jump area, the assignment area completing assignment of different registers of the memory, the operation change area defining whether different registers represented by a current row need to perform operation change when executing a next cycle, and the cycle jump area defining a position of different registers represented by the current row when executing the next cycle and a cycle number; and generating the test vector by using the table. The application adopts a table filling type for generating the test vector, and the whole process only needs to fill corresponding information in the table, so that the operation is simple and convenient, and the table type test vector has strong intuitiveness and good readability.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a method for generating test vectors for testing memory. Background Technology

[0002] With the development of technology, the integrated circuit industry has been rapidly improved, and the quality and reliability of manufactured integrated circuit products have also been further enhanced. In order to ensure that integrated circuit products meet the requirements for use, integrated circuits need to be tested. Taking the testing process of memory chips as an example, when using automated test equipment (ATE) to perform various tests on the device under test, firstly, test vectors need to be generated, and the generated test vectors are used as excitation signals input to the device under test. Then, the output response of the device under test is used to detect whether the device under test is qualified. It can be seen that the generation of test vectors is crucial to the testing efficiency and test results of memory chips.

[0003] Two particularly important concepts in memory chips are the location of the memory cell (address) and the data stored in that cell. The number of memory cells roughly represents the memory capacity. With technological advancements, the storage capacity of a single memory chip is constantly increasing, and the requirements for the reliability of stored data are becoming increasingly stringent. This means that our testing requirements for memory chips are becoming more rigorous. The most basic requirement is that every memory cell should be tested. Therefore, traversing the entire memory cell space by changing addresses is a key characteristic of memory chip testing. In current technology, most memory test vectors are written in text format, assigning values ​​to address and data registers via text, and defining information such as the operations to be performed during register traversal. This writing process is complex and lacks intuitiveness. Summary of the Invention

[0004] The purpose of this invention is to provide a method for generating test vectors for testing memory, in order to solve the problems of complex writing process and lack of intuitiveness in reading caused by the use of text format to write test vectors in the prior art.

[0005] To address the aforementioned technical problems, this invention provides a method for generating test vectors for testing memory. The method includes: generating a table comprising a functional area represented by columns and a loop cycle represented by rows, wherein the intersection of each row and each column constitutes a cell; the functional area comprising an assignment area, an operation change area, and a loop jump area; the assignment area containing assignment information assigning values ​​to different registers of the memory; the operation change area containing operation change information defining whether the different registers represented by the current row need to undergo operation change in the next cycle; and the loop jump area containing loop jump information defining the position and number of loops of the different registers represented by the current row in the next cycle; and generating test vectors using the table.

[0006] Preferably, in the method for generating test vectors for testing the memory, the different registers include multiple address registers and data registers.

[0007] Preferably, in the method for generating test vectors for testing the memory, the assignment area includes assignment cells and blank cells. The assignment information included in the assignment cells assigns values ​​to different registers in the current cycle. The different registers in the cycle to which the blank cells belong retain the values ​​of the corresponding registers in the previous cycle.

[0008] Preferably, in the method for generating test vectors for testing the memory, the computational change region includes a first computational change region and a second computational change region. The first computational change region contains first computational change information that defines whether the address register represented by the current row needs to undergo computational change when executing the next cycle. The second computational change region contains second computational change information that defines whether the data register represented by the current row needs to undergo computational change when executing the next cycle.

[0009] Preferably, in the method for generating test vectors for testing the memory, the first operational change region includes a first data cell and a hold cell, wherein the first data in the first data cell defines the address change of the address register in the current cycle when executing the next cycle, and the hold data in the hold cell defines the address of the address register in the current cycle when executing the next cycle remains unchanged.

[0010] Preferably, in the method for generating test vectors for testing the memory, the second operational change region includes a second data cell and a hold cell, wherein the second data in the second data cell defines the inversion of the value of the data register in the current cycle when the next cycle is executed.

[0011] Preferably, in the method for generating test vectors for testing the memory, the loop jump region includes a jump position region and an execution count region. The jump position region contains jump position information that defines the cycle position to jump to when the register is currently executing the loop, and the execution count region contains execution count information that defines the number of times the register loop executes the current cycle.

[0012] Preferably, in the method for generating test vectors for testing the memory, the jump position area includes indicator cells and automatic jump cells, the indicator cells contain indicator labels, and each register executes the loop cycle specified by the indicator label after completing the current cycle.

[0013] Preferably, in the method for generating test vectors for testing the memory, the indicator label is also located in the cell preceding the loop cycle, indicating the specific loop cycle in which a loop jump needs to be performed.

[0014] Preferably, in the method for generating test vectors for testing the memory, the execution count area includes numerical cells, where the value in the numerical cell defines the number of times each register needs to execute the current cycle. Each time the execution is performed, the value in the corresponding numerical cell is decremented by one until it reaches zero, at which point the current cycle execution ends.

[0015] In summary, this invention provides a method for generating test vectors for testing memory. The method includes generating a table comprising a functional area represented by columns and a loop period represented by rows. The intersection of each row and each column constitutes a cell. The functional area includes an assignment area, an operation change area, and a loop jump area. The assignment area contains assignment information to assign values ​​to different registers in the memory. The operation change area contains operation change information defining whether the different registers represented by the current row need to undergo operation changes in the next cycle. The loop jump area contains loop jump information defining the position and number of loops for the different registers represented by the current row in the next cycle. The method also involves generating test vectors using the table. This invention replaces the existing method of generating test vectors in text format with a table-based approach. The entire process only requires filling in the corresponding information in the table, making it simple and convenient. Furthermore, the tabular test vectors are highly intuitive and easy to read. Attached Figure Description

[0016] Figure 1 This is a flowchart of the method for generating test vectors provided in Embodiment 1 of the present invention;

[0017] Figure 2 This is a schematic diagram of the functional area and cycle of Table 1 provided in Embodiment 1 of the present invention;

[0018] Figure 3 This is a traversal test characterization diagram of Table 1 provided in Embodiment 1 of the present invention. Detailed Implementation

[0019] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the testing method for test vectors proposed in this invention. The advantages and features of this invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise scales, intended only to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales.

[0020] The core idea of ​​this invention is to provide a method for generating test vectors for testing memory. The method includes generating a table comprising a functional area represented by columns and a loop cycle represented by rows, with each cell being the intersection of each row and each column. The functional area includes an assignment area, an operation change area, and a loop jump area. The assignment area contains assignment information that assigns values ​​to different registers in the memory. The operation change area contains operation change information that defines whether the different registers represented by the current row need to undergo operation changes in the next cycle. The loop jump area contains loop jump information that defines the position and number of loops for the different registers represented by the current row in the next cycle. The method also involves generating test vectors using the table.

[0021] Instead of the existing text editing method, test vectors are generated by filling in a form. The whole process only requires filling in the corresponding information in the corresponding position of the form. It is not only easy to operate, but the tabular test vectors are also more intuitive and easier to read.

[0022] Next, this application will further describe the table in conjunction with several specific embodiments.

[0023] Example 1

[0024] First, please combine Figure 2 and Table 1, Figure 2 This is a schematic diagram of the functional areas and cycle of Table 1, in which... Figure 2 The area displayed is A, which is the assignment area; B, which is the operation and change area; and C, which is the loop jump area. The loop period is represented by rows, hence... Figure 2As shown in Table 1, it includes the first cycle, the second cycle, the third cycle, the fourth cycle, and the fifth cycle.

[0025] Table 1

[0026]

[0027] As shown in Table 1, Table 1 includes functional areas represented by columns and cycle periods represented by rows. The intersection of each row and each column is a cell. The assignment information included in the assignment area in Table 1 completes the assignment of values ​​to different registers in the memory. Specifically, the registers include address registers and data registers. In the first cycle, X is taken from XAini, Y from YAini, and data is taken from the Dataini register. The initialization position of the above registers in Table 1 is defined to be directly used in the current row, that is, X = 0X555, Y = 000, Data = 0XAA.

[0028] In this first embodiment, the assignment area includes assignment cells and blank cells. The assignment information included in the assignment cells assigns values ​​to different registers within the current cycle. The different registers of the cycle to which the blank cell belongs continue the values ​​of the corresponding registers of the previous cycle. For example, in the second cycle, X is taken from XBini, Y from YBini, and data is taken from the Dataini register. At this time, the blank cells included in the assignment area of ​​the second cycle represent that the different registers of the cycle to which the blank cell belongs continue the values ​​of the corresponding registers of the previous cycle, that is, X = 0X7AA, Y = 000, Data = 0X55.

[0029] In the third cycle, X is taken from XAini, Y from YAini, and data is taken from the Dataini register. At this time, XAini is reassigned to 0X2AA. Therefore, the third cycle indicates that the address signal input is X = 0X2AA, Y = 000, and Data = 0XA0.

[0030] In the fourth cycle, X is taken from XC, Y from YC, and data is taken from the Dataini register. XC is defined as XC = XCini + XCinc * n, where n is the number of times the current line has been executed.

[0031] In the fifth cycle, X takes its value from XCini, i.e., X = 0, and Y takes its value from YC. YC is defined as YC = YCini + YCinc * m, where m is the number of times the current line has been executed.

[0032] Furthermore, the loop jump area in Table 1 includes a jump position area and an execution count area. The jump position area contains jump position information that defines the cycle position to jump to when the register is currently executing the loop. The execution count area contains execution count information that defines the number of times the register executes the current cycle. Further, the jump position area includes an indicator cell and an automatic jump cell. The indicator cell contains an indicator label. After each register completes the current cycle, it executes the loop cycle specified by the indicator label. Moreover, the indicator label is also located in the cell preceding the loop cycle, used to indicate the specific loop cycle in which a loop jump needs to be performed.

[0033] In addition, the execution count area includes numerical cells, where the value in the numerical cells defines the number of times each register needs to execute the current cycle. Each time the execution is performed, the value in the corresponding numerical cell is decremented by one until it reaches zero, at which point the current cycle execution ends.

[0034] For example, please refer to Table 1. In the first cycle, the corresponding cell in the jump position area is an automatically jump cell, i.e., a blank cell. After the register finishes executing the first cycle, it will automatically jump to execute the next cycle, i.e., the second cycle. In the first cycle, the value in the corresponding value cell in the execution count area is 1. After each register executes the first cycle once, the value in the corresponding value cell in the execution count area is reduced by 1 to 0, i.e., the loop execution of the current cycle ends.

[0035] In the fourth cycle, if the corresponding indicator cell in the jump position area contains the indicator label CYC1, then after the register completes the current fourth cycle, it jumps to the first cycle pointed to by the indicator label CYC1; if the value in the corresponding numerical cell in the execution count area is #800, then the first cycle pointed to by the indicator label CYC1 will cycle a total of #800 times between the fourth cycle and the fourth cycle.

[0036] Similarly, in the fifth cycle, after the register finishes executing the current fifth cycle, it jumps to the first cycle pointed to by the indicator label CYC1, and the value in the corresponding numerical cell contained in the execution count area is #80. Then, the first cycle pointed to by the indicator label CYC1 cycles a total of #80 times between the first cycle and the fifth cycle.

[0037] In this first embodiment, the operation change region includes a first operation change region and a second operation change region. The first operation change region contains first operation change information that defines whether the address register represented by the current row needs to undergo operation change when executing the next cycle. The second operation change region contains second operation change information that defines whether the data register represented by the current row needs to undergo operation change when executing the next cycle.

[0038] Furthermore, the first operational change area includes a first data cell and a hold cell. The first data in the first data cell defines the address change of the address register in the current cycle when executing the next cycle, and the hold data in the hold cell defines the address of the address register in the current cycle when executing the next cycle remains unchanged; for example, combined with Figure 1 In Table 1, the cell to be kept is represented by 0 or blank, which means that the address of the address register in the current cycle remains unchanged when the next cycle is executed; the first data in the first data cell includes 1 or -1. For example, in the fourth cycle, if the first data cell XCinc in the operation change area is 1, it means that the address of XC is incremented by 1 after the current cycle ends.

[0039] Furthermore, the second operational change area includes a second data cell and a hold cell, wherein the second data in the second data cell defines the inversion of the value of the data register in the current cycle when the next cycle is executed. Please continue to combine Figure 2 Referring to Table 1, the "keep" cell is represented by 0 or blank, indicating that the data register value remains unchanged when the next cycle is executed; the first data contained in the second data cell is inv, which means that the value of the data register is inverted when the next cycle is executed.

[0040] Please see Figure 3 Table 1 shows a zero-based X-direction priority traversal test graph. As can be seen from the graph, X changes from 000 to #7FF, and Y changes from 00 to #7F, thereby traversing and testing the entire memory cell space through address changes.

[0041]

Example 2

[0042] This second embodiment provides a method for generating test vectors for testing memory. Please refer to Table 2. The difference between this second embodiment and the first embodiment is that in this second embodiment, the Y address changes first, and the outer loop changes to the X address, as shown in the fourth and fifth cycles of Table 2. Therefore, this second embodiment will not elaborate on the table and method for generating test vectors; please refer to the description in the first embodiment for details.

[0043] Table 2

[0044]

[0045]

Example 3

[0046] This third embodiment provides a method for generating test vectors for testing memory. Please refer to Table 3. The difference between this third embodiment and the first embodiment is that, based on the first embodiment, the only change in the third embodiment is the data. During the program preparation process, it is only necessary to change the assignment of the data register in the table, as shown in the fourth cycle in Table 3. Therefore, this third embodiment will not elaborate on the table and method for generating test vectors; please refer to the description in the first embodiment for details.

[0047] Table 3

[0048]

[0049] In summary, this invention provides a method for generating test vectors for testing memory. The method includes generating a table, which includes a functional area represented by columns and a loop period represented by rows. The intersection of each row and each column forms a cell. The functional area includes an assignment area, an operation change area, and a loop jump area. The assignment area contains assignment information to assign values ​​to different registers in the memory. The operation change area contains operation change information defining whether the different registers represented by the current row need to undergo operation changes in the next cycle. The loop jump area contains loop jump information defining the position and number of loops for the different registers represented by the current row in the next cycle. The method also involves generating test vectors using the table. This invention uses a table-based method to generate test vectors instead of the text-based method used in the prior art. The entire process only requires filling in the corresponding information in the table, making it simple and convenient. Furthermore, the tabular test vectors are highly intuitive and easy to read.

[0050] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

Claims

1. A method for generating test vectors for testing memory, characterized in that, The method includes: A table is generated, comprising a functional area represented by columns and a loop cycle represented by rows. The intersection of each row and each column forms a cell. The functional area includes an assignment area, an operation / change area, and a loop jump area. The assignment area assigns values ​​to different registers in memory. The operation / change area defines whether the different registers represented by the current row need to undergo operation / change in the next cycle. The loop jump area defines the position and loop count of the different registers represented by the current row in the next cycle. Use the table to generate test vectors; The different registers include multiple address registers and data registers; The operation change region includes a first operation change region and a second operation change region. The first operation change region contains first operation change information that defines whether the address register represented by the current row needs to undergo operation change when executing the next cycle. The second operation change region contains second operation change information that defines whether the data register represented by the current row needs to undergo operation change when executing the next cycle.

2. The method for generating test vectors for testing memory as described in claim 1, characterized in that, The assignment area includes assignment cells and blank cells. The assignment information included in the assignment cells assigns values ​​to different registers in the current cycle. The different registers in the cycle to which the blank cells belong retain the values ​​of the corresponding registers in the previous cycle.

3. The method for generating test vectors for testing memory as described in claim 1, characterized in that, The first operational change area includes a first data cell and a hold cell. The first data in the first data cell defines the address change of the address register in the current cycle when the next cycle is executed. The hold data in the hold cell defines the address of the address register in the current cycle when the next cycle is executed.

4. The method for generating test vectors for testing memory as described in claim 1, characterized in that, The second operational change area includes a second data cell and a hold cell. The second data in the second data cell defines the value of the data register in the current cycle as the data register is inverted when the next cycle is executed.

5. The method for generating test vectors for testing memory as described in claim 1, characterized in that, The loop jump region includes a jump position region and an execution count region. The jump position region contains jump position information that defines the cycle position to jump to when the register is currently executing the loop. The execution count region contains execution count information that defines the number of times the register executes the current cycle.

6. The method for generating test vectors for testing memory as described in claim 5, characterized in that, The jump position area includes indicator cells and automatic jump cells. The indicator cells contain indicator labels. After each register completes the current cycle, it executes the cycle specified by the indicator label.

7. The method for generating test vectors for testing memory as described in claim 6, characterized in that, The indicator label is also located in the cell preceding the cycle and is used to indicate the specific cycle in which a cycle jump needs to be performed.

8. The method for generating test vectors for testing memory as described in claim 5, characterized in that, The execution count area includes numerical cells, where the value in each numerical cell defines the number of times each register needs to execute the current cycle. Each time the cycle is executed, the value in the corresponding numerical cell is decremented by one until it reaches zero, at which point the current cycle execution ends.

Images