Shielded gate trench MOSFET and method of making the same

Abstract

The application provides a shielded gate trench MOSFET and a manufacturing method thereof, which comprises a drain layer, a first epitaxial layer, a second epitaxial layer, a first trench, a second trench, a first dielectric layer, a source conductive layer, a gate trench, a gate dielectric layer, a gate conductive layer, a body region, a source region, a source line layer and a gate line layer. The application connects the source conductive layer, the source region and the body region to the source line layer through a via, connects the gate conductive layer of part of the trench to the gate line layer through a hole, and connects the gate conductive layer of adjacent trenches to the source line layer through a via, so as to reduce the zero temperature coefficient cross point of the device, improve the working capacity of the device in the linear working area, significantly reduce the gate capacitance and the gate-source capacitance of the device, improve the switching frequency of the device, and enable the device to be applied to application occasions requiring higher switching frequency. In addition, the manufacturing method of the application is compatible with the manufacturing process of common structures, and does not increase additional cost.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuit design and manufacturing technology, and relates to a shielded gate trench MOSFET and a manufacturing method thereof. BACKGROUND

[0002] The shielded gate trench metal-oxide-semiconductor field-effect transistor (MOSFET) is currently the best low-voltage power rectifier and switching device, which can simultaneously achieve extremely low specific on-resistance (Ron_specific) and miller capacitance (Cgd) by using the charge compensation principle, and the figure of merit (FOM) is extremely excellent. However, the linear operating region capability of such a device is relatively weak, and there is a risk of burning out of the MOSFET device for applications such as hot-swap, e-fuse controller, load-switch controller, etc. In addition, the gate capacitance (Cg) of the MOSFET is required to be more stringent for synchronous rectification applications requiring fast switching.

[0003] The existing device has poor linear operating region capability, which makes the device prone to burn out in some applications. At the same time, the gate capacitance (Cg) and the gate-source capacitance (Cgs) of the entire device are relatively large, which affects the switching speed of the device. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a shielded gate trench MOSFET and a manufacturing method thereof, which are used to solve the problems of easy burning out and slow switching speed of the existing shielded gate trench MOSFET.

[0005] To achieve the above-mentioned purposes and other related purposes, the present application provides a manufacturing method of a shielded gate trench MOSFET, comprising the following steps:

[0006] A substrate is provided, a first epitaxial layer is formed on the substrate, and a second epitaxial layer is formed on the first epitaxial layer, the substrate, the first epitaxial layer and the second epitaxial layer are all of a first conductivity type;

[0007] First and second trenches are formed adjacent to and spaced apart, the first and second trenches are both open from the upper surface of the second epitaxial layer and extend downward, the bottom surfaces of the first and second trenches are both higher than the upper surface of the substrate;

[0008] sequentially forming a first dielectric layer and a source conductive layer in the first trench and the second trench, the first dielectric layer covering inner walls of the first trench and the second trench and covering a sidewall of the source conductive layer;

[0009] removing a part of the first dielectric layer on upper parts of the first trench and the second trench to obtain gate trenches on two sides of the source conductive layer, sequentially forming a gate dielectric layer and a gate conductive layer in the gate trenches, the gate dielectric layer covering inner walls of the gate trenches and covering a sidewall of the gate conductive layer;

[0010] forming a body region on an upper surface layer of the second epitaxial layer and forming a source region on an upper surface layer of the body region, the body region and the source region being of a second conductive type opposite to a first conductive type;

[0011] forming a second dielectric layer on the second epitaxial layer and forming a first via hole, a second via hole, a third via hole, a fourth via hole and a fifth via hole in the second dielectric layer, a bottom of the first via hole exposing the source conductive layer in the first trench, a bottom of the second via hole exposing the source conductive layer in the second trench, the third via hole extending into the body region to expose the source region and the body region, a bottom of the fourth via hole exposing the gate conductive layer in the second trench, and a bottom of the fifth via hole exposing the gate conductive layer in the first trench;

[0012] forming a source line layer and a gate line layer, the source line layer being filled into the first via hole, the second via hole, the third via hole and the fourth via hole, and the gate line layer being filled into the fifth via hole.

[0013] Optionally, a doping concentration of the first epitaxial layer is higher than a doping concentration of the second epitaxial layer, and a total thickness of the first epitaxial layer and the second epitaxial layer ranges from 8 to 20 microns.

[0014] Optionally, a groove depth of the first trench and the second trench ranges from 5 to 10 microns.

[0015] Optionally, a thickness of a part of the first dielectric layer on sidewalls of the first trench and the second trench ranges from 500 to 1000 nanometers.

[0016] Optionally, a material of the source conductive layer and the gate conductive layer comprises conductive polysilicon, a material of the source line layer and the gate line layer comprises conductive metal, the body region is obtained by doping an upper surface layer of the second epitaxial layer, and the source region is obtained by doping an upper surface layer of the body region.

[0017] The application further provides a shielded gate trench MOSFET, comprising:

[0018] a drain layer;

[0019] a first epitaxial layer on the drain layer;

[0020] a second epitaxial layer on the first epitaxial layer;

[0021] a first trench and a second trench adjacent and spaced apart, both the first trench and the second trench are open from the upper surface of the second epitaxial layer and extend downward, the bottom surface of the first trench and the second trench are higher than the upper surface of the drain layer;

[0022] a first dielectric layer and a source conductive layer in the first trench and the second trench, the first dielectric layer covers the inner wall of the first trench and the second trench, and covers the sidewall of the source conductive layer;

[0023] a gate trench on the upper part of the first trench and the second trench and on both sides of the source conductive layer, the gate trench is provided with a gate dielectric layer and a gate conductive layer, the gate dielectric layer covers the inner wall of the gate trench and covers the sidewall of the gate conductive layer;

[0024] a body region on the upper surface layer of the second epitaxial layer;

[0025] a source region on the upper surface layer of the body region;

[0026] a source line layer above the second epitaxial layer, the source conductive layer in the first trench, the source conductive layer in the second trench, the gate conductive layer in the second trench, the body region and the source region are all electrically connected to the source line layer;

[0027] a gate line layer above the second epitaxial layer, the gate conductive layer in the first trench is electrically connected to the gate line layer;

[0028] wherein the drain layer, the first epitaxial layer and the second epitaxial layer are of a first conductivity type, the body region and the source region are of a second conductivity type opposite to the first conductivity type.

[0029] Optionally, the doping concentration of the first epitaxial layer is higher than the doping concentration of the second epitaxial layer, and the total thickness of the first epitaxial layer and the second epitaxial layer ranges from 8 to 20 microns.

[0030] Optionally, the depth of the first trench and the second trench ranges from 5 to 10 microns.

[0031] Optionally, the thickness of the first dielectric layer on part of the sidewall of the first trench and the second trench ranges from 500 to 1000 nanometers.

[0032] Optionally, the material of the source conductive layer and the gate conductive layer comprises conductive polysilicon, and the material of the source line layer and the gate line layer comprises conductive metal.

[0033] As described above, the shielded gate trench MOSFET and the manufacturing method thereof change the connection of the gate conductive layer, connect the source conductive layer, the source region and the body region to the source line layer through the via, open the gate conductive layer of part of the trench to the gate line layer, and connect the gate conductive layer of the adjacent trench to the source line layer through the via, thereby reducing the zero temperature coefficient cross point (ZTC) of the device, improving the working ability of the device in the linear working area, significantly reducing the gate capacitance (Cg) and the gate-source capacitance (Cgs) of the device, improving the switching frequency of the device, and enabling the device to be applied in application occasions requiring higher switching frequency. In addition, the manufacturing method of the shielded gate trench MOSFET of the present application is compatible with the manufacturing process of the common structure, and does not increase additional cost. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A cross-sectional structure schematic diagram of a shielded gate trench power MOSFET is shown.

[0035] Figure 2 A structure schematic diagram after forming a first epitaxial layer on the substrate and forming a second epitaxial layer on the first epitaxial layer in the manufacturing method of the shielded gate trench MOSFET of the present application is shown.

[0036] Figure 3 A structure schematic diagram after forming first and second trenches arranged adjacent to and spaced apart in the manufacturing method of the shielded gate trench MOSFET of the present application is shown.

[0037] Figure 4 A structure schematic diagram after sequentially forming a first dielectric layer and a source conductive layer in the first trench and the second trench in the manufacturing method of the shielded gate trench MOSFET of the present application is shown.

[0038] Figure 5 A structure schematic diagram after removing part of the first dielectric layer located on the upper part of the first trench and the second trench to obtain a gate trench located on both sides of the source conductive layer in the manufacturing method of the shielded gate trench MOSFET of the present application is shown.

[0039] Figure 6 A structure schematic diagram after sequentially forming a gate dielectric layer and a gate conductive layer in the gate trench in the manufacturing method of the shielded gate trench MOSFET of the present application is shown.

[0040] Figure 7A structure diagram showing the structure of the shield gate trench MOSFET after forming the body region on the upper surface of the second epitaxial layer and forming the source region on the upper surface of the body region in the manufacturing method of the shield gate trench MOSFET.

[0041] Figure 8 A structure diagram showing the structure of the shield gate trench MOSFET after forming the second dielectric layer on the second epitaxial layer and forming the first via hole, the second via hole, the third via hole, the fourth via hole and the fifth via hole in the second dielectric layer in the manufacturing method of the shield gate trench MOSFET.

[0042] Figure 9 A structure diagram showing the structure of the shield gate trench MOSFET after forming the source line layer and the gate line layer in the manufacturing method of the shield gate trench MOSFET.

[0043] Element number explanation

[0044] 101 silicon substrate

[0045] 102 silicon epitaxial layer

[0046] 103 dielectric layer

[0047] 104 source polysilicon

[0048] 105 gate polysilicon

[0049] 106 gate oxide

[0050] 107 via hole

[0051] 108 second conductive type body region

[0052] 109 first conductive type source region

[0053] 110 second conductive type source region

[0054] 111 dielectric layer

[0055] 112 source metal

[0056] 113 trench

[0057] 201 substrate

[0058] 202 first epitaxial layer

[0059] 203 second epitaxial layer

[0060] 204 first trench

[0061] 205 second trench

[0062] 206 first dielectric layer

[0063] 207 source conductive layer

[0064] 208 gate trench

[0065] 209 gate dielectric layer

[0066] 210 gate conductive layer

[0067] 211 body region

[0068] 212 source region

[0069] 213 second dielectric layer

[0070] 214 first via

[0071] 215 second via

[0072] 216 third via

[0073] 217 fourth via

[0074] 218 source line layer DETAILED DESCRIPTION

[0075] The present application is herein described, by way of example only, with the

[0076] Please refer to Figures 1 to 9 It is to be understood that the figures included are only schematic and that the dimensions of the various components are not necessarily to scale, and that in actual implementations, the components can have different dimensions and / or shapes.

[0077] As Figure 1As shown, it is a sectional structure diagram of a shield gate trench power MOSFET, including a first conductive type silicon substrate 101, a first conductive type silicon epitaxial layer 102, a dielectric layer 103 (usually an oxide layer), a source polysilicon 104, a gate polysilicon 105, a gate oxide 106, a via 107, a second conductive type body region 108, a first conductive type source region 109, a second conductive type source region 110, a dielectric layer 111, a source metal 112 and a trench 113. In order to further reduce the on-resistance of the deep trench MOSFET, the shield gate trench power MOSFET is often matched with an epitaxial layer with a lower resistivity, but this reduces the working capacity of the device in the linear operating region, making the device prone to burnout in some applications; at the same time, the gate polysilicon 105 is connected to the gate (in another dimension), and the gate capacitance (Cg) and the gate-source capacitance (Cgs) of the entire device are relatively large, affecting the switching speed of the device.

[0078] Therefore, the present application provides a new shield gate trench MOSFET device, especially suitable for medium voltage segment MOSFET (100V-300V voltage resistance), which reduces the zero temperature coefficient cross point (ZTC) of the device by changing the connection method of the gate polysilicon, improves the working capacity of the device in the linear operating region; at the same time, the gate capacitance (Cg) and the gate-source capacitance (Cgs) of the device are significantly reduced, and the application switching frequency of the device is improved. The specific technical solutions of the present application are illustrated by specific examples as follows.

[0079] Example 1

[0080] The embodiment provides a manufacturing method of a shield gate trench MOSFET, including the following steps:

[0081] S1: providing a substrate, forming a first epitaxial layer on the substrate, and forming a second epitaxial layer on the first epitaxial layer, the substrate, the first epitaxial layer and the second epitaxial layer are all of a first conductive type;

[0082] S2: forming a first trench and a second trench adjacent and spaced apart, the first trench and the second trench are both opened from the upper surface of the second epitaxial layer and extend downward, the bottom surface of the first trench and the second trench is higher than the upper surface of the substrate;

[0083] S3: sequentially forming a first dielectric layer and a source conductive layer in the first trench and the second trench, the first dielectric layer covers the inner wall of the first trench and the second trench, and covers the sidewall of the source conductive layer;

[0084] S4: removing the first dielectric layer on the first trench and the upper portion of the second trench to obtain a gate trench on both sides of the source conductive layer, sequentially forming a gate dielectric layer and a gate conductive layer in the gate trench, the gate dielectric layer covering the inner wall of the gate trench and covering the sidewall of the gate conductive layer;

[0085] S5: forming a body region on the upper surface layer of the second epitaxial layer, and forming a source region on the upper surface layer of the body region, the body region and the source region being of a second conductivity type opposite to the first conductivity type;

[0086] S6: forming a second dielectric layer on the second epitaxial layer, and forming a first via hole, a second via hole, a third via hole, a fourth via hole and a fifth via hole in the second dielectric layer, the bottom of the first via hole exposing the source conductive layer in the first trench, the bottom of the second via hole exposing the source conductive layer in the second trench, the third via hole extending into the body region to expose the source region and the body region, the bottom of the fourth via hole exposing the gate conductive layer in the second trench, and the bottom of the fifth via hole exposing the gate conductive layer in the first trench;

[0087] S7: forming a source line layer and a gate line layer, the source line layer being filled into the first via hole, the second via hole, the third via hole and the fourth via hole, and the gate line layer being filled into the fifth via hole.

[0088] First, refer to Figure 2 , the step S1 is performed: providing a substrate 201, forming a first epitaxial layer 202 on the substrate 201, and forming a second epitaxial layer 203 on the first epitaxial layer 202, the substrate 201, the first epitaxial layer 202 and the second epitaxial layer 203 are of a first conductivity type, for example, P type or N type. Among them, the substrate 1 can be used as the drain of the shielded gate trench MOSFET.

[0089] As an example, the substrate 201, the first epitaxial layer 202 and the second epitaxial layer 203 can adopt silicon, germanium, germanium silicon, III-V compound or other suitable semiconductor materials, the doping concentration of the first epitaxial layer 202 is higher than that of the second epitaxial layer 203, and the total thickness of the first epitaxial layer 202 and the second epitaxial layer 203 ranges from 8 to 20 microns.

[0090] Then refer to Figure 3Step S2 is performed: a first trench 204 and a second trench 205 are formed by photolithography and etching processes. The first trench 204 and the second trench 205 open from the upper surface of the second epitaxial layer 202 and extend downward. The bottom surface of the first trench 204 and the second trench 205 is higher than the upper surface of the substrate 201.

[0091] As an example, the depth range of the first trench 204 and the second trench is 5-10 micrometers.

[0092] Please see again Figure 4 Step S3 is performed: a first dielectric layer 206 and a source conductive layer 207 are sequentially formed in the first trench 204 and the second trench 205 using chemical vapor deposition, physical vapor deposition or other suitable methods. The first dielectric layer 206 covers the inner walls of the first trench 204 and the second trench 205 and covers the side walls of the source conductive layer 207.

[0093] As an example, the first dielectric layer 206 is made of silicon oxide or other suitable insulating material, and the thickness of the portion of the first dielectric layer 206 located on the sidewalls of the first trench 204 and the second trench 205 ranges from 500 to 1000 nanometers. The source conductive layer 207 is made of conductive polycrystalline silicon.

[0094] Please see again Figure 5 and Figure 6 Perform step S4 as follows: Figure 5 As shown, the portion of the first dielectric layer 206 located above the first trench 204 and the second trench 205 is removed by dry etching and / or wet etching to obtain the gate trench 208 located on both sides of the source conductive layer 207, as follows. Figure 6 As shown, a gate dielectric layer 209 and a gate conductive layer 210 are sequentially formed in the gate trench 208 using chemical vapor deposition, physical vapor deposition, or other suitable methods. The gate dielectric layer 209 covers the inner wall of the gate trench 208 and the sidewall of the gate conductive layer 210.

[0095] As an example, the gate dielectric layer 209 is made of silicon oxide, and the gate conductive layer 210 is made of conductive polycrystalline silicon.

[0096] Please see again Figure 7 Step S5 is performed: a body region 211 is formed on the upper surface of the second epitaxial layer 203, and a source region 212 is formed on the upper surface of the body region 211. Both the body region 211 and the source region 212 are of the second conductivity type, which is opposite to the first conductivity type.

[0097] As an example, the body region 211 is formed by doping the upper surface of the second epitaxial layer 203, and the source region 212 is formed by doping the upper surface of the body region 211.

[0098] Referring back to Figure 8 , the step S6 is performed to form a second dielectric layer 213 on the second epitaxial layer 203 by chemical vapor deposition, physical vapor deposition or other suitable method, and to form a first via 214, a second via 215, a third via 216, a fourth via 217 and a fifth via (not shown, Figure 8 the cross-section of which is not shown in the drawing) in the second dielectric layer 213 by photolithography and etching process, the bottom of the first via 214 exposes the source conductive layer 207 in the first trench 204, the bottom of the second via 215 exposes the source conductive layer 207 in the second trench 205, the third via 216 extends into the body region 211 to expose the source region 212 and the body region 211, the bottom of the fourth via 217 exposes the gate conductive layer 210 in the second trench 205, and the bottom of the fifth via exposes the gate conductive layer 210 in the first trench 204.

[0099] As an example, the material of the second dielectric layer 213 includes silicon oxide, silicon nitride or other suitable insulating material.

[0100] Referring back to Figure 9 , the step S7 is performed to form a source line layer 218 and a gate line layer (not shown, Figure 8 the cross-section of which is not shown in the drawing) by physical vapor deposition or other suitable method, the source line layer 218 fills into the first via 214, the second via 215, the third via 216 and the fourth via 217, and the gate line layer fills into the fifth via.

[0101] As an example, the material of the source line layer 218 and the gate line layer includes copper, tungsten, gold, aluminum, platinum or other suitable conductive metal.

[0102] Thus, a shielded gate trench MOSFET is produced. The shielded gate trench MOSFET production method of the embodiment reduces the zero temperature coefficient cross point (ZTC) of the device, improves the working ability of the device in the linear working area, and significantly reduces the gate capacitance (Cg) and gate-source capacitance (Cgs) of the device, improves the switching frequency of the device, so that the device can be applied in application occasions requiring higher switching frequency. In addition, the shielded gate trench MOSFET production method of the embodiment is compatible with the manufacturing process of the common structure, and does not increase additional cost.

[0103] Embodiment Two

[0104] In the embodiment, a shielded gate trench MOSFET is provided, which can be produced by the shielded gate trench MOSFET production method described in Embodiment One or other suitable methods.

[0105] Please refer to Figure 9, shown as a cross-sectional structure schematic diagram of the shielded gate trench MOSFET, comprising a drain layer (substrate layer 1), a first epitaxial layer 202, a second epitaxial layer 203, a first trench 204, a second trench 205, a first dielectric layer 206, a source conductive layer 207, a gate trench 208, a gate dielectric layer 209, a gate conductive layer 210, a body region 211, a source region 212, a source line layer 218, and a gate line layer (not shown), wherein the drain layer, the first epitaxial layer 202, and the second epitaxial layer 203 are all of a first conductivity type, the body region 211 and the source region 212 are both of a second conductivity type opposite to the first conductivity type; the first epitaxial layer 202 is located on the drain layer; the second epitaxial layer 203 is located on the first epitaxial layer 202; the first trench 204 and the second trench 205 are adjacently and spacedly arranged, and both open from the upper surface of the second epitaxial layer 203 and extend downward, and the bottom surfaces of the first trench 204 and the second trench 205 are both higher than the upper surface of the drain layer; the first dielectric layer 206 and the source conductive layer 207 are both located in the first trench 204 and the second trench 205, the first dielectric layer 206 covers the inner walls of the first trench 204 and the second trench 205, and covers the sidewalls of the source conductive layer 207; the gate trench 208 is located on the upper parts of the first trench 204 and the second trench 205 and on both sides of the source conductive layer 207, the gate trench 208 is provided with the gate dielectric layer 209 and the gate conductive layer 210, the gate dielectric layer 209 covers the inner walls of the gate trench 208 and covers the sidewalls of the gate conductive layer 210; the body region 211 is located on the upper surface layer of the second epitaxial layer 203; the source region 212 is located on the upper surface layer of the body region 211; the source line layer 218 is located above the second epitaxial layer 203, the source conductive layer 207 in the first trench 204, the source conductive layer 207 in the second trench 205, the gate conductive layer 210 in the second trench 205, the body region 211, and the source region 212 are all electrically connected to the source line layer 218; the gate line layer is located above the second epitaxial layer 203, and the gate conductive layer 210 in the first trench 204 is electrically connected to the gate line layer.

[0106] As an example, the substrate 201, the first epitaxial layer 202 and the second epitaxial layer 203 can be made of silicon, germanium, germanium silicon, III-V compound or other suitable semiconductor material, the doping concentration of the first epitaxial layer 202 is higher than that of the second epitaxial layer 203, the total thickness of the first epitaxial layer 202 and the second epitaxial layer 203 ranges from 8 to 20 microns, the depth of the first trench 204 and the second trench 205 ranges from 5 to 10 microns, the material of the first dielectric layer 206 includes silicon oxide or other suitable insulating material, the thickness of the first dielectric layer 206 on the sidewall of the first trench 204 and the second trench 205 ranges from 500 to 1000 nanometers. The material of the source conductive layer 207 includes conductive polysilicon, the material of the gate dielectric layer 209 includes silicon oxide, the material of the gate conductive layer 210 includes conductive polysilicon, and the material of the source line layer 218 and the gate line layer includes copper, tungsten, gold, aluminum, platinum or other suitable conductive metal.

[0107] In the shielded gate trench MOSFET of the embodiment, the source conductive layer, the source region and the body region are connected to the source line layer through the via, the gate conductive layer of the partial trench is connected to the gate line layer through the opening, and the gate conductive layer of the adjacent trench is connected to the source line layer through the via, thereby reducing the zero temperature coefficient cross point (ZTC) of the device, improving the working ability of the device in the linear working area, significantly reducing the gate capacitance (Cg) and the gate-source capacitance (Cgs) of the device, improving the switching frequency of the device, and enabling the device to be applied in application occasions requiring higher switching frequency. The shielded gate trench MOSFET of the embodiment is particularly suitable for medium-voltage MOSFET (100V-300V voltage resistance).

[0108] In summary, the shielded gate trench MOSFET and the manufacturing method thereof change the connection method of the gate conductive layer, connect the source conductive layer, the source region and the body region to the source line layer through the via, connect the gate conductive layer of the partial trench to the gate line layer through the opening, and connect the gate conductive layer of the adjacent trench to the source line layer through the via, thereby reducing the zero temperature coefficient cross point (ZTC) of the device, improving the working ability of the device in the linear working area, significantly reducing the gate capacitance (Cg) and the gate-source capacitance (Cgs) of the device, improving the switching frequency of the device, and enabling the device to be applied in application occasions requiring higher switching frequency. In addition, the manufacturing method of the shielded gate trench MOSFET of the embodiment is compatible with the manufacturing process of the common structure, without increasing additional cost. Therefore, the shielded gate trench MOSFET effectively overcomes the shortcomings in the prior art and has high industrial utilization value.

[0109] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A method of fabricating a shielded gate trench MOSFET, comprising: The method comprises the following steps: providing a substrate, forming a first epitaxial layer on the substrate, and forming a second epitaxial layer on the first epitaxial layer, the substrate, the first epitaxial layer and the second epitaxial layer are all of a first conductive type; forming a first trench and a second trench which are adjacent and spaced, the first trench and the second trench are both open from the upper surface of the second epitaxial layer and extend downward, the bottom surface of the first trench and the second trench are both higher than the upper surface of the substrate; forming a first dielectric layer and a source conductive layer in the first trench and the second trench in sequence, the first dielectric layer covers the inner wall of the first trench and the second trench, and covers the sidewall of the source conductive layer; removing the part of the first dielectric layer on the upper part of the first trench and the second trench to obtain a gate trench on both sides of the source conductive layer, forming a gate dielectric layer and a gate conductive layer in the gate trench in sequence, the gate dielectric layer covers the inner wall of the gate trench and covers the sidewall of the gate conductive layer; forming a body region on the upper surface layer of the second epitaxial layer, and forming a source region on the upper surface layer of the body region, the body region and the source region are both of a second conductive type which is opposite to the first conductive type; forming a second dielectric layer on the second epitaxial layer, and forming a first via hole, a second via hole, a third via hole, a fourth via hole and a fifth via hole in the second dielectric layer, the bottom of the first via hole exposes the source conductive layer in the first trench, the bottom of the second via hole exposes the source conductive layer in the second trench, the third via hole extends into the body region to expose the source region and the body region, the bottom of the fourth via hole exposes the gate conductive layer in the second trench, and the bottom of the fifth via hole exposes the gate conductive layer in the first trench; forming a source line layer and a gate line layer, the source line layer fills into the first via hole, the second via hole, the third via hole and the fourth via hole, and the gate line layer fills into the fifth via hole.

2. The method of fabricating a shielded gate trench MOSFET of claim 1, wherein: The doping concentration of the first epitaxial layer is higher than the doping concentration of the second epitaxial layer, and the total thickness of the first epitaxial layer and the second epitaxial layer ranges from 8 to 20 microns.

3. The method of fabricating a shielded gate trench MOSFET of claim 1, wherein: The depth of the first trench and the second trench ranges from 5 to 10 microns.

4. The method of fabricating a shielded gate trench MOSFET of claim 1, wherein: The thickness of the part of the first dielectric layer on the sidewall of the first trench and the second trench ranges from 500 to 1000 nanometers.

5. The method of fabricating a shielded gate trench MOSFET of claim 1, wherein: The material of the source conductive layer and the gate conductive layer comprises conductive polysilicon, the material of the source line layer and the gate line layer comprises conductive metal, the body region is obtained by doping the upper surface layer of the second epitaxial layer, and the source region is obtained by doping the upper surface layer of the body region.

6. A shielded gate trench MOSFET, characterized by, comprise: a drain layer; a first epitaxial layer on the drain layer; a second epitaxial layer on the first epitaxial layer; a first trench and a second trench which are adjacent and spaced, the first trench and the second trench are both open from the upper surface of the second epitaxial layer and extend downward, the bottom surface of the first trench and the second trench are both higher than the upper surface of the drain layer; A first dielectric layer and a source conductive layer are located in the first trench and the second trench, the first dielectric layer covers the inner wall of the first trench and the second trench, and covers the sidewall of the source conductive layer; A gate trench is located on the upper part of the first trench and the second trench and on both sides of the source conductive layer, the gate trench is provided with a gate dielectric layer and a gate conductive layer, the gate dielectric layer covers the inner wall of the gate trench and covers the sidewall of the gate conductive layer; A body region is located on the upper surface layer of the second epitaxial layer; A source region is located on the upper surface layer of the body region; A source line layer is located above the second epitaxial layer, the source conductive layer in the first trench, the source conductive layer in the second trench, the gate conductive layer in the second trench, the body region and the source region are all electrically connected to the source line layer; A gate line layer is located above the second epitaxial layer, the gate conductive layer in the first trench is electrically connected to the gate line layer; Wherein, the drain layer, the first epitaxial layer and the second epitaxial layer are all of a first conductive type, the body region and the source region are all of a second conductive type opposite to the first conductive type.

7. The shielded gate trench MOSFET of claim 6, wherein: The doping concentration of the first epitaxial layer is higher than that of the second epitaxial layer, and the total thickness of the first epitaxial layer and the second epitaxial layer ranges from 8 to 20 microns.

8. The shielded gate trench MOSFET of claim 6, wherein: The groove depth of the first trench and the second trench ranges from 5 to 10 microns.

9. The shielded gate trench MOSFET of claim 6, wherein: The thickness of the part of the first dielectric layer located on the sidewall of the first trench and the second trench ranges from 500 to 1000 nanometers.

10. The shielded gate trench MOSFET of claim 6, wherein: The material of the source conductive layer and the gate conductive layer includes conductive polysilicon, and the material of the source line layer and the gate line layer includes conductive metal.

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