Two-dimensional multi-bridge channel transistor with self-aligned source-drain doping and method of fabrication

Abstract

The application provides a two-dimensional multi-bridge channel transistor with self-aligned source-drain doping and a preparation method thereof. The two-dimensional multi-bridge channel transistor comprises a substrate and a plurality of channel structures arranged on the substrate. Each of the plurality of channel structures comprises a gate metal layer arranged on the substrate, a first high-k gate dielectric layer arranged around the first gate metal layer, a low-k gate dielectric layer arranged around the side surface of the first high-k gate dielectric layer, and a two-dimensional semiconductor material layer arranged on the high-k gate dielectric layer and the low-k gate dielectric layer, wherein part of the two-dimensional semiconductor material is induced to phase change into a two-dimensional semimetal / metal material layer by a solid source doping source. According to the two-dimensional multi-bridge channel transistor and the preparation method thereof, the source-drain contact resistance is reduced, the low-k sidewall process compatible with the two-dimensional semiconductor integrated circuit is realized, the parasitic is reduced, and the speed of the transistor is improved.

Description

Technical Field

[0001] This invention specifically relates to a two-dimensional multi-bridge channel transistor with self-aligned source-drain doping and its fabrication method, belonging to the field of two-dimensional semiconductor technology. Background Technology

[0002] As integrated circuit manufacturing processes advance to the sub-10nm node, the traditional approach of increasing transistor density by scaling down transistors proportionally to improve overall chip performance is becoming increasingly difficult. FinFET technology, adopted since the 22nm node, is approaching its physical and engineering limits at the sub-5nm node, necessitating a revolution in transistor structure.

[0003] The multi-bridge channel transistor (MBCFET) structure, employing multi-channel stacking and a full-gate-all-around (GAW) configuration, is one of the most promising structures after FinFET. The GAW structure allows for stronger electrostatic control, suppressing short-channel effects. The multi-channel stacking significantly increases drive current, thereby reducing transistor gate delay and improving speed. The MBCFET structure is also considered a sub-5nm technology roadmap in international semiconductor technology roadmaps. Advanced semiconductor manufacturing companies such as TSMC, Samsung Electronics, and Intel are also working on achieving sub-5nm process nodes based on GAW transistor technology.

[0004] Two-dimensional semiconductor materials, due to their intrinsic advantages of ultrathinness and high mobility, are candidates for core channel materials in MBCFETs, offering significant advantages in speed and power consumption. Combining ultrathin 2D semiconductor materials with a gate-all-around structure can maximize the gate control capability of transistors and suppress short-channel effects, thereby pushing transistors to smaller technology nodes.

[0005] Two-dimensional semiconductor materials suffer from excessively high contact resistance due to the Fermi pinning effect, and silicon-based ion implantation is currently not an option to reduce source-drain contact resistance. This results in poor on-state performance of MBCFETs, even with multi-channel stacking. New contact processes need to be developed to achieve ohmic contacts in MBC transistors, thereby improving transistor speed and reducing circuit delay.

[0006] To reduce parasitic capacitance in 2D MBCFETs and thus improve circuit performance by lowering latency, it is necessary to develop self-aligned processes for new materials to achieve low-k sidewall technology in 2D MBCFETs. Currently, self-alignment in 2D semiconductors is only demonstrated in metal stripping processes, which is incompatible with advanced node large-scale integrated circuit processes.

[0007] Currently, there are no reports on the implementation of low-k sidewall technology in two-dimensional MBCFETs. Given the need to reduce latency and thus improve circuit performance, there is an urgent need for a technical solution that can be compatible with low-k sidewall technology in two-dimensional semiconductor integrated circuits to reduce parasitics and improve speed. Summary of the Invention

[0008] The purpose of this invention is to provide a complete self-aligned two-dimensional semiconductor MBCFET structure and fabrication process, realize the transformation of two-dimensional semiconductor materials from the semiconductor phase to the metal phase, reduce source-drain contact resistance, and obtain a low-k sidewall process compatible with two-dimensional semiconductor integrated circuits to reduce parasitics and improve speed.

[0009] To achieve the above objectives, the present invention adopts the following technical solution.

[0010] A two-dimensional multi-bridge channel transistor with self-aligned source-drain doping includes a substrate and a plurality of channel structures disposed on the substrate. Each of the plurality of channel structures includes: a gate metal layer disposed on the substrate; a first high-k gate dielectric layer disposed around the first gate metal layer; a low-k gate dielectric layer disposed around the side of the first high-k gate dielectric layer; and a two-dimensional semiconductor material layer disposed on the high-k gate dielectric layer and the low-k gate dielectric layer, wherein a portion of the two-dimensional semiconductor material is induced to transform into a two-dimensional half-metal / metal material layer by a solid-state source doping source.

[0011] The low-k gate dielectric layer is formed using a self-aligned process.

[0012] It also includes a second gate metal layer disposed on the plurality of channel structures, a second high-k gate dielectric layer surrounding the second gate metal layer, sidewalls disposed on both sides of the second gate metal layer and the second high-k gate dielectric layer, and passivation layers disposed on both sides of the sidewalls.

[0013] The self-aligned source-drain doped two-dimensional multi-bridge channel transistor further includes a solid source active metal and a conventional metal layer covering the two-dimensional half-metal / metal material layer.

[0014] This invention also provides a method for fabricating a two-dimensional multi-bridge channel transistor with self-aligned source-drain doping, comprising the following steps: Step 1, providing a substrate; Step 2, fabricating a sacrificial layer on the substrate; Step 3, fabricating a two-dimensional semiconductor material layer on the sacrificial layer; Step 4, fabricating a sacrificial layer on the two-dimensional semiconductor material layer; repeating Step 3 and Step 4 at least twice; Step 5, fabricating a dummy gate structure and a sidewall structure on the sacrificial layer furthest from the substrate; Step 6, etching a portion of the sacrificial layer; Step 7, depositing a low-k gate dielectric layer to cover the dummy gate structure and the sidewall structure; Step 8, etching the low-k gate dielectric layer with the sidewall structure as self-alignment, and etching back the low-k gate dielectric layer; Step 9, performing surface modification treatment on the two-dimensional semiconductor material layer; Step 10, evaporating a solid-state source active metal layer; Step 11, evaporating a conventional metal layer; Step 12, performing annealing treatment, so that the two-dimensional semiconductor material layer is induced to undergo a phase transition by the solid-state source doping to obtain a two-dimensional half-metal / metal material layer.

[0015] The surface modification process includes bombarding the two-dimensional semiconductor material layer with ultra-low power soft plasma.

[0016] The annealing process employs a rapid annealing method, annealing at 250°C to 600°C for 2-60 seconds.

[0017] The fabrication method of the self-aligned source-drain doped two-dimensional multi-bridge channel transistor further includes: removing the dummy gate, removing the sacrificial layer, and then growing a high-k gate dielectric layer and a gate metal layer.

[0018] The high-k gate dielectric layer and the gate metal layer are grown using atomic layer deposition (ALD) technology.

[0019] The advantages and technical effects of this invention are as follows:

[0020] The two-dimensional multi-bridge channel transistor proposed in this invention includes a two-dimensional semi-metal / metal material layer that is in direct contact with the two-dimensional semiconductor material, avoiding the Fermi pinning effect, forming an ohmic contact, reducing the source-drain contact resistance, increasing the drive current of the MBCFET, and realizing the low-k sidewall process in the two-dimensional MBCFET, reducing parasitic capacitance, reducing circuit delay, and increasing transistor speed. Attached Figure Description

[0021] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

[0022] Figure 1 This is a schematic diagram of a two-dimensional multi-bridge channel transistor with self-aligned source and drain doping according to an embodiment of the present invention.

[0023] Figures 2-12 This is a schematic diagram of the structure obtained in each step of the fabrication process of a self-aligned source-drain doped two-dimensional multi-bridge channel transistor according to an embodiment of the present invention. Detailed Implementation

[0024] To make the objectives, content, and advantages of this invention clearer, the specific embodiments of this invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are only used to more clearly illustrate the technical solutions of this invention and should not be construed as limiting the scope of protection of this invention.

[0025] Example 1

[0026] Figure 1 This refers to a two-dimensional multi-bridge channel transistor with self-aligned source-drain doping according to an embodiment of the present invention. For example... Figure 1 The two-dimensional multi-bridge channel transistor includes: a substrate 100 and a plurality of channel structures disposed on the substrate. Each of the plurality of channel structures includes: a first gate metal layer 109 disposed on the substrate 100; a first high-k gate dielectric layer 110 surrounding the first gate metal layer 109; a low-k gate dielectric layer 105 disposed surrounding the side of the first high-k gate dielectric layer 110; and a two-dimensional semiconductor material layer 102 disposed on the first high-k gate dielectric layer 110 and the low-k gate dielectric layer 105, wherein a portion of the two-dimensional semiconductor material 102 is induced by a solid-state source doping to transform into a two-dimensional half-metal / metal material layer 108. Figure 1 As shown, in the two-dimensional semiconductor material layer 102, the portion that is not in contact with the first high-k gate dielectric layer 110 and the low-k gate dielectric layer 105 is induced to transform into a two-dimensional half-metal / metal material layer 108.

[0027] Figure 1 The section enclosed by the dashed box 115 schematically illustrates a channel structure. Figure 1 The middle layer has three channel structures stacked, but this is only an example. The present invention proposes that a two-dimensional multi-bridge channel transistor may include two channel structures, or three or more channel structures, and the present invention is not limited thereto.

[0028] In the three channel structures shown in the figure, the low-k gate dielectric layer 105 is formed using a self-aligned process. The low-k gate dielectric layer 105 formed using the self-aligned process serves as an internal sidewall, ensuring that the positions of the internal sidewalls between the channel structures are aligned and unaffected by process fluctuations, especially photolithography fluctuations. This improves device consistency when subsequent source and drain doping is performed using the internal sidewalls as self-alignment.

[0029] The material of the first high-k gate dielectric layer 110 may include, but is not limited to, HfO2, ZrO2, and the material of the low-k gate dielectric layer 105 may include, but is not limited to, porous dielectrics, organosilicon glass SiOCH, etc., but the present invention is not limited to these.

[0030] like Figure 1 As shown, the two-dimensional multi-bridge channel transistor provided in this embodiment further includes a second gate metal layer 112 disposed on the plurality of channel structures, a second high-k gate dielectric layer 113 surrounding the second gate metal layer 112, sidewalls 103 disposed on both sides of the second gate metal layer 112 and the second high-k gate dielectric layer 113, and passivation layers 111 disposed on both sides of the sidewalls 103. The material of the sidewalls 103 includes, but is not limited to, silicon nitride. The material of the passivation layers 11 includes, but is not limited to, SiNx. The material of the second high-k gate dielectric layer 113 is the same as that of the first high-k gate dielectric layer 110, and the first gate metal layer 109 is the same as that of the second gate metal layer 112 and is fabricated using the same process.

[0031] The two-dimensional multi-bridge channel transistor provided in this embodiment also includes a solid-state source active metal 106 and a conventional metal layer 107 covering the two-dimensional semi-metal / metal material layer 108. The solid-state source active metal layer 106 is made of materials including but not limited to Y, Ta, V, Fe, etc., and the conventional metal layer 107 is made of materials including but not limited to Ti, Au, Pd, Ni, TiNx, etc.

[0032] The two-dimensional multi-bridge channel transistor according to this embodiment includes, on the one hand, a two-dimensional semi-metal / metal material layer that is in direct contact with the two-dimensional semiconductor material, forming an ohmic contact. This avoids the strong Fermi pinning effect caused by direct contact between the metal and the two-dimensional semiconductor material, reducing the source-drain contact resistance and thus improving the carrier transport performance and increasing the drive current of the MBCFET. On the other hand, a low-k gate dielectric layer 105 is used as an internal sidewall to realize the low-k sidewall process in the two-dimensional MBCFET, reducing the parasitic effects of the source and drain. The combination of these two aspects reduces the delay and thus improves the transistor speed.

[0033] Example 2

[0034] This embodiment provides a method for fabricating a two-dimensional multi-bridge channel transistor with self-aligned source-drain doping. Figures 2-12The diagram below shows the structural schematics obtained in each step of the fabrication process of a two-dimensional multi-bridge channel transistor using this method. Figures 2-12 The method is described in detail, and includes the following steps.

[0035] Step 1, provide substrate 100.

[0036] Step 2: Prepare a sacrificial layer 101 on the substrate 100. The material of the sacrificial layer 101 includes, but is not limited to, polycrystalline silicon, organic matter, silicon oxide, and metal.

[0037] Step 3: Prepare a two-dimensional semiconductor material layer 102 on the sacrificial layer 101. The two-dimensional semiconductor material layer 102 can be a single layer or multiple layers of material, including but not limited to MoS2, MoSe2, WS2, WSe2, MoTe2, InSe, BP, etc.

[0038] Step 4: A sacrificial layer 101 is fabricated again on the two-dimensional semiconductor material layer 102, as follows: Figure 2 As shown, the preparation of the sacrificial layer 101 and the two-dimensional semiconductor material layer 102 was repeated three times to obtain a three-layer channel structure, but the present invention is not limited thereto. A multi-channel structure can be achieved by repeating steps 3 and 4 twice; this embodiment uses a three-layer structure as an example.

[0039] Step 5: Fabricate a dummy gate structure 104 and sidewalls 103 on the sacrificial layer furthest from the substrate, as follows: Figure 3 As shown. The dummy gate structure 104 includes gate dielectric, polysilicon dummy gate, amorphous silicon dummy gate, etc., and the sidewall 103 is made of materials including but not limited to silicon nitride.

[0040] Step 6, etch the sacrificial layer 101 as follows: Figure 4 As shown.

[0041] Step 7: Deposit a low-k gate dielectric layer 105 to cover the dummy gate structure 104 and the sidewalls 103, as shown. Figure 5 As shown. The material of the low-k gate dielectric layer 105 includes, but is not limited to, porous dielectrics, silicone glass (SiOCH), etc.

[0042] Step 8: Using the sidewall 103 as self-alignment, etch the low-k gate dielectric layer 105 as the inner sidewall, such as... Figure 6 As shown, the low-k gate dielectric layer 105, which serves as the internal sidewall, is then etched back using an atomic layer etching (ALE) system, retaining portions of the low-k gate dielectric layer 105 on both sides of the sacrificial layer 101, as shown. Figure 7 As shown, the low-k gate dielectric layer 105 is etched using a self-aligned process to serve as internal sidewalls, ensuring that the positions of the internal sidewalls between each channel structure are aligned and unaffected by process fluctuations, especially photolithography fluctuations.

[0043] Step 9: Perform surface modification treatment on the two-dimensional semiconductor material layer 102, such as... Figure 8 As shown. The surface modification treatment includes bombarding the two-dimensional semiconductor material layer 102 with ultra-low power soft plasma of 1-100W, such as nitrogen, argon, hydrogen, etc., for about 5-300 seconds to induce active injection sites, which is beneficial to the subsequent induced phase transition of solid doping sources.

[0044] Step 10, vapor deposit solid source active metal layer 106, such as Figure 9 As shown, the material of the solid source active metal layer 106 includes, but is not limited to, Y, Ta, V, Fe, etc.

[0045] Step 11, vapor deposit a conventional metal layer 107, such as Figure 10 As shown, the material of the conventional metal layer 107 includes, but is not limited to, Ti, Au, Pd, Ni, TiNx, etc. The function of the conventional metal layer 107 is passivation to prevent oxidation of the active metal layer.

[0046] Step 12 involves annealing the solid-state active metal layer 106 and the conventional metal layer 107, causing metal atoms from the solid-state active metal layer 106 to be implanted into the two-dimensional semiconductor material layer 102 in contact with the solid-state active metal layer 106, i.e., the two-dimensional semiconductor material layer 102 not in contact with the first high-k gate dielectric layer 110 and the low-k gate dielectric layer 105, resulting in substitutional doping. The substitutionally doped two-dimensional semiconductor material layer 102 is then induced to undergo a phase transition, transforming into a two-dimensional half-metal / metal material layer 108, such as... Figure 11 As shown. The annealing process can be a rapid annealing method from 250℃ to 600℃ for 2-60 seconds, or a conventional annealing method from 150℃ to 250℃ under high vacuum for 15 minutes to 4 hours.

[0047] Step 13, remove the dummy gate structure 104 and remove all sacrificial layers 101, as follows. Figure 12 As shown, the removal process of the sacrificial layer 101 is achieved through a selective wet etching process. The two-dimensional semiconductor material is fixed by solid active metals and conventional metal layers on both sides, and the selective wet etching solution used does not affect the two-dimensional semiconductor material layer.

[0048] Step 14: A high-k gate dielectric layer is grown using atomic layer deposition (ALD) technology, followed by the deposition of a gate metal layer, to obtain the desired result. Figure 1The diagram illustrates a two-dimensional multi-bridge channel transistor structure. The first high-k gate dielectric layer 110 is made of materials including, but not limited to, HfO2 and ZrO2. Using ALD (atomic layer deposition), the first high-k gate dielectric layer 110 can be uniformly grown along all surfaces within the space defined by the two-dimensional semiconductor material layer 102 and the low-k gate dielectric layer 105. Then, the first gate metal layer 109 is grown, and the second high-k gate dielectric layer 113, the first high-k gate dielectric layer 110, the second gate metal layer 112, and the first gate metal layer 109 are grown simultaneously. Unlike other deposition methods that may result in a thicker top layer or thinner sidewalls, ALD allows for uniform growth across all surfaces, ensuring uniform thickness of the high-k gate dielectric layer and the gate metal layer.

[0049] In this embodiment, ultra-low power plasma is used to target the contact area of ​​the two-dimensional MBCFET (i.e., Figure 11 The portion indicated by reference numeral 108 in the attached diagram is processed to generate atomically implanted active sites. Then, a solid-state source active metal and a conventional metal layer are deposited, followed by rapid thermal annealing. This allows active metal atoms to be implanted and substituted into the two-dimensional semiconductor material layer. The substituted-doped two-dimensional semiconductor material transforms into a two-dimensional half-metal / metal material layer 108, which directly contacts the two-dimensional semiconductor material layer 102, avoiding the Fermi pinning effect and forming an ohmic contact, thus increasing the drive current of the MBCFET. The conventional metal layer serves to prevent oxidation of the solid-state source active metal layer, facilitating the full implantation and substituted doping of active metal atoms into the two-dimensional semiconductor material layer.

[0050] The fabrication method of the two-dimensional multi-bridge channel transistor in this embodiment utilizes surface modification treatment to generate atomically implanted active sites, and then through annealing treatment, active metal atoms are implanted and substituted into the two-dimensional semiconductor material layer 102. The two-dimensional semi-metal / metal material layer 108 is in direct contact with the two-dimensional semiconductor material layer 102, avoiding the Fermi pinning effect caused by the direct contact between the two-dimensional semiconductor material layer and the metal layer, reducing the contact resistance of the transistor, thereby increasing the drive current of the MBCFET. In addition, it realizes low-k sidewall technology compatible with two-dimensional semiconductor integrated circuits, reduces parasitics, and improves the speed of the transistor.

[0051] The above embodiments are merely illustrative of the technical concept and features of the present invention, and are preferred embodiments. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and they should not be construed as limiting the scope of protection of the present invention. All equivalent transformations or modifications made according to the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A two-dimensional multi-bridge channel transistor with self-aligned source-drain doping, characterized in that, The system includes a substrate and a plurality of channel structures disposed on the substrate, each of the plurality of channel structures comprising: A first gate metal layer is disposed on the substrate; A first high-k gate dielectric layer is disposed around the first gate metal layer; A low-k gate dielectric layer is disposed around the side of the first high-k gate dielectric layer; A two-dimensional semiconductor material layer is disposed on the first high-k gate dielectric layer and the low-k gate dielectric layer. The surface modification treatment of the two-dimensional semiconductor material layer, including bombardment of the two-dimensional semiconductor material layer with ultra-low power soft plasma, generates active sites for atomic implantation. Then, through annealing treatment, active metal atoms are implanted and substituted into the two-dimensional semiconductor material layer, so that part of the two-dimensional semiconductor material is induced to transform into a two-dimensional half-metal / metal material layer by solid-state source doping.

2. The two-dimensional multi-bridge channel transistor with self-aligned source-drain doping according to claim 1, characterized in that, The low-k gate dielectric layer is formed using a self-aligned process.

3. The two-dimensional multi-bridge channel transistor with self-aligned source-drain doping according to claim 1, characterized in that, It also includes a second gate metal layer disposed on the plurality of channel structures, a second high-k gate dielectric layer surrounding the second gate metal layer, sidewalls disposed on both sides of the second gate metal layer and the second high-k gate dielectric layer, and passivation layers disposed on both sides of the sidewalls.

4. The two-dimensional multi-bridge channel transistor with self-aligned source-drain doping according to any one of claims 1-3, characterized in that, It also includes a solid source active metal and a conventional metal layer covering the two-dimensional semi-metal / metal material layer.

5. A method for fabricating a two-dimensional multi-bridge channel transistor with self-aligned source-drain doping, characterized in that, Includes the following steps: Step 1, Provide the substrate; Step 2: Prepare a sacrificial layer on the substrate; Step 3: Prepare a two-dimensional semiconductor material layer on the sacrificial layer; Step 4: Prepare a sacrificial layer on the two-dimensional semiconductor material layer; Repeat the preparation steps of step 3 and step 4 more than twice; Step 5: Fabricate a dummy gate structure and a sidewall structure on the sacrificial layer furthest from the substrate; Step 6: Etch the sacrificial layer. Step 7: Deposit a low-k gate dielectric layer to cover the dummy gate structure and the sidewall structure; Step 8: Using the sidewall structure as self-alignment, etch the low-k gate dielectric layer, and then etch back the low-k gate dielectric layer. Step 9: The two-dimensional semiconductor material layer is bombarded with ultra-low power soft plasma to perform surface modification treatment on the two-dimensional semiconductor material layer; Step 10: Evaporate the solid source active metal layer; Step 11, vapor deposition of a conventional metal layer; Step 12: Perform annealing treatment to induce a phase transition in the two-dimensional semiconductor material layer by a solid-state doping source to obtain a two-dimensional semi-metal / metal material layer.

6. The method for fabricating a two-dimensional multi-bridge channel transistor with self-aligned source-drain doping according to claim 5, characterized in that, The surface modification process includes bombarding the two-dimensional semiconductor material layer with ultra-low power soft plasma.

7. The method for fabricating a two-dimensional multi-bridge channel transistor with self-aligned source-drain doping according to claim 5, characterized in that, The annealing process employs a rapid annealing method, annealing at 250°C to 600°C for 2-60 seconds.

8. The method for fabricating a two-dimensional multi-bridge channel transistor with self-aligned source-drain doping according to claim 5, characterized in that, Also includes: Remove the dummy gate, remove the sacrificial layer, and then grow a high-k gate dielectric layer and a gate metal layer.

9. The method for fabricating a two-dimensional multi-bridge channel transistor with self-aligned source-drain doping according to claim 8, characterized in that, The high-k gate dielectric layer and the gate metal layer are grown using atomic layer deposition (ALD) technology.

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