A novel structure of thermal tuning laser chip and a manufacturing method thereof
By etching the support layer in a hollow area in the thermally tunable laser chip and using air thermal isolation, the problem of insufficient heat dissipation performance is solved, achieving more efficient thermal tuning and faster response.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ACCELINK TECHNOLOGIES CO LTD
- Filing Date
- 2021-11-11
- Publication Date
- 2026-05-19
AI Technical Summary
Existing thermally tunable lasers have shortcomings in heat dissipation performance, resulting in inconvenient thermal tuning processes and poor control precision and stability.
A novel thermally tunable laser chip, comprising a substrate, a support layer, a sacrificial layer, and a functional layer, employs a novel structure. By etching away the support layer in the hollowed-out area of the ridge waveguide, thermal isolation is achieved using air. Combined with a passive waveguide material with a higher bandgap, absorption loss and chip threshold are reduced.
It improves thermal tuning efficiency and response speed, reduces laser linewidth, and enhances the convenience and stability of control.
Smart Images
Figure CN116111451B_ABST
Abstract
Description
[Technical Field]
[0001] This invention relates to the field of semiconductor laser chip technology, and in particular to a novel thermally tunable laser chip and its fabrication method. [Background Technology]
[0002] Tunable semiconductor lasers, as lasers whose output wavelength can be continuously changed within a certain range, are key components of dense wavelength division multiplexing systems and future all-optical networks. Their advantages will become increasingly prominent as the demand for transmission speed and capacity in network systems continues to rise. The unique advantages of tunable lasers in terms of tuning range and narrow linewidth have attracted numerous researchers to study their structure, aiming to adjust parameters such as temperature and current within the laser cavity to emit different wavelengths.
[0003] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. [Summary of the Invention]
[0004] The technical problem to be solved by the embodiments of the present invention is the inadequacy of the heat dissipation performance of existing thermally tunable lasers, which causes inconvenience in the back-and-forth control during the entire thermal tuning process, and consequently causes problems with the control accuracy and stability.
[0005] The embodiments of the present invention adopt the following technical solutions:
[0006] In a first aspect, the present invention provides a novel thermally tunable laser chip, comprising a substrate 1, a support layer 2, a sacrificial layer 3, and a set of functional layers 4, wherein the support layer 2, the sacrificial layer 3, and the set of functional layers 4 are sequentially grown on the substrate 1, specifically:
[0007] The ridge waveguide portion of the laser is located along its light-emitting axis and is divided into at least two hollowed-out regions 7; wherein the hollowed-out regions are spaced apart by a first preset distance.
[0008] In the hollowed-out area 7, the support layer 2 below the corresponding ridge waveguide portion is etched away; the support layer 2 below the ridge waveguide portion spaced between the hollowed-out areas is still retained.
[0009] Preferably, if the two ends of the laser are the same as the two ends of the thermally tuned laser chip, then the hollowed-out areas 7 near the two ends of the laser are at least a second preset distance away from the corresponding edges of the two ends.
[0010] Preferably, the functional layer 4 specifically includes one or more of the following: a laser layer structure, a detector layer structure, a modulator layer structure, and a passive waveguide layer.
[0011] Preferably, it also includes two parts: resistor 7 and electrode 8. Each resistor 7 is sputtered on the ridge waveguide of the laser above the dielectric layer, and each resistor 7 is connected to a set of electrodes 8.
[0012] Secondly, this invention provides a novel method for fabricating a thermally tunable laser chip, comprising pre-growing a layered substrate, the method including:
[0013] A ridge waveguide structure is etched on the layered substrate, wherein the channel of the ridge waveguide structure is etched with a sacrificial layer;
[0014] On the support layer 2 exposed on both sides of the channel, one or more hollow areas 7 are pre-made and etched with a corresponding number of pre-cut grooves.
[0015] Then, photoresist is used to protect the area outside the pre-etched grooves on the channel. Then, the pre-etched grooves on both sides of the channel, which are parallel to the ridge waveguide, are etched through each other to form one or more hollow areas 7.
[0016] Preferably, the growth layered substrate specifically includes:
[0017] The InAlAs support layer 2, InP sacrificial layer 3, InGaAsP active layer 4, InP cladding layer 42 and contact layer 43 are sequentially grown on the InP substrate 1.
[0018] Preferably, etching the ridge waveguide structure on the layered substrate specifically includes:
[0019] The corresponding ridge waveguide A pattern is defined on the surface of the layered substrate by photolithography. Based on the defined ridge waveguide A pattern, etching is performed on the semiconductor chip, with the etching depth exceeding the contact layer.
[0020] A hydrochloric acid solution is used to etch the chip cladding 42 to form trenches of ridge waveguide A patterns extending along the direction close to the substrate 1 on the left and right sides of the semiconductor chip waveguide.
[0021] Preferred options also include:
[0022] The position of the ridge waveguide B pattern is defined on the surface of the ridge waveguide A pattern by photolithography. The active layer is etched down to the sacrificial layer. Then, a hydrochloric acid solution is used to etch the sacrificial layer 3. Due to the limitation of the active layer material, the etching solution will etch the sacrificial layer material vertically downwards instead of drilling to the sides. The support layer 2 is exposed after the ridge waveguide B pattern is fabricated.
[0023] Preferably, the hydrochloric acid solution is an HCl:H3PO4 = 1:3 solution, the active layer material is InGaAsP, and the sacrificial layer material is InP.
[0024] Preferably, the pre-etched grooves on both sides of the ridge waveguide are etched through to form one or more hollow areas 7, specifically including:
[0025] H3PO4 acid solution was used to etch the InAlAs material of the support layer 2 for a preset time, and finally a suspended heat insulation structure with pillar support was formed.
[0026] Compared with the prior art, the beneficial effects of the embodiments of the present invention are as follows:
[0027] In this invention, since the thermal tuning efficiency of the material is largely unaffected by the material bandgap, materials with higher bandgap can be used as passive waveguide regions for wavelength tuning in chip design. This further reduces the absorption loss of the passive waveguide region material, lowers the chip threshold, and reduces the laser linewidth. Simultaneously, the waveguide layer and substrate are thermally isolated by air, resulting in significantly improved thermal tuning efficiency and tuning response speed for a given chip thermal power. [Attached Image Description]
[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 This is a schematic diagram of the structure of a novel thermally tunable laser chip with a layered substrate grown in an embodiment of the present invention.
[0030] Figure 2 This is a schematic diagram of the cross-sectional structure of a ridge waveguide with a hollowed-out area in a novel thermally tunable laser chip provided by an embodiment of the present invention.
[0031] Figure 3 This is a schematic diagram of the cross-sectional structure of the ridge waveguide in the non-hollowed-out region of a novel thermally tunable laser chip provided in an embodiment of the present invention.
[0032] Figure 4 This is a top view schematic diagram of a novel thermally tunable laser chip provided in an embodiment of the present invention;
[0033] Figure 5 This is a plan view of a semiconductor chip provided according to an embodiment of the present invention;
[0034] Figure 6 This is a schematic diagram of the manufacturing process of a semiconductor chip according to an embodiment of the present invention;
[0035] Figure 7 This is a schematic diagram of the manufacturing process of a semiconductor chip according to an embodiment of the present invention;
[0036] Figure 8 This is a schematic diagram of the manufacturing process of a semiconductor chip according to an embodiment of the present invention;
[0037] Figure 9 This is a schematic diagram of the manufacturing process of a semiconductor chip according to an embodiment of the present invention;
[0038] Figure 10 This is a schematic diagram of the manufacturing process of a semiconductor chip according to an embodiment of the present invention;
[0039] Figure 11 This is a schematic flowchart of a semiconductor chip fabrication method provided in an embodiment of the present invention.
Detailed Implementation Methods
[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0041] In the description of this invention, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and do not require that this invention must be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.
[0042] Research and testing revealed that the heat generated by the chip during normal operation primarily exchanges with the outside air through the substrate material. The sacrificial layer and active layer materials mainly consist of InGaAsP and InP, with thicknesses nearly identical to the sacrificial layer. This significantly increases the gap between the resistor and the substrate. Furthermore, a low-thermal-conductivity support layer, 2InAlAs, is grown between the substrate and the sacrificial layer. The thermal conductivity of this support layer is one-tenth that of the InP substrate; that is, a 1µm thick 2InAlAs support layer provides the same thermal insulation as a 10µm InP layer. This heat exchange through the substrate with the outside air greatly reduces heat dissipation from the substrate, thereby improving the chip's thermal tuning efficiency.
[0043] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0044] Example 1:
[0045] Embodiment 1 of the present invention provides a novel thermally tunable laser chip, such as... Figure 1 As shown, it includes a substrate 1, a support layer 2, a sacrificial layer 3, and a set of functional layers 4, wherein the support layer 2, the sacrificial layer 3, and the set of functional layers 4 are sequentially grown on the substrate 1. Specifically:
[0046] like Figure 4 As shown, the ridge waveguide portion of the laser is located along its light-emitting axis and is divided into at least two hollowed-out regions 7; wherein, the hollowed-out regions are spaced apart by a first preset distance d1; this first preset distance d1 is determined by comprehensively considering the width of the ridge, the thickness of the support layer 2, and the length L of a single hollowed-out region along the light-emitting axis. Generally, the wider the ridge, the thinner the support layer 2, and the smaller the length L of a single hollowed-out region along the light-emitting axis, the smaller the first preset distance d1 can be set; conversely, the first preset distance d1 needs to be increased. In the embodiments of the present invention, as... Figure 2 and Figure 4 As shown, the ridge waveguide structure is intuitively represented as a spine 5 located in the middle and grooves 6 located on both sides of the spine.
[0047] like Figure 3 As shown, in the hollowed-out area 7, the support layer 2 below the corresponding ridge waveguide portion is etched away; as Figure 2 As shown, the support layer 2 below the ridge waveguide portion that is spaced between the hollowed-out areas is still retained.
[0048] In this embodiment, since the thermal tuning efficiency of the material is largely unaffected by the material bandgap, a material with a higher bandgap can be used as the passive waveguide region for wavelength tuning in the chip design. This further reduces the absorption loss of the passive waveguide region material, lowers the chip threshold, and reduces the laser linewidth. Simultaneously, the waveguide layer and substrate are thermally isolated by air, resulting in significantly improved thermal tuning efficiency and tuning response speed for a given chip thermal power.
[0049] In this embodiment of the invention, if the two ends of the laser are the same as the two ends of the thermally tuned laser chip, such as... Figure 4 As shown, the hollowed-out areas 7 near both ends of the laser are at least a second preset distance d2 from their respective end edges. This second preset distance d2 is to prevent the hollowed-out areas from creating an unstable structure where the entire laser is supported by only a single spine. Ideally, it should at least present the following... Figure 4 As shown, the laser has a support layer under the spine at both ends, and there is also at least one support layer under the spine in the middle area.
[0050] As one of the many possible structural embodiments of the present invention, in a novel thermally tunable laser chip, such as... Figures 1-3 The cross-sectional structure shown illustrates the different manifestations of functional layer 4 in various scenarios, specifically including one or more of the following: a laser layer structure, a detector layer structure, a modulator layer structure, and a passive waveguide layer. In practical implementation, these multiple functional layers are typically designed in combination to address the different requirements of thermally tunable laser chips. The laser layer structure and the modulator layer structure are usually the most practically significant in terms of performance.
[0051] In this embodiment of the invention, a more practical complex structure diagram is also provided, such as... Figure 5 As shown, it also includes two parts: resistors 7 and electrodes 8. Each resistor 7 is sputtered on the ridge waveguide of the laser above the dielectric layer, and each resistor 7 is connected to a set of electrodes 8.
[0052] Example 2:
[0053] This invention provides a novel method for fabricating a thermally tunable laser chip, which can be used to fabricate the novel thermally tunable laser chip described in Embodiment 1. It should be noted that this invention focuses on the process output related to substantially differentiating features; other processes, such as electrode fabrication, are not within the scope of this invention and are conventional prior art, therefore they will not be described in detail later. In this embodiment, as shown, a layered substrate is pre-grown, and the method includes:
[0054] In step 201, a ridge waveguide structure is etched on the layered substrate, wherein the channel of the ridge waveguide structure is etched with a sacrificial layer.
[0055] In step 202, on the support layer 2 exposed on both sides of the channel, one or more hollow areas 7 are pre-etched with a corresponding number of pre-cut grooves.
[0056] In step 203, photoresist is used to protect the area outside the pre-etched grooves on the channel. Then, the pre-etched grooves on both sides of the channel located parallel to the ridge waveguide are etched through each other to form one or more hollow areas 7.
[0057] In this embodiment, since the thermal tuning efficiency of the material is largely unaffected by the material bandgap, a material with a higher bandgap can be used as the passive waveguide region for wavelength tuning in the chip design. This further reduces the absorption loss of the passive waveguide region material, lowers the chip threshold, and reduces the laser linewidth. Simultaneously, the waveguide layer and substrate are thermally isolated by air, resulting in significantly improved thermal tuning efficiency and tuning response speed for a given chip thermal power.
[0058] In this embodiment of the invention, a scenario for implementing a laser is provided, such as... Figure 6 As shown, the growth layered substrate specifically includes:
[0059] An InAlAs support layer 2, an InP sacrificial layer 3, an InGaAsP active layer 41, an InP cladding layer 42, and a contact layer 43 are sequentially grown on an InP substrate 1. The InGaAsP active layer 41, InP cladding layer 42, and contact layer 43 represent one example of a set of functional layers 44 in Embodiment 1.
[0060] In addition, the embodiments of the present invention provide a set of feasible parameters to facilitate further clarification of the dimensional relationships between the schemes. For example, the thickness of substrate 1 is greater than 150 μm, the thickness of InAlAs material in support layer 2 is about 1 μm, the thickness of InP material in sacrificial layer is about 1.8 μm, the thickness of InGaAsP material in active layer is about 0.4 μm, the thickness of InP material in cladding layer is about 1.6 μm, and the thickness of InP material in contact layer is about 0.2 μm.
[0061] Next, we will go through Figures 7-10 The process of generating the corresponding ridge waveguide structure and the hollowed-out region in the ridge waveguide structure is described in detail below. The etching of the ridge waveguide structure on the layered substrate specifically includes:
[0062] like Figure 6 As shown, a corresponding ridge waveguide A pattern is defined on the surface of the layered substrate by photolithography. Based on the defined ridge waveguide A pattern, etching is performed on the semiconductor chip, with the etching depth exceeding the contact layer. A hydrochloric acid solution (e.g., HCl:H3PO4 = 1:3) is used to etch the chip cladding 42, thereby forming trenches of the ridge waveguide A pattern extending along the direction close to the substrate 1 on the left and right sides of the semiconductor chip waveguide.
[0063] like Figure 7 As shown, the position of the ridge waveguide B pattern is defined on the surface of the ridge waveguide A pattern by photolithography. The active layer is etched down to the sacrificial layer. Then, a hydrochloric acid solution (e.g., HCl:H3PO4 = 1:3, suitable for scenarios where the active layer material is InGaAsP and the sacrificial layer material is InP) is used to etch the sacrificial layer 3. Due to the limitation of the active layer material, the etching solution will etch the sacrificial layer material vertically downwards and will not drill to the sides. The support layer 2 is exposed after the ridge waveguide B pattern is fabricated.
[0064] The process involves etching through-holes in the pre-etched grooves on both sides of the parallel ridge waveguide to form one or more hollow areas 7. Specifically, this includes etching the InAlAs material of the support layer 2 with an H3PO4 acid (e.g., H2O2 and H3PO4) solution for a preset time, ultimately forming a suspended heat insulation structure supported by pillars. The preset time is determined based on actual testing, and its effect completes the formation of the through-hole structure of the corresponding hollow area 7.
[0065] Example 3:
[0066] This invention will illustrate the method implemented in Embodiment 2 of this invention through a relatively complete processing procedure, after elaborating on the relevant technical details. For example... Figure 5 The image shown is a plan view of a novel semiconductor laser chip. Figure 1 It can be depicted on a plane composed of the horizontal (X) and vertical (Y) axes, where the Z-axis direction is not indicated. In a typical example of a thermally tunable laser chip, it would include, for example... Figure 5 The diagram shows the SOA region, front grating region, gain region, phase region, rear grating region, COA region, etc., among which the regions suitable for forming the cutout region structure described in Embodiment 1 of this invention include, but are not limited to, the front grating region, phase region, and rear grating region shown in the figure. Furthermore, depending on the structure of each region, the size of the corresponding single cutout structure and the spacing between cutouts can be adjusted appropriately according to the actual situation. For example... Figure 5 As shown, the heating part mainly includes two parts: resistor 7 and resistor electrode 8. Each resistor 7 is formed by sputtering above the dielectric layer 9, and each resistor 7 is connected to a set of resistor electrodes 8. This structure mainly reflects the basic principle of realizing the energization and heating mechanism of the present invention.
[0067] Depend on Figure 2 As can be seen, the chip is formed by stacking multiple materials on substrate 1, namely, support layer 2, sacrificial layer 3, active layer 4, upper cladding layer 42, and contact layer 43. The specific structure of the functional layer 4 depends on the actual scenario and can be a laser layer structure, a detector layer structure, a modulator layer structure, or a passive waveguide layer structure.
[0068] In actual manufacturing, the heat generated by the chip during normal operation is mainly exchanged with the outside air through the substrate 1 material. The sacrificial layer 3 material and the active layer material mainly include InGaAsP and InP, and their thicknesses are almost the same as those of the sacrificial layer. This significantly increases the gap between the resistor and the substrate 1. On the other hand, a layer of InAlAs material with low thermal conductivity is grown between the substrate 1 and the sacrificial layer 3. The thermal conductivity of this material is one-tenth that of the InP material on the substrate. That is, the heat insulation effect of 1µm thick InAlAs material is equivalent to that of 10µm InP material. When the heat generated by the chip exchanges with the outside air through the substrate, the heat dissipated from the substrate 1 will be greatly reduced, thereby improving the thermal tuning efficiency of the chip.
[0069] Figure 9 The fabrication process of this novel semiconductor laser chip structure is shown along the vertical Y-axis and Z-axis, while the horizontal X-axis direction is not indicated. First, as... Figure 11As shown, the layered substrate growth discussed in step 301 involves sequentially growing a low thermal conductivity InAlAs support layer 2, an InP sacrificial layer 3, an InGaAsP active layer 4, an InP cladding layer 42, and a contact layer 43 on an InP substrate 1. The substrate 1 has a thickness greater than 150 μm, the InAlAs support layer 2 has a thickness of about 1 μm, the InP sacrificial layer has a thickness of about 1.8 μm, the InGaAsP active layer has a thickness of about 0.4 μm, the InP cladding layer has a thickness of about 1.6 μm, and the InP contact layer has a thickness of about 0.2 μm. Then, as described in step 302, dielectric layer one is redeposited, and the corresponding ridge waveguide A pattern is defined on the chip surface by photolithography 1. Based on the defined ridge waveguide A pattern, RIE etching is performed on the semiconductor chip. If the etching depth exceeds the contact layer whose components include InGaAsP material, a hydrochloric acid solution (HCl:H3PO4 = 1:3) can be used to etch the chip cladding 42 to form trenches extending along the direction close to the substrate 1 on the left and right sides of the semiconductor chip waveguide. Then, as described in step 303, the dielectric layer 1 deposited in step 302 is removed using HF acid etching solution. Dielectric layer 6 is then deposited again, and the deposition of resistance and electrode materials is strictly controlled through photolithography to ensure the intended resistance and power application during chip design. As described in step 304, the position and size of pattern B are defined through the deposition of dielectric layer 2 and photolithography process 2. Dielectric layer 2 can be removed by reactive ion etching and / or wet etching with acidic etchant. Subsequently, under the protection of dielectric layer 2, active layer 4 is etched using RIE until sacrificial layer 3 is reached. Then, a hydrochloric acid solution (HCl:H3PO4 = 1:3) is used to... The sacrificial layer 3 is etched. Due to the constraint of the InGaAsP material, the etchant will etch the InP material vertically downwards without drilling to the sides. At this point, the support layer 2 can be exposed after pattern B is fabricated. As described in step 305, the dielectric layer on the electrode, which was prepared by the aforementioned process, is removed by reactive ion etching and / or wet etching with an acidic etchant to ensure the normal power-carrying structure of the chip. Then, pattern C is fabricated by photolithography 3. Subsequently, the InAlAs material of the support layer 2 is etched for an ideal time using an H3PO4 acidic solution (H2O2 and H3PO4) to finally form a suspended heat-insulating structure with pillar support. The A, B, and C patterns fabricated by photolithography can be square, circular, or other shapes, depending on the actual situation, and are not specifically limited here.
[0070] Figure 2 , Figure 3 The following are shown respectively along Figure 1 The cross-sections taken by lines 1b and 2b are shown in the diagram. Figure 3As shown, the construction of the AB structure provides an operable channel for the subsequent processing of the support layer 2C, and also effectively confines the waveguide. Through comparison... Figure 2 , Figure 3 It can be found that each semiconductor chip of the present invention includes multiple sets of heat insulation structures. The hole structures in the same X direction of each set of heat insulation structures are continuous, and the hole structures in the same set are supported by support pillars with the same structure in the Y direction. Different sets are continuous. This structure can ensure the controllability of corrosion, thereby avoiding the situation where the chip structure collapses due to stress concentration caused by excessive pressure.
[0071] In this embodiment, since the thermal tuning efficiency of the material is largely unaffected by the material bandgap, a material with a higher bandgap can be used as the passive waveguide region for wavelength tuning in the chip design. This further reduces the absorption loss of the passive waveguide region material, lowers the chip threshold, and reduces the laser linewidth. Simultaneously, the waveguide layer and substrate are thermally isolated by air, resulting in significantly improved thermal tuning efficiency and tuning response speed for a given chip thermal power.
[0072] Unlike existing technologies, the semiconductor chip of this invention includes: a substrate, a support layer 2, a sacrificial layer, an active layer, a cladding layer, and a contact layer sequentially stacked on the substrate. The semiconductor chip of this invention has a relatively simple structure. The support layer 2, located below the sacrificial layer, is relatively shallow, but its unique thermal insulation properties result in an air gap between the resistor and the substrate that is 10 times larger than that of a normal chip. This provides better thermal insulation, effectively reducing heat dissipation through the substrate and thus conducting most of the heat to the thermal tuning electrode, improving the chip's thermal tuning efficiency.
[0073] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for fabricating a novel thermally tunable laser chip, characterized in that, Pre-growth of layered substrates, methods including: A ridge waveguide structure is etched on the layered substrate, wherein the channel of the ridge waveguide structure is etched through the sacrificial layer; On the support layer (2) exposed on both sides of the channel, one or more hollow areas (7) are pre-made and etched with a corresponding number of pre-cut grooves. Then, photoresist is used to protect the area outside the pre-etched groove on the channel. Then, the pre-etched grooves on both sides of the channel located parallel to the ridge waveguide are etched through to form one or more hollow areas (7). In the hollow area (7), the support layer (2) below the corresponding ridge waveguide portion is etched away; the support layer (2) below the ridge waveguide portion between the hollow areas is still retained.
2. The method for fabricating a novel thermally tunable laser chip according to claim 1, characterized in that, The growth-layered substrate specifically includes: The InAlAs support layer (2), InP sacrificial layer (3), InGaAsP active layer (4), InP cladding layer (42) and contact layer (43) are sequentially grown on the InP substrate (1).
3. The method for fabricating a novel thermally tunable laser chip according to claim 2, characterized in that, The etching of the ridge waveguide structure on the layered substrate specifically includes: The corresponding ridge waveguide A pattern is defined on the surface of the layered substrate by photolithography. Based on the defined ridge waveguide A pattern, etching is performed on the semiconductor chip, with the etching depth exceeding the contact layer. A hydrochloric acid solution is used to etch the chip cladding (42) to form trenches of ridge waveguide A pattern extending along the direction close to the substrate (1) on the left and right sides of the semiconductor chip waveguide.
4. The method for fabricating a novel thermally tunable laser chip according to claim 3, characterized in that, Also includes: The position of the ridge waveguide B pattern is defined on the surface of the ridge waveguide A pattern by photolithography. The active layer is etched down to the sacrificial layer. Then, a hydrochloric acid solution is used to etch the sacrificial layer (3). Under the constraint of the active layer material, the etching solution will etch the sacrificial layer material vertically downwards instead of drilling to both sides. The support layer (2) is exposed after the ridge waveguide B pattern is fabricated.
5. The method for fabricating a novel thermally tunable laser chip according to claim 4, characterized in that, The hydrochloric acid solution is an HCl:H3PO4 = 1:3 solution, the active layer material is InGaAsP, and the sacrificial layer material is InP.
6. The method for fabricating a novel thermally tunable laser chip according to claim 1, characterized in that, The pre-etched grooves on both sides of the ridge waveguide are etched through each other to form one or more hollow areas (7), specifically including: H3PO4 acid solution was used to corrode the InAlAs material of the support layer (2) for a preset time, and finally a suspended heat insulation structure with support columns was formed.