A current-mode based fixed-frequency PWM controller and control method

Abstract

The present application relates to a kind of current mode-based fixed-frequency PWM controller and control method, belong to analog integrated circuit design field.The fixed-frequency PWM controller includes: filter and feedback module, error amplification and compensation module, voltage current conversion module, first difference module, second difference module, clock generator, PWM trigger and drive module and switching power stage.The present application utilizes the current information of the output VCOMP voltage of error amplification and compensation module, using voltage current conversion module and difference module, so that light load when fixed-frequency PWM controller automatically enters light load variable frequency, its circuit structure and control logic are simple, and light load efficiency is high, PFM entry point can be predicted, and additional operational amplifier is not needed to do PFM management, circuit simplicity is high, with strong portability and lower difficulty of implementation.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit design technology, and in particular to a current-mode-based fixed-frequency PWM controller and control method. Background Technology

[0002] DC / DC converters, as important power management circuits, are widely used in various portable products such as mobile phones, tablets, and digital cameras. In portable applications, the efficiency of the DC / DC converter under light loads largely determines the standby time of the portable product system. Therefore, in recent years, the design of low-power, high-efficiency DC / DC light-load control circuits has become one of the research hotspots for many portable applications.

[0003] In existing fixed-frequency DC / DC light-load control circuits that use clocks, the control logic required for light-load frequency conversion control is relatively complex. It requires a lot of logic circuits and clock synchronization, and additional control circuits are needed to extend the turn-off time or extend the clock cycle to reduce the switching frequency under light load. Therefore, they generally have the technical defects of complex circuit structure and control logic. Summary of the Invention

[0004] The purpose of this invention is to provide a current-mode fixed-frequency PWM controller and control method to achieve high-efficiency DC / DC conversion under light load using a relatively simple circuit structure and control logic.

[0005] To achieve the above objectives, the present invention provides the following solution:

[0006] A current-mode-based fixed-frequency PWM controller includes: a filtering and feedback module, an error amplification and compensation module, a voltage-to-current conversion module, a first difference module, a second difference module, a clock generator, a PWM trigger and drive module, and a switching power stage;

[0007] The output terminal SW pin of the switching power stage is connected to the input terminal SW pin of the filtering and feedback module and the input terminal SW pin of the PWM trigger and drive module, respectively; the output terminal VOUT pin of the filtering and feedback module generates an output voltage VOUT to supply power to the external load.

[0008] The output pin FB of the filtering and feedback module is connected to the input pin FB of the error amplification and compensation module; the output pin VCOMP of the error amplification and compensation module is connected to the input pin of the voltage-to-current conversion module; the output pin of the voltage-to-current conversion module is connected to the positive input pin of the first difference module and the negative input pin of the second difference module, respectively; the negative input pin of the first difference module is connected to the ramp compensation current ISP; the positive input pin of the second difference module is connected to the PFM threshold current ITURN; the output pin of the second difference module is connected to the input pin IOSC of the clock generator; the output pin CLK of the clock generator is connected to the input pin CLK of the PWM trigger and drive module; the output pin of the first difference module is connected to the input pin ISET of the PWM trigger and drive module; the output pin HS of the PWM trigger and drive module is connected to the input pin HS of the switching power stage; the output pin LS of the PWM trigger and drive module is connected to the input pin LS of the switching power stage; the input pin VIN of the switching power stage is connected to the input voltage VIN.

[0009] Optionally, the filtering and feedback module includes: an inductor L, an output capacitor C, an upper voltage divider resistor R1, and a lower voltage divider resistor R2; one end of the inductor L is the input terminal SW pin of the filtering and feedback module, connected to the switching signal SW generated by the output terminal SW pin of the switching power stage; the other end of the inductor L is connected to one end of the output capacitor C and one end of the upper voltage divider resistor R1; the other end of the upper voltage divider resistor R1 is connected to one end of the lower voltage divider resistor R2 and is the output terminal FB pin of the filtering and feedback module, generating a sampling feedback voltage FB; the other end of the lower voltage divider resistor R2 and the other end of the output capacitor C are both grounded; the other end of the inductor L is the output terminal VOUT pin of the filtering and feedback module, generating an output voltage VOUT.

[0010] Optionally, the error amplification and compensation module includes: an error operational amplifier U1; the non-inverting input terminal of the error operational amplifier U1 is connected to the reference voltage VREF; the inverting input terminal of the error operational amplifier U1 is the input terminal FB pin of the error amplification and compensation module, connected to the sampling feedback voltage FB; the output terminal of the error operational amplifier U1 is the output terminal VCOMP pin of the error amplification and compensation module, generating a voltage signal VCOMP.

[0011] Optionally, the voltage-to-current conversion module includes: a voltage-to-current converter U2; the positive input terminal of the voltage-to-current converter U2 is the input pin of the voltage-to-current conversion module and is connected to the voltage signal VCOMP; the negative input terminal of the voltage-to-current converter U2 is grounded; the output terminal of the voltage-to-current converter U2 is the output pin of the voltage-to-current conversion module and generates a current signal ICOMP.

[0012] Optionally, the first difference module includes: a current mirror U3 and a slope-compensated current source ISP; the input terminal of the current mirror U3 is the positive input pin of the first difference module, connected to the current signal ICOMP; the output terminal of the current mirror U3 is connected to one end of the slope-compensated current source; one end of the slope-compensated current source is the negative input pin of the first difference module, generating the slope-compensated current ISP; the other end of the slope-compensated current source is grounded; the connection point of the current mirror U3 and the slope-compensated current source leads out to the output pin of the first difference module, generating a first difference current ISET'.

[0013] Optionally, the second difference module includes: a current mirror U4, a current mirror U5, a diode D1, a diode D2, and a PFM threshold current source ITURN; the input terminal of the current mirror U4 is the negative input pin of the second difference module, connected to the current signal ICOMP; the output terminal of the current mirror U4 is connected to the positive terminal of the diode D1, the negative terminal of the diode D2, and one end of the PFM threshold current source; one end of the PFM threshold current source is the positive input pin of the second difference module, generating the PFM threshold current ITURN; the other end of the PFM threshold current source is grounded; the negative terminal of the diode D1 is connected to the power supply voltage VCC; the positive terminal of the diode D2 is connected to the input terminal of the current mirror U5; the output terminal of the current mirror U5 is the output pin of the second difference module, generating a second difference current IOSC.

[0014] Optionally, the clock generator includes: a clock oscillation current source ICLK, a capacitor C_CLK, a resetter S3, and a comparator U6; one end of the clock oscillation current source ICLK is connected to one end of the capacitor C_CLK, one end of the resetter S3, and the positive input terminal of the comparator U6; the other end of the clock oscillation current source ICLK, the other end of the capacitor C_CLK, and the other end of the resetter S3 are grounded; the positive input terminal of the comparator U6 is the input terminal IOSC pin of the clock generator, connected to the second differential current IOSC; the negative input terminal of the comparator U6 is connected to the reference voltage VREF; the output terminal of the comparator U6 is connected to the control terminal of the resetter S3; the output terminal of the comparator U6 is the output terminal CLK pin of the clock generator, generating a clock signal CLK.

[0015] Optionally, the PWM trigger and drive module includes: a current mirror U7, a current sampling resistor RSNS, a PWM comparator U8, a latch U9, and a drive and dead-time control circuit U10; the input terminal of the current mirror U7 is the input terminal ISET pin of the PWM trigger and drive module, connected to the first differential current ISET'; the output terminal of the current mirror U7 is connected to one end of the current sampling resistor RSNS and the positive input terminal of the PWM comparator U8; the negative input terminal of the PWM comparator U8 is the input terminal SW pin of the PWM trigger and drive module, connected to the switch The signal SW; the output of the PWM comparator U8 is connected to the R input of the latch U9; the S input of the latch U9 is the CLK pin of the PWM flip-flop and drive module, and is connected to the clock signal CLK; the non-inverting output of the latch U9 generates the control signal PWM; the input of the drive and dead-time control circuit U10 is connected to the control signal PWM; the two outputs of the drive and dead-time control circuit U10 are the HS pin and the LS pin of the PWM flip-flop and drive module, respectively, generating the upper transistor drive signal HS and the lower transistor drive signal LS.

[0016] Optionally, the switching power stage includes: an upper power transistor S1 and a lower power transistor S2; the gate of the upper power transistor S1 is the input terminal HS pin of the switching power stage, connected to the upper transistor drive signal HS; the drain of the upper power transistor S1 is the input terminal VIN pin of the switching power stage, connected to the input voltage VIN; the source of the upper power transistor S1 is the output terminal SW pin of the switching power stage, generating the switching signal SW; the gate of the lower power transistor S2 is the input terminal LS pin of the switching power stage, connected to the lower transistor drive signal LS; the drain of the lower power transistor S2 is connected to the source of the upper power transistor S1; the source of the lower power transistor S2 is grounded.

[0017] A current-mode-based fixed-frequency PWM control method, based on the aforementioned fixed-frequency PWM controller; the fixed-frequency PWM control method includes:

[0018] The filtering and feedback module filters the switching signal SW through an LC filter to obtain an output voltage VOUT, which is then used to power the external load. The output voltage VOUT is then sampled and fed back by the voltage sampling of the filtering and feedback module to obtain the sampled feedback voltage FB.

[0019] The error amplification and compensation module sends the sampled feedback voltage FB into its internal system for amplification and compensation processing, and then generates the voltage signal VCOMP.

[0020] The voltage-to-current conversion module converts the voltage signal VCOMP into the current signal ICOMMP according to a preset conversion gain GVI.

[0021] The first difference module takes the difference between the current signal ICOMP and the ramp current compensation ISP to obtain the first difference current ISET';

[0022] The second difference module takes the difference between the current signal ICOMP and the PFM threshold current ITURN to obtain the second difference current IOSC;

[0023] The clock generator adjusts the clock frequency according to the second differential current IOSC to generate the clock signal CLK;

[0024] The PWM trigger and drive module jointly control the turn-on time and timing of the upper transistor and the lower transistor in the switching power stage according to the switching signal SW, the first differential current ISET' and the clock signal CLK, and generate the upper transistor drive signal HS and the lower transistor drive signal LS;

[0025] The switching power stage processes the input voltage VIN into the switching signal SW based on the upper MOSFET drive signal HS and the lower MOSFET drive signal LS.

[0026] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0027] This invention provides a current-mode-based fixed-frequency PWM controller and control method. The fixed-frequency PWM controller includes: a filtering and feedback module, an error amplification and compensation module, a voltage-to-current conversion module, a first difference module, a second difference module, a clock generator, a PWM trigger and drive module, and a switching power stage. This invention utilizes the inherent current information in the output VCOMP voltage of the error amplification and compensation module, and employs the voltage-to-current conversion module and the difference module to enable the fixed-frequency PWM controller to automatically enter light-load frequency conversion under light load conditions. Its circuit structure and control logic are simple, with high efficiency under light load, predictable PFM entry point, and no need for additional operational amplifiers for PFM management. The circuit is highly concise, portable, and has low implementation difficulty. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 A schematic diagram of the overall structure of a current-mode fixed-frequency PWM controller provided in an embodiment of the present invention;

[0030] Figure 2 A schematic diagram of the specific circuit connection of a current-mode-based fixed-frequency PWM controller provided in an embodiment of the present invention;

[0031] Figure 3 The logic flowchart of the current-mode fixed-frequency PWM controller entering the PFM is provided in the embodiment of the present invention;

[0032] Figure 4 A schematic diagram of simulation results for the current-mode-based fixed-frequency PWM control method provided in an embodiment of the present invention. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] The purpose of this invention is to provide a current-mode fixed-frequency PWM controller and control method to achieve high-efficiency DC / DC conversion under light load using a relatively simple circuit structure and control logic.

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] Figure 1 This is a schematic diagram of the overall structure of a current-mode-based fixed-frequency PWM controller provided in an embodiment of the present invention. See also... Figure 1 The current-mode-based fixed-frequency PWM controller includes: a filtering and feedback module 1, an error amplification and compensation module 2, a voltage-to-current conversion module 3, a first difference module 4, a second difference module 5, a clock generator 6, a PWM trigger and drive module 7, and a switching power stage 8.

[0037] See Figure 1 The output pin SW of the switching power stage 8 is connected to the input pin SW of the filtering and feedback module 1 and the input pin SW of the PWM trigger and drive module 7, respectively. The output pin VOUT of the filtering and feedback module 1 generates an output voltage VOUT to power the external load. The output pin FB of the filtering and feedback module 1 is connected to the input pin FB of the error amplification and compensation module 2. The output pin VCOMP of the error amplification and compensation module 2 is connected to the input pin of the voltage-to-current conversion module 3. The output pin of the voltage-to-current conversion module 3 is connected to the positive input pin of the first difference module 4 and the negative input pin of the second difference module 5, respectively. The negative input pin of the first difference module 4 is connected to the ramp compensation current ISP. The positive input pin of the second difference module 5 is connected to the PFM threshold current ITURN. The output pin of the second difference module 5 is connected to... The input pin IOSC of the clock generator 6 is connected to the output pin CLK of the clock generator 6; the output pin CLK of the clock generator 6 is connected to the input pin CLK of the PWM trigger and drive module 7; the output pin of the first difference module 4 is connected to the input pin ISET of the PWM trigger and drive module 7; the output pin HS of the PWM trigger and drive module 7 is connected to the input pin HS of the switching power stage 8; the output pin LS of the PWM trigger and drive module 7 is connected to the input pin LS of the switching power stage 8; and the input pin VIN of the switching power stage 8 is connected to the input voltage VIN.

[0038] The filtering and feedback module 1 has one input pin (SW) and two output pins (FB and VOUT). The switching signal SW connected to the input pin (SW) is one of the outputs of the switching power stage 8. After filtering, the switching signal SW produces the output voltage VOUT, which supplies power to the external load. The output voltage VOUT is then fed back to the sampling feedback voltage FB via voltage sampling feedback and connected to the input of the error amplification and compensation module 2.

[0039] Error amplification and compensation module 2 has one input pin (FB) and one output pin (VCOMP). The sampled feedback voltage FB is amplified and compensated internally, and then the resulting voltage signal VCOMP is sent to voltage-to-current conversion module 3.

[0040] Voltage-to-current conversion module 3 converts the VCOMP signal into a voltage-to-current converter with the on-resistance R of the upper transistor. ds(on) Sampling resistor value R SNS After the preset ratio related to the upper and lower limits of the VCOMP pin voltage is converted into a current signal ICOMP, it is sent to the first difference module 4 to calculate the difference between the ICOMP current and the slope compensation current ISP, and to the second difference module 5 to calculate the difference between the ICOMP current and the PFM threshold current ITURN. Specifically, when differing from ISP, ICOMP is positive and ISP is negative; the sum is ISET', which is sent to the input of the PWM trigger and drive module 7. When differing from ITURN, ICOMP is negative and ITURN is positive; the sum is the net IOSC current value, which is sent to the clock generator 6.

[0041] Clock generator 6 adjusts the clock CLK frequency according to the input current IOSC, and the generated new clock signal CLK is input to the input terminal of PWM trigger and drive module 7.

[0042] The PWM trigger and driver module 7 has three inputs: the SW, ISET, and clock CLK signals of the switching power stage 8. Its outputs are the HS and LS signals, which control the turn-on and turn-off of the upper and lower transistors of the switching power stage 8. The SW, ISET, and CLK signals jointly control the turn-on time and timing of HS and LS. The SW and VIN signals reflect the current information of the upper transistor and are used for loop control.

[0043] The switching power stage 8 is controlled by HS and LS to generate the SW signal based on VIN, and the SW signal is input to the filtering and feedback module 1.

[0044] Figure 2 This is a schematic diagram of the specific circuit connection of a current-mode-based fixed-frequency PWM controller provided in an embodiment of the present invention. See also... Figure 2The filtering and feedback module 1 includes: an inductor L, an output capacitor C, an upper voltage divider resistor R1, and a lower voltage divider resistor R2; one end of the inductor L is the input terminal SW pin of the filtering and feedback module, connected to the switching signal SW generated by the output terminal SW pin of the switching power stage; the other end of the inductor L is connected to one end of the output capacitor C and one end of the upper voltage divider resistor R1; the other end of the upper voltage divider resistor R1 is connected to one end of the lower voltage divider resistor R2; the other end of the lower voltage divider resistor R2 and the other end of the output capacitor C are both grounded; the other end of the inductor L is the output terminal VOUT pin of the filtering and feedback module, generating an output voltage VOUT; the other end of the upper voltage divider resistor R1 is the output terminal FB pin of the filtering and feedback module, generating a sampling feedback voltage FB.

[0045] As can be seen, the filtering and feedback module 1 consists of an inductor L, an output capacitor C, an upper voltage divider resistor R1, and a lower voltage divider resistor R2. The switching signal SW is filtered by an LC circuit to obtain the output voltage VOUT. R1 and R2 sample VOUT to obtain the sampling feedback voltage FB, which represents the voltage information of VOUT.

[0046] See Figure 2 The error amplification and compensation module 2 includes: an error operational amplifier U1; the non-inverting input terminal of the error operational amplifier U1 is connected to the reference voltage VREF; the inverting input terminal of the error operational amplifier U1 is the input terminal FB pin of the error amplification and compensation module, which is connected to the sampling feedback voltage FB; the output terminal of the error operational amplifier U1 is the output terminal VCOMP pin of the error amplification and compensation module, which generates a voltage signal VCOMP.

[0047] As can be seen, the sampled feedback voltage FB is connected to the inverting input of the error operational amplifier (EA) U1 in the error amplification and compensation module 2. The non-inverting input of EA is the reference voltage VREF. After comparing VREF with the sampled FB voltage, the error is amplified and compensated to obtain the voltage signal VCOMP. For a peak current mode controlled DC / DC, VCOMP represents the peak current reference of the inductor current. When the output voltage VOUT increases due to disturbance, FB increases, VCOMP decreases, the peak inductor current decreases, and the output voltage decreases, and vice versa. Therefore, VCOMP can characterize the inductor current information required to maintain stable operation of the DC / DC. When the DC / DC is operating stably, the inductor current equals the load current, and VCOMP can characterize the load current information.

[0048] See Figure 2The voltage-to-current conversion module 3 includes: a voltage-to-current converter U2; the positive input terminal of the voltage-to-current converter U2 is the input pin of the voltage-to-current conversion module and is connected to the voltage signal VCOMP; the negative input terminal of the voltage-to-current converter U2 is grounded; the output terminal of the voltage-to-current converter U2 is the output pin of the voltage-to-current conversion module and generates the current signal ICOMP.

[0049] As can be seen, the voltage signal VCOMP is sent to the voltage-to-current conversion module 3, converted into a current signal, and the conversion gain is set to the preset value GVI, resulting in the current signal ICOMP.

[0050] See Figure 2 The first difference module 4 includes: a current mirror U3 and a slope compensation current source; the input terminal of the current mirror U3 is the positive input terminal pin of the first difference module, connected to the current signal ICOMP; the output terminal of the current mirror U3 is connected to one end of the slope compensation current source; the other end of the slope compensation current source is grounded; one end of the slope compensation current source is the negative input terminal pin of the first difference module, generating a slope compensation current ISP; the connection point of the current mirror U3 and the slope compensation current source leads out to the output terminal pin of the first difference module, generating a first difference current ISET'.

[0051] The second difference module 5 includes: a current mirror U4, a current mirror U5, diode D1, diode D2, and a PFM threshold current source; the input terminal of the current mirror U4 is the negative input pin of the second difference module, connected to the current signal ICOMP; the output terminal of the current mirror U4 is connected to the positive terminal of diode D1, the negative terminal of diode D2, and one end of the PFM threshold current source; one end of the PFM threshold current source is the positive input pin of the second difference module, generating the PFM threshold current ITURN; the other end of the PFM threshold current source is grounded; the negative terminal of diode D1 is connected to the power supply voltage VCC; the positive terminal of diode D2 is connected to the input terminal of the current mirror U5; the output terminal of the current mirror U5 is the output pin of the second difference module, generating the second difference current IOSC.

[0052] As can be seen, the ICOMMP current is sent to the first difference module 4 and the second difference module 5 respectively, and U3 and U4 are 1:1 current mirrors. In the first difference module 4, the ICOMMP current is subtracted from the preset slope compensation current ISP. According to the node current law, the current value of the first difference circuit ISET' is ICOMMP minus ISP. However, the comparison logic is slightly different for the second difference module 5, which subtracts the ICOMMP current from the PFM threshold current ITURN. The second difference module 5 consists of a current mirror U4, two diodes D1 and D2, VCC power supply voltage, PFM threshold current ITURN, and a 1:1 current mirror U5. When ICOMMP is greater than ITURN, D1 is turned on, D2 is turned off, the input current of U5 is 0, and IOSC is 0. When the load current and ICOMMP drop to less than ITURN, D1 is turned off, D2 is turned on, and the input current of U5 is ITURN minus ICOMMP, which is the net difference between the two, thus obtaining the second difference current IOSC, which is given to the clock generator 6.

[0053] See Figure 2 The clock generator 6 includes: a clock oscillation current source ICLK, a capacitor C_CLK, a reset device S3, and a comparator U6; one end of the clock oscillation current source ICLK is connected to one end of the capacitor C_CLK, one end of the reset device S3, and the positive input terminal of the comparator U6; the other end of the clock oscillation current source ICLK, the other end of the capacitor C_CLK, and the other end of the reset device S3 are grounded; the positive input terminal of the comparator U6 is the input terminal IOSC pin of the clock generator, connected to the second differential current IOSC; the negative input terminal of the comparator U6 is connected to the reference voltage VREF; the output terminal of the comparator U6 is connected to the control terminal of the reset device S3; the output terminal of the comparator U6 is the output terminal CLK pin of the clock generator, generating a clock signal CLK.

[0054] As can be seen, clock generator 6 consists of a clock oscillation current source ICLK, capacitor C_CLK, reset circuit S3, reference voltage VREF, and comparator U6. The principle of clock generator 6 is as follows: assuming the voltage across C_CLK is 0, the non-inverting input voltage of U6 is less than the inverting input voltage VREF, CLK is 0, and ICLK charges C_CLK. When C_CLK is charged to the point where its voltage is greater than VREF, CLK becomes 1, S3 conducts, resetting the C_CLK capacitor, and CLK returns to 0. The duration of CLK being 1 depends on the propagation delay of U6, which is typically in the nanosecond range. The pulse interval between two CLK pulses is defined as one clock cycle, or switching cycle. When the ICOMMP current and the current IOSC generated by the second difference module 5 are supplied to clock generator 6, the actual current charging C_CLK is ICLK minus IOSC. The larger the IOSC value, the smaller the charging slope of C_CLK, the longer the time required for the voltage across C_CLK to charge from 0 to VREF, the longer the switching cycle, and the smaller the switching frequency.

[0055] Based on the principles of ICOMP current and the second difference module 5 and clock generator 6, it can be seen that when the load current decreases, EA controls VCOMP to decrease, and ICOMP to decrease. When ICOMP decreases to the preset ITURN, that is, when the load current decreases to the preset value corresponding to ITURN, the switching cycle of the clock generator begins to decrease. The smaller the load current, the smaller ICOMP, and the larger the difference between ITURN and ICOMP, the longer the switching cycle and the lower the switching frequency. This achieves the efficient control effect of fixed frequency under heavy load and reduced frequency under light load.

[0056] See Figure 2The PWM trigger and drive module 7 includes: a current mirror U7, a current sampling resistor RSNS, a PWM comparator U8, a latch U9, and a drive and dead-time control circuit U10; the input terminal of the current mirror U7 is the ISET pin of the PWM trigger and drive module, connected to the first difference current ISET'; the output terminal of the current mirror U7 is connected to one end of the current sampling resistor RSNS and the positive input terminal of the PWM comparator U8; the negative input terminal of the PWM comparator U8 is the SW pin of the PWM trigger and drive module, connected to the switching signal. SW; The output of the PWM comparator U8 is connected to the R input of the latch U9; The S input of the latch U9 is the CLK pin of the PWM flip-flop and drive module, connected to the clock signal CLK; The non-inverting output of the latch U9 generates the control signal PWM; The input of the drive and dead-time control circuit U10 is connected to the control signal PWM; The two outputs of the drive and dead-time control circuit U10 are the HS pin and the LS pin of the PWM flip-flop and drive module, respectively, generating the upper transistor drive signal HS and the lower transistor drive signal LS.

[0057] The switching power stage 8 includes an upper power transistor S1 and a lower power transistor S2. The gate of the upper power transistor S1 is the input terminal HS pin of the switching power stage, connected to the upper transistor drive signal HS. The drain of the upper power transistor S1 is the input terminal VIN pin of the switching power stage, connected to the input voltage VIN. The source of the upper power transistor S1 is the output terminal SW pin of the switching power stage, generating a switching signal SW. The gate of the lower power transistor S2 is the input terminal LS pin of the switching power stage, connected to the lower transistor drive signal LS. The drain of the lower power transistor S2 is connected to the source of the upper power transistor S1. The source of the lower power transistor S2 is grounded.

[0058] As can be seen, the PWM trigger and drive module 7 consists of a current mirror U7, a current sampling resistor RSNS, a PWM comparator 8, a latch U9, and a drive and dead-time control circuit U10. Its working principle is as follows: at the beginning of each cycle, CLK is high, SET of U9 is set to 1, Q is high, PWM is high, and the drive and dead-time control circuit U10 controls HS to be high, turning on the upper power transistor S1. The SW voltage should be VIN minus the upper transistor current IDS multiplied by the upper transistor's on-resistance Rds(on). When the upper transistor current increases, the SW voltage decreases. The inverting input of U8 decreases. According to the loop voltage law, the non-inverting input voltage of U8 should be VIN minus RSNS multiplied by ISET. When the upper transistor is on, ISP increases, ISET decreases, and the non-inverting input of U8 increases. When it exceeds the SW voltage, the PWM comparator U8 is high, the RESET input of the latch U9 is 1, and PWM is low. When the drive and dead-time control chip U10 controls HS to be low, the upper power transistor S1 is turned off, and the lower power transistor S2 is turned on for freewheeling. Note that when the load current decreases and ISET is lower than ISET_MIN, the output of U7 no longer decreases. This means that when the load current is low, the peak value of the inductor current is constant and no longer decreases with the decrease of the load.

[0059] Figure 3 This is a flowchart illustrating the logic of a current-mode-based fixed-frequency PWM controller entering the PFM stage, as provided in an embodiment of the present invention. See also... Figure 3 For ease of understanding, the input voltage VIN is set to 12V, the output voltage VOUT to 5V, and the switching signal TSW period to 1µs, i.e., the switching frequency to 1MHz. The control mode is Peak Current Mode (PCM). When the load is not light, the conduction time of the upper power transistor S1 is controlled by the error amplifier U1 and the clock CLK. The output voltage VCOMP of the error amplifier U1 is converted to the current ICOMMP by a voltage-to-current (VI) converter with a ratio of GVI. When the load decreases, VCOMP decreases, and ICOMMP also decreases. If ICOMMP is greater than ITURN, the switching period remains unchanged. When ICOMMP is less than ITURN, the difference between the two, IOSC, is taken. The next switching period becomes longer, the switching frequency decreases, and the controller enters PFM control mode. The smaller the load, the larger the IOSC, the longer the switching period, the lower the switching frequency, and the higher the efficiency. When the load increases, VCOMP also increases. When ICOMMP obtained through VI conversion is greater than ITURN, the controller exits PFM and returns to PWM control, and the switching period returns to CLK clock control.

[0060] Based on the aforementioned fixed-frequency PWM controller, the present invention also provides a current-mode-based fixed-frequency PWM control method, the fixed-frequency PWM control method comprising:

[0061] The filtering and feedback module 1 filters the switching signal SW through an LC filter to obtain an output voltage VOUT, which is then used to power an external load. The output voltage VOUT is then fed back through the voltage sampling of the filtering and feedback module to obtain a sampling feedback voltage FB.

[0062] The error amplification and compensation module 2 sends the sampled feedback voltage FB into its internal system for amplification and compensation processing, and then generates a voltage signal VCOMP.

[0063] Voltage-to-current conversion module 3 converts the voltage signal VCOMP into a current signal ICOMP according to a preset conversion gain GVI;

[0064] The first difference module 4 takes the difference between the current signal ICOMMP and the ramp current compensation ISP to obtain the first difference current ISET'.

[0065] The second difference module 5 takes the difference between the current signal ICOMMP and the PFM threshold current ITURN to obtain the second difference current IOSC.

[0066] Clock generator 6 adjusts the clock frequency according to the second differential current IOSC to generate clock signal CLK;

[0067] The PWM trigger and drive module 7 controls the turn-on time and timing of the upper and lower transistors in the switching power stage according to the switching signal SW, the first differential current ISET' and the clock signal CLK, and generates the upper transistor drive signal HS and the lower transistor drive signal LS.

[0068] The switching power stage 8 processes the input voltage VIN into a switching signal SW based on the upper transistor drive signal HS and the lower transistor drive signal LS.

[0069] The core of this invention's current-mode fixed-frequency PWM controller consists of an error amplification and compensation module, a voltage-to-current conversion module, and a current comparator. The related control method is applicable to Current Mode (CM). In this control mode, the output voltage VCOMP of EA can characterize the peak / valley or average value of the inductor current in the topology, and similarly, it can also characterize the load current. When the load decreases, the VCOMP voltage will inevitably decrease as well. After VI transformation, a current ICOMP containing inductor current information is obtained. If this current is greater than the preset current ITURN, the clock frequency is not reduced. If this current is less than the preset ITURN, the difference between ICOMP and ITURN is used to reduce the clock frequency. The smaller the load, the smaller ICOMP, and the larger the difference between ICOMP and ITURN, the lower the clock frequency, achieving a high-efficiency control effect under heavy loads (fixed frequency) and light loads (reduced frequency).

[0070] Existing light-load frequency converter control requires complex control logic, necessitating numerous logic circuits and clock synchronization. It also requires additional control circuitry to extend the turn-off time or clock cycle to reduce the switching frequency under light load conditions. Furthermore, some techniques are unsuitable for applications requiring extremely high / low duty cycles. In contrast, the method of this invention utilizes the inherent current information from the output COMP voltage of the EA (Electronic Amplifier), employing VI (Vibration Variable Interval) conversion and a current comparator to automatically enable the fixed-frequency PWM controller to switch to light-load frequency conversion under light load conditions. This method features simple logic, high light-load efficiency, predictable PFM (Power Factor Flow) entry point, and eliminates the need for additional operational amplifiers for PFM management, resulting in high circuit simplicity. Moreover, the control logic and method provided by this invention can be applied to various clock-based fixed-frequency DC / DC circuits, exhibiting strong portability and low implementation difficulty.

[0071] Figure 4 Simulation results of the control method of this invention are shown, with time on the horizontal axis and output voltage VOUT on the vertical axis. Figure 4 As can be seen, the initial load is 5mA. After 1ms, a load with a current of 2A / µs is added, causing a sudden increase to 2.005A. At 3ms, the load suddenly drops back to 5mA, with a slope of 2A / µs. This demonstrates that the control method of this invention effectively meets the requirements of light-load frequency conversion, reducing the switching frequency under light load and improving light-load efficiency.

[0072] The current-mode-based fixed-frequency PWM controller and control method provided by this invention are applied to clock-based fixed-frequency PWM DC / DC converters. Based on the current-mode principle, the controller automatically adjusts its frequency when operating under light loads, reducing switching-related losses and ensuring high efficiency under light loads. This invention offers high versatility and can be used under various operating conditions, including extremely high / low duty cycles and high / low switching frequencies. Furthermore, the single-pulse control ensures minimal output voltage ripple, demonstrating broad application prospects.

[0073] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the control method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A current-mode fixed-frequency PWM controller, characterized in that, include: The system includes a filtering and feedback module, an error amplification and compensation module, a voltage-to-current conversion module, a first difference module, a second difference module, a clock generator, a PWM trigger and drive module, and a switching power stage. The output terminal SW pin of the switching power stage is connected to the input terminal SW pin of the filtering and feedback module and the input terminal SW pin of the PWM trigger and drive module, respectively; the output terminal VOUT pin of the filtering and feedback module generates an output voltage VOUT to supply power to the external load. The output pin FB of the filtering and feedback module is connected to the input pin FB of the error amplification and compensation module; the output pin VCOMP of the error amplification and compensation module is connected to the input pin of the voltage-to-current conversion module; the output pin of the voltage-to-current conversion module is connected to the positive input pin of the first difference module and the negative input pin of the second difference module, respectively; the negative input pin of the first difference module is connected to the ramp compensation current ISP; the positive input pin of the second difference module is connected to the PFM threshold current ITURN; the output pin of the second difference module is connected to the input pin IOSC of the clock generator; the output pin CLK of the clock generator is connected to the input pin CLK of the PWM trigger and drive module; the output pin of the first difference module is connected to the input pin ISET of the PWM trigger and drive module; the output pin HS of the PWM trigger and drive module is connected to the input pin HS of the switching power stage; the output pin LS of the PWM trigger and drive module is connected to the input pin LS of the switching power stage; the input pin VIN of the switching power stage is connected to the input voltage VIN. The first difference module includes: a current mirror U3 and a slope compensation current source; the input terminal of the current mirror U3 is the positive input terminal pin of the first difference module, connected to the current signal ICOMP; the output terminal of the current mirror U3 is connected to one end of the slope compensation current source; one end of the slope compensation current source is the negative input terminal pin of the first difference module, generating the slope compensation current ISP; the other end of the slope compensation current source is grounded; the connection point of the current mirror U3 and the slope compensation current source leads out to the output terminal pin of the first difference module, generating a first difference current ISET'; The current value of the first difference circuit ISET' is ICOMMP minus ISP; The PWM trigger and drive module includes: a current mirror U7, a current sampling resistor RSNS, a PWM comparator U8, a latch U9, and a drive and dead-time control circuit U10; the input terminal of the current mirror U7 is the input terminal ISET pin of the PWM trigger and drive module, which is connected to the first differential current ISET'.

2. The fixed-frequency PWM controller according to claim 1, characterized in that, The filtering and feedback module includes: an inductor L, an output capacitor C, an upper voltage divider resistor R1, and a lower voltage divider resistor R2; one end of the inductor L is the input terminal SW pin of the filtering and feedback module, connected to the switching signal SW generated by the output terminal SW pin of the switching power stage; the other end of the inductor L is connected to one end of the output capacitor C and one end of the upper voltage divider resistor R1; the other end of the upper voltage divider resistor R1 is connected to one end of the lower voltage divider resistor R2 and is the output terminal FB pin of the filtering and feedback module, generating a sampling feedback voltage FB; the other end of the lower voltage divider resistor R2 and the other end of the output capacitor C are both grounded; the other end of the inductor L is the output terminal VOUT pin of the filtering and feedback module, generating an output voltage VOUT.

3. The fixed-frequency PWM controller according to claim 2, characterized in that, The error amplification and compensation module includes: an error operational amplifier U1; the non-inverting input terminal of the error operational amplifier U1 is connected to the reference voltage VREF; the inverting input terminal of the error operational amplifier U1 is the input terminal FB pin of the error amplification and compensation module, which is connected to the sampling feedback voltage FB; the output terminal of the error operational amplifier U1 is the output terminal VCOMP pin of the error amplification and compensation module, which generates a voltage signal VCOMP.

4. The fixed-frequency PWM controller according to claim 3, characterized in that, The voltage-to-current conversion module includes: a voltage-to-current converter U2; the positive input terminal of the voltage-to-current converter U2 is the input pin of the voltage-to-current conversion module and is connected to the voltage signal VCOMP; the negative input terminal of the voltage-to-current converter U2 is grounded; the output terminal of the voltage-to-current converter U2 is the output pin of the voltage-to-current conversion module and generates the current signal ICOMP.

5. The fixed-frequency PWM controller according to claim 4, characterized in that, The second difference module includes: a current mirror U4, a current mirror U5, diode D1, diode D2, and a PFM threshold current source; the input terminal of the current mirror U4 is the negative input pin of the second difference module, connected to the current signal ICOMP; the output terminal of the current mirror U4 is connected to the anode of diode D1, the cathode of diode D2, and one end of the PFM threshold current source; one end of the PFM threshold current source is the positive input pin of the second difference module, generating the PFM threshold current ITURN; the other end of the PFM threshold current source is grounded; the cathode of diode D1 is connected to the power supply voltage VCC; the anode of diode D2 is connected to the input terminal of the current mirror U5; the output terminal of the current mirror U5 is the output pin of the second difference module, generating the second difference current IOSC.

6. The fixed-frequency PWM controller according to claim 5, characterized in that, The clock generator includes: a clock oscillation current source ICLK, a capacitor C_CLK, a reset device S3, and a comparator U6; one end of the clock oscillation current source ICLK is connected to one end of the capacitor C_CLK, one end of the reset device S3, and the positive input terminal of the comparator U6; the other end of the clock oscillation current source ICLK, the other end of the capacitor C_CLK, and the other end of the reset device S3 are grounded; the positive input terminal of the comparator U6 is the input terminal IOSC pin of the clock generator, connected to the second differential current IOSC; the negative input terminal of the comparator U6 is connected to the reference voltage VREF; the output terminal of the comparator U6 is connected to the control terminal of the reset device S3; the output terminal of the comparator U6 is the output terminal CLK pin of the clock generator, generating a clock signal CLK.

7. The fixed-frequency PWM controller according to claim 6, characterized in that, The output terminal of the current mirror U7 is connected to one end of the current sampling resistor RSNS and the positive input terminal of the PWM comparator U8, respectively; the negative input terminal of the PWM comparator U8 is the input terminal SW pin of the PWM trigger and drive module, and is connected to the switching signal SW; the output terminal of the PWM comparator U8 is connected to the R input terminal of the latch U9; the S input terminal of the latch U9 is the input terminal CLK pin of the PWM trigger and drive module, and is connected to the clock signal CLK; the positive output terminal of the latch U9 generates the control signal PWM; the input terminal of the drive and dead-time control circuit U10 is connected to the control signal PWM; the two output terminals of the drive and dead-time control circuit U10 are the output terminal HS pin and the output terminal LS pin of the PWM trigger and drive module, respectively, generating the upper transistor drive signal HS and the lower transistor drive signal LS.

8. The fixed-frequency PWM controller according to claim 7, characterized in that, The switching power stage includes an upper power transistor S1 and a lower power transistor S2. The gate of the upper power transistor S1 is the input terminal HS pin of the switching power stage, connected to the upper transistor drive signal HS. The drain of the upper power transistor S1 is the input terminal VIN pin of the switching power stage, connected to the input voltage VIN. The source of the upper power transistor S1 is the output terminal SW pin of the switching power stage, generating the switching signal SW. The gate of the lower power transistor S2 is the input terminal LS pin of the switching power stage, connected to the lower transistor drive signal LS. The drain of the lower power transistor S2 is connected to the source of the upper power transistor S1. The source of the lower power transistor S2 is grounded.

9. A current-mode-based fixed-frequency PWM control method, characterized in that, Based on any one of claims 1-8, the fixed-frequency PWM controller; the fixed-frequency PWM control method includes: The filtering and feedback module filters the switching signal SW through an LC filter to obtain an output voltage VOUT, which is then used to power the external load. The output voltage VOUT is then fed back through the voltage sampling of the filtering and feedback module to obtain a sampled feedback voltage FB. The error amplification and compensation module sends the sampled feedback voltage FB into its internal system for amplification and compensation processing, and then generates a voltage signal VCOMP. The voltage-to-current conversion module converts the voltage signal VCOMP into a current signal ICOMMP according to a preset conversion gain GVI. The first difference module takes the difference between the current signal ICOMP and the slope compensation current ISP to obtain the first difference current ISET'; The second difference module takes the difference between the current signal ICOMP and the PFM threshold current ITURN to obtain the second difference current IOSC; The clock generator adjusts the clock frequency according to the second differential current IOSC to generate a clock signal CLK; The PWM trigger and drive module jointly control the turn-on time and timing of the upper and lower transistors in the switching power stage according to the switching signal SW, the first differential current ISET' and the clock signal CLK, and generate the upper transistor drive signal HS and the lower transistor drive signal LS; The switching power stage processes the input voltage VIN into the switching signal SW based on the upper MOSFET drive signal HS and the lower MOSFET drive signal LS.

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