Programmable gain amplifier circuit for extending dynamic range of an image sensor

Abstract

The application relates to a programmable gain amplifier circuit for extending the dynamic range of an image sensor, comprising a switched capacitor circuit and a negative feedback DC offset cancellation circuit; the switched capacitor circuit is used for twice correlated double sampling and amplification processing of the output signal of the image sensor pixel column, eliminating the fixed pattern noise and reset thermal noise, and outputting high-sensitivity and low-sensitivity analog voltages; the negative feedback DC offset cancellation circuit is used for reducing the influence of the offset voltage of the main operational amplifier on the output voltage by adopting an operational amplifier offset voltage storage mode. In the application, the image column fixed pattern noise caused by the offset voltage of the main operational amplifier can be greatly reduced through the operational amplifier offset storage technology, and the high-sensitivity and low-sensitivity analog signal inputs can be provided for the post-processing circuit in time through the twice correlated double sampling processing technology, so that the dynamic range of the image sensor is extended, and the image imaging quality is improved.

Description

Technical Field

[0001] This invention belongs to the field of image sensor technology and relates to a programmable gain amplifier circuit that extends the dynamic range of an image sensor. Background Technology

[0002] With the development of modern computer technology and information processing technology, intelligent systems are increasingly helping humans process various complex information from the outside world, including sounds, light, temperature, pressure, and smells from nature. Humans receive information from the outside world through their five senses, with the eyes acquiring the largest amount of information through images. Statistics show that 75% of the information humans acquire is through their visual organs. Based on the enormous amount of information in visual images, advanced image acquisition technology has become an important component of modern intelligent systems. With the continuous development of CMOS technology, the application of CMOS image sensors is becoming increasingly widespread due to their low power consumption, simple power supply, high integration, and low cost. As the requirements for image quality continue to increase, the dynamic range of image sensors is constantly expanding, placing higher demands on the corresponding readout circuits.

[0003] Changes in the application environment (such as variations in temperature and light intensity) or significant differences in light intensity within the same image can directly affect the signal strength and performance of a CMOS image sensor. To adapt to changes in signal strength, a programmable gain amplifier (PGA) is typically placed at the output of the CMOS image sensor to adjust the signal strength and meet the requirements for a large dynamic range. In existing technologies, the PGA circuit employs a PGA circuit with offset cancellation technology, internally implementing functions such as sample-and-hold, correlation double sampling, and offset calibration. The operation involves two steps: the first step samples the pixel reset signal and the amplifier's offset voltage signal, and outputs a reference voltage; the second step samples the integrated pixel signal, and outputs the difference between the two sampled analog signals, thereby eliminating fixed-mode noise in the pixel unit and KTC noise in the reset transistor, while also performing offset calibration to reduce the impact of fixed-mode noise. However, existing PGAs can only acquire one pixel reset signal and one pixel integration signal, and cannot be used in high dynamic range image sensors that extend the dynamic range of the image sensor. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a programmable gain amplifier circuit that extends the dynamic range of an image sensor.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A programmable gain amplifier circuit for extending the dynamic range of an image sensor includes a switched capacitor circuit and a negative feedback DC offset cancellation circuit; the switched capacitor circuit and the negative feedback DC offset cancellation circuit have a common circuit, which is a main operational amplifier.

[0007] The switched capacitor circuit is used to perform two correlation double sampling and amplification processing on the output signal of the pixel column of the image sensor, eliminate fixed pattern noise and reset thermal noise, and output high-sensitivity and low-sensitivity analog voltages.

[0008] The negative feedback DC offset cancellation circuit is used to reduce the impact of the main operational amplifier's offset voltage on the output voltage by storing the operational amplifier's offset voltage, thereby reducing the image column fixed-mode noise caused by the main operational amplifier's offset voltage.

[0009] Furthermore, the main operational amplifier is a differential input, single-ended output amplifier; the main operational amplifier adopts a single-stage differential structure or a two-stage differential structure.

[0010] Furthermore, the switched-capacitor circuit includes a main operational amplifier and a low-sensitivity sampling capacitor C. s_a Low-sensitivity sampling switch Sa, high-sensitivity sampling capacitor C s_b and the high-sensitivity sampling switch Sb; the low-sensitivity sampling capacitor C s_-a The first terminal is connected to the high-sensitivity sampling capacitor C s_b The first terminal, after being electrically connected, serves as the input terminal of the switched capacitor circuit for connecting the output signal of the image sensor pixel column; the low-sensitivity sampling capacitor C s_a The second terminal is electrically connected to the first terminal of the low-sensitivity sampling switch Sa, and the high-sensitivity sampling capacitor C... s_b The second terminal of the low-sensitivity sampling switch Sa is electrically connected to the first terminal of the high-sensitivity sampling switch Sb. After the second terminal of the low-sensitivity sampling switch Sa is electrically connected to the second terminal of the high-sensitivity sampling switch Sb, it serves as the output terminal of the switched capacitor circuit and is electrically connected to the inverting input terminal of the main operational amplifier. The non-inverting input terminal of the main operational amplifier is connected to the common-mode voltage.

[0011] Furthermore, the negative feedback DC offset cancellation circuit includes an offset voltage sampling capacitor C. F The system comprises a first switch S1, a second switch S2, a third switch S3, and a main operational amplifier; the first terminal of the first switch S1 is electrically connected to the inverting input terminal of the main operational amplifier, and the second terminal of the first switch S1 is electrically connected to the output terminal of the main operational amplifier; the offset voltage sampling capacitor C... F The first terminal is electrically connected to the first terminal of the first switch S1, and the offset voltage sampling capacitor C FThe second terminal is electrically connected to the first terminal of the second switch S2 and the first terminal of the third switch S3, respectively; the second terminal of the second switch S2 is connected to the common-mode voltage, and the second terminal of the third switch S3 is electrically connected to the output terminal of the main operational amplifier.

[0012] Furthermore, the offset voltage sampling capacitor C F The DC offset cancellation capacitor serves as negative feedback in the DC offset cancellation circuit.

[0013] Furthermore, when the programmable gain amplifier circuit performs time-division offset storage processing and correlation double sampling processing on the signal output from the pixel column of the high dynamic range image sensor, it includes the following steps:

[0014] S101, low-sensitivity sampling switch Sa, high-sensitivity sampling switch Sb, first switch S1 and second switch S2 are closed, third switch S3 is open, and the high dynamic range image sensor pixel column outputs a low-sensitivity pixel reset signal RST_L; offset voltage sampling capacitor C F The offset voltage of the main operational amplifier is sampled; simultaneously, the low-sensitivity sampling capacitor C... s_a and high-sensitivity sampling capacitor C s_b Sample the low-sensitivity pixel reset signal RST_L;

[0015] S102, the low-sensitivity sampling switch Sa is open. At this time, the low-sensitivity pixel reset signal RST_L is stored in the low-sensitivity sampling capacitor C. s_a middle;

[0016] S103, High Dynamic Range Image Sensor Pixel Column Output High Sensitivity Pixel Reset Signal RST_H, High Sensitivity Sampling Capacitor C s_b Sample the high-sensitivity pixel reset signal RST_H;

[0017] S104, the first switch S1 and the second switch S2 are opened sequentially. At this time, the high-sensitivity pixel reset signal RST_H is stored in the high-sensitivity sampling capacitor C. s_b In the process, the offset voltage of the main operational amplifier is stored in the offset voltage sampling capacitor C. F In the middle; then the third switch S3 closes, and the high dynamic range image sensor pixel column outputs a high-sensitivity pixel integration signal SIG_H. The high-sensitivity pixel integration signal SIG_H interacts with the high-sensitivity sampling capacitor C. s_b The high-sensitivity pixel reset signal RST_H is stored, and the difference is taken to obtain the high-sensitivity effective image signal. The high-sensitivity effective image signal is amplified by the main operational amplifier, and after passing through a negative feedback DC offset cancellation circuit to reduce the influence of the offset voltage of the main operational amplifier, a high-sensitivity analog output signal V is output. out_H ;

[0018] S105, the high-sensitivity sampling switch Sb is opened. Subsequently, the third switch S3 is opened, and the first switch S1 and the second switch S2 are closed. The offset voltage sampling capacitor C... F The offset voltage of the main operational amplifier is sampled again, and stored in the offset voltage sampling capacitor C. F middle;

[0019] S106. The high dynamic range image sensor pixel column outputs a low-sensitivity pixel integration signal SIG_L, and the first switch S1 is opened; subsequently, the second switch S2 is also opened, and the low-sensitivity sampling switch Sa and the third switch S3 are closed. The low-sensitivity pixel integration signal SIG_L interacts with the low-sensitivity sampling capacitor C. s_a The low-sensitivity pixel reset signal RST_L is subtracted to obtain the low-sensitivity effective image signal. This low-sensitivity effective image signal is amplified by the main operational amplifier and then passed through a negative feedback DC offset cancellation circuit to reduce the influence of the main operational amplifier's offset voltage before being output as a low-sensitivity analog output signal V. out_L .

[0020] Furthermore, the high-sensitivity analog output signal V out_H The calculation formula is:

[0021]

[0022] Low-sensitivity analog output signal V out_L The calculation formula is:

[0023]

[0024] Among them, V RST_H This represents the voltage level of the high-sensitivity pixel reset signal RST_H; V SIG_H This indicates the level value of the high-sensitivity pixel integration signal SIG_H; A Indicates the gain of the main operational amplifier; V OS V represents the offset voltage of the main operational amplifier. CM Indicates the common-mode voltage value; V RST_L This represents the level value of the low-sensitivity pixel reset signal RST_L; V SIG_L This indicates the level value of the low-sensitivity pixel integration signal SIG_L.

[0025] Furthermore, when the programmable gain amplifier circuit performs offset storage processing and correlation double sampling processing on the signal output from the pixel column of a common image sensor, it includes the following steps:

[0026] S201, low-sensitivity sampling switch Sa, high-sensitivity sampling switch Sb, first switch S1 and second switch S2 are closed, third switch S3 is open, and the pixel column output of the ordinary image sensor is a pixel reset signal RST; offset voltage sampling capacitor C F The offset voltage of the main operational amplifier is sampled and stored in the offset voltage sampling capacitor C. F In the middle; at the same time, the low-sensitivity sampling capacitor C s_a and high-sensitivity sampling capacitor C s_b Sample the pixel reset signal RST and store it in the low-sensitivity sampling capacitor C. s_a and high-sensitivity sampling capacitor C s_b middle;

[0027] Switches S202, S1, and S2 are sequentially opened, followed by the closing of the third switch S3. The ordinary image sensor outputs a pixel integration signal SIG from its pixel column. This pixel integration signal SIG interacts with the low-sensitivity sampling capacitor C. s_a and high-sensitivity sampling capacitor C s_b The difference between the stored pixel reset signal RST and the actual image signal is obtained from the pixel column output of a common image sensor. This effective image signal is amplified by the main operational amplifier and then passed through a negative feedback DC offset cancellation circuit to reduce the influence of the main operational amplifier's offset voltage before being output as a common image analog output signal V. out .

[0028] Furthermore, the ordinary image analog output signal V out The calculation formula is:

[0029]

[0030] Among them, V RST This indicates the voltage level of the pixel reset signal RST; V SIG This indicates the level value of the pixel integration signal SIG; V CM Indicates the common-mode voltage value; A The gain of the main operational amplifier; V OS This is the offset voltage of the main operational amplifier.

[0031] In this invention, by employing operational amplifier offset storage technology, the impact of the main operational amplifier's offset voltage on the output voltage can be significantly reduced, thereby reducing image column fixed-mode noise caused by the main operational amplifier's offset voltage. Simultaneously, for the high-sensitivity and low-sensitivity signals output by a high dynamic range image sensor in a time-division multiplexing manner, double correlation double sampling processing technology is used to eliminate pixel fixed-mode noise and reset thermal noise in the high-sensitivity and low-sensitivity signals. The programmable gain amplifier circuit can output in two states. In the extended dynamic range mode of the image sensor, it can output high-sensitivity PGA processed signals and low-sensitivity PGA processed signals in time-division multiplexing, providing high-sensitivity and low-sensitivity analog signal inputs to the subsequent processing circuits. The subsequent processing circuits perform image synthesis processing, extending the dynamic range of the image sensor and thus improving image quality. In normal mode, the programmable gain amplifier can also perform correlation double sampling (CDS) and column fixed-mode noise reduction processing on ordinary image signals, only performing output offset reduction and CDS processing, outputting high-sensitivity / low-sensitivity PGA processed signals, reducing image sensor noise and improving image quality. Attached Figure Description

[0032] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0033] Figure 1 This is a circuit diagram of a preferred embodiment of the programmable gain amplifier circuit for extending the dynamic range of an image sensor according to the present invention.

[0034] Figure 2 A timing diagram for extending the dynamic range mode of an image sensor.

[0035] Figure 3 Another timing diagram for extending the dynamic range mode of an image sensor.

[0036] Figure 4 This is a timing diagram for the normal mode. Detailed Implementation

[0037] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0038] like Figure 1As shown, a preferred embodiment of the programmable gain amplifier circuit for extending the dynamic range of an image sensor according to the present invention includes a switched capacitor circuit and a negative feedback DC offset cancellation circuit; the switched capacitor circuit and the negative feedback DC offset cancellation circuit have a common circuit, which is a main operational amplifier U1; the main operational amplifier U1 is used for signal buffering and amplification. The main operational amplifier U1 is a differential input, single-ended output amplifier; the main operational amplifier U1 can adopt a single-stage differential structure or a two-stage differential structure.

[0039] The switched-capacitor circuit is used to perform double correlation sampling and amplification processing on the output signal of the image sensor pixel column, eliminating fixed-mode noise and reset thermal noise, and providing high-sensitivity and low-sensitivity analog voltage inputs for subsequent processing circuits. The switched-capacitor circuit may include a main operational amplifier U1 and a low-sensitivity sampling capacitor C. s_a Low-sensitivity sampling switch Sa, high-sensitivity sampling capacitor C s_b and the high-sensitivity sampling switch Sb; the low-sensitivity sampling capacitor C s_a and high-sensitivity sampling capacitor C s_b All are variable capacitors, and their capacitance values ​​can be changed through external programming. The low-sensitivity sampling capacitor C... s_-a The first terminal is connected to the high-sensitivity sampling capacitor C s_b The first terminal, after being electrically connected, serves as the input terminal of the switched capacitor circuit and also as the input terminal (Pixel_in terminal) of the programmable gain amplifier circuit, used to input the output signal of the image sensor pixel column; the low-sensitivity sampling capacitor C s_a The second terminal is electrically connected to the first terminal of the low-sensitivity sampling switch Sa, and the high-sensitivity sampling capacitor C... s_b The second terminal of the low-sensitivity sampling switch Sa is electrically connected to the first terminal of the high-sensitivity sampling switch Sb. The second terminal of the low-sensitivity sampling switch Sa, after being electrically connected to the second terminal of the high-sensitivity sampling switch Sb, serves as the output terminal of the switched capacitor circuit and is electrically connected to the inverting input terminal of the main operational amplifier U1 and the negative feedback DC offset cancellation circuit. The non-inverting input terminal of the main operational amplifier U1 is connected to a common-mode voltage.

[0040] The negative feedback DC offset cancellation circuit is used to reduce the impact of the offset voltage of the main operational amplifier U1 on the output voltage by storing the operational amplifier offset voltage, thereby reducing the image column fixed-mode noise caused by the offset voltage of the main operational amplifier U1. The negative feedback DC offset cancellation circuit may include an offset voltage sampling capacitor C. F The circuit consists of the first switch S1, the second switch S2, the third switch S3, and the main operational amplifier U1, which is a common circuit for the switched capacitor circuit and the negative feedback DC offset cancellation circuit. The offset voltage sampling capacitor C... FIt is a variable capacitor, and its capacitance value can be changed through external programming. The first terminal of the first switch S1 is electrically connected to the inverting input terminal of the main operational amplifier U1, and the second terminal of the first switch S1 is electrically connected to the output terminal of the main operational amplifier U1; the offset voltage sampling capacitor C... F The DC offset cancellation capacitor, which serves as negative feedback in the DC offset cancellation circuit, and the offset voltage sampling capacitor C F The first terminal is electrically connected to the first terminal of the first switch S1, and the offset voltage sampling capacitor C F The second terminal is electrically connected to the first terminal of the second switch S2 and the first terminal of the third switch S3, respectively. The second terminal of the second switch S2 is connected to the common-mode voltage, and the second terminal of the third switch S3 is electrically connected to the output terminal of the main operational amplifier U1.

[0041] Because a low-sensitivity sampling capacitor C is set in the switched capacitor circuit s_a and high-sensitivity sampling capacitor C s_b The on / off state of the capacitors is controlled by a low-sensitivity sampling switch Sa and a high-sensitivity sampling switch Sb, respectively. This allows for time-division processing of the high-sensitivity and low-sensitivity image signals output from the pixel column of the high dynamic range image sensor to reduce column fixed-mode noise and perform double correlation sampling (CDS) processing. Under high dynamic timing control, a high-sensitivity analog output signal V can be output in time segments. out_H and low-sensitivity analog output signal V out_L Of course, it's also possible to perform only noise reduction processing and output a normal image analog output signal V under normal timing control. out .

[0042] When the programmable gain amplifier circuit performs time-division offset storage processing and correlation double sampling processing on the signal output from the pixel column of the high dynamic range image sensor, the programmable gain amplifier circuit operates in the extended dynamic range mode of the image sensor, such as... Figure 2 The diagram shows the control timing of the low-sensitivity sampling switch Sa, the high-sensitivity sampling switch Sb, the first switch S1, the second switch S2, and the third switch S3 in this operating mode (3.3V is high level, 0V is low level in the diagram); the processing steps in this operating mode include the following:

[0043] S101, low-sensitivity sampling switch Sa, high-sensitivity sampling switch Sb, first switch S1 and second switch S2 are closed, and third switch S3 is open. The high dynamic range image sensor pixel column outputs a low-sensitivity pixel reset signal RST_L to the Pixel_in terminal of the programmable gain amplifier circuit. Offset voltage sampling capacitor C F The offset voltage of the main operational amplifier U1 is sampled; simultaneously, the low-sensitivity sampling capacitor C... s_a and high-sensitivity sampling capacitor Cs_b The low-sensitivity pixel reset signal RST_L is sampled from the pixel column output of the high dynamic range image sensor.

[0044] S102, the low-sensitivity sampling switch Sa is open. At this time, the low-sensitivity pixel reset signal RST_L output by the high dynamic range image sensor pixel column is stored in the low-sensitivity sampling capacitor C. s_a middle.

[0045] S103, the high dynamic range image sensor pixel column outputs a high-sensitivity pixel reset signal RST_H to the Pixel_in terminal of the programmable gain amplifier circuit, and the high-sensitivity sampling capacitor C... s_b The high-sensitivity pixel reset signal RST_H is sampled from the pixel column output of the high dynamic range image sensor.

[0046] S104, the first switch S1 and the second switch S2 are opened sequentially. At this time, the high-sensitivity pixel reset signal RST_H is stored in the high-sensitivity sampling capacitor C. s_b In the process, the offset voltage of the main operational amplifier U1 is stored in the offset voltage sampling capacitor C. F In the middle. Then, the third switch S3 closes, and the high dynamic range image sensor pixel column outputs a high-sensitivity pixel integration signal SIG_H to the Pixel_in terminal of the programmable gain amplifier circuit. The high-sensitivity pixel integration signal SIG_H output by the high dynamic range image sensor pixel column interacts with the high-sensitivity sampling capacitor C. s_b The difference between the stored high-sensitivity pixel reset signal RST_H and the high-sensitivity effective image signal output from the pixel column of the high-sensitivity image sensor is obtained. The obtained high-sensitivity effective image signal eliminates pixel fixed-mode noise and reset thermal noise in the high-sensitivity pixel integral signal SIG_H, and minimizes the offset voltage of the main operational amplifier U1, thereby improving the high-sensitivity image imaging quality of the image sensor. The high-sensitivity effective image signal is amplified by the main operational amplifier U1, and after passing through a negative feedback DC offset cancellation circuit to reduce the influence of the offset voltage of the main operational amplifier U1, a high-sensitivity analog output signal V is output. out_H .

[0047] High-sensitivity analog output signal V out_H The calculation formula is:

[0048]

[0049] Among them, V RST_H This represents the voltage level of the high-sensitivity pixel reset signal RST_H, measured in volts (V). SIG_H This represents the voltage level of the high-sensitivity pixel integration signal SIG_H, in volts. A V represents the amplification factor of the main operational amplifier U1; OSV represents the offset voltage of the main operational amplifier U1; CM This indicates the common-mode voltage value, measured in volts.

[0050] From the above calculation formula, it can be seen that the high-sensitivity analog output signal V out_H The offset voltage was reduced This minimizes the impact of the offset voltage of the main operational amplifier U1 on the output signal. Simultaneously, (V) RST_H -V SIG_H The CDS processing of the high-sensitivity pixel integral signal SIG_H eliminates pixel fixed pattern noise and reset thermal noise.

[0051] S105, the high-sensitivity sampling switch Sb is opened. Subsequently, the third switch S3 is opened, and the first switch S1 and the second switch S2 are closed. The offset voltage sampling capacitor C... F The offset voltage of the main operational amplifier U1 is sampled again, and stored in the offset voltage sampling capacitor C. F middle.

[0052] S106, the high dynamic range image sensor pixel column outputs a low-sensitivity pixel integration signal SIG_L, and the first switch S1 is opened. The earliest possible time for the high dynamic range image sensor pixel column to output the low-sensitivity pixel integration signal SIG_L can be the moment the first switch S1 is closed in step S105, such as... Figure 2 As shown; the latest possible time is when the first switch S1 is turned off in this step, such as... Figure 3 As shown. Of course, the moment when the high dynamic range image sensor pixel column outputs the low sensitivity pixel integral signal SIG_L can also be any time between the two moments mentioned above (i.e., during the time period when the first switch S1 is closed for the second time). Afterwards, the second switch S2 also opens, the low sensitivity sampling switch Sa and the third switch S3 close, and the low sensitivity pixel integral signal SIG_L output by the high dynamic range image sensor pixel column interacts with the low sensitivity sampling capacitor C. s_a The low-sensitivity effective image signal output from the low-sensitivity image sensor pixel column is obtained by subtracting the stored low-sensitivity pixel reset signal RST_L. This obtained low-sensitivity effective image signal eliminates pixel fixed-mode noise and reset thermal noise, minimizing the offset voltage of the main operational amplifier U1 and improving the imaging quality of the low-sensitivity image. After amplification by the main operational amplifier U1 and reduction of the offset voltage effect by a negative feedback DC offset cancellation circuit, the low-sensitivity analog output signal V is output. out_L .

[0053] Low-sensitivity analog output signal V out_L The calculation formula is:

[0054]

[0055] Among them, V RST_L This represents the voltage level of the low-sensitivity pixel reset signal RST_L, in volts; V SIG_L This represents the level value of the low-sensitivity pixel integration signal SIG_L, in volts.

[0056] From the above calculation formula, it can be seen that the low-sensitivity analog output signal V out_L The offset voltage was reduced This minimizes the impact of the offset voltage of the main operational amplifier U1 on the output signal. Simultaneously, (V) RST_L -V SIG_L The CDS processing eliminates pixel fixed-mode noise and reset thermal noise in the low-sensitivity pixel integral signal SIG_L.

[0057] When the programmable gain amplifier circuit performs offset storage processing and correlation double sampling processing on the ordinary image signal output from the pixel column of an ordinary image sensor, the programmable gain amplifier circuit operates in normal mode, such as... Figure 4 The diagram shows the control timing of the low-sensitivity sampling switch Sa, the high-sensitivity sampling switch Sb, the first switch S1, the second switch S2, and the third switch S3 in this operating mode; the processing procedure in this operating mode includes the following steps:

[0058] S201, low-sensitivity sampling switch Sa, high-sensitivity sampling switch Sb, first switch S1 and second switch S2 are closed, and third switch S3 is open. The pixel reset signal RST output from the pixel column of the ordinary image sensor is sent to the Pixel_in terminal of the programmable gain amplifier circuit. Offset voltage sampling capacitor C F The offset voltage of the main operational amplifier U1 is sampled and stored in the offset voltage sampling capacitor C. F In the middle; at the same time, the low-sensitivity sampling capacitor C s_a and high-sensitivity sampling capacitor C s_b Sample the pixel reset signal RST and store it in the low-sensitivity sampling capacitor C. s_a and high-sensitivity sampling capacitor C s_b middle.

[0059] Switches S202, S1, and S2 are sequentially opened, followed by the closing of the third switch S3. The pixel column output of the ordinary image sensor, SIG, is then sent to the Pixel_in terminal of the programmable gain amplifier circuit. The pixel integration signal SIG is then compared with the low-sensitivity sampling capacitor C. s_a and high-sensitivity sampling capacitor C s_bThe difference between the stored pixel reset signal RST and the actual image signal is obtained from the pixel column output of a common image sensor. This actual image signal is amplified by the main operational amplifier U1 and then passed through a negative feedback DC offset cancellation circuit to reduce the influence of the offset voltage of the main operational amplifier U1 before being output as a common image analog output signal V. out .

[0060] Ordinary image analog output signal V out The calculation formula is:

[0061]

[0062] Among them, V RST This represents the voltage level of the pixel reset signal RST output by a pixel column of a typical image sensor, measured in volts; V SIG This represents the level value of the pixel integral signal SIG output by a pixel column of a common image sensor, in volts.

[0063] In this embodiment, by employing operational amplifier offset storage technology, the impact of the offset voltage of the main operational amplifier U1 on the output voltage can be minimized, thereby reducing image column fixed-mode noise caused by the offset voltage of the main operational amplifier U1. Simultaneously, through double correlation double sampling processing, pixel fixed-mode noise and reset thermal noise are eliminated. The programmable gain amplifier circuit can output in two states: extended image sensor dynamic range mode and normal mode. In extended image sensor dynamic range mode, high-sensitivity PGA processing signals and low-sensitivity PGA processing signals can be output in time-division multiplexing, providing high-sensitivity and low-sensitivity analog signal inputs to subsequent processing circuits. The subsequent processing circuit performs image synthesis processing, extending the dynamic range of the image sensor, thereby improving image imaging quality. In normal mode, the programmable gain amplifier can also perform correlation double sampling (CDS) and column fixed-mode noise reduction processing on ordinary image signals, only performing output offset reduction and CDS processing, outputting high-sensitivity / low-sensitivity PGA processing signals, reducing image sensor noise, and improving image imaging quality.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A programmable gain amplifier circuit for extending the dynamic range of an image sensor, characterized in that: It includes a switched capacitor circuit and a negative feedback DC offset cancellation circuit; the switched capacitor circuit and the negative feedback DC offset cancellation circuit have a common circuit, which is a main operational amplifier; The switched capacitor circuit is used to perform two correlation double sampling and amplification processing on the output signal of the pixel column of the image sensor, eliminate fixed pattern noise and reset thermal noise, and output high-sensitivity and low-sensitivity analog voltages. The negative feedback DC offset cancellation circuit is used to reduce the impact of the main operational amplifier's offset voltage on the output voltage by storing the operational amplifier's offset voltage, thereby reducing the image column fixed pattern noise caused by the main operational amplifier's offset voltage. The switched capacitor circuit includes a main operational amplifier and a low-sensitivity sampling capacitor C. s_a Low-sensitivity sampling switch Sa, high-sensitivity sampling capacitor C s_b and the high-sensitivity sampling switch Sb; the low-sensitivity sampling capacitor C s_a The first terminal is connected to the high-sensitivity sampling capacitor C s_b The first terminal, after being electrically connected, serves as the input terminal of the switched capacitor circuit for connecting the output signal of the image sensor pixel column; the low-sensitivity sampling capacitor C s_a The second terminal is electrically connected to the first terminal of the low-sensitivity sampling switch Sa, and the high-sensitivity sampling capacitor C... s_b The second terminal of the low-sensitivity sampling switch Sa is electrically connected to the first terminal of the high-sensitivity sampling switch Sb. After the second terminal of the low-sensitivity sampling switch Sa is electrically connected to the second terminal of the high-sensitivity sampling switch Sb, it serves as the output terminal of the switched capacitor circuit and is electrically connected to the inverting input terminal of the main operational amplifier. The non-inverting input terminal of the main operational amplifier is connected to the common-mode voltage. The negative feedback DC offset cancellation circuit includes an offset voltage sampling capacitor C. F The system comprises a first switch S1, a second switch S2, a third switch S3, and a main operational amplifier; the first terminal of the first switch S1 is electrically connected to the inverting input terminal of the main operational amplifier, and the second terminal of the first switch S1 is electrically connected to the output terminal of the main operational amplifier; the offset voltage sampling capacitor C... F The first terminal is electrically connected to the first terminal of the first switch S1, and the offset voltage sampling capacitor C F The second terminal is electrically connected to the first terminal of the second switch S2 and the first terminal of the third switch S3, respectively; the second terminal of the second switch S2 is connected to the common-mode voltage, and the second terminal of the third switch S3 is electrically connected to the output terminal of the main operational amplifier. When the programmable gain amplifier circuit performs time-division offset storage processing and correlation double sampling processing on the signal output from the pixel column of the high dynamic range image sensor, it includes the following steps: S101, low-sensitivity sampling switch Sa, high-sensitivity sampling switch Sb, first switch S1 and second switch S2 are closed, third switch S3 is open, and the high dynamic range image sensor pixel column outputs a low-sensitivity pixel reset signal RST_L; offset voltage sampling capacitor C F The offset voltage of the main operational amplifier is sampled; simultaneously, the low-sensitivity sampling capacitor C... s_a and high-sensitivity sampling capacitor C s_b Sample the low-sensitivity pixel reset signal RST_L; S102, the low-sensitivity sampling switch Sa is open. At this time, the low-sensitivity pixel reset signal RST_L is stored in the low-sensitivity sampling capacitor C. s_a middle; S103, High Dynamic Range Image Sensor Pixel Column Output High Sensitivity Pixel Reset Signal RST_H, High Sensitivity Sampling Capacitor C s_b Sample the high-sensitivity pixel reset signal RST_H; S104, the first switch S1 and the second switch S2 are opened sequentially. At this time, the high-sensitivity pixel reset signal RST_H is stored in the high-sensitivity sampling capacitor C. s_b In the process, the offset voltage of the main operational amplifier is stored in the offset voltage sampling capacitor C. F In the middle; then the third switch S3 closes, and the high dynamic range image sensor pixel column outputs a high-sensitivity pixel integration signal SIG_H. The high-sensitivity pixel integration signal SIG_H interacts with the high-sensitivity sampling capacitor C. s_b The high-sensitivity pixel reset signal RST_H is stored, and the difference is taken to obtain the high-sensitivity effective image signal. The high-sensitivity effective image signal is amplified by the main operational amplifier, and after passing through a negative feedback DC offset cancellation circuit to reduce the influence of the offset voltage of the main operational amplifier, a high-sensitivity analog output signal V is output. out_H ; S105, the high-sensitivity sampling switch Sb is opened. Subsequently, the third switch S3 is opened, and the first switch S1 and the second switch S2 are closed. The offset voltage sampling capacitor C... F The offset voltage of the main operational amplifier is sampled again, and stored in the offset voltage sampling capacitor C. F middle; S106. The high dynamic range image sensor pixel column outputs a low-sensitivity pixel integration signal SIG_L, and the first switch S1 is opened; subsequently, the second switch S2 is also opened, and the low-sensitivity sampling switch Sa and the third switch S3 are closed. The low-sensitivity pixel integration signal SIG_L interacts with the low-sensitivity sampling capacitor C. s_a The low-sensitivity pixel reset signal RST_L is subtracted to obtain the low-sensitivity effective image signal. This low-sensitivity effective image signal is amplified by the main operational amplifier and then passed through a negative feedback DC offset cancellation circuit to reduce the influence of the main operational amplifier's offset voltage before being output as a low-sensitivity analog output signal V. out_L .

2. The programmable gain amplifier circuit for extending the dynamic range of an image sensor according to claim 1, characterized in that: The main operational amplifier is a differential input, single-ended output amplifier; the main operational amplifier adopts a single-stage differential structure or a two-stage differential structure.

3. The programmable gain amplifier circuit for extending the dynamic range of an image sensor according to claim 1, characterized in that: The offset voltage sampling capacitor C F The DC offset cancellation capacitor serves as negative feedback in the DC offset cancellation circuit.

4. The programmable gain amplifier circuit for extending the dynamic range of an image sensor according to claim 1, characterized in that, High-sensitivity analog output signal V out_H The calculation formula is: Low-sensitivity analog output signal V out_L The calculation formula is: Among them, V RST_H This represents the voltage level of the high-sensitivity pixel reset signal RST_H; V SIG_H This indicates the level value of the high-sensitivity pixel integration signal SIG_H; A Indicates the gain of the main operational amplifier; V OS V represents the offset voltage of the main operational amplifier. CM Indicates the common-mode voltage value; V RST_L This represents the level value of the low-sensitivity pixel reset signal RST_L; V SIG_L This indicates the level value of the low-sensitivity pixel integration signal SIG_L.

5. The programmable gain amplifier circuit for extending the dynamic range of an image sensor according to claim 1, characterized in that: When the programmable gain amplifier circuit performs offset storage processing and correlation double sampling processing on the signal output from the pixel column of a common image sensor, it includes the following steps: S201, low-sensitivity sampling switch Sa, high-sensitivity sampling switch Sb, first switch S1 and second switch S2 are closed, third switch S3 is open, and the pixel column output of the ordinary image sensor is a pixel reset signal RST; offset voltage sampling capacitor C F The offset voltage of the main operational amplifier is sampled and stored in the offset voltage sampling capacitor C. F In the middle; at the same time, the low-sensitivity sampling capacitor C s_a and high-sensitivity sampling capacitor C s_b Sample the pixel reset signal RST and store it in the low-sensitivity sampling capacitor C. s_a and high-sensitivity sampling capacitor C s_b middle; Switches S202, S1, and S2 are sequentially opened, followed by the closing of the third switch S3. The ordinary image sensor outputs a pixel integration signal SIG from its pixel column. This pixel integration signal SIG interacts with the low-sensitivity sampling capacitor C. s_a and high-sensitivity sampling capacitor C s_b The difference between the stored pixel reset signal RST and the actual image signal is obtained from the pixel column output of a typical image sensor. This actual image signal is amplified by the main operational amplifier and then passed through a negative feedback DC offset cancellation circuit to reduce the influence of the main operational amplifier's offset voltage before being output as a typical image analog output signal V. out .

6. The programmable gain amplifier circuit for extending the dynamic range of an image sensor according to claim 5, characterized in that, Ordinary image analog output signal V out The calculation formula is: Among them, V RST This indicates the voltage level of the pixel reset signal RST; V SIG This indicates the level value of the pixel integration signal SIG; V CM Indicates the common-mode voltage value; A The gain of the main operational amplifier; V OS This is the offset voltage of the main operational amplifier.

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