Pixel Circuit, CMOS Image Sensor, and Control Method

Abstract

The present invention provides a pixel circuit, comprising: a reset module, a gain control module, a photosensitive control module and a reading module; the reading module includes a high-gain reading unit and a low-gain reading unit, both of which are connected to a floating diffusion point, the high-gain reading unit is configured to read the voltage signal of the floating diffusion point in the high-gain transmission mode and output it, and the low-gain reading unit is configured to read the voltage signal of the floating diffusion point in the low-gain transmission mode and output it; the high-gain reading unit includes a first capacitor, and the low-gain reading unit includes a second capacitor, the first capacitor is used to obtain the voltage difference between the image signal and the reset signal in the high-gain transmission mode, and the second capacitor is used to obtain the voltage difference between the image signal and the reset signal in the low-gain transmission mode. Through the pixel circuit provided by the present invention, the problem of low dynamic range of the existing CMOS image sensor is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of CMOS image sensors, and particularly to a pixel circuit, a CMOS image sensor, and a control method. Background Art

[0002] The global shutter technology is an imaging technology that needs to be applied in high-speed photography. All signals are exposed simultaneously to generate an undistorted image. The main implementation principle is that a storage capacitor is added to each pixel circuit. All pixel circuits are exposed simultaneously, and then the photoelectric conversion signal is stored in the storage capacitor and waits to be read out by the subsequent circuit.

[0003] In some environments with large light differences, the dynamic range is a key indicator affecting the imaging effect. It determines the light intensity distribution range from the darkest shadow part to the brightest highlight part that the CMOS image sensor can accept, that is, it determines the details, levels, and features of the captured image. Therefore, how to improve the dynamic range of the CMOS image sensor is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a pixel circuit, a CMOS image sensor, and a control method to solve the problem of the low dynamic range of the existing CMOS image sensors.

[0005] To achieve the above purpose and other related purposes, the present invention provides a pixel circuit, which includes: a reset module, a gain control module, a photosensitive control module, and a reading module. Among them,

[0006] The reset module includes a reset transistor. The gate terminal of the reset transistor is connected to a reset control signal, the first connection terminal is connected to a power supply voltage, and the second connection terminal is connected to a floating diffusion point;

[0007] The gain control module is connected between the second connection terminal of the reset transistor and the floating diffusion point and is controlled by a gain control signal, and is used to adjust the equivalent charge storage capacity of the floating diffusion point according to the gain control signal, so that the pixel circuit operates in different gain transmission modes;

[0008] The photosensitive control module is connected between the floating diffusion point and a first reference voltage and is controlled by a transmission control signal, and is used to generate exposure charges according to the photoelectric effect and transfer and output the exposure charges according to the transmission control signal;

[0009] The reading module includes a high-gain reading unit and a low-gain reading unit, both of which are connected to the floating diffusion point. Among them, the high-gain reading unit is used to read the voltage signal of the floating diffusion point in the high-gain transmission mode and output it; the low-gain reading unit is used to read the voltage signal of the floating diffusion point in the low-gain transmission mode and output it; the high-gain reading unit includes a first capacitor, and the low-gain reading unit includes a second capacitor. The first capacitor is used to obtain the voltage difference between the image signal and the reset signal in the high-gain transmission mode, and the second capacitor is used to obtain the voltage difference between the image signal and the reset signal in the low-gain transmission mode.

[0010] Optionally, the high-gain transmission mode includes a first high-gain transmission mode and a second high-gain transmission mode. In the first high-gain transmission mode, the left plate of the first capacitor stores the high-gain reset voltage signal Vrsthcg, and the right plate stores the first power supply voltage signal Vdd. In the second high-gain transmission mode, the left plate of the first capacitor stores the high-gain image voltage signal Vsig hcg, and the right plate stores the high-gain output voltage signal Vsig hcg+(Vdd-Vrst hcg); and / or, the low-gain transmission mode includes a first low-gain transmission mode and a second low-gain transmission mode. In the first low-gain transmission mode, the left plate of the second capacitor stores the low-gain reset voltage signal Vrstlcg, and the right plate stores the first power supply voltage signal Vdd. In the second low-gain transmission mode, the left plate of the second capacitor stores the low-gain image voltage signal Vsig lcg, and the right plate stores the output low-gain voltage signal Vsig lcg+(Vdd-Vrst lcg).

[0011] Optionally, the high-gain reading unit further includes at least: a first high-gain source follower transistor, a first high-gain storage control transistor, a second high-gain storage control transistor, a second high-gain source follower transistor, and a first row selection transistor; a gate terminal of the first high-gain source follower transistor is connected to the floating diffusion point, a first connection terminal accesses a first variable voltage, and a second connection terminal is connected to a first connection terminal of the first high-gain storage control transistor; a gate terminal of the first high-gain storage control transistor accesses a first high-gain storage control signal, and a second connection terminal is connected to a left plate of the first capacitor; a right plate of the first capacitor is connected to a second connection terminal of the second high-gain storage control transistor and a gate terminal of the second high-gain source follower transistor; a gate terminal of the second high-gain storage control transistor accesses a second high-gain storage control signal, and a first connection terminal accesses a first power supply voltage; a first connection terminal of the second high-gain source follower transistor accesses a second power supply voltage, and a second connection terminal is connected to a first connection terminal of the first row selection transistor; a gate terminal of the first row selection transistor accesses a high-gain row selection signal, and a second connection terminal serves as an output terminal of the high-gain reading unit;

[0012] The low-gain reading unit further includes at least: a first low-gain source follower transistor, a first low-gain storage control transistor, a second low-gain storage control transistor, a second low-gain source follower transistor, and a second row selection transistor; a gate terminal of the first low-gain source follower transistor is connected to the floating diffusion point, a first connection terminal accesses a second variable voltage, and a second connection terminal is connected to a first connection terminal of the first low-gain storage control transistor; a gate terminal of the first low-gain storage control transistor accesses a first low-gain storage control signal, and a second connection terminal is connected to a left plate of the second capacitor; a right plate of the second capacitor is connected to a second connection terminal of the second low-gain storage control transistor and a gate terminal of the second low-gain source follower transistor; a gate terminal of the second low-gain storage control transistor accesses a second low-gain storage control signal, and a first connection terminal accesses a third power supply voltage; a first connection terminal of the second low-gain source follower transistor accesses a fourth power supply voltage, and a second connection terminal is connected to a first connection terminal of the second row selection transistor; a gate terminal of the second row selection transistor accesses a low-gain row selection signal, and a second connection terminal serves as an output terminal of the low-gain reading unit.

[0013] Optionally, the first high-gain source follower transistor and the first low-gain source follower transistor are the same source follower transistor. A gate terminal of the shared source follower transistor is connected to the floating diffusion point, a first connection terminal accesses a variable voltage, and a second connection terminal is respectively connected to a first connection terminal of the first high-gain storage control transistor and a first connection terminal of the first low-gain storage control transistor.

[0014] Optionally, the high-gain reading unit includes a third capacitor connected between the second connection terminal of the first high-gain storage control transistor and the second reference voltage; and / or, the low-gain reading unit includes a fourth capacitor connected between the second connection terminal of the first low-gain storage control transistor and the third reference voltage.

[0015] Optionally, the gain control module includes: a gain control transistor and a gain adjustment capacitor. The gate terminal of the gain control transistor is connected to the gain control signal, the first connection terminal is connected to the second connection terminal of the reset transistor, and is connected to the fourth reference voltage through the gain adjustment capacitor, and the second connection terminal is connected to the floating diffusion point.

[0016] Optionally, the gain adjustment capacitor is the parasitic capacitance between the connection point of the reset transistor and the gain control transistor and the ground; or, the gain adjustment capacitor is a device capacitor.

[0017] Optionally, the photosensitive control module includes: a photoelectric conversion element and a transfer transistor. The output terminal of the photoelectric conversion element is connected to the first connection terminal of the transfer transistor, and the other end is connected to the first reference voltage; the gate terminal of the transfer transistor is connected to the transfer control signal, and the second connection terminal is connected to the floating diffusion point.

[0018] Optionally, the high-gain reading unit and the low-gain reading unit correspond to the same or different column lines to respectively realize serial output or parallel output of signals.

[0019] The present invention also provides a control method for a pixel circuit, including the following steps: providing a pixel circuit as described in any one of the above; realizing global exposure based on the pixel circuit, and obtaining the voltage difference between the image signal and the reset signal in the high-gain transmission mode through the first capacitor, and obtaining the voltage difference between the image signal and the reset signal in the low-gain transmission mode through the second capacitor, so that the pixel circuit operates in different gain transmission modes.

[0020] Optionally, the control method includes: in the first high-gain transmission mode, the left plate of the first capacitor stores the high-gain reset voltage signal Vrst hcg, the right plate stores the first power supply voltage signal Vdd, and the voltage difference between the left and right plates of the first capacitor is Vdd - Vrst hcg, such that in the second high-gain transmission mode, when the left plate of the first capacitor stores the high-gain image voltage signal Vsig hcg, the right plate stores the high-gain output voltage signal Vsig hcg+(Vdd - Vrst hcg); in the first low-gain transmission mode, the left plate of the second capacitor stores the low-gain reset voltage signal Vrst lcg, the right plate stores the first power supply voltage signal Vdd, and the voltage difference between the left and right plates of the second capacitor is Vdd - Vrst lcg, such that in the second low-gain transmission mode, when the left plate of the second capacitor stores the low-gain image voltage signal Vsig lcg, the right plate stores the low-gain output voltage signal Vsig lcg+(Vdd - Vrst lcg).

[0021] Optionally, during the process of implementing global exposure based on the pixel circuit, the signal transmission method includes: sequentially performing reset signal reset, low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition, and low-gain image signal acquisition; or, the signal transmission method includes: reset signal reset, low-gain reset signal acquisition, high-gain reset signal acquisition while performing image signal reset of the low-gain reading unit, high-gain image signal acquisition while performing image signal reset of the low-gain reading unit, and low-gain image signal acquisition.

[0022] Optionally, the readout process of the pixel circuit includes a first stage and a second stage. In the first stage, the pixel circuit outputs the output voltage signal Vsig+(Vdd - Vrst), and in the second stage, the pixel circuit outputs the first power supply voltage signal Vdd.

[0023] Optionally, the signal output methods of the high-gain reading unit and the low-gain reading unit include serial output or parallel output.

[0024] Optionally, after the reset signal is reset, the reset transistor is set to the first potential, and low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition, and low-gain image signal acquisition are performed at the first potential; and / or, when there is a first high-gain source follower transistor and a first low-gain source follower transistor or they are shared, during the reset signal reset process and the image signal reset process, the potential of the first high-gain source follower transistor is the same, and the potential of the first low-gain source follower transistor is the same.

[0025] The present invention also provides a CMOS image sensor, which includes: the pixel circuit as described in any one of the above.

[0026] Optionally, the image sensor includes a first semiconductor substrate and a second semiconductor substrate stacked, the photosensitive control module is located in the first semiconductor substrate, and the reading module is located in the second semiconductor substrate; or, the image sensor includes a first semiconductor substrate, a second semiconductor substrate and a third semiconductor substrate stacked, the photosensitive control module is located in the first semiconductor substrate, the reading module is located in the second semiconductor substrate, and the image sensor further includes a logic circuit, and the logic circuit is located in the third semiconductor substrate; or, the image sensor includes a first semiconductor substrate and a second semiconductor substrate stacked, the photosensitive control module and the reading module are located in the first semiconductor substrate, and the image sensor further includes a logic circuit, and the logic circuit is located in the second semiconductor substrate.

[0027] As described above, a pixel circuit, a CMOS image sensor and a control method of the present invention effectively improve the dynamic range of the CMOS image sensor by adopting the dual conversion gain technology through the design of the gain control module and the reading module; a larger capacitor is used for the high-intensity light illumination area to increase the stored charge and reduce the gain to improve the dynamic range, and a smaller capacitor is used for the low-intensity light illumination area to increase the gain and achieve high sensitivity. Description of the Drawings

[0028] Figure 1 It shows a schematic diagram of the parallel output pixel circuit in the first embodiment of the present invention.

[0029] Figure 2 It shows Figure 1 A schematic diagram when the shown pixel circuits share the first source follower transistor.

[0030] Figure 3 It shows a schematic diagram of the serial output pixel circuit in the first embodiment of the present invention.

[0031] Figure 4 It shows Figure 2 A timing diagram of each signal in the shown pixel circuit.

[0032] Description of Component Labels

[0033] 100 Reset module

[0034] 200 Gain control module

[0035] 300 Photosensitive control module

[0036] 400 Reading module

[0037] 401 High-gain reading unit

[0038] 402 Low-gain reading unit Specific embodiments

[0039] The following uses specific examples to illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] Please refer to Figures 1 to 4 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Although only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation, the form, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the layout form of its components may also be more complex.

[0041] Embodiment 1

[0042] As Figure 1 shown Figure 1 This shows a schematic diagram of a parallel output pixel circuit in Embodiment 1 of the present invention. This embodiment provides a pixel circuit, which includes a reset module 100, a gain control module 200, a photosensitive control module 300, and a reading module 400.

[0043] As Figure 1 shown, the reset module 100 includes a reset transistor M1. The gate terminal of the reset transistor M1 is connected to the reset control signal rst, the first connection terminal is connected to the power supply voltage VDD, and the second connection terminal is connected to the floating diffusion point FD, and is used to reset the voltage of the floating diffusion point FD according to the reset control signal rst, and complete the reset operation of the photoelectric conversion element (such as a photodiode PD) in the photosensitive control module 300. Optionally, the reset transistor M1 is an NMOS transistor, and its first connection terminal is the drain terminal, and the second connection terminal is the source terminal.

[0044] As Figure 1 shown, the gain control module 200 is connected between the second connection terminal of the reset transistor M1 and the floating diffusion point FD, and is controlled by the gain control signal dcg, and is used to adjust the equivalent charge storage capacity of the floating diffusion point FD according to the gain control signal dcg, so that the pixel circuit operates in different gain transfer modes, that is, the CMOS image sensor composed of the pixel circuit operates in different gain transfer modes.

[0045] Specifically, as Figure 1As shown in the figure, the gain control module 200 includes a gain control transistor M2 and a gain adjustment capacitor Cdcg. The gate terminal of the gain control transistor M2 is connected to the gain control signal dcg, the first connection terminal is connected to the second connection terminal of the reset transistor M1, and is connected to the fourth reference voltage through the gain adjustment capacitor Cdcg, and the second connection terminal is connected to the floating diffusion point FD. Optionally, the gain control transistor M2 is an NMOS transistor, its first connection terminal is the drain terminal, and the second connection terminal is the source terminal; the gain adjustment capacitor Cdcg can be the parasitic capacitance between the connection point of the reset transistor M1 and the gain control transistor M2 to the ground, or it can be a device capacitor (i.e., an externally connected capacitor); optionally, the fourth reference voltage is the ground voltage.

[0046] In this embodiment, when the gain control signal dcg is at a high level, the gain control transistor M2 is turned on, and the equivalent charge storage capacity of the floating diffusion point FD is increased through the gain adjustment capacitor Cdcg, so that the final charge storage capacity is the sum of the charge storage capacity of the floating diffusion point FD itself and the charge storage capacity of the gain adjustment capacitor Cdcg. At this time, the CMOS image sensor composed of the pixel circuit operates in the low gain transmission mode (LCG); conversely, when the gain control signal dcg is at a low level, the gain control transistor M2 is turned off, so that the charge storage capacity of the floating diffusion point FD itself is the final charge storage capacity. At this time, the CMOS image sensor composed of the pixel circuit operates in the high gain transmission mode (HCG).

[0047] As Figure 1 shown in the figure, the photosensitive control module 300 is connected between the floating diffusion point FD and the first reference voltage, and is controlled by the transmission control signal tx, and is used to generate exposure charges according to the photoelectric effect and transfer and output the exposure charges according to the transmission control signal tx.

[0048] Specifically, as Figure 1 shown in the figure, the photosensitive control module 300 includes a photoelectric conversion element and a transmission transistor M3. The output terminal of the photoelectric conversion element is connected to the first connection terminal of the transmission transistor M3, and the other end is connected to the first reference voltage; the gate terminal of the transmission transistor M3 is connected to the transmission control signal tx, and the second connection terminal is connected to the floating diffusion point FD. Optionally, the photoelectric conversion element is a photodiode PD, its output terminal is the negative electrode of the photodiode PD, and the other end is the positive electrode of the photodiode PD; the transmission transistor M3 is an NMOS transistor, its first connection terminal is the drain terminal, and the second connection terminal is the source terminal; in the embodiment of the present invention, optionally, the first reference voltage is the ground voltage.

[0049] In this embodiment, the photodiode PD generates exposure charges according to the photoelectric effect in response to the incident light, and the transmission transistor M3 is turned on when the transmission control signal tx is at a high level, and transfers and outputs the exposure charges generated by the photodiode PD.

[0050] As shown Figure 1 in FIG.

[0050] , the reading module 400 includes a high-gain reading unit 401 and a low-gain reading unit 402, both of which are connected to the floating diffusion point FD. Among them, the high-gain reading unit 401 is used to read the voltage signal of the floating diffusion point FD in the high-gain transmission mode and output it; the low-gain reading unit 402 is used to read the voltage signal of the floating diffusion point FD in the low-gain transmission mode and output it; the high-gain reading unit 401 includes a first capacitor C1, and the low-gain reading unit 402 includes a second capacitor C2. The first capacitor C1 is used to obtain the voltage difference between the image signal and the reset signal in the high-gain transmission mode, and the second capacitor C2 is used to obtain the voltage difference between the image signal and the reset signal in the low-gain transmission mode.

[0051] Specifically, the high-gain transmission mode includes a first high-gain transmission mode and a second high-gain transmission mode. In the first high-gain transmission mode, the left plate of the first capacitor C1 stores the high-gain reset voltage signal Vrst hcg, and the right plate stores the first power supply voltage signal Vdd. In the second high-gain transmission mode, the left plate of the first capacitor stores the high-gain image voltage signal Vsig hcg, and the right plate stores the high-gain output voltage signal Vsig hcg+(Vdd-Vrst hcg), so as to use the first capacitor C1 to obtain the voltage difference between the image signal and the reset signal in the high-gain transmission mode; and / or, the low-gain transmission mode includes a first low-gain transmission mode and a second low-gain transmission mode. In the first low-gain transmission mode, the left plate of the second capacitor stores the low-gain reset voltage signal Vrst lcg, and the right plate stores the first power supply voltage signal Vdd. In the second low-gain transmission mode, the left plate of the second capacitor stores the low-gain image voltage signal Vsig lcg, and the right plate stores the output low-gain voltage signal Vsig lcg+(Vdd-Vrst lcg), so as to use the second capacitor C2 to obtain the voltage difference between the image signal and the reset signal in the low-gain transmission mode. Optionally, the first power supply voltage Vdd is the power supply voltage VDD with a positive potential.

[0052] Specifically, as Figure 1As shown, the high-gain reading unit 401 further includes at least: a first high-gain source follower transistor M4, a first high-gain storage control transistor M5, a second high-gain storage control transistor M6, a second high-gain source follower transistor M7, and a first row selection transistor M8; the gate terminal of the first high-gain source follower transistor M4 is connected to the floating diffusion point FD, the first connection terminal is connected to the first variable voltage Vrsf1, and the second connection terminal is connected to the first connection terminal of the first high-gain storage control transistor M5; the gate terminal of the first high-gain storage control transistor M5 is connected to the first high-gain storage control signal SHCG, and the second connection terminal is connected to the left plate of the first capacitor C1; the right plate of the first capacitor C1 is connected to the second connection terminal of the second high-gain storage control transistor M6 and the gate terminal of the second high-gain source follower transistor M7; the gate terminal of the second high-gain storage control transistor M6 is connected to the second high-gain storage control signal rstH, and the first connection terminal is connected to the first power supply voltage Vdd1; the first connection terminal of the second high-gain source follower transistor M7 is connected to the second power supply voltage Vdd2, and the second connection terminal is connected to the first connection terminal of the first row selection transistor M8; the gate terminal of the first row selection transistor M8 is connected to the high-gain row selection signal rsH, and the second connection terminal is used as the output terminal of the high-gain reading unit 401. Optionally, the first high-gain source follower transistor M4, the first high-gain storage control transistor M5, the second high-gain storage control transistor M6, the second high-gain source follower transistor M7, and the first row selection transistor M8 are all NMOS transistors, the first connection terminal is the drain terminal, and the second connection terminal is the source terminal.

[0053] The low-gain reading unit 402 further includes at least: a first low-gain source follower transistor M9, a first low-gain storage control transistor M10, a second low-gain storage control transistor M11, a second low-gain source follower transistor M12, and a second row selection transistor M13; the gate terminal of the first low-gain source follower transistor M9 is connected to the floating diffusion point FD, the first connection terminal is connected to the second variable voltage Vrsf2, and the second connection terminal is connected to the first connection terminal of the first low-gain storage control transistor M10; the gate terminal of the first low-gain storage control transistor M10 is connected to the first low-gain storage control signal SLCH, and the second connection terminal is connected to the left plate of the second capacitor C2; the right plate of the second capacitor C2 is connected to the second connection terminal of the second low-gain storage control transistor M11 and the gate terminal of the second low-gain source follower transistor M12; the gate terminal of the second low-gain storage control transistor M11 is connected to the second low-gain storage control signal rstL, and the first connection terminal is connected to the third power supply voltage Vdd3; the first connection terminal of the second low-gain source follower transistor M12 is connected to the fourth power supply voltage Vdd4, and the second connection terminal is connected to the first connection terminal of the second row selection transistor M13; the gate terminal of the second row selection transistor M13 is connected to the low-gain row selection signal rsL, and the second connection terminal is used as the output terminal of the low-gain reading unit 402.

[0054] Optionally, the first high-gain source-follower transistor M4, the first high-gain storage control transistor M5, the second high-gain storage control transistor M6, the second high-gain source-follower transistor M7, the first row selection transistor M8, the first low-gain source-follower transistor M9, the first low-gain storage control transistor M10, the second low-gain storage control transistor M11, the second low-gain source-follower transistor M12, and the second row selection transistor M13 are all NMOS transistors, the first connection terminal is the drain terminal, and the second connection terminal is the source terminal; optionally, the first variable voltage Vrsf1 and the second variable voltage Vrsf2 are the same variable voltage Vrsf, that is to say, the first high-gain storage control transistor M5 and the first low-gain source-follower transistor M9 are the same source-follower transistor, and the drain of this source-follower transistor is connected to the variable voltage Vrsf; alternatively, the first variable voltage Vrsf1 and the second variable voltage Vrsf2 are different variable voltages, that is to say, the first high-gain storage control transistor M5 and the first low-gain source-follower transistor M9 are different source-follower transistors, and the drains of the two are respectively connected to the first variable voltage Vrsf1 and the second variable voltage Vrsf2; the first power supply voltage Vdd1, the second power supply voltage Vdd2, the third power supply voltage Vdd3, and the fourth power supply voltage Vdd4 are all power supply voltages VDD with positive potentials.

[0055] In this embodiment, for the high-gain reading unit 401: In the first high-gain transmission mode, the variable voltage Vrsf is at a high level, the first high-gain source follower transistor M4, the first high-gain storage control transistor M5, and the second high-gain storage control transistor M6 are turned on, so that the left plate of the first capacitor C1 stores the high-gain reset voltage signal Vrst hcg, and the right plate stores the power supply voltage signal VDD; In the second high-gain transmission mode, the variable voltage Vrsf is at a high level, the first high-gain source follower transistor M4 and the first high-gain storage control transistor M5 are turned on, and the second high-gain storage control transistor M6 is turned off, so that the left plate of the first capacitor C1 stores the high-gain image voltage signal Vsig hcg. To maintain the voltage difference between the left and right plates of the first capacitor C1, the right plate of the first capacitor C1 stores the high-gain output voltage signal Vsig hcg+(VDD-Vrst hcg). For the low-gain reading unit 402: In the first low-gain transmission mode, the variable voltage Vrsf is at a high level, the first low-gain source follower transistor M9, the first low-gain storage control transistor M10, and the second low-gain storage control transistor M11 are turned on, so that the left plate of the second capacitor C2 stores the low-gain reset voltage signal Vrst lcg, and the right plate stores the power supply voltage signal VDD; In the second low-gain transmission mode, the variable voltage Vrsf is at a high level, the first low-gain source follower transistor M9 and the first low-gain storage control transistor M10 are turned on, and the second low-gain storage control transistor M11 is turned off, so that the left plate of the second capacitor C2 stores the low-gain image voltage signal Vsig lcg. To maintain the voltage difference between the left and right plates of the second capacitor C2, the right plate of the second capacitor C2 stores the output low-gain voltage signal Vsig lcg+(VDD-Vrst lcg).

[0056] Further, as Figure 1 shown, the high-gain reading unit 401 includes a third capacitor C3. The third capacitor C3 is connected between the second connection end of the first high-gain storage control transistor M5 and the second reference voltage, and is used to absorb the charge at the moment when the first high-gain storage control transistor M5 is turned off; and / or, the low-gain reading unit 402 includes a fourth capacitor C4. The fourth capacitor C4 is connected between the second connection end of the first low-gain storage control transistor M10 and the third reference voltage, and is used to absorb the charge at the moment when the first low-gain storage control transistor M10 is turned off. It should be noted that in the reading module 400 of this embodiment, only one of the third capacitor C3 and the fourth capacitor C4 may be included, or both the third capacitor C3 and the fourth capacitor C4 may be included. Optionally, both the third capacitor C3 and the fourth capacitor C4 are included in the reading module 400, and the second reference voltage and the third reference voltage are both ground voltages.

[0057] To simplify the circuit, as Figure 2 shown,Figure 2 Shown as Figure 1 A schematic diagram when the pixel circuits shown share the first source follower transistor. The first high-gain source follower transistor M4 and the first low-gain source follower transistor M9 are the same source follower transistor. The gate terminal of the shared source follower transistor is connected to the floating diffusion point FD, the first connection terminal is connected to the variable voltage Vrsf, and the second connection terminal is respectively connected to the first connection terminal of the first high-gain storage control transistor M5 and the first connection terminal of the first low-gain storage control transistor M10. Specifically, the high-gain reading unit 401 and the low-gain reading unit 402 correspond to the same or different column lines to respectively realize serial output or parallel output of signals; if the high-gain reading unit 401 and the low-gain reading unit 402 correspond to different column lines to realize parallel output of signals (such as Figure 1 and Figure 2 shown); the high-gain reading unit 401 and the low-gain reading unit 402 correspond to the same column line to realize serial output of signals (such as Figure 3 shown, Figure 3 Shown as a schematic diagram of the serial output pixel circuit in Embodiment 1 of the present invention.). In practical applications, parallel output and serial output can be selected according to specific requirements, which has no impact on this embodiment, and only the conduction timing of the high-gain row selection signal rsH and the low-gain row selection signal rsL needs to be adjusted.

[0058] Next, please combine Figure 2 with Figure 4 and Figure 4 Shown as Figure 2 the timing diagram of each signal in the pixel circuit shown to describe in detail the specific working process of the pixel circuit in this embodiment.

[0059] Before time t0, it is the global reset stage (global reset); in this stage, the transfer transistor M3 is turned on, and at the same time, the reset transistor M1 and the gain control transistor M2 are in the on state. The voltage of the floating diffusion point FD is reset through the reset transistor M1 to complete the reset operation of the photodiode PD; after the reset operation is completed, the transfer transistor M3 is turned off, and the global exposure starts.

[0060] From time t1 to t2, it is the pre-charge (pre-chg rst) stage of the reset signal; in this stage, the reset transistor M1, the gain control transistor M2, the second high-gain storage control transistor M6, and the second low-gain storage control transistor M11 are all in the on state, the variable voltage Vrsf changes from a high potential to a low potential. At the same time, the first high-gain storage control transistor M5 and the first low-gain storage control transistor M10 are turned on, setting the left plates of the first capacitor C1 and the second capacitor C2 to a low potential, and the right plates of the first capacitor C1 and the second capacitor C2 to VDD. After the setting is completed, the first high-gain storage control transistor M5 and the first low-gain storage control transistor M10 are turned off first, and then the variable voltage Vrsf is set to a high potential.

[0061] From time t2 to t3, it is the global LCG reset voltage sampling stage (global sample LCG rst); in this stage, first the reset transistor M1 is turned off, that is, the reset ends; then the first low-gain storage control transistor M10 is turned on, and the low-gain reset voltage signal voltage Vrst_lcg is stored on the left plate of the second capacitor C2 through the first source follower transistor M4. At this time, the voltage difference between the capacitor plates of the second capacitor C2 is (VDD - Vrst_lcg); after the voltage storage is completed, the first low-gain storage control transistor M10 returns to the off state.

[0062] From time t3 to t4, it is the global HCG reset voltage sampling stage (global sample HCG rst); in this stage, first the second low-gain storage control transistor M11 is turned off, then the gain control transistor M2 is turned off, and then the first high-gain storage control transistor M5 is turned on, and the high-gain reset voltage signal Vrst_hcg is stored on the left plate of the first capacitor C1 through the first source follower transistor M4. At this time, the voltage difference between the capacitor plates of the first capacitor C1 is (VDD - Vrst_hcg); after the voltage storage is completed, the first high-gain storage control transistor M5 returns to the off state.

[0063] From time t4 to t5, it is the pixel voltage pre-charge stage (pre-chg sig); in this stage, the variable voltage Vrsf changes from a high potential to a low potential. At the same time, the first high-gain storage control transistor M5 and the first low-gain storage control transistor M10 are turned on, setting the left plates of the first capacitor C1 and the second capacitor C2 to a low potential.

[0064] From t5 to t6, it is the HCG image voltage sampling stage (global sample HCG sig); in this stage, the transfer transistor M3 is turned on, and the photodiode PD transfers the exposure charge to the floating diffusion point FD, causing the voltage at this point to change. Then, the first high-gain storage control transistor M5 is turned on, connecting the source terminal of the first source follower transistor M4 to the left plate of the first capacitor C1, and sampling the high-gain image voltage signal Vsig_hcg onto the left plate of the first capacitor C1; the second high-gain storage control transistor M6 is in the off state, and the right plate of the first capacitor C1 is in a floating state. At this time, to maintain the voltage difference between the left and right plates of the first capacitor C1, the voltage of the right plate of the first capacitor C1 is Vsig_hcg+(VDD-Vrst_hcg).

[0065] From t6 to t7, it is the LCG image voltage sampling stage (global sample LCG sig); in this stage, first turn on the gain control transistor M2, then turn on the transfer transistor M3. The photodiode PD transfers the exposure charge to the floating diffusion point FD and the gain adjustment capacitor Cdcg to achieve charge redistribution. Finally, turn on the first low-gain storage control transistor M10, connect the source terminal of the first source follower transistor M4 to the left plate of the second capacitor C2, and sample the low-gain image voltage signal Vlsig_lcg onto the left plate of the second capacitor C2; the second low-gain storage control transistor M11 is in the off state, and the right plate of the second capacitor C2 is in a floating state. At this time, to maintain the voltage difference between the left and right plates of the second capacitor C2, the voltage of the right plate of the second capacitor C2 is Vsig_lcg+(VDD-Vrst_lcg); after sampling, the first low-gain storage control transistor M10 returns to the off state, the reset transistor M1 returns to the on state, and the subsequent readout operation (such as from t9 to t10) is controlled by the high-gain row select signal rsH and the low-gain row select signal rsL.

[0066] During the entire process from t2 to t7, the global conversion operation is completed; using the characteristic of the capacitor to store charge, the high-gain image voltage signal is stored on the first capacitor C1, and the low-gain image voltage signal is stored on the second capacitor C2. Subsequently, the image voltage will be read out row by row through the high-gain row select signal rsH and the low-gain row select signal rsL. In the readout stage, first read the signal on the capacitor plate, and then read a power supply signal VDD. The difference between the two can obtain the required Vrst-Vsig. It should be noted that Figure 4 az in represents the clear signal of the readout circuit, and clk represents the clock signal of the readout circuit. The clock start indicates readout.

[0067] Embodiment 2

[0068] This embodiment provides a control method for a pixel circuit, including the following steps: providing a pixel circuit as in Embodiment 1, implementing global exposure based on the pixel circuit, obtaining the voltage difference between the image signal and the reset signal in the high-gain transfer mode through a first capacitor, and obtaining the voltage difference between the image signal and the reset signal in the low-gain transfer mode through a second capacitor, so that the pixel circuit operates in different gain transfer modes.

[0069] Specifically, during the process of implementing global exposure based on Figure 1 the pixel circuit shown (the high-gain reading unit 401 and the low-gain reading unit 402 do not share a source follower transistor), the signal transmission method may include: sequentially performing reset signal reset, low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition, and low-gain image signal acquisition, or may include: reset signal reset, low-gain reset signal acquisition, high-gain reset signal acquisition while performing image signal reset of the low-gain reading unit, high-gain image signal acquisition while performing image signal reset of the low-gain reading unit, and low-gain image signal acquisition.

[0070] In practical applications, by making the first high-gain source follower transistor M4 and the first low-gain source follower transistor M9 access different variable voltages, such as the first high-gain source follower transistor M4 accessing a high-level variable voltage and the first low-gain source follower transistor M9 accessing a low-level variable voltage, the image signal reset of the low-gain reading unit is achieved while performing high-gain reset signal acquisition. The first low-gain source follower transistor M9 accesses a high-level variable voltage and the first high-gain source follower transistor M4 accesses a low-level variable voltage, so that the image signal reset of the high-gain reading unit is achieved while performing low-gain image signal acquisition. The second signal transmission method (i.e., the signal transmission sequence is: reset signal reset, low-gain reset signal acquisition, high-gain reset signal acquisition while performing image signal reset of the low-gain reading unit, high-gain image signal acquisition while performing image signal reset of the low-gain reading unit, low-gain image signal acquisition) saves the time of an image signal reset compared with the first signal transmission method, thus saving the time of the pixel cycle. Among them, the second signal transmission method can be implemented based on a circuit that does not share the first source follower transistor.

[0071] After the reset signal is reset, the reset transistor M1 is set to the first potential, and low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition, and low-gain image signal acquisition are performed at the first potential; when there are a first high-gain source follower transistor and a first low-gain source follower transistor, during the reset signal reset process and the image signal reset process, the potentials of the first high-gain source follower transistor are the same, and the potentials of the first low-gain source follower transistor are the same. Optionally, the first potential, the potential of the first high-gain source follower transistor, and the potential of the first low-gain source follower transistor are all ground potential or close to ground potential. During the reset signal reset process and the image signal reset process, by setting the potentials of the first high-gain source follower transistor and the first low-gain source follower transistor to a sufficiently low level, the problem that the subsequent source follower transistor cannot conduct due to the reduction of the potential of the floating diffusion point FD (caused by too long exposure time) is avoided, so that low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition, and low-gain image signal acquisition can all be performed at the first potential, thereby saving power consumption; moreover, due to the design of the gain control transistor M2, the potential of the floating diffusion point FD is less affected by the exposure time.

[0072] Specifically, based on Figure 2 During the process of global exposure implemented by the shown pixel circuit (the high-gain reading unit 401 and the low-gain reading unit 402 share the source follower transistor), the signal transmission method includes: sequentially performing reset signal reset, low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition, and low-gain image signal acquisition.

[0073] After the reset signal is reset, the reset transistor M1 is set to the first potential, and low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition, and low-gain image signal acquisition are performed at the first potential; during the reset signal reset process and the image signal reset process, the potentials of the shared source follower transistor are the same. Optionally, the first potential and the potential of the shared source follower transistor are both ground potential or close to ground potential. During the reset signal reset process and the image signal reset process, by setting the potential of the shared source follower transistor to a sufficiently low level, the problem that the subsequent source follower transistor cannot conduct due to the reduction of the potential of the floating diffusion point FD (caused by too long exposure time) is avoided, so that low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition, and low-gain image signal acquisition can all be performed at the first potential, thereby saving power consumption; moreover, due to the design of the gain control transistor M2, the potential of the floating diffusion point FD is less affected by the exposure time.

[0074] Specifically, the control method includes: in the first high-gain transmission mode, the left plate of the first capacitor stores the high-gain reset voltage signal Vrst hcg, the right plate stores the first power supply voltage signal Vdd, and the voltage difference between the left and right plates of the first capacitor is Vdd - Vrst hcg. So that in the second high-gain transmission mode, when the left plate of the first capacitor stores the high-gain image voltage signal Vsig hcg, the right plate stores the high-gain output voltage signal Vsig hcg+(Vdd - Vrst hcg); in the first low-gain transmission mode, the left plate of the second capacitor stores the low-gain reset voltage signal Vrst lcg, the right plate stores the first power supply voltage signal Vdd, and the voltage difference between the left and right plates of the second capacitor is Vdd - Vrst lcg. So that in the second low-gain transmission mode, when the left plate of the second capacitor stores the low-gain image voltage signal Vsig lcg, the right plate stores the low-gain output voltage signal Vsig lcg+(Vdd - Vrst lcg). It should be noted that the specific control method can be found in detail in Embodiment 1 and will not be elaborated here.

[0075] More specifically, the reading process of the pixel circuit includes a first stage and a second stage. In the first stage, the pixel circuit outputs the voltage signal Vsig+(Vdd - Vrst). In the second stage, the pixel circuit outputs the first power supply voltage signal Vdd. By taking the difference between the voltage signals output in the first stage and the second stage, the voltage difference between the image voltage signal and the reset voltage signal in different gain transmission modes, that is, the pixel signal, can be obtained.

[0076] Specifically, the signal output methods of the high-gain reading unit and the low-gain reading unit include serial output or parallel output. In practical applications, serial output and parallel output can be selected according to specific requirements, which has no impact on this embodiment. Only the conduction timing of the high-gain row selection signal rsH and the low-gain row selection signal rsL needs to be adjusted.

[0077] Embodiment 3

[0078] This embodiment provides a CMOS image sensor, which includes: at least one pixel circuit as in Embodiment 1.

[0079] Specifically, the CMOS image sensor includes a plurality of pixels. The pixels are arranged in rows and columns to form a pixel array, and the pixels correspond to the pixel circuits. In practical applications, the pixels correspond to the pixel circuits one by one, that is, each pixel is composed of a pixel circuit; of course, multiple pixels can also share the same reading module 400, which has no impact on this embodiment.

[0080] Specifically, in one example, the CMOS image sensor includes a first semiconductor substrate and a second semiconductor substrate stacked thereon. The photosensitive control module 300 is located in the first semiconductor substrate, and the reading module 400 is located in the second semiconductor substrate. In another example, the CMOS image sensor includes a first semiconductor substrate and a second semiconductor substrate stacked thereon. The photosensitive control module 300 and the reading module 400 are located in the first semiconductor substrate, and the CMOS image sensor further includes a logic circuit located in the second semiconductor substrate. In yet another example, the CMOS image sensor includes a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate stacked thereon. The photosensitive control module 300 is located in the first semiconductor substrate, the reading module 400 is located in the second semiconductor substrate, and the CMOS image sensor further includes a logic circuit located in the third semiconductor substrate. It should be noted that the electrical connection (bonding) method between each substrate can be implemented based on the circuit using existing processes. For example, metal pads and interconnects or TSV vias are used to achieve electrical connection between transistor devices.

[0081] In summary, a pixel circuit, a CMOS image sensor, and a control method according to the present invention effectively improve the dynamic range of the CMOS image sensor by using the dual conversion gain technology through the design of the gain control module and the reading module; a larger capacitor is used for the high-intensity illumination area to increase the stored charge and reduce the gain to improve the dynamic range, and a smaller capacitor is used for the low-intensity illumination area to increase the gain and achieve high sensitivity. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0082] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A pixel circuit, characterized in that, the pixel circuit includes: a reset module, a gain control module, a photosensitive control module and a reading module, wherein, the reset module includes a reset transistor, the gate terminal of the reset transistor is connected to a reset control signal, the first connection terminal is connected to a power supply voltage, and the second connection terminal is connected to a floating diffusion point; the gain control module is connected between the second connection terminal of the reset transistor and the floating diffusion point, and is controlled by a gain control signal, and is used to adjust the equivalent charge storage capacity of the floating diffusion point according to the gain control signal, so that the pixel circuit operates in different gain transfer modes; the photosensitive control module is connected between the floating diffusion point and a first reference voltage, and is controlled by a transfer control signal, and is used to generate exposure charges according to the photoelectric effect, and transfer and output the exposure charges according to the transfer control signal; the reading module includes a high-gain reading unit and a low-gain reading unit, both of which are connected to the floating diffusion point. Among them, the high-gain reading unit is used to read the voltage signal of the floating diffusion point in the high-gain transfer mode and output it; the low-gain reading unit is used to read the voltage signal of the floating diffusion point in the low-gain transfer mode and output it; the high-gain reading unit includes a first capacitor, the low-gain reading unit includes a second capacitor, the first capacitor is used to obtain the voltage difference between the image signal and the reset signal in the high-gain transfer mode, and the second capacitor is used to obtain the voltage difference between the image signal and the reset signal in the low-gain transfer mode.

2. The pixel circuit according to claim 1, characterized in that, the high-gain transfer mode includes a first high-gain transfer mode and a second high-gain transfer mode. In the first high-gain transfer mode, the left plate of the first capacitor stores a high-gain reset voltage signal Vrst hcg, and the right plate stores a first power supply voltage signal Vdd. In the second high-gain transfer mode, the left plate of the first capacitor stores a high-gain image voltage signal Vsig hcg, and the right plate stores a high-gain output voltage signal Vsig hcg+(Vdd-Vrst hcg); and / or, the low-gain transfer mode includes a first low-gain transfer mode and a second low-gain transfer mode. In the first low-gain transfer mode, the left plate of the second capacitor stores a low-gain reset voltage signal Vrst lcg, and the right plate stores a first power supply voltage signal Vdd. In the second low-gain transfer mode, the left plate of the second capacitor stores a low-gain image voltage signal Vsig lcg, and the right plate stores an output low-gain voltage signal Vsig lcg+(Vdd-Vrst lcg).

3. The pixel circuit according to claim 1, characterized in that, the high-gain reading unit further includes at least: a first high-gain source follower transistor, a first high-gain storage control transistor, a second high-gain storage control transistor, a second high-gain source follower transistor and a first row selection transistor; The gate terminal of the first high-gain source follower transistor is connected to the floating diffusion point, the first connection terminal is connected to a first variable voltage, and the second connection terminal is connected to the first connection terminal of the first high-gain storage control transistor; the gate terminal of the first high-gain storage control transistor is connected to a first high-gain storage control signal, and the second connection terminal is connected to the left plate of the first capacitor; the right plate of the first capacitor is connected to the second connection terminal of the second high-gain storage control transistor and the gate terminal of the second high-gain source follower transistor; the gate terminal of the second high-gain storage control transistor is connected to a second high-gain storage control signal, and the first connection terminal is connected to a first power supply voltage; the first connection terminal of the second high-gain source follower transistor is connected to a second power supply voltage, and the second connection terminal is connected to the first connection terminal of the first row selection transistor; the gate terminal of the first row selection transistor is connected to a high-gain row selection signal, and the second connection terminal serves as the output terminal of the high-gain reading unit; The low-gain reading unit further includes at least: a first low-gain source follower transistor, a first low-gain storage control transistor, a second low-gain storage control transistor, a second low-gain source follower transistor, and a second row selection transistor; The gate terminal of the first low-gain source follower transistor is connected to the floating diffusion point, the first connection terminal is connected to a second variable voltage, and the second connection terminal is connected to the first connection terminal of the first low-gain storage control transistor; the gate terminal of the first low-gain storage control transistor is connected to a first low-gain storage control signal, and the second connection terminal is connected to the left plate of the second capacitor; the right plate of the second capacitor is connected to the second connection terminal of the second low-gain storage control transistor and the gate terminal of the second low-gain source follower transistor; the gate terminal of the second low-gain storage control transistor is connected to a second low-gain storage control signal, and the first connection terminal is connected to a third power supply voltage; the first connection terminal of the second low-gain source follower transistor is connected to a fourth power supply voltage, and the second connection terminal is connected to the first connection terminal of the second row selection transistor; the gate terminal of the second row selection transistor is connected to a low-gain row selection signal, and the second connection terminal serves as the output terminal of the low-gain reading unit.

4. The pixel circuit according to claim 3, wherein, the first high-gain source follower transistor and the first low-gain source follower transistor are the same source follower transistor, the gate terminal of the shared source follower transistor is connected to the floating diffusion point, the first connection terminal is connected to a variable voltage, and the second connection terminal is respectively connected to the first connection terminal of the first high-gain storage control transistor and the first connection terminal of the first low-gain storage control transistor.

5. The pixel circuit according to claim 3 or 4, wherein, the high-gain reading unit includes a third capacitor, and the third capacitor is connected between the second connection terminal of the first high-gain storage control transistor and a second reference voltage; and / or, the low-gain reading unit includes a fourth capacitor, and the fourth capacitor is connected between the second connection terminal of the first low-gain storage control transistor and a third reference voltage.

6. The pixel circuit according to claim 1, It is characterized in that the gain control module includes: a gain control transistor and a gain adjustment capacitor, wherein the gate terminal of the gain control transistor is connected to the gain control signal, the first connection terminal is connected to the second connection terminal of the reset transistor, and is connected to the fourth reference voltage through the gain adjustment capacitor, and the second connection terminal is connected to the floating diffusion point.

7. The pixel circuit according to claim 6, It is characterized in that the gain adjustment capacitor is the parasitic capacitance of the connection point between the reset transistor and the gain control transistor to the ground; or, the gain adjustment capacitor is a device capacitor.

8. The pixel circuit according to claim 1, It is characterized in that the photosensitive control module includes: a photoelectric conversion element and a transmission transistor, wherein the output terminal of the photoelectric conversion element is connected to the first connection terminal of the transmission transistor, and the other end is connected to the first reference voltage; the gate terminal of the transmission transistor is connected to the transmission control signal, and the second connection terminal is connected to the floating diffusion point.

9. The pixel circuit according to claim 1, It is characterized in that the high-gain reading unit and the low-gain reading unit correspond to the same or different column lines to respectively realize serial output or parallel output of signals.

10. A control method for a pixel circuit, It is characterized in that comprises the following steps: providing a pixel circuit according to any one of claims 1-9; realizing global exposure based on the pixel circuit, and obtaining the voltage difference between the image signal and the reset signal in the high-gain transmission mode through the first capacitor, and obtaining the voltage difference between the image signal and the reset signal in the low-gain transmission mode through the second capacitor, so that the pixel circuit operates in different gain transmission modes.

11. The control method for a pixel circuit according to claim 10, It is characterized in that the control method includes: in the first high-gain transmission mode, the left plate of the first capacitor stores the high-gain reset voltage signal Vrsthcg, the right plate stores the first power supply voltage signal Vdd, and the voltage difference between the left and right plates of the first capacitor is Vdd-Vrsthcg, so that in the second high-gain transmission mode, when the left plate of the first capacitor stores the high-gain image voltage signal Vsighcg, the right plate stores the high-gain output voltage signal Vsig hcg+(Vdd-Vrst hcg); in the first low-gain transmission mode, the left plate of the second capacitor stores the low-gain reset voltage signal Vrstlcg, the right plate stores the first power supply voltage signal Vdd, and the voltage difference between the left and right plates of the second capacitor is Vdd-Vrstlcg, so that in the second low-gain transmission mode, when the left plate of the second capacitor stores the low-gain image voltage signal Vsiglcg, the right plate stores the output low-gain voltage signal Vsig lcg+(Vdd-Vrst lcg).

12. The control method for a pixel circuit according to claim 11, It is characterized in that during the process of realizing global exposure based on the pixel circuit, the signal transmission mode includes: Perform reset signal reset, low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition, and low-gain image signal acquisition in sequence; or, The signal transmission method includes: performing reset signal reset, low-gain reset signal acquisition, and high-gain reset signal acquisition while performing image signal reset of the low-gain reading unit, performing high-gain image signal acquisition while performing image signal reset of the low-gain reading unit, and low-gain image signal acquisition.

13. The control method of the pixel circuit according to claim 11, characterized in that, The reading process of the pixel circuit includes a first stage and a second stage. In the first stage, the pixel circuit outputs an output voltage signal Vsig+(Vdd-Vrst). In the second stage, the pixel circuit outputs a first power supply voltage signal Vdd.

14. The control method of the pixel circuit according to claim 10, characterized in that, The signal output methods of the high-gain reading unit and the low-gain reading unit include serial output or parallel output.

15. The control method of the pixel circuit according to any one of claims 10-14, characterized in that, After the reset signal is reset, the reset transistor is set to the first potential, and low-gain reset signal acquisition, high-gain reset signal acquisition, image signal reset, high-gain image signal acquisition, and low-gain image signal acquisition are performed at the first potential; and / or, when there is a first high-gain source follower transistor and a first low-gain source follower transistor or they are shared, during the reset signal reset process and the image signal reset process, the potentials of the first high-gain source follower transistor are the same, and the potentials of the first low-gain source follower transistor are the same.

16. A CMOS image sensor, characterized in that, The CMOS image sensor includes: a pixel circuit according to any one of claims 1-9.

17. The image sensor according to claim 16, characterized in that, The image sensor includes a first semiconductor substrate and a second semiconductor substrate stacked, the photosensitive control module is located in the first semiconductor substrate, and the reading module is located in the second semiconductor substrate; or, the image sensor includes a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate stacked, the photosensitive control module is located in the first semiconductor substrate, the reading module is located in the second semiconductor substrate, and the image sensor further includes a logic circuit, and the logic circuit is located in the third semiconductor substrate; or, the image sensor includes a first semiconductor substrate and a second semiconductor substrate stacked, the photosensitive control module and the reading module are located in the first semiconductor substrate, and the image sensor further includes a logic circuit, and the logic circuit is located in the second semiconductor substrate.

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