A graph computing apparatus, processing method and related device

Abstract

A kind of graph computing device (11), processing method and related equipment, wherein the graph computing device (11) includes at least one processing engine PE (101), each processing engine PE (101) in at least one processing engine PE (101) includes M state buffer (1011-1, 1011-2, …, 1011-M), arbitration logic unit (1012) and X operation unit (1013-1, 1013-2, …, 1013-X);Wherein, each state buffer (1011) in M state buffer (1011-1, 1011-2, …, 1011-M), for storing the state data of once iteration computing task;Arbitration logic unit (1012) is used to determine L graph computing instructions to be executed in current clock cycle based on the state data in M state buffer (1011-1, 1011-2, …, 1011-M), and L graph computing instructions are distributed to X operation unit (1013-1, 1013-2, …, 1013-X);Each operation unit (1013) in X operation unit (1013-1, 1013-2, …, 1013-X) is used to execute the graph computing instruction distributed by arbitration logic unit (1012).The graph computing device (11) can improve the performance of processor (10).

Description

Technical Field

[0001] The present invention relates to the field of directed graph computing technology, and in particular to a graph computing device, a processing method, and related equipment. Background Art

[0002] As data volumes and computational complexity continue to increase across various fields, the demands on processor computing power and performance are also increasing. While traditional control flow (Central Processing Unit) processors (CPUs) can achieve instruction-level parallel computing within a single core, they are unable to further enhance the performance of a single core. For example, they encounter bottlenecks in frequency, power consumption, complexity, and memory. Consequently, performance improvements in processors for mobile phones, servers, and desktop computers can only be achieved by increasing the number of cores.

[0003] In comparison, dataflow processors are more efficient. Unlike control flow architectures, dataflow architectures lack instruction counters. The timing of instruction execution depends on the availability of operands, and the execution order is determined by the dependencies between instructions. In other words, as long as there are enough function units (FUs) and a large enough instruction window, all instructions that are not data-dependent can be executed in parallel, greatly improving instruction parallelism.

[0004] For example, the data flow method described above is used to perform calculations for hot loop iteration instructions, hot instruction sequences, and repeatedly executed instruction sequences. This allows instructions to be repeatedly executed in a data flow architecture processor, reducing the number of times the processor core fetches instructions from memory and the bandwidth, and reducing the overhead of inter-instruction dependency checks, jump prediction, and register access overhead, effectively utilizing the processor's computing resources and improving processor performance. However, in traditional data flow architectures, the blocking of certain instructions may prevent instructions with dependencies from executing normally, ultimately significantly reducing the execution efficiency of instructions.

[0005] Therefore, how to utilize the above advantages of the data flow architecture to further improve the performance of the CPU in the field of general computing has become a technical problem that needs to be solved urgently. Summary of the Invention

[0006] Embodiments of the present invention provide a graph computing device, a processing method, and related equipment, which improve the instruction execution efficiency in directed graph computing.

[0007] In a first aspect, an embodiment of the present invention provides a graph computing device, comprising at least one processing engine (PE), each of the at least one PE comprising M state buffers, an arbitration logic unit, and X operation units; M is an integer greater than 1, and X is an integer greater than or equal to 1; wherein each of the M state buffers is used to store state data of an iterative computing task; wherein the iterative computing task is one of N iterative computing tasks included in the graph computing task, and N is an integer greater than 1; the arbitration logic unit is used to determine, based on the state data in the M state buffers, L graph computing instructions to be executed in the current clock cycle, and allocate the L graph computing instructions to the X operation units; wherein the L graph computing instructions are instructions corresponding to T iterative computing tasks, respectively, and the N iterative computing tasks include the T iterative computing tasks; L and T are both integers greater than or equal to 1 and less than or equal to X; and each of the X operation units is used to execute the graph computing instructions allocated by the arbitration logic unit.

[0008] The embodiment of the present invention sets multiple state buffers in the processing engine PE of the graph computing device, and each state buffer is used to store the state data of one of the iterative computing tasks of the graph computing task, so that the state data of different iterative computing tasks can be stored independently and separately in different state buffers without interfering with each other; thereby, the graph computing instructions in any iterative computing task do not need to be restricted by the execution progress of the previous iterative computing task, but can start execution as soon as its input data arrives, thereby ensuring the parallelism between multiple iterative computing tasks and improving the execution efficiency of the graph computing tasks. This solves the technical problem in the prior art that the blocking of a graph computing instruction in a certain iterative computing task causes the blocking of other or even all graph computing instructions. In summary, the embodiments of the present invention assume from a hardware perspective that the instructions between multiple iterative computing tasks are repeated but the input data are different, so that the dependencies between the iterations of each iterative computing task in the graph computing task are clarified during the compilation phase, and multiple state buffers are further used to perform hardware expansion of the multiple iterative loops of the graph computing task; and the cross-iteration instruction dependencies are implemented by using the data flow + control flow with the same concept of the graph computing architecture; finally, the graph computing instructions in different iterative computing tasks can be executed simultaneously after complying with the cross-iteration dependencies, thereby improving the execution efficiency of the graph computing task from the dimension of cross-iteration parallelism, and thus improving the performance of the processor.

[0009] In one possible implementation, the graph calculation task includes P graph calculation instructions; the device also includes an instruction buffer; the instruction buffer is used to store the P graph calculation instructions, wherein the N iterative calculation tasks share the P graph calculation instructions.

[0010] In this embodiment of the present invention, since the graph computation instructions executed by different iterative computation tasks can be considered identical, differing only in the input data, the P computation instructions contained in the graph computation task are stored in a shared instruction buffer to save storage space and instruction space. In other words, only one copy of the P graph computation instructions needs to be stored, unlike the N copies of the state data for the iterative computation task, thereby reducing storage overhead during the execution of the graph computation task.

[0011] In one possible implementation, the graph calculation task includes P graph calculation instructions; the status data of one iterative calculation task includes the input data of the P graph calculation instructions in the corresponding iterative calculation task; the arbitration logic unit is specifically used to: monitor whether the input data of the P graph calculation instructions in the iterative calculation task corresponding to the M status buffers are ready; select L graph calculation instructions corresponding to the earliest T iterative calculation tasks of the corresponding iterative calculation task from the graph calculation instructions whose current input data are ready, wherein one or more graph calculation instructions are selected in one iterative calculation task; and distribute the L graph calculation instructions to L of the X operation units from the instruction buffer, wherein one operation unit corresponds to one graph calculation instruction.

[0012] In an embodiment of the present invention, the arbitration logic unit monitors the state data currently stored in M ​​state buffers. When the input data of some graph calculation instructions in each state buffer are ready, the arbitration logic unit can select L graph calculation instructions with ready input data from them and send them to the operation unit for execution in the current clock cycle. The principle of selection is to give priority to selecting from the prepared graph calculation instructions in the L iterative calculation tasks with earlier iterations to ensure the overall execution efficiency of the graph calculation tasks. It should be noted that T and L can be equal or unequal, that is, one graph calculation instruction or multiple graph calculation instructions can be selected in one iterative calculation task. That is, in each clock cycle, a maximum of X graph calculation instructions can be selected from the M iterative calculation tasks corresponding to the M state buffers, and respectively assigned to X operation units for calculation, that is, one operation unit corresponds to one graph calculation instruction in one clock cycle. Of course, it is understandable that when the number of graph computing instructions prepared for the current input data is insufficient (i.e., less than X), graph computing instructions for iterative computing tasks with a number of times less than X may be selected and allocated to T operation units, which is equivalent to having operation units in an idle state.

[0013] In one possible implementation, the processing engine further includes a write-back unit; the X operation units are respectively connected to the write-back unit; and each of the X operation units is further configured to send a calculation result obtained by executing a graph calculation instruction to the write-back unit.

[0014] In an embodiment of the present invention, any processing engine in the graph computing device also includes a write-back unit, which is respectively connected to the X computing units in the processor engine. When each of the X computing units completes executing the graph computing instruction and obtains the corresponding computing result, the computing result can be sent to the write-back unit, so that the write-back unit writes the computing result back to the corresponding position in the corresponding state buffer according to the result address corresponding to the computing result, thereby realizing the data dependency relationship between the instructions within the iterative computing task of the graph computing task, and the data dependency relationship between different iterative computing tasks.

[0015] In one possible implementation, the graph calculation instruction includes an iterative intra-graph calculation instruction; the iterative intra-graph calculation instruction carries a result address; the write-back unit is used to send the i-th iterative calculation result to the result address in the status buffer corresponding to the i-th iterative calculation task, wherein the value range of i is a positive integer less than or equal to N, and the i-th iterative calculation result is the result obtained by executing the iterative intra-graph calculation instruction in the i-th iterative calculation task in the N iterative calculation tasks.

[0016] In an embodiment of the present invention, a graph calculation task includes an iterative intra-graph calculation instruction, and the iterative intra-graph calculation instruction includes a result address to which the calculation result ultimately points, that is, the result address to which the calculation result obtained by the graph calculation instruction needs to be transferred (for example, as input data for other graph calculation instructions in this iterative calculation task). After the iterative intra-graph calculation instruction in a certain iterative calculation task in the graph calculation task is executed by the operation unit, the write-back unit sends its calculation result to the state buffer where the state data of the iterative calculation task itself is stored according to the iterative intra-graph calculation instruction, so as to facilitate the execution of other instructions in the iterative calculation task that have data dependencies thereon. That is, for any iterative calculation task of the graph calculation task, when executing the iterative intra-graph calculation instruction, the calculation result of the graph calculation instruction is fed back to the state buffer where the state data of the iterative calculation task itself is stored, so that the relevant instructions in the iterative calculation task continue to use the calculation result as data input and continue to execute.

[0017] In one possible implementation, the graph calculation instruction includes a cross-iteration graph calculation instruction, which carries a result address and a cross-iteration identifier; the write-back unit is used to send the i-th iteration calculation result to the result address in the status buffer corresponding to the i+1-th iteration calculation task according to the cross-iteration identifier; wherein the value range of i is a positive integer less than or equal to N-1, and the i-th iteration calculation result is the result obtained by executing the cross-iteration graph calculation instruction in the i-th iteration calculation task in the N-iteration calculation tasks.

[0018] In an embodiment of the present invention, a graph calculation task includes a cross-iteration graph calculation instruction, and the cross-iteration graph calculation instruction includes a result address to which the calculation result ultimately points, that is, the result address to which the calculation result obtained by the graph calculation instruction needs to be transferred (for example, as input data for other graph calculation instructions in the next iterative calculation task). After the intra-iteration graph calculation instruction in a certain iterative calculation task in the graph calculation task is executed by the operation unit, the write-back unit sends its calculation result to the state buffer where the state data of the next iterative calculation task of the iterative calculation task is stored according to the intra-iteration graph calculation instruction, so as to facilitate the execution of other instructions with data dependencies in the next iterative calculation task. That is, for any iterative calculation task of the graph calculation task, when executing the cross-iteration graph calculation instruction, the calculation result of the graph calculation instruction is fed back to the state buffer where the state data of the next iterative calculation task of the iterative calculation task is stored, so that the relevant instructions in the next iterative calculation task continue to use the calculation result as data input and continue to execute.

[0019] In one possible implementation, the write-back unit is specifically used to: when the calculation results corresponding to multiple iterative calculation tasks need to be written back to the corresponding status buffers, the calculation results corresponding to the iterative calculation tasks with earlier iterations are preferentially written back to the status buffers corresponding to the iterative calculation tasks with earlier iterations.

[0020] In an embodiment of the present invention, when the calculation results corresponding to multiple iterative calculation tasks need to be written back to the corresponding state buffer respectively, the write-back unit will give priority to writing the results of the iterative calculation tasks with earlier iterations back to the corresponding state buffer, so as to complete the iterative calculation tasks with earlier iterations as soon as possible, so as to start the new iterative calculation tasks as soon as possible, and thus complete the calculation of the N iterative calculation tasks of the graph calculation task as soon as possible. The reason is that since the graph calculation task contains N iterative calculation tasks, and usually the value of N is large and the value of X is small, it may take multiple rounds to complete the execution of the N iterative calculation tasks of the graph calculation task. Between the replacement of the state data of multiple iterative calculation tasks, the earlier iterative calculation tasks need to be calculated and the corresponding state data cleared before the loading of data for the new iterative calculation task can be started. That is, if the calculation results of the iterative calculation tasks with earlier iterations (oldest) are written back first, the iterative calculation tasks with earlier iterations (oldest) can be completed and cleared faster, so that the new iterative calculation tasks can be loaded into the state buffer as soon as possible, thereby improving the overall execution efficiency of the graph calculation tasks.

[0021] In one possible implementation, the graph calculation instruction includes an iterative window moving instruction; each state buffer is further used to: when the graph calculation instruction in the j-th iterative calculation task has been calculated, according to the iterative window moving instruction, clear the state data in the state buffer corresponding to the j-th iterative calculation task, and load the state data of the j+M-th calculation task into the cleared state buffer; wherein the j-th iterative calculation task is the earliest iterative calculation task among the currently corresponding iterative calculation tasks in the M state buffers.

[0022] In this embodiment of the present invention, since the number of state buffers M is limited, when the number of iterative computation tasks N included in a graph computation task is large, it is understood that multiple rounds of iterative computation tasks are required to complete the N iterative computation tasks. Between the state data changes of multiple iterative computation tasks, the earlier iterative computation tasks must be completed and the corresponding state data cleared before loading the data for the new iterative computation task can begin. In this embodiment of the present invention, when the graph computation instructions in the jth iterative computation task have been calculated, according to the parallel processing width M in this embodiment of the present invention, the state data of the earliest iterative computation task that has not yet been executed, i.e., the j+Mth iterative computation task, can be loaded into the cleared state buffer, forming a sliding window of width M. Therefore, when the earliest iterative computation task completes its calculation, the state data of the latest iterative computation task outside the window can be loaded, thereby creating the effect of a cross-iterative window of width M. As the window moves, the N iterative computation tasks of the graph computation task are completed.

[0023] In one possible implementation, the write-back unit is further used to: prohibit the calculation result of the (j+M-1)th iterative calculation task from being sent to the status buffer corresponding to the (j+M)th iterative calculation task before the status data of the j+Mth calculation task is loaded into the cleared status buffer; and allow the calculation result of the (j+M-1)th iterative calculation task to be sent to the status buffer corresponding to the (j+M)th iterative calculation task after the status data of the j+Mth calculation task is loaded into the cleared status buffer.

[0024] In this embodiment of the present invention, since the number of state buffers M is limited, if the M iterative computation tasks corresponding to these M state buffers have not yet completed computation, the state data of the new iterative computation task cannot be loaded. Therefore, it is necessary to wait until at least one of the M iterative computation tasks in the current round has completed before the latest uncomputed iterative computation task can be loaded. Furthermore, in this embodiment of the present invention, each repeated execution of a graph computation task is referred to as an "iteration," and the result obtained from each iterative computation task is used as the initial value for the next iterative computation task. In other words, there is a direct data dependency between two consecutive iterative computation tasks. Therefore, based on the relationship between iterations, in this embodiment of the present invention, the state data of the latest uncomputed iterative computation task is loaded only after the oldest iterative computation task has completed. This ensures that the M iterative computation tasks currently in the M state buffers are always continuous, avoiding computational chaos caused by the inability of the instruction window to move based on the oldest state buffer due to discontinuity between the M parallel iterative computation tasks, thereby improving the overall computational efficiency of the graph computation task.

[0025] In one possible implementation, the graph calculation instruction includes a calculation termination instruction; each state buffer is further used to clear the state data of the iterative calculation tasks exceeding the Nth iterative calculation task in the N iterative calculation tasks according to the calculation termination instruction when the calculation of the Nth iterative calculation task is completed, and jump out of the loop.

[0026] In an embodiment of the present invention, if no termination instruction is received when the Nth iteration of a computation task is calculated, the loop iteration task may continue to execute, exceeding the expected number of iterations and causing an instruction execution overflow effect. Therefore, in an embodiment of the present invention, a termination instruction is used to instruct the graph computation task to terminate its computation while also clearing the relevant data of the overflowed iteration task, thus avoiding the problem of incorrect computation results caused by the overflow effect of the iterative computation task execution.

[0027] In a second aspect, an embodiment of the present invention provides a processing method applied to a graph computing device, wherein the graph computing device includes at least one processing engine PE, each of the at least one PE includes M status buffers, an arbitration logic unit and X operation units; M is an integer greater than 1, and X is an integer greater than or equal to 1; each of the M status buffers stores status data of an iterative computing task; wherein the iterative computing task is one of the N iterative computing tasks included in the graph computing task, and N is an integer greater than 1; the method may include: based on the status data in the M status buffers, determining L graph computing instructions to be executed in the current clock cycle through the arbitration logic unit, and allocating the L graph computing instructions to the X operation units; wherein the L graph computing instructions are instructions corresponding to T iterative computing tasks, and the N iterative computing tasks include the T iterative computing tasks; L and T are both integers greater than or equal to 1 and less than or equal to X; and executing the graph computing instructions allocated by the arbitration logic unit through the X operation units.

[0028] In a possible implementation, the graph calculation task includes P graph calculation instructions; the device further includes an instruction buffer; the instruction buffer stores the P graph calculation instructions, wherein the N iterative calculation tasks share the P graph calculation instructions.

[0029] In one possible implementation, the graph calculation task includes P graph calculation instructions; the status data of one iterative calculation task includes input data of the P graph calculation instructions in the corresponding iterative calculation task; the determining, based on the status data in the M status buffers, L graph calculation instructions to be executed in the current clock cycle by the arbitration logic unit, and distributing the L graph calculation instructions to the X operation units includes: monitoring, by the arbitration logic unit, whether the input data of the iterative calculation tasks corresponding to the P graph calculation instructions in the M status buffers are ready; selecting, from the graph calculation instructions whose current input data are ready, L graph calculation instructions corresponding to the earliest T iterative calculation tasks of the corresponding iterative calculation task, wherein one or more graph calculation instructions are selected in one iterative calculation task; and distributing the L graph calculation instructions from the instruction buffer to L of the X operation units, wherein one operation unit corresponds to one graph calculation instruction.

[0030] In one possible implementation, the graph computing task includes P graph computing instructions; the status data of an iterative computing task of the graph computing task includes input data of the P graph computing instructions under the corresponding iterative computing task; the determining, based on the status data in the M status buffers, L graph computing instructions to be executed in the current clock cycle by the arbitration logic unit, and distributing the L graph computing instructions to the X operation units includes: monitoring, by the arbitration logic unit, whether the input data required by the P graph computing instructions corresponding to the currently corresponding iterative computing tasks in the M status buffers are ready; selecting, from the graph computing instructions for which the input data of the current instruction is ready, the L graph computing instructions corresponding to the earliest T iterative computing tasks of the corresponding iterative computing task, wherein one or more graph computing instructions are selected in one iterative computing task; and distributing the L graph computing instructions to L operation units among the X operation units, wherein one operation unit corresponds to one graph computing instruction.

[0031] In one possible implementation, the processing engine further includes a write-back unit; the X operation units are respectively connected to the write-back units; and the method further includes: sending calculation results obtained by executing graph calculation instructions through the X operation units to the write-back unit.

[0032] In one possible implementation, the graph calculation instruction includes an iterative intra-graph calculation instruction; the iterative intra-graph calculation instruction carries a result address; the method further includes: sending the i-th iterative calculation result to the result address in the status buffer corresponding to the i-th iterative calculation task through the write-back unit, wherein the value range of i is a positive integer less than or equal to N, and the i-th iterative calculation result is the result obtained by executing the iterative intra-graph calculation instruction in the i-th iterative calculation task in the N iterative calculation tasks.

[0033] In one possible implementation, the graph calculation instruction includes a cross-iteration graph calculation instruction, which carries a result address and a cross-iteration identifier; the method also includes: according to the cross-iteration identifier, sending the i-th iteration calculation result to the result address in the status buffer corresponding to the i+1-th iteration calculation task through the write-back unit; wherein the value range of i is a positive integer less than or equal to N-1, and the i-th iteration calculation result is the result obtained by executing the cross-iteration graph calculation instruction in the i-th iteration calculation task in the N-iteration calculation tasks.

[0034] In one possible implementation, when the calculation results corresponding to multiple iterative calculation tasks need to be written back to the corresponding status buffers, the write-back unit preferentially writes the calculation results corresponding to the iterative calculation tasks with earlier iterations back to the status buffers corresponding to the iterative calculation tasks with earlier iterations.

[0035] In one possible implementation, the graph calculation instruction includes an iterative window moving instruction; the method also includes: when the graph calculation instruction in the j-th iterative calculation task has been calculated, according to the iterative window moving instruction, the state data in the state buffer corresponding to the j-th iterative calculation task is cleared through the M state buffers, and the state data of the j+M-th calculation task is loaded into the cleared state buffer; wherein, the j-th iterative calculation task is the earliest iterative calculation task among the currently corresponding iterative calculation tasks in the M state buffers.

[0036] In one possible implementation, the method further includes: before the status data of the j+Mth computing task is loaded into the cleared status buffer, prohibiting the calculation result of the (j+M-1)th iterative computing task from being sent to the status buffer corresponding to the (j+M)th iterative computing task through the write-back unit; after the status data of the j+Mth computing task is loaded into the cleared status buffer, allowing the calculation result of the (j+M-1)th iterative computing task to be sent to the status buffer corresponding to the (j+M)th iterative computing task through the write-back unit.

[0037] In one possible implementation, the graph calculation instruction includes a calculation termination instruction; the method also includes: when the Nth iterative calculation task in the N iterative calculation tasks is completed, according to the calculation termination instruction, the M state buffers will clear the state data of the iterative calculation tasks that exceed the Nth iterative calculation task and jump out of the loop.

[0038] In a third aspect, the present application provides a semiconductor chip, which may include a graph computing device provided by any one of the implementation methods in the first aspect above.

[0039] In a fourth aspect, the present application provides a semiconductor chip, which may include: a graph computing device provided by any one of the implementation methods in the above-mentioned first aspect, an internal memory coupled to the graph computing device, and an external memory.

[0040] In a fifth aspect, the present application provides a system-on-chip (SoC) chip, comprising a graph computing device according to any one of the implementations of the first aspect, and internal and external memory coupled to the graph computing device. The SoC chip may consist solely of a chip or may include a chip and other discrete components.

[0041] In a sixth aspect, the present application provides a chip system comprising the graph computing device provided by any one of the implementations of the first aspect. In one possible design, the chip system further comprises a memory configured to store program instructions and data necessary or relevant for the operation of the graph computing device. The chip system may be comprised solely of a chip, or may include a chip and other discrete components.

[0042] In a seventh aspect, the present application provides a processing device having the function of implementing any one of the processing methods described in the second aspect. This function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-mentioned functions.

[0043] In an eighth aspect, the present application provides a processor comprising the graph computing device provided by any one of the implementations of the first aspect. The processor may further include other functional units, such as an instruction fetch unit, an instruction decoding unit, and an instruction scheduling unit, which are configured to couple with the graph computing device to perform general computing tasks or graph computing tasks.

[0044] In a ninth aspect, the present application provides a terminal, comprising a processor, the processor comprising the graph computing apparatus provided by any one of the implementations of the first aspect. The terminal may further comprise a memory coupled to the processor and storing program instructions and data necessary for the terminal. The terminal may further comprise a communication interface for communicating with other devices or a communication network.

[0045] In a tenth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a graph computing device, the processing method flow described in any one of the above-mentioned second aspects is implemented.

[0046] In the eleventh aspect, an embodiment of the present invention provides a computer program, which includes instructions. When the computer program is executed by a graph computing device, the graph computing device can execute the processing method flow described in any one of the above-mentioned second aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 This is an example of loop calculation under the static data flow architecture in the prior art.

[0048] Figure 2 This is an example of loop calculation under the dynamic data flow architecture in the prior art.

[0049] Figure 3A An abstract model of graph computing instructions provided by an embodiment of the present invention.

[0050] Figure 3B A schematic diagram of a graph computing instruction provided by an embodiment of the present invention.

[0051] Figure 3C A schematic diagram of a model of a graph computing task including multiple graph computing instructions provided in an embodiment of the present invention.

[0052] Figure 4A This is a schematic diagram of the structure of a processor provided by an embodiment of the present invention.

[0053] Figure 4B It is a structural diagram of another processor provided by an embodiment of the present invention.

[0054] Figure 4C This is a structural diagram of another processor provided by an embodiment of the present invention.

[0055] Figure 4D This is a structural diagram of another processor provided by an embodiment of the present invention.

[0056] Figure 5A It is a structural diagram of a graph computing device provided by an embodiment of the present invention.

[0057] Figure 5B It is a structural diagram of another graph computing device provided by an embodiment of the present invention.

[0058] Figure 6A It is a structural diagram of a processing engine provided by an embodiment of the present invention.

[0059] Figure 6B A schematic diagram of a cyclic directed graph and an acyclic graph provided in this application.

[0060] Figure 6C A data flow graph for a graph computing task provided by an embodiment of the present invention.

[0061] Figure 7A It is a structural diagram of another processing engine provided by an embodiment of the present invention.

[0062] Figure 7B A schematic diagram of a model corresponding to the expansion of a graph computing task in a PE provided in an embodiment of the present invention.

[0063] Figure 8AA schematic diagram of the dependency relationship of iterative computing tasks in a state buffer provided by an embodiment of the present invention.

[0064] Figure 8B A schematic diagram of a certain operation unit executing instructions in a graph computing task in multiple clock cycles provided by an embodiment of the present invention.

[0065] Figure 9A A schematic diagram of an iterative window provided by an embodiment of the present invention.

[0066] Figure 9B A schematic diagram of an iterative window after movement provided by an embodiment of the present invention.

[0067] Figure 9C A schematic diagram of the cyclic execution of an iterative computing task provided by an embodiment of the present invention.

[0068] Figure 9D A schematic diagram of establishing a new iterative computing task provided by an embodiment of the present invention.

[0069] Figure 9E A schematic diagram of preventing further iterative computing task submission provided by an embodiment of the present invention.

[0070] Figure 10 It is a flowchart of a processing method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0071] The embodiments of the present invention will be described below with reference to the accompanying drawings.

[0072] The terms "first," "second," "third," and "fourth," etc., in the specification and claims of this application and the accompanying drawings are used to distinguish between different objects, rather than to describe a specific order. In addition, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0073] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0074] As used in this specification, the terms "component," "module," "system," and the like are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and a computing device can be a component. One or more components can reside in a process and / or an execution thread, and a component can be located on a computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media having various data structures stored thereon. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component on a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0075] First, some terms in this application are explained to facilitate understanding by those skilled in the art.

[0076] (1) A graph is an abstract data structure used to represent the relationship between objects. It is described using vertices and edges: vertices represent objects, and edges represent the relationship between objects.

[0077] (2) Superscalar processor architecture refers to a type of parallel computing that implements instruction-level parallelism within a processor core. This technology can achieve higher CPU throughput at the same CPU frequency.

[0078] (3) Single Instruction Multiple Data (SIMD), a set of instructions that can copy multiple operands and pack them into large registers.

[0079] (4) Instruction pipelining is a method of improving the efficiency of the processor's instruction execution by dividing the operation of an instruction into multiple small steps, each of which is completed by a dedicated circuit. For example, an instruction must go through three stages to be executed: instruction fetch, decoding, and execution. Each stage takes one machine cycle. If the pipeline technology is not used, then the execution of this instruction requires three machine cycles. If the instruction pipelining technology is used, then when the instruction completes the "fetch" and enters the "decoding" stage, the next instruction can be "fetched", thus improving the execution efficiency of the instruction.

[0080] (5) Execution Unit (EU) It is responsible for the execution of instructions and actually has the functions of both a controller and an arithmetic unit.

[0081] (6) The register file, also known as the register stack, is an array of multiple registers in the CPU, usually implemented as a fast static random access memory (SRAM). This RAM has dedicated read and write ports, allowing multiple concurrent accesses to different registers.

[0082] (7) Integrated Circuit (IC) is a microelectronic device or component. Using a certain process, the transistors, resistors, capacitors, inductors and other components required in a circuit are interconnected with wiring and manufactured on a small piece or several small pieces of semiconductor wafers or dielectric substrates. Then, they are packaged in a tube shell to form a microstructure with the required circuit function. In other words, an IC chip is an integrated circuit formed by a large number of microelectronic components (transistors, resistors, capacitors, etc.) placed on a plastic substrate to form a chip.

[0083] (8) Directed Acyclic Graph (DAG), where "directed" means having a direction, or more precisely, the same direction, and "acyclic" means not being able to form a closed loop. A directed acyclic graph is a directed graph without loops. If there is a non-directed acyclic graph, and a node A goes from point A to point B and back to point A via point C, forming a loop. If the direction of the edge from point C to point A is changed to point A to point C, it becomes a directed acyclic graph. The number of spanning trees of a directed acyclic graph is equal to the in-degree product of the nodes with non-zero in-degree.

[0084] (9) A thread is the smallest unit that an operating system can schedule operations on. It is contained within a process and is the actual operating unit within the process. A thread refers to a single sequential flow of control within a process. A process can have multiple threads running concurrently, each executing different tasks in parallel. In Unix System V and SunOS, these are also called lightweight processes, but lightweight processes more often refer to kernel threads, while user threads are called threads.

[0085] (10) Iteration. Each repetition of a process is called an "iteration," and the result of each iteration serves as the initial value for the next iteration. In this application, the repetition of a subroutine (a set of instructions) in a specific computer program that needs to be executed repeatedly, that is, the repetition of a loop in the program until a certain condition is met, is called an iteration.

[0086] (11) Clock cycle: A machine cycle is divided into several equal time periods. Such time periods are called beats or clock cycles. A CPU clock cycle is also called a beat or a beat.

[0087] (12) Instructions per Clock (IPC), which refers to the number of instructions executed by the CPU per clock cycle. IPC represents the design architecture of a CPU. Once the CPU design is completed, the upper limit of IPC is fixed. In one way to judge CPU performance, CPU performance = IPC (the number of instructions executed by the CPU per clock cycle) × frequency (MHz clock speed). For example, a 15% increase in IPC means a 15% performance increase at the same CPU frequency.

[0088] (13) The opcode is the instruction sequence number that tells the CPU which instruction to execute. Each instruction in the instruction system has an opcode that indicates the nature of the operation to be performed. Different instructions are represented by different encodings of the opcode field, and each encoding represents an instruction. Operations such as transfer, calculation, shift, and jump are indispensable components of the instruction.

[0089] (14) An operand is a component of a computer instruction that specifies the amount of numerical computation to be performed in the instruction. The operand indicates the source of the data required for the operation to be performed by the instruction. The operand is a field in an assembly language instruction. For example, the operand field can contain the operand itself, the address of the operation, or the method for calculating the operation address.

[0090] (15) LD (Load) stands for load instruction, which indicates the first normally open contact directly connected to the bus in each line of program.

[0091] (16) Directed Acyclic Graph (DAG) is a directed graph without loops (acyclic). If there is a non-directed acyclic graph, and a path from point A to point B via point C can return to point A, such as A->B->C->A, which forms a cycle and then returns to point A, then the graph has a cycle.

[0092] In order to facilitate understanding of the embodiments of the present invention, the technical problems to be specifically solved by this application are further analyzed and proposed.

[0093] In a dataflow program, when the target of the dataflow points to the input of the previous instruction, then this instruction is a dataflow loop (Back Edge). According to the way the dataflow architecture handles loops, the dataflow architecture can include static and dynamic dataflow architectures.

[0094] Solution 1: Static Data Flow Architecture

[0095] The Static Dataflow Architecture stipulates that when each data flow passes data to the previous instruction, if the returning data blocks the data flow being calculated, the previous instruction will backpressure the current operation. Backpressure checks need to check whether the target node needs to accept new input. See Figure 1 , Figure 1 This example illustrates loop computation under a static dataflow architecture in the prior art. For example, assume a graph computation task includes five instructions: instruction 1: add, instruction 2: add, instruction 3: ld, instruction 4: add, and instruction 5: st. Furthermore, assume the graph computation task includes at least four iterative computation tasks, corresponding sequentially to the first cycle, Cycle 0, the second cycle, Cycle 1, the third cycle, Cycle 2, and the fourth cycle, Cycle 3. Each complete and repeated execution of these five instructions is called an "iterative computation task," and the partial or complete execution results of each iterative computation task serve as the initial value for the next iterative computation task. For example, after executing instruction 1 in Cycle 0, instruction 2 is executed. The execution result of instruction 2 serves as input not only to instruction 3 in Cycle 0 but also to instruction 1 in the next cycle, Cycle 1. Similarly, the execution result of instruction 2 in Cycle 1 serves as input not only to instruction 3 in Cycle 1 but also to instruction 1 in the next cycle, Cycle 2. Similarly, the execution result of instruction 2 in each subsequent iterative computing task serves as the input of instruction 3 in the iterative computing task and also as the input of instruction 1 in the next iterative computing task. In the above-mentioned static data flow architecture, when computing iterations, back pressure is used to prevent the reflux node from generating the initial value of the next iteration. Similarly, cross-iteration dependencies can be complied with through data reflux and back pressure. For example, in Cycle3, when instruction 3:ld miss is always in a blocked state, instruction 2 can be prevented from generating the initial value of instruction 1 in the next iterative computing task through reflux, thereby preventing the next iterative computing task from starting to execute.

[0096] The disadvantage of the first scheme: Since it cannot be guaranteed which data stream will flow back first in a complex bus communication, the compiler needs to add barrier (stop) or select (select) instructions to ensure that all nodes of the graph are executed correctly in a more complex graph. In addition, in memory processing, the compiler often needs to add too much data backflow to ensure the correctness of memory reading and writing. Therefore, for complex graphs, the performance of the traditional static graph architecture can only complete the inter-instruction parallelism of one iteration (or the lower half of one iteration and the upper half of the next iteration).

[0097] The second scheme: dynamic data flow architecture

[0098] In comparison, dynamic data flow architecture (Dynamic Dataflow Architecture), such as WaveScalar and other dynamic architectures, allows simultaneous operation between different iterations. See Figure 2 , Figure 2 As an example of loop calculation in the prior art dynamic data flow architecture, each input of the graph will be equipped with a Wave Advance instruction during operation. The function of the Wave Advance instruction is to update the token (i.e. Figure 2 Iter0 i = 0, Iter1 i = 1, Iter2 i = 2, Iter3 i = 3) of the input. In this way, the dynamic data flow architecture can simultaneously operate instructions of different iteration calculation tasks. Specifically, the dynamic data flow architecture adds tokens to the data flow and input of different iteration calculation tasks. Only when the input token (such as Iter0, Iter1, Iter2, Iter3) corresponds can it be operated, that is, different iteration calculation tasks are distinguished by the token carried by the data. For example, data with Iter0 is considered to be the data corresponding to the first iteration calculation task of the graph calculation task, data with Iter2 is considered to be the third iteration calculation task of the graph calculation task, and so on. Since different tokens share a set of state buffers, and the iteration calculation task with a small token will back up the iteration calculation task with a large token, the iterations of different tokens cannot be completely parallel executed. That is, the above dynamic data flow architecture still determines how many iterations a graph can operate simultaneously through back pressure.

[0099] The disadvantage of the second scheme: too many Wave Advance instructions occupy a large amount of instruction space; the parallelism across iterations is limited by storage (a set of operand buffers are shared by multiple iterations), and the Write after Write parallelism does not improve significantly; it cannot effectively distinguish and execute the current iteration instruction first; it cannot effectively handle the dependency relationship between iterations.

[0100] Therefore, the technical problems to be solved by this application may include the following:

[0101] 1. Further improve the parallelism in data flow loop calculations; 2. Reduce the instruction space occupied by instructions; 3. Further improve the overall efficiency of loop iterative calculations.

[0102] In order to further understand the embodiments of the present invention, the following describes in detail the concepts of data flow architecture, processing engine (PE), graph computing task, iterative computing task, state data, graph computing instruction, etc. involved in this application. The data flow architecture involved in this application is to explicitly describe the dependency relationship of instructions at the instruction set level and directly present the parallelism between instructions to the hardware for execution. The theoretical computing model of this data flow architecture can be abstracted into a directed graph consisting of P nodes, and the connection between nodes represents a data flow (Dataflow) or control flow (ControlFlow). Each node is a graph instruction (also referred to as a graph computing instruction in this application). Once the input of each node is ready (Ready), the current node can perform the operation and pass the result to the input of the corresponding node. Therefore, nodes that are not on the same path in the same graph can be executed in parallel, thereby improving the parallelism of processing. It should be noted that the data flow architecture in this application also needs to support the control flow. Therefore, in this application, (data flow + control flow) is collectively referred to as a directed graph computing flow architecture, and is referred to as a graph computing flow architecture or graph computing architecture (GraphflowArchitecture). It should also be noted that the control flow in the graph computing architecture in this application is not completely equivalent to the control flow of a general-purpose processor. The control flow in the general-purpose processor architecture mainly refers to the execution instructions for general operations, while the control flow of the graph computing architecture in this application mainly refers to various graph computing control instructions within the graph (such as switch / gate / predicate / gate instructions, etc.).

[0103] Since the theoretical computing model of the Graphflow architecture in this application can be abstracted into P nodes, each node can place an instruction, perform an operation, and pass the result to itself or other nodes. Therefore, this application also defines the basic format of a flow instruction (also called a graph computing instruction) in the graph computing instruction set (Graphflow Instruction-Set Architecture, Graphflow ISA). That is, the operation method of the P graph computing instructions contained in the graph computing task in this application, and the connection and sequence information between the P graph computing instructions, wherein the format of a graph computing instruction corresponding to a single node can be expressed as: [ID+opcode+dest0ID+dest1ID].

[0104] See Figure 3A , Figure 3A An abstract model of a graph computing instruction provided by an embodiment of the present invention is provided. Graph computing instructions based on IDs will be placed at nodes with the corresponding IDs. The range of IDs is [0, P-1], and P is the total number of nodes in Graphflow. A graph computing instruction can express one or two dependency relationships, indicating that the result data is passed to dest0ID and dest1ID. Figure 3A As shown in the figure, each abstract node can hold one instruction and up to two outputs. Each abstract node has its own left input (l), right input (r), conditional input (p) buffer, operation code (opcode), and two destination pointers (dest0T, dest1T, where T represents the left / right input of the target instruction). Assuming that P nodes are fully connected, the range of dest is [0, P-1], meaning that the output of any node can point to the left input (l) or right input (r) buffer of any node. The (opcode, dest0T, dest1T) fields in the abstract node can be written to during the construction phase but are fixed to read-only during the execution phase. Once in the execution phase, all nodes must concurrently check whether their left and right inputs have arrived. If both inputs are ready, the operation can be performed and the result passed to the left and right outputs of the next node. Nodes whose inputs have not arrived are placed in an idle state.

[0105] For example, see Figure 3B , Figure 3BA schematic diagram of a graph computing instruction provided for an embodiment of the present invention assumes that the inputs required for each graph computing instruction are a left input (l), a right input (r), and a conditional input (p). Once the inputs required by the instruction are ready, the operation can be performed, and the result of the operation is passed to the input of the corresponding node behind. For example, after the operation a+b of add in instruction 1 is completed, it can be passed to the left input (l) of instruction 4. The dependency relationship between the above instructions can be expressed as "1add 4l" in the graph architecture instruction set involved in this application. This means that for instruction 1, once its input is ready, the result is passed to the left input of instruction 4. In the graph computing instruction set in this application, only the output address needs to be provided without providing the input information of the instruction. The input only needs to ensure that the input of each instruction has a single or multiple instructions passed in. From Figure 3B As can be seen, the parallelism between instructions is obvious. Instructions without dependencies can naturally run concurrently. For example, instructions 0, 1, and 2 run in parallel, and instructions 3 and 4 run in parallel. The graph computing architecture in this application only needs to check the ready and valid fields of each node's input to complete dependency checking in hardware. The graph computing tasks in this application do not require extensive hardware to check dependencies between registers.

[0106] See Figure 3C , Figure 3C A schematic diagram of a model of a graph computing task including multiple graph computing instructions provided by an embodiment of the present invention, Figure 3C A simplified hardware model of a graph computing task in a PE is shown. In this model, there are 8 graph computing instructions with instruction IDs of 0, 1, 2, 3, 4, 5, 6, and 7. In each beat, each graph computing instruction will detect its own valid bit and the ready bit of the operand to see if it is ready. The arbitration logic in the PE then sends one of the ready instructions to the Arithmetic and Logic Unit (ALU) for calculation. The operand after the instruction is sent sets the ready bit of the instruction to unset. After the instruction is calculated, the result of the calculation is written back to the input of the corresponding instruction, and the ready bit of the corresponding destination address is set. According to different main frequency requirements, the PE can be configured according to different timing requirements in this application. A PE101 can allow X input instructions to be selected and sent in one beat and calculated in parallel in X ALUs, where X is an integer greater than or equal to 1.

[0107] Based on the above, the graph computing device and related equipment provided in combination with the embodiments of the present invention are described below.

[0108] The graph computing device in this application or the processor containing the graph computing device is designed and implemented based on the above-mentioned graph computing architecture (Dataflow Architecture). Among them, the graph computing device can be a dedicated processor for graph computing, or it can be a functional unit for graph computing in a general-purpose processor. The graph computing device or the processor containing the graph computing device can be located in any electronic device, such as computers, computers, mobile phones, tablets and other types of devices. The graph computing device or the processor containing the graph computing device can specifically be a chip or chipset or a circuit board equipped with a chip or chipset, and the chip or chipset or the circuit board equipped with a chip or chipset can work under the necessary software drive. The following exemplifies several implementation methods of the graph computing device in this application in a processor.

[0109] See Figure 4A , Figure 4A It is a structural diagram of a processor provided by an embodiment of the present invention. The processor 10 can execute graph computing tasks. The processor 10 may only include the graph computing device 11 itself. Optionally, the processor 10 may also include other functional modules besides the graph computing device 11.

[0110] See Figure 4B , Figure 4B FIG1 is a schematic diagram of the structure of another processor provided by an embodiment of the present invention. The processor 10 may be a multi-core processor and may include at least one processor core 12 (e.g., a general-purpose processor core) and at least one graph computing device 11. The processor core 12 may be used to perform general-purpose computing tasks, while the graph computing device 11 may implement the function of executing graph computing tasks. Optionally, the processor core 12 and the graph computing device 11 may be coupled and communicated via a bus or other means to jointly complete the computing tasks of the processor 10.

[0111] See Figure 4C , Figure 4C This is a structural diagram of another processor provided by an embodiment of the present invention. The processor 10 may be a superscalar processor. The processor 10 may include at least one processor core 12 (such as a general-purpose processor core). The graph computing device 11 may serve as a functional execution unit (Function Unit) in the processor core 12, independently executing graph computing tasks in the execution pipeline stage of the processor 10, or concurrently executing graph computing tasks with other general-purpose computing units, thereby realizing the function of executing graph computing tasks in the same processor. That is, the graph computing device 102 can be integrated into the processor core 12 of the processor 10 and serve as one of the multiple execution units in the processor core 12, running in the execution pipeline stage.

[0112] It should be noted that Figures 4A-4CThe various functional modules within the processor can communicate with each other via a bus or other connection methods. The connection relationship shown in the figure does not limit the connection relationship between them. The various functional modules will be further described in subsequent embodiments and will not be described in detail here. It should also be noted that the essence of the graph computing task in this application can be the task of converting general operation code into a graph for operation.

[0113] It is understandable that Figures 4A-4C The structures of the processors in the embodiments of the present invention are only some exemplary implementations provided by the embodiments of the present invention. The structures of the processors in the embodiments of the present invention include but are not limited to the above implementations.

[0114] Based on the above, see Figure 4D , Figure 4D This is a structural diagram of another processor provided by an embodiment of the present invention. The processor 10 may be a superscalar processor. Figure 4C The architecture of the processor in the ,provides a more specific processor structure. Figure 4D The structure and function of the processor 10 in the embodiment of the present invention are described, and the process from compiling to executing the target program is described.

[0115] 1. Provide program source code written in a high-level language, for example, source code written by developers in various programming languages ​​(such as C language, JAVA, etc.).

[0116] 2. Based on the cost estimation model, determine which parts of the source code are suitable for general operation mode compilation and which parts are suitable for graph computing flow mode compilation, and then compile them into general operation object files or graph computing flow object files (both are binary) according to different compilation modes. For example, an application (APP) may have millions of instructions, and there are actually input-output relationships between multiple instructions. For example, if the input condition for the execution of one instruction is the output result of another instruction, then the two instructions can constitute the basic elements of graph computing (vertices and edges). Therefore, during the source program compilation stage, based on the cost estimation model, complex instruction sequences (such as instruction sequences with complex relationships, indirect jumps or interrupts) or instruction sequences that are only used once can be compiled using the general operation mode; while for instruction sequences suitable for repeated repetition, such as loops or repeatedly called functions (their relationships can be complex or simple, but they usually need to be executed repeatedly), graph computing flow mode compilation is used. Among them, the use of graph computing flow mode compilation means abstracting the logic involved in the code into a graph computing architecture, and converting all operations originally performed by the processor, such as checking, jumping, and prediction, into binary machine instructions under the graph computing architecture during the program compilation phase (i.e., through the graph computing flow mode compiler). Since the instructions under these graph computing architectures contain the relationship between the input and output of each instruction, when the graph computing device 11 (in the processor) Figure 4D The Graphflow Unit (GFU) can also be called the Graphflow Unit (GFU) in the actual operation, which can greatly reduce the logical judgment between instructions, greatly saving the overhead in the CPU core, with good performance and low power consumption.

[0117] 3. The compiled general operation object files and graph calculation flow object files are linked (linked) into a comprehensive program (executable file) through a linker. For example, the object file is a .o file, etc., and when the program is to be executed, it needs to be linked. In the linking process, the above object files (such as .o files) are mainly linked with the library to create an executable file. It is understandable that the compilation stages corresponding to the above 1, 2, and 3 can be completed on a device other than the device where the processor 10 is located (such as a server, compiler, etc.), can be pre-compiled on the device where the processor 10 is located, or can be executed or compiled on the device where the processor 10 is located, and no specific limitation is made here.

[0118] 4. After the above executable file is executed on the processor 10, the processor 10 will load the target program to be executed in the executable file (such as code segment, data segment, BSS segment or stack, etc.) into the memory unit 126 through a series of instruction loading, instruction prefetching, instruction predecoding and division prediction operations.

[0119] 5. The instruction fetch unit 121 can fetch the target program from the memory unit 126 in a manner of fetching one instruction at a time for multiple times, and each instruction enters the instruction decoding unit 122 for decoding from the instruction fetch unit 121 .

[0120] 6. The instruction decoding unit 122 will split and interpret the instructions to be executed according to a predetermined instruction format to further obtain micro-operation instructions, that is, the decoded instructions to be executed in this application, and send them to the instruction scheduling unit 123.

[0121] 7. After the instruction scheduling unit 123 receives the decoded instructions to be executed, it distributes them to various execution units (Execution Unit) for calculation according to the type of each instruction, for example, it schedules them to the general operation unit 124 or the graph computing device 11 for calculation. Since the graph computing device 11 is set in the processor core 12 of the processor 10, the instruction scheduling unit 123 can be directly connected and communicated with the graph computing device 11, thereby scheduling the identified graph computing control instructions directly to the graph computing device 11 without the need to communicate through other message channels or memory read and write methods, which greatly reduces the communication delay. In one possible implementation method, the general computing instructions and graph computing control instructions in this application can be identified by different identification bits (the identification bits can be added in the above-mentioned compilation stage), that is, different types of instructions can correspond to different instruction IDs, so that the instruction scheduling unit 123 can identify them according to the instruction ID.

[0122] 8. The graph computing device 11 receives and executes the graph computing control instructions, and further executes the graph computing task to obtain the execution result of the graph computing task. One or more general-purpose computing units 124 receive and execute the general-purpose computing instructions to obtain the execution result of the general-purpose computing task. Optionally, the graph computing device 11 and the general-purpose computing units 124 can execute instructions in parallel or serially, depending on the logical relationship between the instructions executed by these execution units in the target program. This is not specifically limited in this embodiment of the present invention.

[0123] 9、Finally, the graph computing device 11 and the general-purpose computing unit 124 can send the computing result to the result write-back unit 125, and the result write-back unit 125 can feed back part or all of the computing result to the instruction scheduling unit 123, for example, as a parameter in the instruction scheduled by the subsequent instruction scheduling unit 123. Alternatively, the first execution result or the second execution result can be directly written into the memory unit 126 or written into the memory unit 126 through the memory read-write unit 1013A, so that the relevant execution unit (such as the graph computing device 11 or the memory read-write unit 1013A) can obtain the required parameter from the corresponding storage location. Since the graph computing device 11 is arranged in the processor core 12 of the processor 10, the processor core 12 has the right and condition to obtain the relevant computing state of the graph computing device 11 and other general-purpose computing units 1013, and thus can control the synchronous or asynchronous operation between the graph computing device 11 and other general-purpose computing units 1013, thereby improving the operation efficiency of the processor.

[0124] In summary, the graph computing device 11 receives the liveIn data on the register sent from the instruction scheduling unit 123 (such as including the instruction launch and reservation station) and transmits the input to the corresponding computing node of the graph computing device 11. Similarly, the graph computing device 11 also writes the liveOut output data back to the result write-back unit 125 (such as including the register and the reorder buffer), so as to write the output of the graph into the corresponding register and the instruction reservation station depending on the output of the graph.

[0125] In the above-mentioned Figure 4D processor structure, the data flow architecture is combined into the processor of the control flow architecture, so that the data flow optimization can be performed on the hot loop iteration instruction, the hot instruction sequence, and the repeatedly executed instruction sequence in the general-purpose computing. The instruction fetch number and the dependency check of the hot instruction are significantly reduced, and the power consumption is greatly reduced. The data flow architecture also effectively increases the width of the CPU instruction window and improves the performance of the CPU.

[0126] Based on the above, the present application provides a graph computing device. Please refer to Figure 5A , Figure 5A is a structural schematic diagram of a graph computing device provided by an embodiment of the present application. The graph computing device 10 includes at least one processing engine 101 (PE), Figure 5A In the above-mentioned

[0127] Each processing engine 101 is used to execute a graph computing task, including all iterative computing tasks of the graph computing task. Multiple processing engines 101 can execute multiple graph computing tasks in this application in parallel. Among them, the graph computing task in this application can be considered as the directed graph composed of N nodes mentioned above, with each node serving as a graph computing instruction.

[0128] The routing unit 103 is used to forward the instructions when multiple processing engines 101 execute different graph computing tasks respectively and there is a dependency relationship between the instructions. The routing unit 102 (router) can then be used to perform corresponding forwarding and perform cooperative computing between different processing engines.

[0129] above Figure 5A This section shows a simplified hardware model of C (e.g., C=4) PEs combined into a cluster. PEs within a cluster can run concurrently, so one beat can run C*X instructions. When the destination of an instruction within a PE points to the input of an instruction in another PE, such as instruction 4 pointing to instruction 12, communication must occur via the output unit of the current PE through a crossbar. Assuming the cluster's crossbar is not congested, PEs within a cluster can write to the operand buffer of another PE within one beat.

[0130] From above Figure 5A As can be seen, different PEs in a cluster can execute C*X non-dependent instructions in each tick. Under ideal scheduling, the hardware shown above can achieve the performance of a superscalar processor with a peak IPC of C*X. Understandably, due to communication limitations, data transfers between PEs require a single tick of latency. To minimize this latency, the compiler's scheduling can pre-calculate graph computation instructions that require communication between different PEs as much as possible.

[0131] See Figure 5B , Figure 5B This is a schematic diagram of the structure of another graph computing device provided by an embodiment of the present invention. In the graph computing device (graph architecture), the degree of parallelism can be further improved by extending the number of clusters. Each cluster communicates through a router. According to the design of the bus, the communication delay and complexity between clusters will increase with the number of clusters R. Therefore, the compiler can schedule subgraphs with no dependencies to run on different clusters, avoiding the critical path running across clusters and avoiding the large-scale movement of excessive data.

[0132] If a graph consists of P nodes, then the ideal hardware required to execute this graph is that each node has an operation unit, and the results can be passed to the corresponding next-level operation unit in the next cycle through an ideal N-to-N crossbar. However, when P is very large, this NN crossbar is difficult to implement. Therefore, in the actual hardware design, this application defines that P instructions share X operation units / PEs (Process Engines). This is equivalent to selecting at most X instructions from P instructions in a PE per cycle (instructions that must be input as ready) to be operated simultaneously.

[0133] It should be noted that the above Figure 5A and Figure 5B In the provided graph computing device, the structure of each PE may be the same or different, and at least one PE has the structure and function of the PE provided in this application. This application does not specifically limit the structure and function of other PEs.

[0134] It is understandable that Figures 5A-5B The structures of the graph computing device are only some exemplary implementations provided by the embodiments of the present invention. The structures of the graph computing device in the embodiments of the present invention include but are not limited to the above implementations.

[0135] Based on the above, this application provides a graph computing device. Figure 6A , Figure 6A It is a structural diagram of a processing engine provided by an embodiment of the present invention, and the processing engine 101 is a specific structure of at least one processing engine PE in any of the above-mentioned graph computing devices. The graph computing device 11 includes at least one processing engine 101 ((Process Engine, PE), each PE101 in the at least one PE 101 includes M status buffers 1011 (respectively 1011-1, 1011-2, ..., 1011-M), an arbitration logic unit 1012 and X operation units (respectively 1013-1, 1013-2, ..., 1013-X). M is an integer greater than 1, and X is an integer greater than or equal to 1. It should be noted that the subsequent embodiments are mainly described based on one of the processing engines 101 in the at least one processing engine 101, and the subsequent description will not be repeated. Among them,

[0136] Each state buffer (operand buffer) 1011 in the M state buffers 1011 is used to store the state data of an iterative computing task; wherein, the iterative computing task is one of the N iterative computing tasks included in the graph computing task, and N is an integer greater than 1. Specifically, each state buffer 1011 is a storage area, which can be composed of a dedicated hardware register, or a memory can be used as a buffer. That is, the M state buffers can be a logical division or a hardware division, which is not specifically limited in the embodiment of the present invention. The graph computing task is a graph computing program that includes N iterative computing tasks. It is assumed that the graph computing task includes P graph computing instructions, and the graph computing task needs to be executed N times for the P graph computing instructions, and each iterative computing task needs to be calculated based on the relevant calculation results of the previous iterative computing task. The state data of an iterative computing task includes all input data used to perform the iterative computing task, for example, the left input, right input, conditional input, etc. of each graph computing instruction included therein. For example, state buffer 1011-1 is used to store the state data of the first iterative computing task of the graph computing task, state buffer 1011-2 is used to store the state data of the second iterative computing task of the graph computing task, state buffer 1011-3 is used to store the state data of the third iterative computing task of the graph computing task, and so on.

[0137] That is, in the present application, the status data of multiple iterative computing tasks of the graph computing task are stored separately in different status buffers, so that the operation states between the multiple iterative computing tasks can be independent of each other and do not interfere with each other. Therefore, the instructions in different iterative computing tasks can be run in parallel when the input data (such as left input, right input or conditional input) is ready. For example, if an instruction in a certain iterative computing task is blocked, it will not cause blocking interference to the related instructions in other iterative computing tasks. This avoids the technical defect in the prior art that the data of multiple iterative computing tasks are distinguished only by iteration tokens, and the iterative computing tasks with small tokens will back-pressure the iterative computing tasks with large tokens, which in turn causes iterations of different tokens to be unable to be executed completely in parallel.

[0138] The arbitration logic unit 1012 is configured to determine, based on the status data in the M status buffers, L graph calculation instructions to be executed in the current clock cycle, and distribute the L graph calculation instructions to the X operation units; wherein the L graph calculation instructions are instructions corresponding to T-iteration calculation tasks, and the N-iteration calculation tasks include the T-iteration calculation tasks; and L and T are both integers greater than or equal to 1 and less than or equal to X. Specifically, assuming that the graph calculation task includes P graph calculation instructions, since the M status buffers 1011 may store at most P*M graph calculation instructions when executing the graph calculation task in this application, multiple graph calculation instructions may be ready, that is, their input data has arrived. At this time, the arbitration logic unit 1012 determines which of the P*M graph calculation instructions have ready input data based on signals from the chip circuit direct connection lines between the M status buffers 1011 and the M status buffers 1011, thereby selecting the L graph calculation instructions to be executed in the next clock cycle. Among them, the L graph calculation instructions are respectively instructions in T iterative calculation tasks. In other words, multiple graph calculation instructions may be selected in one iterative task, or one graph calculation instruction may be selected. That is, for the N iterative calculation tasks of the graph calculation task, L instructions of the current specific execution conditions are selected and distributed to each operation unit 1013 in the graph calculation device 11 for calculation, so as to increase the parallelism between the iterative calculation tasks and improve the execution efficiency of the graph calculation tasks as much as possible. The value of L can be an integer greater than or equal to 1 and less than or equal to X, that is, the maximum value can be X, and the parallelism is X. If the instructions in the different iterative calculation tasks currently prepared are insufficient, it may also be less than X, that is, there may be a situation where the operation unit is idle in one or some clock cycles.

[0139] The arbitration logic unit 1012 can make a judgment based on the M status buffers and the direct connection lines between them and the chip circuits. For example, each area in each status buffer 1011 used to store the status data of a graph calculation instruction can instantly report to the arbitration logic unit 1012 via the connection line whether the current input data has arrived. For example, if there are a total of P*M (assuming P=8, M=4) = 32 lines, the signal sent by the M status buffers to the arbitration logic unit may be a signal such as 00101010001010110010101010101000, where 1 represents ready and 0 represents not ready. As a result, when the input data of any of the P*M graph calculation instructions is ready, the arbitration logic unit 1012 can immediately know and select the L graph calculation instructions for the next clock cycle based on this.

[0140] In one possible implementation, the graph calculation task includes P graph calculation instructions; the status data of one iterative calculation task includes the input data of the P graph calculation instructions in the corresponding iterative calculation task; the arbitration logic unit is specifically configured to: monitor whether the input data of the iterative calculation tasks corresponding to the P graph calculation instructions in the M state buffers are ready; select L graph calculation instructions corresponding to the earliest T iterative calculation tasks of the corresponding iterative calculation task from the graph calculation instructions whose input data are currently ready, wherein one or more graph calculation instructions may be selected in one iterative calculation task; and distribute the L graph calculation instructions from the instruction buffer to L of the X operation units, wherein one operation unit corresponds to one graph calculation instruction. Specifically, the arbitration logic unit monitors the status data currently stored in the M state buffers. When the input data of some graph calculation instructions in each state buffer are ready, the arbitration logic unit can select the L graph calculation instructions whose input data are ready from the M state buffers and send them to the operation units for execution in the current clock cycle. Among them, the principle of selection is to give priority to selecting from the prepared graph calculation instructions in the L iterative calculation tasks with earlier iterations, so as to ensure the overall execution efficiency of the graph calculation tasks. It should be noted that T and L can be equal or unequal, that is, one graph calculation instruction can be selected in one iterative calculation task, or multiple graph calculation instructions can be selected. That is, in each clock cycle, a maximum of X graph calculation instructions can be selected from the M iterative calculation tasks corresponding to the M state buffers, and respectively assigned to X operation units for calculation, that is, one operation unit corresponds to one graph calculation instruction in one clock cycle. Of course, it is understandable that when the number of graph calculation instructions prepared for the current input data is insufficient (that is, less than X), the graph calculation instructions of the iterative calculation tasks with a number less than X may be selected and assigned to T operation units, which is equivalent to having operation units in an idle state.

[0141] Each of the X operation units 1013 is used to execute the graph computing instructions assigned by the arbitration logic unit 1012. Each operation unit 1013 is responsible for executing the graph computing instructions assigned by the arbitration logic unit 1012, thereby achieving the technical feature of parallel computing tasks between multiple iterative computing tasks. Optionally, since different operation units 1013 can execute graph computing instructions in different iterative computing tasks, the parallelism of the execution of iterative computing tasks during the execution of the graph computing tasks can be guaranteed. Further optionally, the X operation units 1013 are operation units that perform the same computing function, that is, the X operation units 1013 have the same function. Therefore, when executing any graph computing instruction in the graph computing task, it can be arbitrarily assigned to any operation unit. It is understandable that in some cases, it is possible that because the prepared graph computing instructions are less than X, it is possible that some operation units 1013 do not receive the graph computing instructions assigned by the arbitration logic unit in one or several clock cycles.

[0142] In one possible implementation, the processing engine 101 further includes a write-back unit 1014; the X operation units 1013 are respectively connected to the write-back unit; and each of the X operation units is further configured to send a calculation result obtained by executing a graph calculation instruction to the write-back unit 1014. Specifically, any one of the processing engines 101 in the graph computing device 10 further includes a write-back unit 1014, which is respectively connected to the X operation units 1013 in the processor engine 101. When each of the X operation units 1013 completes executing a graph calculation instruction and obtains a corresponding calculation result, the calculation result can be sent to the write-back unit 1014, so that the write-back unit 1014 writes the calculation result back to the corresponding position in the corresponding state buffer 1011 according to the result address corresponding to the calculation result, thereby realizing the data dependency relationship between instructions within the iterative computing task of the graph computing task, as well as the data dependency relationship between different iterative computing tasks.

[0143] Based on the structure and function of the above-mentioned graph computing device, the graph computing tasks involved in this application and the iterative computing tasks included therein are further explained. Figure 6B , Figure 6BA schematic diagram of a cyclic directed graph and an acyclic graph provided for the present application. When a program requires less data, but more recursive operations (the calculation requires long-term recursive / iterative / convergent operations based on the input initial value), the data flow graph of the program can include cycle operations, that is, the data flows repeatedly in the cycle until the condition is met. The graph computing task in this application is a data flow graph based on the Graphflow computing model and containing a cycle. For example, the semantics of the cycle in the program can be reflected as the data transfer of induction / reduction variables; and the semantics of the control loop in the program are reflected as a loop or recursion. When the cycle is converted into a Graphflow graph, the data flow across iterations is reflected as a backflow (Back Edge / Across Edge).

[0144] In the data flow graph instruction set architecture (Graphflow ISA) in this application, it is necessary to distinguish between normal flow instructions (i.e., intra-iteration graph computation instructions in this application) and reflux instructions (i.e., cross-iteration graph computation instructions in this application). This will be further explained later and will not be described in detail here. After the Graphflow computation model extracts the reflux instructions separately, the remaining data flow graph can be transformed into a directed acyclic graph, which can be expanded and operated in parallel based on the reflux instructions. For example, see Figure 6C , Figure 6C A data flow diagram of a graph computing task provided by an embodiment of the present invention, Figure 6C The description of the 2D (two-dimensional) data flow graph corresponding to the graph computing task (also known as the graph computing program) is shown in FIG. That is, in the embodiment of the present invention, M state buffers can share this data flow graph (i.e., P instructions in the graph computing task). For the loop ( Figure 6C Assuming that the mul instruction → add instruction is a reflux instruction), the compiler can choose to mark an edge in the loop as a cross-iteration graph calculation instruction (MoveAcross instruction) during the compilation phase, so that Figure 6C The 2D circulation in the graph is transformed into a 3D spiral, wherein the cross-iteration graph calculation instructions will be further explained in subsequent embodiments and will not be described in detail here. Therefore, when the data flow passes through the Across instruction, it can jump to the corresponding iterative calculation task in the next state buffer through the corresponding bus. In an embodiment of the present invention, M state buffers 1011 can share a set of codes and do not need to become an ultra-large data flow graph, but can still complete the performance that can be achieved by a fully expanded data flow graph calculation, that is, to complete the parallel operation of program nodes in M ​​planes.

[0145] Because, in the traditional static data flow architecture, although the data flow graph with loops after the conversion from the loop can be correctly executed, for all nodes, one loop / multiple loops can only allow one iteration of operation through back pressure. In the Graphflow ISA in this application, the programmer / compiler needs to distinguish between normal flow instructions and reflux instructions in the data flow loop. After the reflux instructions are extracted separately by the graph computing device 11, the remaining data flow graph can be transformed into a directed acyclic graph DAG (such as Figure 6B (Remove the dotted arrows to form a directed acyclic graph) and parallelize it. In the graph computing device 11, each node can be abstracted into a computing unit 1013 that can support M different versions of input. This is equivalent to adding four concurrent threads to the current node to calculate the circulation of different loops. Without adding computing units, as long as any version of the input is ready, it can be calculated and the result will be emitted to the corresponding thread.

[0146] Based on the above analysis, it can be concluded that the performance improvement of traditional graph architectures and superscalar processors mainly relies on exploiting inter-instruction parallelism to improve performance through concurrent instructions. Typically, the inter-instruction parallelism of superscalar processors is scanned within the width of a reorder buffer (ROB), for example, a typical ROB of 192 entries. The inter-instruction parallelism of traditional graph architectures is scanned within the length of an instruction operand buffer (OOB), extracted using concurrent PEs. However, both architectures are subject to the inter-instruction parallelism determined by the logic of the original program. In addition to the two aforementioned parallelisms, this application also proposes a third dimension of parallelism: loop-level parallelism for loops. Based on inter-iteration parallelism, this application introduces cross-iteration dependencies, and implements cross-iteration dependencies using the same data flow + control flow concept of graph computing architecture. Therefore, after complying with cross-iteration dependencies, instructions from different iterations can be executed simultaneously. This application refers to the parallel method of transmitting the dependencies between iterations through the flow of graph computation by instructions of different iterations as DoAcross Parallelism.

[0147] In summary, the present application aims at the shortcomings of the traditional dynamic data flow architecture, and realizes the cross-iteration concurrent execution scheme of the graph computation after the overall design from the instruction set, the compiler and the processing architecture. If the instructions are repeated from the hardware perspective, and the compiler explicitly indicates the inter-iteration dependency of the iteration computation tasks in the graph computation task, then the iteration loop of the graph computation task can be hardware-unfolded through the state buffer.

[0148] In a possible implementation, referring to Figure 7A , Figure 7A is another structural schematic diagram of a processing engine provided by the embodiment of the present application, any one of the processing engines 101 in the graph computation device 10 can further include an instruction buffer 1014, assuming that the graph computation task includes P pieces of graph computation instructions; the instruction buffer 1014 is configured to store the P pieces of graph computation instructions, wherein the N times of iteration computation tasks share the P pieces of graph computation instructions. Optionally, based on the description of the format of the graph computation instruction in the above Figure 3A , the instruction buffer 1014 can be configured to store the instruction ID, the operation code (opcode) and the valid bit (Valid) flag of the graph computation instruction. Since the instruction content between the N times of iteration computation tasks of the graph computation task is actually the same, that is, the instruction ID, the operation code (opcode) and the valid bit (Valid) are the same, the M state buffers 1011 can share the P pieces of instructions of the graph computation task stored in the instruction buffer 1014, that is, the instruction buffer 1014 only needs to store a set of instructions, and does not need to store multiple copies like the state data.

[0149] For example, referring to Figure 7B , Figure 7B is a model schematic diagram corresponding to the graph computation task after the unfolding in the PE provided by the embodiment of the present application, the model is based on the above Figure 6A or Figure 7AThe provided DoAcross architecture processing engine (PE) increases the concurrency of graph computing tasks by expanding the storage of graph computing tasks in the state buffer (operand buffer) along the iteration dimension. Assuming P = 8, X = 4, and M = 4, that is, the graph computing task includes 8 graph computing instructions, the state buffer is expanded by 4 times, representing the storage expansion of the next four iterations of computing tasks. The state buffers of the four iterations of computing tasks share 4 operation units (such as ALUs). Specifically, the instruction IDs of the eight graph computing instructions included in the graph computing task are 0, 1, 2, 3, 4, 5, 6, and 7, respectively. The operation codes of the instructions are add, mul, add, cmp.ge, st, sll, pld, etc., respectively. The left inputs are 0l, 1l, 2l, 3l, 4l, 5l, 6l, and 7l, respectively. The right inputs are 0r, 1r, 2r, 3r, 4r, 5r, 6r, and 7r, respectively. The conditional inputs are 0p, 1p, 2p, 3p, 4p, 5p, 6p, and 7p, respectively. Each graph computing instruction also has three ready flags to indicate whether the left input, right input, or conditional input of the current graph computing instruction is ready, and three valid bits to indicate whether the left input, right input, and conditional input of the current graph computing instruction need to be monitored. Each plane represents an iterative computing task of the graph computing task, for example Figure 7B 3, 4, 5, and 6, respectively. The graph computation instructions that meet the execution conditions in these four iterative computation tasks are assigned to four arithmetic logic units (ALUs). Each clock cycle can generate the results of up to four graph computation instructions. Part of these results are then returned to an instruction in each iterative computation task as input data, either for the current iteration or the next, depending on the dependencies between the graph computation instructions.

[0150] Based on the structure and function of the above-mentioned graph computing device 11 and at least one of the processing engines 101 provided by this application, the P graph computing instructions included in the graph computing task can include graph computing instructions with multiple different functions, thereby completing different functions in the graph computing task. From the different perspectives of the functions of the instructions, the graph computing instructions provided by this application include at least intra-iteration graph computing instructions, cross-iteration graph computing instructions, iterative window moving instructions, and calculation termination instructions. The following is a detailed description of the characteristics and functions of the above-mentioned instructions:

[0151] In one possible implementation, the graph calculation instruction includes an intra-iterative graph calculation instruction; the intra-iterative graph calculation instruction carries a result address; the write-back unit is used to send the i-th iterative calculation result to the result address in the state buffer corresponding to the i-th iterative calculation task, wherein the value range of i is a positive integer less than or equal to N, and the i-th iterative calculation result is the result obtained by executing the intra-iterative graph calculation instruction in the i-th iterative calculation task among the N iterative calculation tasks. For example, in the instruction set, the intra-iterative graph calculation instruction in the embodiment of the present invention defines that the calculation result of the current iteration only needs to be passed to the instruction of the current iteration. For example, the intra-iterative graph calculation instruction is 1 add 21, which means that the result of instruction 1add only needs to be passed to instruction 2 in the current iterative calculation task.

[0152] In one possible implementation, the graph computation instruction includes a cross-iteration graph computation instruction, which carries a result address and a cross-iteration identifier; the write-back unit is configured to send the i-th iteration computation result to the result address in the state buffer corresponding to the i+1-th iteration computation task based on the cross-iteration identifier; wherein the value range of i is a positive integer less than or equal to N-1, and the i-th iteration computation result is the result obtained by executing the cross-iteration graph computation instruction in the i-th iteration computation task among the N iteration computation tasks. Specifically, in the instruction set, the cross-iteration graph computation instruction in the embodiment of the present invention (which may be referred to as Move Across or Across instruction) is an instruction that defines the calculation result of the current iteration and can be passed to the next iteration. Optionally, for the cross-iteration graph computation instruction, the embodiment of the present invention needs to add an Across(x) mark based on the original destination address. For example, the cross-iteration graph computation instruction is 1add 2lx, where x is the cross-iteration identifier. This cross-iteration graph computation instruction indicates that the result of instruction 1add needs to be passed to instruction 2 in the next iteration computation task. That is, the result of instruction 1 add can only be passed to instruction 2 of the current iteration, but through the cross-iteration identifier (that is, the special Across destination encoding) in the embodiment of the present invention, instruction 1 can pass the result of add to instruction 2 of the next dimension (dynamic version), so that the operation of two iterative computing tasks can be started at the same time. That is, by carrying a specific cross-iteration identifier in the instruction, the data relationship of cross-iteration dependency is realized. Through the instruction set provided by the embodiment of the present invention, the compiler can distinguish between intra-iteration dependencies and cross-iteration dependencies. In this way, a simple and effective way is provided for the hardware to maximize the use of the information provided by the compiler. Through the cross-iteration Move Across instruction, the data flow can start the data flow of the next Epoch through the current iterative computing task (Epoch). Through the above-mentioned Across instruction, PE can automatically unfold a planar data flow graph and make it 3D. The data flow not only flows within the current plane, but also flows to the subsequent plane. After each reflux through the Across mark (cross-iteration identifier) ​​( Figure 7Athe dynamic version number of the data (i.e. the iteration number) + 1. That is, the graph computing device 11 in the present application increases the version number based on the backflow instruction, and then the data dynamic version number in the form of Token passes the version number and data to the remaining sub-graphs. The hardware can expand the directed ring graph without a dynamic version number into a directed acyclic graph with a version number. After the graph computing device 11 expands the directed ring operation, the data derived from different versions of the ring can be operated in parallel in different threads. However, the dynamic version number Token is allocated by the hardware architecture and can be recycled, which is the same as the Reorder Buffer Entry ID in the superscalar processor, and is invisible to the outside.

[0153] Please refer to Figure 8A , Figure 8A A schematic diagram of the dependency relationship of an iterative computing task in a state buffer is provided for an embodiment of the present application, for example, state buffers 1011-1, 1011-2, 1011-3, 1011-4, each of which stores the state data of an iterative computing task. It is assumed that the graph computing task includes 11 instructions, which are instruction 1, instruction 2, instruction 3, instruction 4, instruction 5, instruction 6, instruction 7, instruction 8, instruction 9, instruction 10, and instruction 11. Then, all the instructions of the first iteration computing task of the graph computing task stored in the state buffer 1011-1 are marked as: 1_0, 2_0, 3_0, 4_0, 5_0, 6_0, 7_0, 8_0, 9_0, 10_0, and 11_0. Correspondingly, all the instructions of the second iteration computing task of the graph computing task stored in the state buffer 1011-2 are marked as: 1_1, 2_1, 3_1, 4_1, 5_1, 6_1, 7_1, 8_1, 9_1, 10_1, and 11_1; all the instructions of the third iteration computing task of the graph computing task stored in the state buffer 1011-3 are marked as: 1_2, 2_2, 3_2, 4_2, 5_2, 6_2, 7_2, 8_2, 9_2, 10_2, and 11_2; and all the instructions of the fourth iteration computing task of the graph computing task stored in the state buffer 1011-4 are marked as: 1_3, 2_3, 3_3, 4_3, 5_3, 6_3, 7_3, 8_3, 9_3, 10_3, and 11_3. Among them, 1_0 represents instruction 1 in the first iteration computing task, 2_0 represents instruction 2 in the first iteration computing task, and 3_0 represents instruction 3 in the first iteration computing task; 1_1 represents instruction 1 in the second iteration computing task, 2_1 represents instruction 2 in the second iteration computing task, and 3_1 represents instruction 3 in the second iteration computing task; and so on.

[0154] Specifically, each complete and repeated execution of the above 11 instructions is called an "iterative computing task", and part or all of the execution results of each iterative computing task will be used as the initial value of the next iterative computing task. It should be noted that the iterative computing tasks in this application will be referred to as (iteration, iter) in the following, that is, the first iterative computing task will be referred to as iter0, the second iterative computing task will be referred to as iter1, and so on, and will not be repeated in the following. Figure 8A For example, after executing instruction 1_0 in iter0, you can execute instruction 2_0 in iter0 and instruction 1_1 in iter1. That is, the execution result of instruction 1_0 here is not only the input of instruction 2 in the first iteration task, but also the input of instruction 1 in the next iteration task. Similarly, the execution result of instruction 1 in iter1 is not only the input of instruction 2 in iter1, but also the input of instruction 1 in iter2. The execution result of instruction 1 in iter1 is not only the input of instruction 2 in iter1, but also the input of instruction 1 in iter2, and so on. That is, in Figure 8A , the data flows pointed to by solid arrows correspond to intra-iteration graph computing instructions, and the data flows pointed to by dotted arrows correspond to cross-iteration graph computing instructions. For example, the dotted data flows pointed to by instructions 1, 5, and 9 in each iterative computing task all correspond to cross-iteration graph computing instructions, and the solid data flows pointed to by instructions 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10 in each iterative computing task all correspond to intra-iterative graph computing instructions. The dependency relationship of instruction 1 in each of the above-mentioned iterative computing tasks is also referred to and will not be repeated here.

[0155] Based on any of the graph computing devices 10 provided in this application, after the graph computing instruction 1_0 in the iterative computing task iter1 corresponding to the state buffer 1011-1 is assigned to a certain computing unit (such as 1013-1) among the X computing units 1013 through the arbitration logic unit 1012 for computation, the computing unit 1013-1 sends the computation result obtained by executing the graph computing instruction 1_0 to the write-back unit 1014. Since the graph computing instruction 1_0 (dashed line edge) is a cross-iteration graph computing instruction, the write-back unit 1014 needs to write the computation result of the instruction 1_0 back to the result address in the state buffer 1011-1 corresponding to iter1, that is, the address where the status data of the instruction 2_0 is stored. In the next clock cycle, after graph calculation instruction 2_0 in the iterative calculation task iter0 corresponding to status buffer 1011-1 is assigned to a certain operation unit (e.g., 1013-2) among the X operation units 1013 via arbitration logic unit 1012 for calculation, operation unit 1013-2 sends the calculation result obtained by executing graph calculation instruction 2_0 to write-back unit 1014. Since graph calculation instruction 2_0 is an intra-iteration graph calculation instruction, write-back unit 1014 needs to write the calculation result of instruction 2_0 back to the result address in status buffer 1011-1 corresponding to iter0, which is the address where the status data of instruction 3_0 and instruction 4_0 are stored.

[0156] See Figure 8B , Figure 8BA schematic diagram of an embodiment of the present invention provides a method for executing instructions in a graph computing task in multiple clock cycles by a certain operation unit. For 12 consecutive clock cycles Cycle0, Cycle1, Cycle2, Cycle3, Cycle4, Cycle5, Cycle6, Cycle7, Cycle8, Cycle9, Cycle10, and Cycle11, it is assumed that Cycle0, Cycle1, and Cycle2 execute instructions 1_0, 2_0, and load in Iter0; Cycle3, Cycle4, and Cycle5 execute instructions 1_1, 2_1, and load in Iter1; Cycle6 and Cycle7 execute instructions 4_0 and load in Iter0, respectively; Cycle8 executes instruction 1_2 in Iter2; Cycle9 and Cycle10 execute instruction 4_1 and load in Iter1, respectively; and Cycle11 executes instruction 6_0 in Iter0. In other words, any one of the X arithmetic units can execute any graph computation instruction in different iterative computation tasks, with ready input data, in different clock cycles. This also means that any arithmetic unit can execute any instruction in any iterative computation task in the M state buffers, with ready input data. Since all iterative computation tasks, except for dependent instructions, are completely independent and do not interfere with each other, they can be executed as long as the input data is ready, significantly improving parallelism.

[0157] The cross-iteration concurrent execution in the embodiments of the present invention can significantly improve the performance of traditional data flow architectures. This application addresses the problem of excessive bubbles caused by load misses and communication in traditional architectures, which can be filled by instructions in subsequent iterative computing tasks, thereby significantly improving the IPC index.

[0158] In one possible implementation, the write-back unit is specifically configured to: when the calculation results corresponding to multiple iterative calculation tasks need to be written back to the corresponding state buffers, give priority to writing the calculation results corresponding to the iterative calculation tasks with earlier iterations back to the state buffers corresponding to the iterative calculation tasks with earlier iterations. Specifically, when the calculation results corresponding to multiple iterative calculation tasks need to be written back to the corresponding state buffers, the write-back unit gives priority to writing the results of the iterative calculation tasks with earlier iterations back to the corresponding state buffers, so as to complete the iterative calculation tasks with earlier iterations as soon as possible, so as to start the new iterative calculation tasks as soon as possible, and thus complete the calculation of the N iterative calculation tasks of the graph calculation task as soon as possible. The reason is that since the graph calculation task contains N iterative calculation tasks, and usually the value of N is large and the value of X is small, it may take multiple rounds to complete the execution of the N iterative calculation tasks of the graph calculation task. Between the replacement of the state data of multiple iterative calculation tasks, the earlier iterative calculation tasks need to be calculated and the corresponding state data cleared before the data loading of the new iterative calculation task can be started. That is, if the calculation results of the iterative calculation tasks with earlier iterations are written back first, the iterative calculation tasks with earlier iterations can be completed and cleared faster, so that the new iterative calculation tasks can be loaded into the state buffer as soon as possible, thereby improving the overall computing efficiency.

[0159] In one possible implementation, the graph computation instructions include iterative window movement instructions; each state buffer is further configured to: when the graph computation instructions in the jth iterative computation task have been computed, clear the state data in the state buffer corresponding to the jth iterative computation task according to the iterative window movement instruction, and load the state data of the j+Mth computation task into the cleared state buffer; wherein the jth iterative computation task is the earliest iterative computation task among the currently corresponding iterative computation tasks in the M state buffers. Due to the storage capacity limitations of the graph computing device 10, it cannot be expanded indefinitely. Therefore, an embodiment of the invention automatically constructs a window in the iterative direction of the graph computing architecture based on the hardware capacity of the graph computing device, so that all nodes within the window can run concurrently. When the execution of the first iterative computation task (epoch) in the window is completed, the window can be moved to start the next epoch. Optionally, each iterative computation task in this application corresponds to a token, and the oldest iteration is marked. When the oldest iterative computation task is completed, the token is transferred to the next adjacent iteration. For example, when the status data of the first iterative computing task, the second iterative computing task, the third iterative computing task and the fourth iterative computing task are respectively stored in M ​​status buffers (assuming M=4), then after the execution of the first iterative computing task of the Oldest is completed, the tag of the Oldest can be transferred to the next adjacent second iterative computing task, that is, the second iterative computing task becomes the earliest (Oldest). In the selection logic of L graph computing instructions, the present application can give priority to the graph computing instructions in the Oldest iteration, and arrange the selection priority according to the newness of the iteration. For each PE, if there is no operation that can be executed in the current iteration, then it can execute the operation of the next iteration. This is equivalent to the PE in the graph computing device in the present application using the instructions that need to be calculated in the next iteration to fill the bubble in the current iteration, which can effectively improve the current calculation.

[0160] For example, Figure 9A and Figure 9B As shown, Figure 9A A schematic diagram of an iterative window provided by an embodiment of the present invention, Figure 9B A schematic diagram of an iterative window after movement provided by an embodiment of the present invention. Figure 9A and Figure 9B The embodiment of the present invention shows a solution for completing multiple or even infinite software states by iterative window movement using M state buffers (assuming M=4) provided by the graph computing device. Figure 9AThe arrows shown in are Across data flow channels. Each state buffer can be considered as a loop iteration, that is, it stores the state data of an iterative computing task of the graph computing task. Assuming that the graph computing task in this application has 10,000 loop iterations (i.e., iterative computing tasks), then the graph computing device 11 in this application can provide parallel computing of M=4 iterations. Assuming that the current state buffer 1011-1 stores the state data in the j-th iterative computing task (assuming it is Iter1), the state buffer 1011-2 stores the state data of the j+1-th iterative computing task (Iter2), the state buffer 1011-3 stores the state data of the j+2-th iterative computing task (Iter3), and the state buffer 1011-4 stores the state data of the j+3-th iterative computing task (Iter4); as shown in FIG. Figure 9B As shown, when the graph calculation instructions in the j-th iterative calculation task have been calculated, the iterative window moves backward, and the state data of the j+4-th calculation task (Ite5) can be loaded into the cleared state buffer 1011-1, that is, the state data of the sixth iterative calculation task Ite5 can flow in. Among them, the four state buffers in the gray part framed by the iterative window represent the iterative calculation tasks that have been loaded into the M state buffers in the graph calculation device 11, and the other white parts that are not framed are iterative calculation tasks that have been calculated or iterative calculation tasks waiting to be loaded. The window moves backward, specifically, first clearing the state data in the iterative calculation task (Iter1) corresponding to the state buffer 1011-1, and then loading the state data of the j+M-th calculation task (Iter5) into the cleared state buffer.

[0161] In one possible implementation, the write-back unit is further configured to: prohibit the computation result of the (j+M-1)th iterative computation task from being sent to the state buffer corresponding to the (j+M)th iterative computation task before the state data of the j+Mth iterative computation task is loaded into the cleared state buffer; and allow the computation result of the (j+M-1)th iterative computation task to be sent to the state buffer corresponding to the (j+M)th iterative computation task after the state data of the j+Mth iterative computation task is loaded into the cleared state buffer. Specifically, because the number of state buffers M is limited, if the M iterative computation tasks corresponding to the M state buffers have not yet completed computation, there is no space to load the state data of the new iterative computation task. Therefore, it is necessary to wait until at least one of the M iterative computation tasks in the current round has completed before the latest uncomputed iterative computation task can be loaded. Furthermore, in this embodiment of the present invention, each repeated execution of a graph computation task is referred to as an "iteration," and the result obtained from each iterative computation task is used as the initial value for the next iterative computation task. That is, there is a direct data dependency between two consecutive iterative computing tasks. Therefore, according to the correlation between iterations, in an embodiment of the present invention, only after the oldest iterative computing task is completed, the state data of the latest iterative computing task that has not yet been calculated is loaded in, so as to ensure that the M iterative computing tasks currently in the M state buffers are always continuous, avoiding the computing disorder caused by the inability of the instruction window to move based on the oldest state buffer due to the discontinuity between the M parallel iterative tasks, thereby improving the overall computing efficiency of the graph computing task.

[0162] For example, Figure 9C As shown, Figure 9C A schematic diagram of a cyclic execution of an iterative computing task provided by an embodiment of the present invention. In order to ensure that the window moves as quickly as possible to improve performance, the arbitration logic unit 1012 will give priority to the operation of the front Epoch to move the window. In the instruction set, this application designs an iterative window movement instruction (which can be named itad instruction) and uses hardware to move the window backward. Only the Epoch with the Oldest can execute the itad instruction and ensure that all instructions of the current Epoch are executed. In this way, it can be ensured that each iterative computing task is submitted (committed) to its own storage buffer (store buffer) in order to ensure the correctness of the program. Figure 9D As shown, Figure 9DA schematic diagram of establishing a new iterative computing task provided by an embodiment of the present invention. After the Itad instruction is executed, the label of the current Epoch is converted from Oldest to Youngest and the next adjacent Epoch is marked as Oldest. The Youngest Epoch will not be selected when executing the Move Across instruction, thus ensuring that the instructions in the window will not transfer data to the subsequent Epochs. Figure 9D As shown, it can be launched only after the current OldestEpoch instruction is executed and it is no longer Youngest.

[0163] In one possible implementation, the graph calculation instruction includes a calculation termination instruction; each state buffer is further configured to, upon completion of the Nth iterative calculation task in the N iterative calculation tasks, clear the state data of the iterative calculation tasks exceeding the Nth iterative calculation task according to the calculation termination instruction, and exit the loop. For example, exiting the loop may involve the write-back unit 1014 transmitting the calculation result to the result write-back unit 125 of the CPU, entering the reorder buffer and writing it into the CPU register. After the output is complete, all state buffers are cleared. In this embodiment of the present invention, when the Nth iterative calculation task is calculated, if no instruction to terminate the calculation is received, the loop iterative calculation task may continue to execute, i.e., the expected number of iterations may be exceeded, resulting in an instruction execution overflow effect. Therefore, in this embodiment of the present invention, the calculation termination instruction is used to instruct the graph calculation task to terminate the calculation while also clearing the relevant data of the overflowed iterative calculation task, thereby avoiding the problem of incorrect calculation results caused by the overflow effect of the iterative calculation task execution.

[0164] like Figure 9E As shown, Figure 9E A schematic diagram of preventing further iterative computing tasks from being submitted is provided for an embodiment of the present invention. When the loop is executed to the last iteration, it is possible that future Epochs will also be expanded. The embodiment of the present invention assumes that before the oldest Epoch has completed executing the itad instruction, the other subsequent Epochs are speculatively executed. In this way, when the last iteration is reached, the last iteration does not execute the itad instruction, but executes the calculation termination instruction that jumps out of the loop (which may be referred to as the fni instruction in this application). Therefore, iterations that exceed the execution range need to be cleared, including the storage buffer (store buffer) of future iterative computing tasks (Epoch). If some instructions of the future Epoch (such as the load instruction) fail, the memory read and write error (memory fault) will be ignored and will not affect the execution of the entire graph computing device. If the load instruction of the current Oldest Epoch fails, it means that the original program has an error.

[0165] See Figure 10 , Figure 10 This is a flow chart of a processing method provided by an embodiment of the present invention, which is applied to a graph computing device, which includes at least one processing engine PE, each of the at least one PE includes M state buffers, an arbitration logic unit and X operation units; M is an integer greater than 1, and X is an integer greater than or equal to 1; each state buffer of the M state buffers stores state data of an iterative computing task; wherein the iterative computing task is one of the N iterative computing tasks included in the graph computing task, and N is an integer greater than 1; and the processing method is applicable to the above Figures 1-3C Any one of the graph computing devices and devices containing the graph computing device (such as mobile phones, computers, servers, etc.). The method may include the following steps S201-S202, wherein,

[0166] Step S201: Based on the status data in the M status buffers, determine, through the arbitration logic unit, L graph calculation instructions to be executed in the current clock cycle, and distribute the L graph calculation instructions to the X operation units; wherein the L graph calculation instructions are instructions corresponding to T iterative calculation tasks, and the N iterative calculation tasks include the T iterative calculation tasks; L and T are both integers greater than or equal to 1 and less than or equal to X.

[0167] Step S201: executing the graph computing instructions assigned by the arbitration logic unit through the X computing units.

[0168] In a possible implementation, the graph calculation task includes P graph calculation instructions; the device further includes an instruction buffer; the instruction buffer stores the P graph calculation instructions, wherein the N iterative calculation tasks share the P graph calculation instructions.

[0169] In one possible implementation, the graph calculation task includes P graph calculation instructions; the status data of one iterative calculation task includes input data of the P graph calculation instructions in the corresponding iterative calculation task; the determining, based on the status data in the M status buffers, L graph calculation instructions to be executed in the current clock cycle by the arbitration logic unit, and distributing the L graph calculation instructions to the X operation units includes: monitoring, by the arbitration logic unit, whether the input data of the iterative calculation tasks corresponding to the P graph calculation instructions in the M status buffers are ready; selecting, from the graph calculation instructions whose current input data are ready, L graph calculation instructions corresponding to the earliest T iterative calculation tasks of the corresponding iterative calculation task, wherein one or more graph calculation instructions are selected in one iterative calculation task; and distributing the L graph calculation instructions from the instruction buffer to L of the X operation units, wherein one operation unit corresponds to one graph calculation instruction.

[0170] In one possible implementation, the processing engine further includes a write-back unit; the X operation units are respectively connected to the write-back units; and the method further includes: sending calculation results obtained by executing graph calculation instructions through the X operation units to the write-back unit.

[0171] In one possible implementation, the graph calculation instruction includes an iterative intra-graph calculation instruction; the iterative intra-graph calculation instruction carries a result address; the method further includes: sending the i-th iterative calculation result to the result address in the status buffer corresponding to the i-th iterative calculation task through the write-back unit, wherein the value range of i is a positive integer less than or equal to N, and the i-th iterative calculation result is the result obtained by executing the iterative intra-graph calculation instruction in the i-th iterative calculation task in the N iterative calculation tasks.

[0172] In one possible implementation, the graph calculation instruction includes a cross-iteration graph calculation instruction, which carries a result address and a cross-iteration identifier; the method also includes: according to the cross-iteration identifier, sending the i-th iteration calculation result to the result address in the status buffer corresponding to the i+1-th iteration calculation task through the write-back unit; wherein the value range of i is a positive integer less than or equal to N-1, and the i-th iteration calculation result is the result obtained by executing the cross-iteration graph calculation instruction in the i-th iteration calculation task in the N-iteration calculation tasks.

[0173] In one possible implementation, when the calculation results corresponding to multiple iterative calculation tasks need to be written back to the corresponding status buffers, the write-back unit preferentially writes the calculation results corresponding to the iterative calculation tasks with earlier iterations back to the status buffers corresponding to the iterative calculation tasks with earlier iterations.

[0174] In a possible implementation, the graph calculation instruction includes an iterative window movement instruction; and the method further includes:

[0175] When the graph calculation instructions in the j-th iterative calculation task have been calculated, according to the iterative window movement instruction, the state data in the state buffer corresponding to the j-th iterative calculation task is cleared through the M state buffers, and the state data of the j+M-th calculation task is loaded into the cleared state buffer; wherein, the j-th iterative calculation task is the earliest iterative calculation task among the iterative calculation tasks currently corresponding to the M state buffers.

[0176] In one possible implementation, the method further includes: before the status data of the j+Mth computing task is loaded into the cleared status buffer, prohibiting the calculation result of the (j+M-1)th iterative computing task from being sent to the status buffer corresponding to the (j+M)th iterative computing task through the write-back unit; after the status data of the j+Mth computing task is loaded into the cleared status buffer, allowing the calculation result of the (j+M-1)th iterative computing task to be sent to the status buffer corresponding to the (j+M)th iterative computing task through the write-back unit.

[0177] In one possible implementation, the graph calculation instruction includes a calculation termination instruction; the method also includes: when the Nth iterative calculation task in the N iterative calculation tasks is completed, according to the calculation termination instruction, the M state buffers will clear the state data of the iterative calculation tasks that exceed the Nth iterative calculation task and jump out of the loop.

[0178] It should be noted that the specific process of the processing method described in the embodiment of the present invention can be found in the above Figures 1-9D The relevant descriptions in the embodiments of the invention described in will not be repeated here.

[0179] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium may store a program, and when the program is executed by a processor, the processor may execute part or all of the steps of any one of the above method embodiments.

[0180] An embodiment of the present invention further provides a computer program, which includes instructions. When the computer program is executed by a multi-core processor, the processor can execute part or all of the steps of any one of the above method embodiments.

[0181] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0182] It should be noted that for the aforementioned method embodiments, for simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0183] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0184] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0185] In addition, the functional units in the embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0186] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device) to execute all or part of the steps of the above-mentioned methods of each embodiment of the present application. Among them, the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviated: ROM) or random access memory (Random Access Memory, abbreviated: RAM) and other media that can store program codes.

[0187] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A graph computing device, characterized in that: The graph computing device includes at least one processing engine PE, each of the at least one PE includes M state buffers, an arbitration logic unit and X operation units; the device also includes an instruction buffer; M is an integer greater than 1, and X is an integer greater than or equal to 1; wherein, Each of the M state buffers is used to store state data of one iterative computing task; wherein the one iterative computing task is one of the N iterative computing tasks included in the graph computing task, where N is an integer greater than 1; The arbitration logic unit is configured to determine, based on the status data in the M status buffers, L graph calculation instructions to be executed in the current clock cycle, and distribute the L graph calculation instructions to the X operation units; wherein the L graph calculation instructions are instructions corresponding to T iterative calculation tasks, and the N iterative calculation tasks include the T iterative calculation tasks; L and T are both integers greater than or equal to 1 and less than or equal to X; Each of the X operation units is configured to execute the graph computing instruction assigned by the arbitration logic unit; The graph calculation task includes P graph calculation instructions; the instruction buffer is used to store the P graph calculation instructions; The state data of one iterative computing task includes input data of the P-bar graph computing instructions in the corresponding iterative computing task; the arbitration logic unit is specifically configured to: Monitoring whether input data in iterative calculation tasks corresponding to the P graph calculation instructions in the M status buffers are ready; From the graph computing instructions prepared for the current input data, select L graph computing instructions corresponding to the earliest T iterative computing tasks of the corresponding iterative computing task, wherein one or more graph computing instructions are selected in one iterative computing task; The L graph calculation instructions are distributed from the instruction buffer to L operation units among the X operation units, wherein one operation unit corresponds to one graph calculation instruction.

2. The device according to claim 1, characterized in that The N iterative computing tasks share the P graph computing instructions.

3. The device according to claim 1 or 2, characterized in that The processing engine further includes a write-back unit; the X computing units are respectively connected to the write-back units; Each of the X operation units is further configured to send a calculation result obtained by executing the graph calculation instruction to the write-back unit.

4. The device according to claim 3, characterized in that The graph calculation instruction includes an iterative intra-graph calculation instruction; the iterative intra-graph calculation instruction carries a result address; The write-back unit is used to send the i-th iterative calculation result to the result address in the status buffer corresponding to the i-th iterative calculation task, where the value range of i is a positive integer less than or equal to N, and the i-th iterative calculation result is the result obtained by executing the iterative intra-graph calculation instruction in the i-th iterative calculation task in the N iterative calculation tasks.

5. The device according to claim 3, characterized in that The graph calculation instruction includes a cross-iteration graph calculation instruction, and the cross-iteration graph calculation instruction carries a result address and a cross-iteration identifier; The write-back unit is used to send the i-th iteration calculation result to the result address in the status buffer corresponding to the i+1-th iteration calculation task according to the cross-iteration identifier; wherein the value range of i is a positive integer less than or equal to N-1, and the i-th iteration calculation result is the result obtained by executing the cross-iteration graph calculation instruction in the i-th iteration calculation task in the N-iteration calculation tasks.

6. The device according to claim 4 or 5, characterized in that The write-back unit is specifically configured to: When the calculation results corresponding to multiple iterative calculation tasks need to be written back to the corresponding state buffers, the calculation results corresponding to the iterative calculation tasks with earlier iterations are preferentially written back to the state buffers corresponding to the iterative calculation tasks with earlier iterations.

7. The device according to claim 3, characterized in that The graph computing instruction includes an iterative window moving instruction; each state buffer is further configured to: When the graph calculation instructions in the j-th iterative calculation task have been calculated, the state data in the state buffer corresponding to the j-th iterative calculation task is cleared according to the iterative window movement instruction, and the state data of the j+M-th calculation task is loaded into the cleared state buffer; wherein, the j-th iterative calculation task is the earliest iterative calculation task among the iterative calculation tasks currently corresponding to the M state buffers.

8. The device according to claim 7, characterized in that The write-back unit is further configured to: Before the state data of the j+Mth computing task is loaded into the cleared state buffer, the calculation result of the (j+M-1)th iterative computing task is prohibited from being sent to the state buffer corresponding to the (j+M)th iterative computing task; After the state data of the j+Mth computation task is loaded into the cleared state buffer, the computation result of the (j+M-1)th iterative computation task is allowed to be sent to the state buffer corresponding to the (j+M)th iterative computation task.

9. The device according to claim 7 or 8, characterized in that The graph calculation instructions include calculation termination instructions; Each state buffer is further used to clear the state data of the iterative computing tasks exceeding the Nth iterative computing task and exit the loop according to the calculation termination instruction when the Nth iterative computing task among the N iterative computing tasks is completed.

10. A processing method, characterized in that: Applied to a graph computing device, the graph computing device includes at least one processing engine (PE), each of the at least one PE includes M state buffers, an arbitration logic unit, and X operation units; the device also includes an instruction buffer; M is an integer greater than 1, and X is an integer greater than or equal to 1; each of the M state buffers stores state data of an iterative computing task; wherein the iterative computing task is one of N iterative computing tasks included in the graph computing task, and N is an integer greater than 1; the method includes: Based on the status data in the M status buffers, the arbitration logic unit determines L graph calculation instructions to be executed in the current clock cycle, and distributes the L graph calculation instructions to the X operation units; wherein the L graph calculation instructions are instructions corresponding to T iterative calculation tasks, and the N iterative calculation tasks include the T iterative calculation tasks; L and T are both integers greater than or equal to 1 and less than or equal to X; Executing the graph computing instructions assigned by the arbitration logic unit through the X computing units; The graph calculation task includes P graph calculation instructions; the instruction buffer stores the P graph calculation instructions; The state data of one iterative computing task includes input data of the P graph computing instructions in the corresponding iterative computing task; The method of determining, based on the status data in the M status buffers, L graph calculation instructions to be executed in the current clock cycle by the arbitration logic unit, and distributing the L graph calculation instructions to the X operation units includes: The arbitration logic unit monitors whether the input data of the iterative computing tasks corresponding to the P graph computing instructions in the M status buffers are ready; selects L graph computing instructions corresponding to the earliest T iterative computing tasks of the corresponding iterative computing tasks from the graph computing instructions whose current input data are ready, wherein one or more graph computing instructions are selected in one iterative computing task; and distributes the L graph computing instructions from the instruction buffer to L computing units among the X computing units, wherein one computing unit corresponds to one graph computing instruction.

11. The method according to claim 10, characterized in that The N iterative computing tasks share the P graph computing instructions.

12. The method according to claim 10 or 11, characterized in that The processing engine further includes a write-back unit; the X computing units are respectively connected to the write-back unit; and the method further includes: The calculation results obtained by executing the graph calculation instructions are sent to the write-back unit through the X operation units.

13. The method according to claim 12, characterized in that The graph calculation instruction includes an iterative intra-graph calculation instruction; the iterative intra-graph calculation instruction carries a result address; and the method further includes: The i-th iterative calculation result is sent to the result address in the status buffer corresponding to the i-th iterative calculation task through the write-back unit, where the value range of i is a positive integer less than or equal to N, and the i-th iterative calculation result is the result obtained by executing the iterative intra-graph calculation instruction in the i-th iterative calculation task in the N iterative calculation tasks.

14. The method according to claim 12, characterized in that The graph calculation instruction includes a cross-iteration graph calculation instruction, and the cross-iteration graph calculation instruction carries a result address and a cross-iteration identifier; the method further includes: According to the cross-iteration identifier, the i-th iteration calculation result is sent to the result address in the status buffer corresponding to the i+1-th iteration calculation task through the write-back unit; wherein the value range of i is a positive integer less than or equal to N-1, and the i-th iteration calculation result is the result obtained by executing the cross-iteration graph calculation instruction in the i-th iteration calculation task in the N-iteration calculation tasks.

15. The method according to claim 13 or 14, characterized in that When the calculation results corresponding to multiple iterative calculation tasks need to be written back to the corresponding status buffers, the write-back unit preferentially writes the calculation results corresponding to the iterative calculation tasks with earlier iterations back to the status buffers corresponding to the iterative calculation tasks with earlier iterations.

16. The method according to claim 12, characterized in that The graph calculation instruction includes an iterative window movement instruction; the method further includes: When the graph calculation instructions in the j-th iterative calculation task have been calculated, according to the iterative window movement instruction, the state data in the state buffer corresponding to the j-th iterative calculation task is cleared through the M state buffers, and the state data of the j+M-th calculation task is loaded into the cleared state buffer; wherein, the j-th iterative calculation task is the earliest iterative calculation task among the iterative calculation tasks currently corresponding to the M state buffers.

17. The method according to claim 16, characterized in that The method further comprises: Before the state data of the j+Mth computing task is loaded into the cleared state buffer, the writing back unit is prohibited from sending the calculation result of the (j+M-1)th iterative computing task to the state buffer corresponding to the (j+M)th iterative computing task; After the state data of the j+Mth computing task is loaded into the cleared state buffer, the write-back unit allows the calculation result of the (j+M-1)th iterative computing task to be sent to the state buffer corresponding to the (j+M)th iterative computing task.

18. The method according to claim 16 or 17, characterized in that The graph calculation instruction includes a calculation termination instruction; the method further includes: When the Nth iterative computing task in the N iterative computing tasks is completed, according to the calculation termination instruction, the M status buffers clear the status data of the iterative computing tasks exceeding the Nth iterative computing task and jump out of the loop.

19. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the method according to any one of claims 10 to 18.

20. A computer program, characterized in that The computer-readable program comprises instructions, which, when executed by a processor, cause the processor to perform the method according to any one of claims 10 to 18.

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