A power semiconductor junction temperature calibration circuit, a calibration method and a short circuit protection method

Abstract

The application discloses a kind of power semiconductor junction temperature calibration circuit, calibration method and short-circuit protection method, circuit includes: power semiconductor, power input end, pulse input end and sampling circuit;The source of the power semiconductor includes first source and second source;First source and the gate of the power semiconductor are accessed to the pulse input end;Second source is provided with parasitic inductance, and is accessed to the power input end;The drain of power semiconductor is accessed to the power input end;The two ends of sampling circuit are respectively connected with the two ends of the parasitic inductance.This application is not limited to the scheme of module package, and the corresponding relationship between the voltage collected and the junction temperature inside the device is used to calibrate the junction temperature, compared with existing thermal imager and thermistor, the circuit of the application is convenient, safe and simple, and the steps are easy to operate, and the problem of low accuracy of existing junction temperature calibration is avoided by the thermosensitive characteristics of power semiconductor itself.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor technology, and in particular to a power semiconductor junction temperature calibration circuit, calibration method, and short-circuit protection method. Background Technology

[0002] The junction temperature of power semiconductors is a limitation on their performance. In the main drive system of new energy vehicles, the over-temperature warning and protection strategy of power modules is a very important protection measure.

[0003] Currently, existing junction temperature calibration schemes include the black module thermal imaging scheme and the thermal resistance network model prediction scheme. The black module thermal imaging scheme can directly measure the junction temperature using a thermal imager, but it requires special processing modules and driver boards, and is limited to module packaging schemes that can be opened. Furthermore, it can damage the power module, and the specially processed heat dissipation path cannot completely simulate heat dissipation from the top, resulting in low versatility. The thermal resistance network model prediction scheme can directly measure the resistance value of the thermistors on the ceramic copper-clad laminate (DBC copper substrate), calibrate the thermal resistance using a thermal resistance network, and indirectly calibrate the junction temperature based on power loss. However, it suffers from complex thermal resistance calibration and low accuracy.

[0004] Therefore, there is an urgent need for a power semiconductor junction temperature calibration circuit that can be used without thermal imagers and thermal resistance calibration. Summary of the Invention

[0005] This invention provides a power semiconductor junction temperature calibration circuit, calibration method, and short-circuit protection method to solve the technical problems in the prior art that result in low versatility, complex thermal resistance calibration, and low accuracy.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a power semiconductor junction temperature calibration circuit, comprising: a power semiconductor, a power input terminal, a pulse input terminal, and a sampling circuit;

[0007] The power semiconductor has a source including a first source and a second source; the first source and the gate of the power semiconductor are connected to the pulse input terminal; the second source is provided with a parasitic inductance and is connected to the power input terminal; the drain of the power semiconductor is connected to the power input terminal.

[0008] The two ends of the sampling circuit are respectively connected to the two ends of the parasitic inductor.

[0009] As a preferred embodiment, an active resistor is provided between the parasitic inductance and the power input terminal; a gate resistor is provided between the gate and the pulse input terminal.

[0010] As a preferred embodiment, the sampling circuit includes: an optocoupler, an operational amplifier, and a digital signal processing module;

[0011] The first input terminal of the optocoupler is connected to one end of the parasitic inductor, and the first output terminal of the optocoupler is connected to the other end of the parasitic inductor.

[0012] The second and third output terminals of the optocoupler are respectively connected to the first and second input terminals of the operational amplifier.

[0013] The output of the operational amplifier is connected to the digital signal processing module.

[0014] As a preferred embodiment, a positive resistor is further connected between the first input terminal of the operational amplifier and the second output terminal of the optocoupler, and a negative resistor is further connected between the second input terminal of the operational amplifier and the third output terminal of the optocoupler; the resistance values ​​of the positive resistor and the negative resistor are equal.

[0015] An amplification resistor is also connected between the second input terminal and the output terminal of the operational amplifier;

[0016] The amplification factor of the operational amplifier is the ratio between the amplification resistor and the negative terminal resistor.

[0017] As a preferred embodiment, the power semiconductor is a field-effect transistor.

[0018] Accordingly, the present invention also provides a power semiconductor junction temperature calibration method, implemented by the power semiconductor junction temperature calibration circuit described in any one of the above claims, comprising:

[0019] According to the preset temperature calibration range, the ambient temperature around the power semiconductor is set sequentially;

[0020] After setting an ambient temperature, a single pulse signal is input to the pulse input terminal, and the sampling voltage of the parasitic inductance at the current ambient temperature is collected through the sampling circuit.

[0021] Once a corresponding sampling voltage has been collected for each ambient temperature within the preset temperature calibration range, the curve relationship between the sampling voltage and the ambient temperature is obtained, thereby completing the junction temperature calibration of the power semiconductor.

[0022] As a preferred embodiment, before inputting the single-pulse signal to the pulse input terminal, the method further includes:

[0023] Set the voltage at the power input terminal and set the resistance value of the source resistor so that the current after the source and drain of the power semiconductor are turned on is within a preset range.

[0024] The current after the source and drain of the power semiconductor are turned on is as follows: I dU is the current after the source and drain of the power semiconductor are turned on. DC R1 is the voltage at the power input terminal, and R1 is the resistance value of the source resistor.

[0025] As a preferred embodiment, the present invention further includes:

[0026] The real-time sampling voltage of the parasitic inductance is acquired through the sampling circuit.

[0027] Based on the curve relationship between the sampling voltage and the ambient temperature, the real-time ambient temperature corresponding to the real-time sampling voltage is obtained, and thus used as the junction temperature of the current power semiconductor.

[0028] Accordingly, the present invention also provides a power semiconductor short-circuit protection method, implemented by the power semiconductor junction temperature calibration circuit described in any one of the preceding claims, comprising:

[0029] The sampling circuit collects the sampling voltage of the parasitic inductance in real time at the current ambient temperature.

[0030] Determine the difference between the sampled voltage and the preset voltage value;

[0031] When the difference exceeds a preset value, the power semiconductor enters a short-circuit protection state.

[0032] As a preferred embodiment, the present invention further includes:

[0033] When the difference is less than or equal to a preset value, the power semiconductor is kept in its current operating state.

[0034] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0035] The technical solution of this invention, by setting a sampling circuit in the power semiconductor and inputting power supply voltage and pulse at the power input terminal and pulse input terminal respectively, makes the invention not limited to the module packaging scheme, and the scheme has high versatility. This allows the sampling circuit to acquire the voltage of the first and second sources of the power semiconductor and the parasitic inductance set on the second source. Then, the junction temperature is calibrated by the correspondence between the acquired voltage and the internal junction temperature of the device. Compared with existing thermal imagers and thermistors, the circuit of this invention is convenient, safe and simple, and the steps of inputting pulse and voltage are easy to operate. It also avoids the problem of low accuracy of external thermistors by utilizing the thermal characteristics of the power semiconductor itself. Attached Figure Description

[0036] Figure 1 This is a structural diagram of a power semiconductor junction temperature calibration circuit provided in an embodiment of the present invention;

[0037] Figure 2This is a schematic diagram of the specific structure of the power semiconductor junction temperature calibration circuit provided in an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of a power semiconductor junction temperature calibration circuit provided in an embodiment of the present invention;

[0039] Figure 4 This is a flowchart illustrating the steps of a power semiconductor junction temperature calibration method provided in an embodiment of the present invention.

[0040] Figure 5 This is a flowchart illustrating the steps of a power semiconductor short-circuit protection method provided in an embodiment of the present invention. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] Example 1

[0043] Please refer to Figure 1 The present invention provides a power semiconductor junction temperature calibration circuit, comprising: a power semiconductor 1, a power input terminal 2, a pulse input terminal 3, and a sampling circuit 4.

[0044] As a preferred embodiment, the power semiconductor 1 is a field-effect transistor.

[0045] It should be noted that in practical applications, power semiconductor 1 components are analog semiconductor components used for power control, usually referred to as power devices, including: rectifier diodes, power transistors (power MOSFETs, insulated gate bipolar transistors, IGBTs, etc.), thyristors, etc.

[0046] The power semiconductor 1 has a source including a first source and a second source; the first source and the gate of the power semiconductor 1 are connected to the pulse input terminal 3; the second source is provided with a parasitic inductance and is connected to the power input terminal 2; the drain of the power semiconductor 1 is connected to the power input terminal 2.

[0047] The two ends of the sampling circuit 4 are respectively connected to the two ends of the parasitic inductor.

[0048] In this embodiment, please refer to Figure 2The power semiconductor 1 has a first source S-kelvin (Kelvin pin) and a second source S. The parasitic inductance between the first source S-kelvin and the power S is Ls1. Using a single-pulse testing method, a single-pulse signal is input to the pulse input terminal 3, causing the current in Ls1 to increase. This connects the second source S to the drain D, allowing real-time monitoring of the voltage value Ls1 * di / dt. Specifically, the voltage U across the parasitic inductance Ls1 between S-kelvin (Kelvin pin) and the power S is sampled as U = Ls1 * di / dt. The sampling circuit 4 uses a DSADC to quickly and accurately sample the voltage U. The single-pulse width is 1 ms.

[0049] It should be noted that the first source pin S-Kelvin is used to eliminate the influence of voltage drop on the wires in the circuit, thereby eliminating the influence of voltage drop on the detection value at both ends, thus enabling accurate voltage sampling of parasitic inductance Ls1.

[0050] In a preferred embodiment, an active resistor is provided between the parasitic inductance and the power input terminal 2; and a gate resistor is provided between the gate and the pulse input terminal 3.

[0051] In this embodiment, the gate resistor between the gate and the pulse input terminal 3 can act as a bias voltage on the gate, while the source resistor between the parasitic inductance and the power input terminal 2 can be used to calculate the magnitude of the current when the drain D and source S of the power semiconductor 1 are connected. Preferably, the power input terminal 2U DC The voltage is set to 800V, and the resistance of the source resistor R1 is 40KΩ.

[0052] In a preferred embodiment, the sampling circuit 4 includes an optocoupler, an operational amplifier, and a digital signal processing module; the first input terminal of the optocoupler is connected to one end of the parasitic inductor, and the first output terminal of the optocoupler is connected to the other end of the parasitic inductor; the second and third output terminals of the optocoupler are respectively connected to the first and second input terminals of the operational amplifier; and the output terminal of the operational amplifier is connected to the digital signal processing module.

[0053] In this embodiment, please refer to Figure 2 and Figure 3 Optical coupler IC1 is Figure 3 In the configuration, U2, the optocoupler IC1, is specifically an isolation optocoupler that isolates the high and low voltage levels of the input and output electrical signals. Operational amplifier IC2 is... Figure 3 In this configuration, U1 and operational amplifier IC2 are differential operational amplifiers. The digital signal processing module is...Figure 3 In the above, U3 is preferably a comparator U3 in the digital signal processing module. Pin 3 of the comparator U3 is a short-circuit threshold voltage, and the threshold voltage U is... th The threshold voltage U is set by voltage division using resistors R10 and R7. th =5V*R10 / (10+R7).

[0054] In this embodiment, the optocoupler IC1 (U2) has eight pins: VDD1, VDD2, VIN, V0+, SHDN, V0-, GND1, and GND2. VDD1 is connected to a 5V DC power supply and then connected to GND_LW via two capacitors. VDD2 is connected to a 5V DC power supply and then connected to GND via two capacitors. VIN is connected to one end of Ls1 via R2. SHDN is connected to GND1 and then to ground GND_LW via the other end of Ls1. A capacitor C7 is also placed between the VIN and GND1 pins. V0+ is connected to R3, V0- is connected to R4, and GND2 is grounded.

[0055] In this embodiment, operational amplifier IC2 (U1) has five pins: the first input (+), the second input (-), VSS, VDD, and the output. The first input (+) is connected in parallel with capacitor C6 and resistor R1, and is connected to GND. The second input (-) is connected in parallel with the output with resistor R6 and capacitor C7. VSS is grounded, and VDD is connected to 5V.

[0056] In this embodiment, comparator U3 has 8 pins. Pins 5, 6, 7 and 4 are grounded, pin 2 is connected to the output of the operational amplifier through resistor R9, pin 3 is connected in parallel with R10 and R7 and connected to REFw_5V, and pin 1 is the output.

[0057] It should be noted that the Ls1 inductor can also be used as overcurrent protection for power semiconductor 1, allowing for real-time online monitoring of Ls1. If the real-time monitored voltage value of Ls1*di / dt is too large, exceeding the threshold voltage U, th If the circuit is short-circuited, it will quickly enter the short-circuit protection state, making the protection response of power semiconductor 1 rapid.

[0058] In a preferred embodiment, a positive resistor is connected between the first input terminal of the operational amplifier and the second output terminal of the optocoupler, and a negative resistor is connected between the second input terminal of the operational amplifier and the third output terminal of the optocoupler; the resistance values ​​of the positive resistor and the negative resistor are equal; an amplification resistor is also connected between the second input terminal of the operational amplifier and the output terminal of the operational amplifier; the amplification factor of the operational amplifier is the ratio between the amplification resistor and the negative resistor.

[0059] In this embodiment, the amplification factor of operational amplifier IC2 is set by the positive terminal resistor R3 or the negative terminal resistor R4 (R3 = R4) and the amplification resistor R6 (R6 = R1), and the amplification factor is R1 / R3.

[0060] Implementing the embodiments of the present invention has the following effects:

[0061] The technical solution of this invention, by setting a sampling circuit in the power semiconductor and inputting power supply voltage and pulse at the power input terminal and pulse input terminal respectively, makes the invention not limited to the module packaging scheme, and the scheme has high versatility. This allows the sampling circuit to acquire the voltage of the first and second sources of the power semiconductor and the parasitic inductance set on the second source. Then, the junction temperature is calibrated by the correspondence between the acquired voltage and the internal junction temperature of the device. Compared with existing thermal imagers and thermistors, the circuit of this invention is convenient, safe and simple, and the steps of inputting pulse and voltage are easy to operate. It also avoids the problem of low accuracy of external thermistors by utilizing the thermal characteristics of the power semiconductor itself.

[0062] Furthermore, parasitic inductance can also be used as overcurrent protection, enabling real-time online monitoring of parasitic inductance voltage and resulting in rapid overcurrent protection response.

[0063] Example 2

[0064] Accordingly, the present invention also provides a method for calibrating the junction temperature of a power semiconductor, implemented by the junction temperature calibration circuit of the power semiconductor 1 described in Embodiment 1, comprising the following steps S101-S103:

[0065] Step S101: Set the ambient temperature around the power semiconductor 1 sequentially according to the preset temperature calibration range.

[0066] It should be noted that the preset temperature calibration range can be determined according to the required range of junction temperature measurement. For example, the preset temperature calibration range can be -55℃ to 175℃, with a temperature gradient of 3℃ intervals, so that each temperature is set sequentially, and then the sampling voltage corresponding to the current ambient temperature is obtained in step S102.

[0067] Step S102: After setting an ambient temperature, input a single pulse signal to the pulse input terminal 3, and collect the sampling voltage of the parasitic inductance at the current ambient temperature through the sampling circuit 4.

[0068] As a preferred embodiment, before inputting the single-pulse signal to the pulse input terminal 3, the method further includes:

[0069] Set the voltage at power input terminal 2 and set the resistance value of the source resistor so that the current after the source and drain of the power semiconductor 1 are turned on is within a preset range; wherein, the current after the source and drain of the power semiconductor 1 are turned on is: I d U is the current after the source and drain of the power semiconductor 1 are turned on. DC R1 is the voltage at power input terminal 2, and R1 is the resistance value of the source resistor.

[0070] In this embodiment, preferably, the voltage U at the power input terminal 2 is... DC The voltage is set to 800V, the source resistor R1 is set to 40KΩ, the single pulse signal width is 1ms, and the current preset range is [0mA, 20mA], which is the low current mode. Furthermore, the voltage value of Ls1*di / dt is sampled through the isolation optocoupler IC1, the differential operational amplifier circuit IC2, and the DSADC sampling port of the DSP.

[0071] It is understandable that after a single pulse signal is input to pulse input terminal 3, the drain and source of power semiconductor 1 become conductive, resulting in a drain-source current I. d At the same time, due to That is I d Within the preset current range, the current after the source and drain of power semiconductor 1 are turned on is small, meaning power semiconductor 1 is in low-current mode. Low-current mode implies that the heat dissipation power of the silicon-mospheric FET in power semiconductor 1 is very small, meaning its operating temperature does not change significantly (rises) and can be ignored. Therefore, the junction temperature of power semiconductor 1 is almost equal to the ambient temperature, which is the set ambient temperature. Furthermore, by successively adjusting the ambient temperature, the ambient temperature in low-current mode equals the junction temperature of power semiconductor 1. Measuring the Ls1*di / dt voltage value at different ambient temperatures, i.e., acquiring the sampling voltage corresponding to that ambient temperature, allows us to obtain the relationship between the junction temperature of power semiconductor 1 and the sampling voltage.

[0072] Step S103: After sampling voltage is collected for each ambient temperature in the preset temperature calibration range, the curve relationship between sampling voltage and ambient temperature is obtained, thereby completing the junction temperature calibration of the power semiconductor 1.

[0073] It should be noted that by collecting each ambient temperature and its corresponding sampling voltage, the curve relationship between the sampling voltage and the ambient temperature can be obtained. Therefore, compared with the existing technology, this embodiment calibrates the junction temperature by extracting the correspondence between the external electrical characteristic parameters of the power device and the internal junction temperature of the device, which is more accurate and efficient. At the same time, it makes the circuit structure convenient, safe and simple, and easy to operate.

[0074] As a preferred embodiment, this embodiment further includes:

[0075] The real-time sampling voltage of the parasitic inductance is acquired through the sampling circuit 4. Based on the curve relationship between the sampling voltage and the ambient temperature, the real-time ambient temperature corresponding to the real-time sampling voltage is obtained, and thus used as the junction temperature of the current power semiconductor 1.

[0076] It should be noted that, in this embodiment, after the sampling circuit 4 collects the real-time sampling voltage of the parasitic inductance, the junction temperature of the current power semiconductor 1 corresponding to the real-time sampling voltage can be accurately obtained based on the relationship curve between the sampling voltage and the ambient temperature, thereby realizing the calibration and monitoring of the junction temperature of the power semiconductor 1.

[0077] Implementing the above embodiments has the following effects:

[0078] This embodiment achieves junction temperature calibration of power semiconductors through a method and circuit. The circuit using parasitic inductance is not limited to module packaging, which leads to low versatility. At the same time, parasitic inductance also avoids the complexity and low accuracy of thermal resistance calibration.

[0079] Example 3

[0080] Please see Figure 5 This invention provides a power semiconductor short-circuit protection method, implemented by the power semiconductor junction temperature calibration circuit described in Example 1, including the following steps S201-S203:

[0081] Step S201: The sampling voltage of the parasitic inductance at the current ambient temperature is collected in real time through the sampling circuit.

[0082] Step S202: Determine the difference between the sampled voltage and the preset voltage value.

[0083] Step S203: When the difference is greater than a preset value, the power semiconductor is put into short-circuit protection state.

[0084] In this embodiment, the preset voltage value is the threshold voltage described in Embodiment 1. Preferably, the preset value can be set to 0. That is, when the difference between the real-time sampling voltage and the preset voltage value is greater than 0, it indicates that the real-time sampling voltage is greater than the threshold voltage, that is, a short circuit event has occurred in the power semiconductor 1.

[0085] It should be noted that when a single pulse is received at Vgs between the gate and the first source S-kelvin of power semiconductor 1, the drain and source conduct, causing Id to rise and generating a voltage on Ls1. When power semiconductor 1 is short-circuited, the Id current is the short-circuit current, making the value of di / dt very large, resulting in a large sampling voltage U on Ls1. Thus, by monitoring the sampling voltage U in real time, it is possible to monitor and determine whether power semiconductor 1 is short-circuited, thereby entering the short-circuit protection state.

[0086] In this embodiment, for example, when the detected di / dt exceeds a certain threshold t, that is, when the U value of Ls1*di / dt exceeds the threshold voltage (preset voltage value), it is determined to be a short circuit. The threshold voltage is calibrated according to the bridge arm short circuit test.

[0087] As a preferred embodiment, the present invention further includes step S204:

[0088] Step S204: When the difference is less than or equal to a preset value, the power semiconductor is kept in its current operating state.

[0089] In this embodiment, when the difference between the sampled voltage and the preset voltage value is less than or equal to the preset value, it indicates that the U value of Ls1*di / dt on the power semiconductor has not exceeded the threshold voltage (preset voltage value). Therefore, the power semiconductor only needs to maintain the current working state to operate.

[0090] Implementing the above embodiments has the following effects:

[0091] In this embodiment of the invention, parasitic inductance can also be used as overcurrent protection and short-circuit protection, thereby enabling real-time online monitoring of the voltage of the parasitic inductance, resulting in faster and more accurate response speed for overcurrent protection.

[0092] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A power semiconductor junction temperature calibration circuit, characterized in that, include: Power semiconductor, power input terminal, pulse input terminal, and sampling circuit; The sampling circuit includes: an optocoupler, an operational amplifier, and a digital signal processing module; The power semiconductor has a source including a first source and a second source; the first source and the gate of the power semiconductor are connected to the pulse input terminal; the second source is provided with a parasitic inductance and is connected to the power input terminal; the drain of the power semiconductor is connected to the power input terminal. The two ends of the sampling circuit are respectively connected to the two ends of the parasitic inductor; The first input terminal of the optocoupler is connected to one end of the parasitic inductor, and the first output terminal of the optocoupler is connected to the other end of the parasitic inductor. The second and third output terminals of the optocoupler are respectively connected to the first and second input terminals of the operational amplifier. The output of the operational amplifier is connected to the digital signal processing module.

2. The power semiconductor junction temperature calibration circuit as described in claim 1, characterized in that, An active resistor is provided between the parasitic inductance and the power input terminal; a gate resistor is provided between the gate and the pulse input terminal.

3. The power semiconductor junction temperature calibration circuit as described in claim 2, characterized in that, A positive resistor is connected between the first input terminal of the operational amplifier and the second output terminal of the optocoupler, and a negative resistor is connected between the second input terminal of the operational amplifier and the third output terminal of the optocoupler; the resistance values ​​of the positive resistor and the negative resistor are equal. An amplification resistor is also connected between the second input terminal and the output terminal of the operational amplifier; The amplification factor of the operational amplifier is the ratio between the amplification resistor and the negative terminal resistor.

4. A power semiconductor junction temperature calibration circuit as described in any one of claims 1-3, characterized in that, The power semiconductor is a field-effect transistor.

5. A method for calibrating the junction temperature of a power semiconductor, characterized in that, Implemented by the power semiconductor junction temperature calibration circuit according to any one of claims 1-4, comprising: According to the preset temperature calibration range, the ambient temperature around the power semiconductor is set sequentially; After setting an ambient temperature, a single pulse signal is input to the pulse input terminal, and the sampling voltage of the parasitic inductance at the current ambient temperature is collected through the sampling circuit. Once a corresponding sampling voltage has been collected for each ambient temperature within the preset temperature calibration range, the curve relationship between the sampling voltage and the ambient temperature is obtained, thereby completing the junction temperature calibration of the power semiconductor.

6. The power semiconductor junction temperature calibration method as described in claim 5, characterized in that, Before inputting a single-pulse signal to the pulse input terminal, the method further includes: Set the voltage at the power input terminal and set the resistance value of the source resistor so that the current after the source and drain of the power semiconductor are turned on is within a preset range. The current after the source and drain of the power semiconductor are turned on is as follows: ; This refers to the current after the source and drain of the power semiconductor are turned on. This is the voltage at the power input terminal. This is the resistance value of the source resistor.

7. The power semiconductor junction temperature calibration method as described in claim 5, characterized in that, Also includes: The real-time sampling voltage of the parasitic inductance is acquired through the sampling circuit. Based on the curve relationship between the sampling voltage and the ambient temperature, the real-time ambient temperature corresponding to the real-time sampling voltage is obtained, and thus used as the junction temperature of the current power semiconductor.

8. A power semiconductor short-circuit protection method, characterized in that, Implemented by the power semiconductor junction temperature calibration circuit according to any one of claims 1-4, comprising: The sampling circuit collects the sampling voltage of the parasitic inductance in real time at the current ambient temperature. Determine the difference between the sampled voltage and the preset voltage value; When the difference exceeds a preset value, the power semiconductor enters a short-circuit protection state.

9. A power semiconductor short-circuit protection method as described in claim 8, characterized in that, Also includes: When the difference is less than or equal to a preset value, the power semiconductor is kept in its current operating state.

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