Display device

Abstract

The disclosure provides a display device including a display panel including a first optical area having a plurality of light emitting areas and a plurality of transmissive areas and a normal area having a plurality of light emitting areas, a first optical electronic device located below the display panel in a lower portion of the display panel and overlapping at least a portion of the first optical area of the display area, and among a plurality of first horizontal lines crossing the first optical area, a bypass line connected to sub-pixels at two boundaries of the first optical area and not connected to other sub-pixels inside the first optical area and a non-bypass line connected to sub-pixels at the two boundaries of the first optical area and sub-pixels inside the first optical area, the bypass line and the non-bypass line carrying the same type of signal.

Description

Technical Field

[0001] This disclosure relates to electronic devices, and more specifically, to display devices. Background Technology

[0002] With advancements in display technology, display devices can offer enhanced functionality such as image capture, sensing, and image display capabilities. To provide these functions, display devices may require the inclusion of optoelectronic components, such as cameras and sensors for image detection.

[0003] In order to receive light passing through the front surface of the display device, it is desirable for the optical electronics to be located in an area of ​​the display device where the incident light entering from the front surface can be advantageously received or detected. Therefore, in such a display device, the optical electronics can be located in the front of the display device to effectively expose the optical electronics to the incident light. To mount the optical electronics in this way, an increased bezel can be designed for the display device, or a notch or hole can be formed in the display area of ​​the display panel of the display device.

[0004] Therefore, since display devices require optical electronics to receive or detect incident light and perform desired functions, the bezel size in the front of the display device may be increased, or significant defects may be encountered when designing the front of the display device. Summary of the Invention

[0005] The present inventors have developed a technique for arranging or placing one or more optical electronic devices in a display device without reducing the area of ​​the display area of ​​the display panel of the display device. Through this development, the inventors have invented a display panel and display device with a light-transmitting structure in which the optical electronic devices can normally and appropriately receive or detect light even when the optical electronic devices are located below the display area of ​​the display panel and are thus not exposed to the front surface of the display device.

[0006] Furthermore, the inventors have recognized that optical regions constructed in the overlapping areas of display areas with such optoelectronic devices are expected to possess excellent light-emitting performance and high transmission performance for displaying images, and thus, it is desirable to arrange signal lines passing through the optical regions in consideration of these requirements. However, in the case of typical display panels or display devices, signal lines passing through the optical regions have already been arranged without properly taking into account the characteristics of the optical regions. To solve these problems, the inventors have invented a display device in which one or more signal lines passing through the optical regions overlapping with one or more optoelectronic devices are arranged in a manner suitable for the characteristics of the optical regions.

[0007] Embodiments of this disclosure provide a display panel and a display device that, by placing optical electronic devices such as cameras and sensors below the display area of ​​the display panel, can reduce the non-display area of ​​the display panel and prevent the optical electronic devices from being exposed on the front surface of the display panel.

[0008] Embodiments of this disclosure provide a display panel and a display device having a light-transmitting structure that enables optical electronics below the display area of ​​the display panel to properly receive light transmitted through the display panel.

[0009] Embodiments of this disclosure provide a display panel and a display device that are capable of performing display driving normally in the display area included in the display panel and in the optical area overlapping with the optical electronics.

[0010] Embodiments of this disclosure provide a display device that enables signal lines to pass through an optical region in a manner suitable for the characteristics of an optical region overlapping with an optoelectronic device.

[0011] Therefore, embodiments of this disclosure are directed to a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0012] According to an aspect of this disclosure, a display device is provided, comprising: a display panel including a display area and a non-display area, and including a plurality of sub-pixels and a plurality of signal lines, the display area including a first optical area and a normal area located outside the first optical area, the first optical area including a plurality of light-emitting areas and a plurality of first transmissive areas, and the normal area including a plurality of light-emitting areas; and a first optical electronic device located below and in a lower portion of the display panel, and overlapping at least a portion of the first optical area included in the display area.

[0013] The display panel may include multiple first horizontal lines that cross the first optical area, among multiple signal lines.

[0014] The display panel may include bypass lines and non-bypass lines among multiple first horizontal lines. The bypass lines are connected to the sub-pixels at the two boundaries of the first optical region but not to other sub-pixels inside the first optical region. The non-bypass lines are connected to the sub-pixels at the two boundaries of the first optical region and to the sub-pixels inside the first optical region.

[0015] Bypass lines and non-bypass lines can carry the same type of signal.

[0016] Bypass routes and non-bypass routes can be set alternately.

[0017] The display panel may also include an encapsulation layer on the cathode electrode and a touch sensor metal with a mesh pattern on the encapsulation layer.

[0018] The touch sensor metal can be configured to avoid multiple light-emitting areas within the normal area. The touch sensor metal can be configured to avoid both the multiple light-emitting areas and multiple first transmissive areas included in the first optical area.

[0019] The touch sensor metal in the first optical region may include a portion with a larger linewidth than the touch sensor metal in the normal region.

[0020] The touch sensor metal may include a cross portion and a link portion for connecting the cross portion, and the line width of the link portion may be greater than the line width of the cross portion.

[0021] According to embodiments of the present disclosure, a display panel and a display device can be provided that can reduce the non-display area of ​​the display panel and prevent the optical electronic devices from being exposed on the front surface of the display panel by placing optical electronic devices such as cameras and sensors below the display area of ​​the display panel.

[0022] According to embodiments of the present disclosure, a display panel and a display device can be provided having a light-transmitting structure for enabling optical electronics below the display area of ​​the display panel to normally receive light transmitted through the display panel.

[0023] According to embodiments of the present disclosure, a display panel and a display device can be provided that are capable of performing display driving normally in the display area included in the display panel and in the optical area overlapping with the optical electronics.

[0024] According to embodiments of the present disclosure, a display device can be provided that enables signal lines to traverse an optical region in a manner suitable for the characteristics of an optical region overlapping with an optical electronic device.

[0025] Additional features and aspects will be set forth in part in the following description and will become apparent in part from the description, or may be learned by practicing the inventive concepts provided herein. Other features and aspects of the conception of this disclosure may be realized and obtained by means of structures particularly pointed out or deduced in the written description, its claims and drawings.

[0026] Other systems, methods, features, and advantages will be or will become apparent to those skilled in the art upon examination of the following drawings and detailed description. All such additional systems, methods, features, and advantages are intended to be included in this specification, fall within the scope of this disclosure, and are protected by the appended claims. Nothing in this section should be construed as limiting those claims.

[0027] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0028] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this disclosure. The drawings illustrate various aspects of this disclosure and, together with the description, serve to explain the principles of this disclosure. In the drawings:

[0029] Figure 1A , Figure 1B and Figure 1C This is a plan view illustrating an example display device according to aspects of the present disclosure;

[0030] Figure 2 An example system configuration of a display device according to aspects of this disclosure is illustrated;

[0031] Figure 3 An example equivalent circuit for a subpixel in a display panel according to an aspect of this disclosure is illustrated;

[0032] Figure 4 An example arrangement of subpixels in three regions included in the display area of ​​a display panel according to aspects of this disclosure is illustrated;

[0033] Figure 5A An example arrangement of signal lines in each of the first optical region and the normal region in a display panel according to aspects of this disclosure is illustrated;

[0034] Figure 5B An example arrangement of signal lines in each of the second optical region and the normal region in a display panel according to aspects of this disclosure is illustrated;

[0035] Figure 6 and Figure 7 This is an example cross-sectional view of the normal area, the first optical area, and the second optical area included in the display area of ​​the display panel according to aspects of this disclosure;

[0036] Figure 8 This is an example cross-sectional view of the outer edge of the display panel according to aspects of this disclosure;

[0037] Figure 9 An example pixel circuit of a display device according to aspects of the present disclosure is illustrated;

[0038] Figure 10 An example first optical region of a display device according to aspects of the present disclosure is illustrated;

[0039] Figure 11An example arrangement of signal lines traversing a first optical region of a display device according to aspects of this disclosure is illustrated;

[0040] Figure 12 and Figure 13 A more specific example arrangement of a bypass line within the first optical region of a display device according to aspects of the present disclosure is illustrated.

[0041] Figure 14 An example arrangement of touch sensor metal in each of the normal area and the first optical area of ​​a display device according to aspects of this disclosure is illustrated; and

[0042] Figure 15 This is an enlarged view of an example arrangement structure of the touch sensor metal within the first optical region of the display device according to aspects of this disclosure. Detailed Implementation

[0043] Referring now to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, unless otherwise stated, the structures, implementations, methods, and operations described herein are not limited to one or more specific examples set forth herein and may be varied as is known in the art. Unless otherwise stated, similar reference numerals always refer to similar elements. The names of the various elements used in the following description are chosen only for convenience in drafting the specification and may therefore differ from those used in actual products. The advantages and features of this disclosure and methods of implementation thereof will be elucidated by the following exemplary embodiments described with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided to make this disclosure sufficiently thorough and complete to assist those skilled in the art in fully understanding its scope. Furthermore, the scope of protection of this disclosure is defined by the claims and their equivalents. In the following description, detailed descriptions of relevant known functions or constructions may be omitted where such detailed descriptions may unnecessarily obscure aspects of this disclosure. Shapes, dimensions, ratios, angles, quantities, etc., illustrated in the drawings for the purpose of describing various exemplary embodiments of this disclosure are given by way of example only. Therefore, this disclosure is not limited to the illustrations in the drawings. When using terms such as “including,” “having,” “containing,” “comprising,” “forming,” “composed of,” “formed by,” etc., one or more additional elements may be added unless a term such as “only” is used. Elements described in the singular are intended to include multiple elements, and vice versa, unless the context explicitly indicates otherwise.

[0044] Although the terms “first,” “second,” A, B, (a), (b), etc., may be used herein to describe various elements, these elements should not be construed as being limited by these terms, as they are not used to define a particular order or priority. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0045] When describing a component or layer as "connected," "joined," or "adhered" to another component or layer, unless otherwise stated, the component or layer may not only be directly connected, joined, or adhered to another component or layer, but also indirectly connected, joined, or adhered to another component or layer, and one or more intermediary components or layers may be "set" or "inserted" between these components or layers. When describing a component or layer as "contacting," "overlapping," etc., with another component or layer, unless otherwise stated, the component or layer may not only directly contact or overlap with another component or layer, but also indirectly contact or overlap with another component or layer, and one or more intermediary components or layers may be "set" or "inserted" between these components or layers.

[0046] When describing positional relationships, such as using terms like "on top of," "above," "below," "above," "under," "next to," or "next to" to describe the positional relationship between two parts, one or more other parts may be located between the two parts, unless more restrictive terms such as "right next to," "directly," or "immediately following" are used. For example, when an element or layer is placed "on" another element or layer, a third element or layer may be inserted between them. Furthermore, the terms "left," "right," "top," "bottom," "down," "upward," "above," "below," etc., refer to any frame of reference. When describing temporal relationships, when the temporal sequence is described as, for example, "after," "following," "next," or "before," discontinuous situations may be included unless more restrictive terms such as "exactly," "immediately following," or "directly" are used.

[0047] When interpreting elements, elements are to be interpreted as including a range of errors or tolerances, even if no explicit description of such a range of errors or tolerances is provided. Furthermore, the term "may" fully encompasses all meanings of the term "capable of". The term "at least one" should be understood to include any combination or all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first element, the second element, and the third element" covers combinations of all three listed elements, combinations of any two of the three elements, and each individual element, the first element, the second element, and the third element. The expression "first element, second element, and / or third element" should be understood to mean one of the first element, the second element, and the third element, or any combination or all combinations of the first element, the second element, and the third element. As an example, A, B, and / or C may refer to only A, only B, or only C; any combination or some combinations of A, B, and C; or all of A, B, and C. Various exemplary embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Additionally, for ease of description, the scale of each element illustrated in the drawings may differ from the actual scale. Therefore, the illustrated elements are not limited to the specific scales illustrated in the drawings.

[0048] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, for ease of description, the scale of each element illustrated in the drawings may differ from the actual scale. Therefore, the illustrated elements are not limited to the specific scales illustrated in the drawings.

[0049] Figure 1A , Figure 1B and Figure 1C This is a plan view illustrating an example display device according to aspects of this disclosure.

[0050] Reference Figure 1A , Figure 1B and Figure 1C The display apparatus according to aspects of this disclosure may include a display panel 110 for displaying images and one or more optical electronic devices (11, 12). Hereinafter, the optical electronic devices may be referred to as photodetectors, photoreceivers, or photosensing devices. The optical electronic devices may include one or more of a camera, camera lens, sensor, or sensor for detecting images.

[0051] The display panel 110 may include a display area DA for displaying images and a non-display area NDA for not displaying images.

[0052] Multiple subpixels can be arranged in the display area DA, and various types of signal lines used to drive the multiple subpixels can be arranged therein.

[0053] The non-display area NDA can refer to the area outside the display area DA. Various signal lines can be arranged in the non-display area NDA, and various driving circuits can be connected to the signal lines. At least a portion of the non-display area NDA can be bent to be invisible from the front of the display panel, or it can be covered by the housing (not shown) of the display panel 110 or the display device 100. The non-display area NDA can also be referred to as a bezel or bezel area.

[0054] Reference Figure 1A , Figure 1B and Figure 1C In the display device 100 according to aspects of the present disclosure, one or more optical electronic devices (11, 12) may be located below or in the lower portion of the display panel 110 (on the opposite side of the viewing surface of the display panel).

[0055] Light can enter the front surface (viewing surface) of the display panel 110, pass through the display panel 110, and reach one or more optical electronic devices (11, 12) located below or in the lower part of the display panel 110 (opposite to the viewing surface).

[0056] One or more optical electronic devices (11, 12) can receive or detect light transmitted through the display panel 110 and perform a predetermined function based on the received light. For example, one or more optical electronic devices (11, 12) may include one or more image capture devices such as a camera (image sensor) and sensors such as a proximity sensor and an illuminance sensor.

[0057] Reference Figure 1A , Figure 1B and Figure 1C In the display panel 110 according to aspects of this disclosure, the display area DA may include one or more optical areas (OA1, OA2) and a normal area NA. Here, the term "normal area" NA is an area that exists in the display area DA but does not overlap with one or more optical electronic devices (11, 12) and may also be referred to as a non-optical area.

[0058] Reference Figure 1A , Figure 1B and Figure 1C As shown, one or more optical regions (OA1, OA2) may be one or more regions that overlap with one or more optical electronic devices (11, 12).

[0059] according to Figure 1A For example, the display area DA may include a first optical area OA1 and a normal area NA. In this example, at least a portion of the first optical area OA1 may overlap with the first optical electronics 11.

[0060] according to Figure 1B For example, the display area DA may include a first optical area OA1, a second optical area OA2, and a normal area NA. Figure 1B In this example, at least a portion of the normal region NA may exist between the first optical region OA1 and the second optical region OA2. In this example, at least a portion of the first optical region OA1 may overlap with the first optical electronic device 11, and at least a portion of the second optical region OA2 may overlap with the second optical electronic device 12.

[0061] according to Figure 1C For example, the display area DA may include a first optical area OA1, a second optical area OA2, and a normal area NA. Figure 1C In this example, a normal region NA may not exist between the first optical region OA1 and the second optical region OA2. For example, the first optical region OA1 and the second optical region OA2 may be in contact with each other (e.g., in direct contact). In this example, at least a portion of the first optical region OA1 may overlap with the first optoelectronic device 11, and at least a portion of the second optical region OA2 may overlap with the second optoelectronic device 12.

[0062] In some implementations, it is desirable to form an image display structure and a light-transmitting structure within one or more optical regions (OA1, OA2). For example, since one or more optical regions (OA1, OA2) are part of the display area DA, the one or more optical regions (OA1, OA2) require sub-pixels for displaying the image. Furthermore, a light-transmitting structure is required in order for light to pass through one or more optoelectronic devices (11, 12), and therefore a light-transmitting structure is formed within one or more optical regions (OA1, OA2).

[0063] According to embodiments of this disclosure, even when one or more optical electronic devices (11, 12) are required to receive or detect light, these devices are sometimes located on the back side of the display panel 110 (e.g., on the opposite side of the viewing surface). Therefore, in these embodiments, one or more optical electronic devices (11, 12) are located, for example, below or in the lower portion of the display panel 110 and are configured to receive light that has already passed through the display panel 110.

[0064] For example, one or more optical electronic devices (11, 12) are not exposed on the front surface (viewing surface) of the display panel 110. Therefore, when a user faces the front surface of the display device 100, one or more optical electronic devices (11, 12) are positioned such that they are invisible to the user.

[0065] In one embodiment, the first optical electronic device 11 may be a camera, while the second optical electronic device 12 may be a sensor, such as a proximity sensor, an illumination sensor, an infrared sensor, etc. For example, the camera may be a camera lens, an image sensor, or a unit that includes at least one of a camera lens and an image sensor. For example, the sensor may be an infrared sensor capable of detecting infrared light.

[0066] In another embodiment, the first optical electronic device 11 may be a sensor, while the second optical electronic device 12 may be a camera.

[0067] In the following discussion, for convenience only, reference will be made to an embodiment in which the first optical electronic device 11 is a camera and the second optical electronic device 12 is a sensor. However, it should be understood that the scope of this disclosure includes embodiments in which the first optical electronic device 11 is a sensor and the second optical electronic device 12 is a camera. For example, a camera may be a camera lens, an image sensor, or a unit including at least one of a camera lens and an image sensor.

[0068] In an example where the first optical electronic device 11 is a camera, the camera may be located on the back of the display panel 110 (e.g., below or in the lower portion) and is a front-facing camera capable of capturing objects or images in the frontal direction of the display panel 110. Therefore, a user can capture images or objects by means of a camera that is not visible on the viewing surface when looking at the viewing surface of the display panel 110.

[0069] Despite Figure 1A , Figure 1B and Figure 1C In each of the above, the normal region NA and one or more optical regions (OA1, OA2) included in the display area DA are areas where images can be displayed. However, the normal region NA is an area that does not need to form a light-transmitting structure, while the one or more optical regions (OA1, OA2) are areas that need to form a light-transmitting structure. Therefore, in some embodiments, the normal region NA is an area that does not implement or does not include a light-transmitting structure, while the one or more optical regions (OA1, OA2) are areas that implement or include a light-transmitting structure.

[0070] Therefore, one or more optical regions (OA1, OA2) may have a transmittance greater than or equal to a predetermined level, i.e., relatively high transmittance, while the normal region NA may have no transmittance or a transmittance less than the predetermined level, i.e., relatively low transmittance.

[0071] For example, one or more optical regions (OA1, OA2) may have different resolutions, subpixel arrangement structures, number of subpixels per unit area, electrode structures, line structures, electrode arrangement structures, and / or line arrangement structures than the normal region NA.

[0072] In this implementation, the number of subpixels per unit area in one or more optical regions OA1, OA2 may be less than the number of subpixels per unit area in the normal region NA. For example, the resolution of one or more optical regions (OA1, OA2) may be lower than the resolution of the normal region NA. Here, the number of pixels per unit area can be measured using pixels per inch (PPI), which represents the number of pixels per inch.

[0073] exist Figure 1A , Figure 1B and Figure 1C In each of the embodiments, the number of sub-pixels per unit area in the first optical region OA1 can be less than the number of sub-pixels per unit area in the normal region NA. Figure 1A , Figure 1B and Figure 1C In each of the embodiments, the number of sub-pixels per unit area in the second optical region OA2 can be greater than or equal to the number of sub-pixels per unit area in the first optical region OA1, and less than the number of sub-pixels per unit area in the normal region NA.

[0074] exist Figure 1A , Figure 1B and Figure 1C In each of these, the first optical region OA1 can have various shapes, such as circular, elliptical, quadrilateral, hexagonal, octagonal, etc. Figure 1B and Figure 1C In each of these regions, the second optical region OA2 can have various shapes, such as circular, elliptical, quadrilateral, hexagonal, octagonal, etc. The first optical region OA1 and the second optical region OA2 can have the same shape or different shapes.

[0075] Reference Figure 1C In the example where the first optical region OA1 and the second optical region OA2 are in contact with each other, the entire optical region including the first optical region OA1 and the second optical region OA2 can also have various shapes, such as circles, ellipses, quadrilaterals, hexagons, octagons, etc.

[0076] In the following discussion, for ease of description, embodiments in which each of the first optical region OA1 and the second optical region OA2 has a circular shape will be provided. However, it should be understood that the scope of this disclosure includes embodiments in which one or both of the first optical region OA1 and the second optical region OA2 have a shape other than a circular shape.

[0077] When the display device 100 according to aspects of the present disclosure has a structure in which a first optical electronic device 11 (such as a camera) is located below or in the lower portion of the display panel 110 and is not exposed to the outside, such a display device 100 according to aspects of the present disclosure can be referred to as a display that implements under-display camera (UDC) technology.

[0078] According to this example, in the display device 100 according to aspects of this disclosure, since it is not necessary to form a notch or camera hole in the display panel 110 for exposing the camera, it is possible to prevent a reduction in the area or size of the display area DA.

[0079] Since it is not necessary to form a notch or camera hole in the display panel 110 to expose the camera, the display device 100 is able to have the further advantages of reducing the size of the bezel area and increasing design freedom due to the removal of such restrictions on the design.

[0080] Although one or more optical electronics (11, 12) are located on the back of the display panel 110 of the display device 100 (e.g., below or in the lower portion) (e.g., hidden or not exposed to the outside), in some respects, one or more optical electronics (11, 12) are able to perform normal predefined functions and thus receive or detect light.

[0081] Furthermore, in the display device 100 according to aspects of this disclosure, although one or more optical electronics (11, 12) are located on the back side of the display panel 110 (e.g., below or in the lower portion) to be hidden and positioned to overlap with the display area DA, it is necessary to normally perform image display in one or more optical regions (OA1, OA2) overlapping with one or more optical electronics (11, 12) in the display area DA. Therefore, in one or more examples, even if one or more optical electronics 11 and 12 are located on the back side of the display panel, it is possible to display images in a normal manner (e.g., without degrading image quality) in one or more optical regions OA1 and OA2 overlapping with one or more optical electronics 11 and 12 in the display area DA.

[0082] Figure 2 An example system configuration of a display device 100 according to aspects of this disclosure is illustrated.

[0083] Reference Figure 2 The display device 100 may include a display panel 110 and a display driving circuit as components for displaying images.

[0084] The display driver circuit is a circuit used to drive the display panel 110, and may include a data driver circuit 220, a gating driver circuit 230, a display controller 240, and other components.

[0085] The display panel 110 may include a display area DA for displaying images and a non-display area NDA for not displaying images. The non-display area NDA may be an area outside the display area DA, and may also be referred to as an edge area or border area. All or part of the non-display area NDA may be an area visible from the front surface of the display device 100, or a curved and invisible area from the front surface of the display device 100.

[0086] The display panel 110 may include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB. The display panel 110 may also include various types of signal lines to drive the plurality of sub-pixels SP.

[0087] The display device 100 according to aspects of this disclosure may be a liquid crystal display device or a self-emissive display device that emits light from the display panel 110 itself. When the display device 100 according to aspects of this disclosure is a self-emissive display device, each of the plurality of sub-pixels SP may include a light-emitting element.

[0088] In one embodiment, the display device 100 according to aspects of the present disclosure may be an organic light-emitting display device that uses organic light-emitting diodes (OLEDs) to realize light-emitting elements. In another embodiment, the display device 100 according to aspects of the present disclosure may be an inorganic light-emitting display device that uses light-emitting diodes based on inorganic materials to realize light-emitting elements. In yet another embodiment, the display device 100 according to aspects of the present disclosure may be a quantum dot display device that uses quantum dots, which are self-emissive semiconductor crystals, to realize light-emitting elements.

[0089] The structure of each of the plurality of sub-pixels SP can vary depending on the type of display device 100. For example, when the display device 100 is a self-emissive display device that includes self-emissive sub-pixels SP, each sub-pixel SP may include a self-emissive element, one or more transistors, and one or more capacitors.

[0090] For example, various types of signal lines arranged in the display device 100 may include multiple data lines DL for carrying data signals (which may be referred to as data voltage or image signals), gating lines for carrying gating signals (which may be referred to as scan signals), etc.

[0091] Multiple data lines (DL) and multiple gating lines (GL) can intersect each other. Each of the multiple data lines (DL) can extend in a first direction. Each of the multiple gating lines (GL) can extend in a second direction.

[0092] For example, the first direction can be a column direction or a vertical direction, and the second direction can be a row direction or a horizontal direction. In another example, the first direction can be a row direction, and the second direction can be a column direction.

[0093] The data driver circuit 220 is used to drive multiple data lines DL and can provide data signals to the multiple data lines DL. The gating driver circuit 230 is used to drive multiple gating lines GL and can provide gating signals to the multiple gating lines GL.

[0094] The display controller 240 can be a device for controlling the data drive circuit 220 and the gating drive circuit 230, and can control the driving timing of multiple data lines DL and multiple gating lines GL.

[0095] The display controller 240 can provide the data drive control signal DCS to the data drive circuit 220 to control the data drive circuit 220, and provide the gating drive control signal GCS to the gating drive circuit 230 to control the gating drive circuit 230.

[0096] The display controller 240 can receive input image data from the host system 250 and provide image data Data to the data drive circuit 220 based on the input image data.

[0097] The data drive circuit 220 can provide data signals to multiple data lines DL according to the driving timing control of the display controller 240.

[0098] The data drive circuit 220 can receive digital image data Data from the display controller 240, convert the received image data Data into an analog data signal, and provide the obtained analog data signal to multiple data lines DL.

[0099] The gating drive circuit 230 can provide gating signals to multiple gating lines GL according to the timing control of the display controller 240. The gating drive circuit 230 can receive a first gating voltage corresponding to the on-level voltage and a second gating voltage corresponding to the off-level voltage, as well as various gating drive control signals GCS, generate gating signals, and provide the generated gating signals to the multiple gating lines GL.

[0100] In some implementations, the data drive circuit 220 may be connected to the display panel 110 via a tape-on-board (TAB) method, or to conductive pads such as bonding pads on the display panel 110 via a chip-on-glass (COG) or chip-on-panel (COP) type, or to the display panel 110 via a chip-on-film (COF) type.

[0101] In some embodiments, the gate drive circuit 230 can be connected to the display panel 110 via tape-on-board (TAB) assembly, or to conductive pads such as bonding pads on the display panel 110 via chip-on-glass (COG) or chip-on-panel (COP) assembly, or to chip-on-film (COF) assembly. In another embodiment, the gate drive circuit 230 can be disposed in the non-display area NDA of the display panel 110 via a gate-in-panel (GIP) assembly. The gate drive circuit 230 can be disposed on or above the substrate, or connected to the substrate. That is, in the case of the GIP type, the gate drive circuit 230 can be disposed in the non-display area NDA of the substrate. The gate drive circuit 230 can be connected to the substrate in the case of chip-on-glass (COG), chip-on-film (COF), etc.

[0102] In some embodiments, at least one of the data driving circuit 220 and the gating driving circuit 230 may be disposed in the display area DA of the display panel 110. For example, at least one of the data driving circuit 220 and the gating driving circuit 230 may be configured not to overlap with the sub-pixel SP, or configured to overlap with one or more or all of the sub-pixels SP.

[0103] The data driving circuit 220 may also be located on only one side or a portion (e.g., the upper edge or the lower edge) of the display panel 110. In some embodiments, depending on the driving scheme, panel design, etc., the data driving circuit 220 may be located on both sides or two portions (e.g., the upper edge and the lower edge) of the display panel 110 or at least two of the four sides or four portions (e.g., the upper edge, the lower edge, the left edge, and the right edge) of the display panel 110.

[0104] The gating drive circuit 230 may be located on only one side or a portion of the display panel 110 (e.g., the left edge or the right edge). In some embodiments, depending on the driving scheme, panel design, etc., the gating drive circuit 230 may be connected to both sides or two portions of the display panel 110 (e.g., the left edge and the right edge), or connected to at least two of the four sides or four portions of the display panel 110 (e.g., the top edge, the bottom edge, the left edge, and the right edge).

[0105] The display controller 240 can be implemented in a component separate from the data drive circuit 220, or integrated with the data drive circuit 220, thereby being implemented as an integrated circuit.

[0106] The display controller 240 may be a timing controller used in typical display technologies, or a controller or control device capable of performing other control functions besides those of a typical timing controller. In some embodiments, the display controller 240 may be a controller or control device different from the timing controller, or may be a circuit or component included in a controller or control device. The display controller 240 may be implemented using various circuits or electronic components such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), and / or processors.

[0107] The display controller 240 can be mounted on a printed circuit board and / or flexible printed circuit, etc., and is electrically connected to the gating drive circuit 230 and the data drive circuit 220 via the printed circuit board and / or flexible printed circuit, etc.

[0108] The display controller 240 can send signals to and receive signals from the data drive circuit 220 via one or more predefined interfaces. In some embodiments, such interfaces may include a low-voltage differential signaling (LVDS) interface, an EPI interface, a serial peripheral interface (SP), etc.

[0109] To further provide touch sensing and image display functions, the display device 100 according to aspects of this disclosure may include at least one touch sensor and a touch sensing circuit, which can detect whether a touch event has occurred by a touch object such as a finger or a pen, or detect the corresponding touch position by sensing the touch sensor.

[0110] The touch sensing circuit may include a touch driver circuit 260 capable of generating and providing touch sensing data by driving and sensing a touch sensor, a touch controller 270 capable of using the touch sensing data to detect the occurrence of a touch event or to detect the touch position, and one or more other components.

[0111] The touch sensor may include multiple touch electrodes. The touch sensor may also include multiple touch lines for electrically connecting the multiple touch electrodes to the touch driving circuitry 260.

[0112] The touch sensor can be implemented externally to the display panel 110, within the touch panel, or as a form of the touch panel, or it can be implemented internally to the display panel 110. In the example where the touch sensor is implemented externally to the display panel 110, within the touch panel, or as a form of the touch panel, this type of touch sensor is referred to as add-on type. In the example of using an add-on type touch sensor, the touch panel and the display panel 110 can be manufactured separately and joined during the assembly process. The add-on type touch panel may include a touch panel substrate and multiple touch electrodes on the touch panel substrate.

[0113] In an example where the touch sensor is implemented inside the display panel 110, the process of manufacturing the display panel 110 may include placing the touch sensor together with signal lines and electrodes associated with driving the display device 100 above the substrate SUB.

[0114] The touch driving circuit 260 can provide a touch driving signal to at least one of the plurality of touch electrodes and sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0115] Touch sensing circuits can use self-capacitance sensing or mutual capacitance sensing to perform touch sensing.

[0116] In an example where the touch sensing circuit performs touch sensing using a self-capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and the touch object (e.g., a finger, a pen, etc.).

[0117] According to the self-capacitance sensing method, each of the plurality of touch electrodes can be used as both a driving touch electrode and a sensing touch electrode. The touch driving circuit 260 can drive all or one or more of the plurality of touch electrodes and sense all or one or more of the plurality of touch electrodes.

[0118] In an example where the touch sensing circuit performs touch sensing using a mutual capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes.

[0119] According to the mutual capacitance sensing method, multiple touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 260 can drive the driving touch electrodes and sense the sensing touch electrodes.

[0120] The touch driving circuit 260 and touch controller 270 included in the touch sensing circuit can be implemented as separate devices or as a single device. Furthermore, the touch driving circuit 260 and data driving circuit 220 can be implemented as separate devices or as a single device.

[0121] The display device 100 may also include a power supply circuit for providing various types of power to the display driving circuit and / or touch sensing circuit.

[0122] The display device 100 according to various aspects of this disclosure can be a mobile terminal such as a smartphone, tablet computer, or a monitor, television (TV), etc. Such a device can have various types, sizes, and shapes. The display device 100 according to embodiments of this disclosure is not limited thereto, and includes displays of various types, sizes, and shapes for displaying information or images.

[0123] As described above, the display area DA of the display panel 110 may include a normal area NA and one or more optical areas (OA1, OA2), for example, such as Figure 1A , Figure 1B and Figure 1C As shown.

[0124] The normal region NA and one or more optical regions (OA1, OA2) are areas where images can be displayed. However, the normal region NA is not an area that does not require a light-transmitting structure, while one or more optical regions (OA1, OA2) are areas that do require a light-transmitting structure.

[0125] As mentioned above Figure 1A , Figure 1B and Figure 1C As discussed in the examples, although the display area DA of the display panel 110 may include one or more optical areas (OA1, OA2) in addition to the normal area NA, for ease of description, in the following discussion, it is assumed that the display area DA includes the first optical area (OA1), the second optical area (OA2), and the normal area NA; and unless otherwise explicitly stated, its normal area NA includes Figures 1A to 1C The normal region NA in the image, and its first optical region (OA1) and second optical region (OA2) respectively include Figure 1A , Figure 1B and Figure 1C The first optical region OA1 and Figure 1B and Figure 1C The second optical region OA2 in the middle.

[0126] Figure 3 An example equivalent circuit of a sub-pixel SP in a display panel 110 according to an aspect of this disclosure is illustrated.

[0127] Each sub-pixel SP set in the normal area NA, the first optical area OA1 and the second optical area OA2 included in the display area DA of the display panel 110 may include a light-emitting element ED, a driving transistor DRT for driving the light-emitting element ED, a scanning transistor SCT for transmitting the data voltage Vdata to the first node N1 of the driving transistor DRT, a storage capacitor Cst for maintaining the voltage at an approximately constant level during a frame, etc.

[0128] The driving transistor DRT may include a first node N1 to which a data voltage is applied, a second node N2 electrically connected to a light-emitting element ED, and a third node N3 to which a driving voltage ELVDD is applied via a driving voltage line DVL. In the driving transistor DRT, the first node N1 may be a gate node, the second node N2 may be a source node or a drain node, and the third node N3 may be a drain node or a source node.

[0129] The light-emitting element ED may include an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE. The anode electrode AE ​​may be a pixel electrode disposed in each sub-pixel SP and may be electrically connected to the second node N2 of the driving transistor DRT of each sub-pixel SP. The cathode electrode CE may be a common electrode disposed in multiple sub-pixels SP, and a base voltage ELVSS, such as a low-level voltage, may be applied to the cathode electrode CE.

[0130] For example, the anode electrode AE ​​can be a pixel electrode, and the cathode electrode CE can be a common electrode. In another example, the anode electrode AE ​​can be a common electrode, and the cathode electrode CE can be a pixel electrode. For ease of description, in the following discussion, it is assumed that the anode electrode AE ​​is a pixel electrode and the cathode electrode CE is a common electrode, unless otherwise explicitly stated.

[0131] For example, the light-emitting element ED can be an organic light-emitting diode (OLED), an inorganic light-emitting diode, a quantum dot light-emitting element, etc. In an example using an organic light-emitting diode as the light-emitting element ED, the light-emitting layer EL included in the light-emitting element ED can include an organic light-emitting layer containing organic materials.

[0132] The scanning transistor SCT can be turned on and off by the scanning signal SCAN, which is applied as a gating signal via the gating line GL, and is electrically connected between the first node N1 of the driving transistor DRT and the data line DL.

[0133] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

[0134] Each subpixel SP can include, for example: Figure 3The diagram shows two transistors (2T: DRT and SCT) and a capacitor (1C: Cst) (which may be referred to as a "2T1C structure"), and in some cases, it may also include one or more transistors, or one or more capacitors.

[0135] In some implementations, the storage capacitor Cst that may exist between the first node Nx and the second node Ny of the driving transistor DRT may be an external capacitor that is intentionally constructed or designed to be located outside the driving transistor DRT, rather than an internal capacitor such as a parasitic capacitor (e.g., gate-source capacitance Cgs, gate-drain capacitance Cgd, etc.).

[0136] Each of the driving transistor DRT and the scanning transistor SCT can be an n-type transistor or a p-type transistor.

[0137] Since the circuit elements in each sub-pixel SP (e.g., specifically, the light-emitting element ED) are susceptible to external moisture or oxygen, an encapsulation layer ENCAP can be provided in the display panel 110 to prevent external moisture or oxygen from penetrating into the circuit elements (e.g., particularly the light-emitting element ED). The encapsulation layer ENCAP can be configured to cover the light-emitting element ED.

[0138] Figure 4 An example arrangement of subpixels SP in three regions (NA, OA1, and OA2) included in the display area DA of a display panel 110 according to an aspect of the present disclosure is illustrated.

[0139] Reference Figure 4 Multiple sub-pixels SP can be set in each of the normal area NA, the first optical area OA1, and the second optical area OA2 included in the display area DA.

[0140] For example, multiple sub-pixels SP may include a red sub-pixel that emits red light (red SP), a green sub-pixel that emits green light (green SP), and a blue sub-pixel that emits blue light (blue SP).

[0141] Therefore, each of the normal region NA, the first optical region OA1, and the second optical region OA2 may include one or more light-emitting regions EA of one or more red sub-pixels (red SPs), one or more light-emitting regions EA of one or more green sub-pixels (green SPs), and one or more light-emitting regions EA of one or more blue sub-pixels (blue SPs).

[0142] Reference Figure 4 In some implementations, the normal region NA may not include a light-transmitting structure, but may include a light-emitting region EA.

[0143] However, in some implementations, the first optical region OA1 and the second optical region OA2 need to include both the light-emitting region EA and the light-transmitting structure.

[0144] Therefore, the first optical region OA1 may include the light-emitting region EA and the first transmission region TA1, and the second optical region OA2 may include the light-emitting region EA and the second transmission region TA2.

[0145] The luminescent area EA and the transmissive areas (TA1, TA2) can differ depending on whether light transmission is permitted. For example, the luminescent area EA can be an area where light transmission is not permitted (e.g., light is not permitted to transmit to the back of the display panel), and the transmissive areas (TA1, TA2) can be areas where light transmission is permitted (e.g., light is permitted to transmit to the back of the display panel).

[0146] The luminescent region EA and the transmissive regions (TA1, TA2) can also differ depending on whether a specific metal layer is included. For example, as... Figure 3 The cathode electrode CE shown can be disposed in the light-emitting region EA, while the cathode electrode CE may not be disposed in the transmission regions (TA1, TA2). In some embodiments, a light-shielding layer may be disposed in the light-emitting region EA, while a light-shielding layer may not be disposed in the transmission regions (TA1, TA2).

[0147] Since the first optical region OA1 includes the first transmission region TA1 and the second optical region OA2 includes the second transmission region TA2, both the first optical region OA1 and the second optical region OA2 are regions through which light can pass.

[0148] In one embodiment, the transmittance of the first optical region OA1 and the transmittance of the second optical region OA2 can be substantially equal.

[0149] For example, the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 can have substantially the same shape or size. In another example, even when the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 have different shapes or sizes, the ratio of the first transmission region TA1 to the first optical region OA1 and the ratio of the second transmission region TA2 to the second optical region OA2 can be substantially equal. In the example, each first transmission region TA1 has the same shape and size. In the example, each second transmission region TA2 has the same shape and size.

[0150] In another embodiment, the transmittance of the first optical region OA1 and the transmittance of the second optical region OA2 may be different.

[0151] For example, the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 can have different shapes or sizes. In another example, even when the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 have substantially the same shape or size, the ratio of the first transmission region TA1 to the first optical region OA1 and the ratio of the second transmission region TA2 to the second optical region OA2 can be different from each other.

[0152] For example, in such Figure 1A , Figure 1B and Figure 1C The first optical electronic device 11, which overlaps with the first optical region OA1, is a camera, and as shown... Figure 1B and Figure 1C The second optical electronics 12 shown, which overlaps with the second optical region OA2, is an example of a sensor used to detect an image. The camera may require a much larger amount of light than the sensor.

[0153] Therefore, the transmittance of the first optical region OA1 can be greater than that of the second optical region OA2.

[0154] For example, the first transmission region TA1 of the first optical region OA1 can have a larger size than the second transmission region TA2 of the second optical region OA2. In another example, even when the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 have substantially the same size, the ratio of the first transmission region TA1 to the first optical region OA1 can be greater than the ratio of the second transmission region TA2 to the second optical region OA2.

[0155] For ease of description, the following discussion is provided for an implementation in which the transmittance (transmittance) of the first optical region OA1 is greater than that of the second optical region OA2.

[0156] In addition, such as Figure 4 The transmissive regions (TA1, TA2) shown can be called transparent regions, and the term transmittance can be referred to as transparency.

[0157] Furthermore, in the following discussion, unless otherwise explicitly stated, it is assumed that the first optical region OA1 and the second optical region OA2 are located at the upper edge of the display area DA of the display panel 110 and are arranged to be horizontally adjacent to each other, such as being arranged in the direction extending from the upper edge, as shown below. Figure 4 As shown.

[0158] Reference Figure 4The horizontal display area with a first optical region OA1 and a second optical region OA2 is called the first horizontal display area HA1, and the other horizontal display area without the first optical region OA1 and the second optical region OA2 is called the second horizontal display area HA2.

[0159] Reference Figure 4 The first horizontal display area HA1 may include a portion of the normal area NA, a first optical area OA1, and a second optical area OA2. The second horizontal display area HA2 may include only another portion of the normal area NA.

[0160] Figure 5A An example arrangement of signal lines in each of the first optical region OA1 and the normal region NA of a display panel 110 according to aspects of this disclosure is illustrated, while Figure 5B An example arrangement of signal lines in each of the second optical region OA2 and the normal region NA of a display panel 110 according to aspects of this disclosure is illustrated.

[0161] Figure 5A and Figure 5B The first horizontal display area HA1 shown is a portion of the first horizontal display area HA1 of the display panel 110, and the second horizontal display area HA2 within it is a portion of the second horizontal display area HA2 of the display panel 110.

[0162] Figure 5A The first optical region OA1 shown is a part of the first optical region OA1 of the display panel 110, and Figure 5B The second optical region OA2 shown is a part of the second optical region OA2 of the display panel 110.

[0163] Reference Figure 5A and Figure 5B The first horizontal display area HA1 may include a portion of the normal area NA, a first optical area OA1, and a second optical area OA2. The second horizontal display area HA2 may include another portion of the normal area NA.

[0164] Various types of horizontal lines (HL1, HL2) and various types of vertical lines (VLn, VL1, VL2) can be set in the display panel 110.

[0165] In some implementations, the terms "horizontal" and "vertical" are used to refer to two directions intersecting the display panel; however, it should be noted that the horizontal and vertical directions can change depending on the viewing direction. The horizontal direction can refer to, for example, the direction in which a gate line GL is set to extend, while the vertical direction can refer to, for example, the direction in which a data line DL is set to extend. Therefore, the terms horizontal and vertical are used to represent two directions.

[0166] Reference Figure 5A and Figure 5B The horizontal lines set in the display panel 110 may include a first horizontal line HL1 set in the first horizontal display area HA1 and a second horizontal line HL2 set in the second horizontal display area HA2.

[0167] The horizontal lines set in the display panel 110 can be gate lines GL. That is, the first horizontal line HL1 and the second horizontal line HL2 can be gate lines GL. Depending on the structure of one or more sub-pixels SP, the gate lines GL can include various types of gate lines.

[0168] Reference Figure 5A and Figure 5B The vertical lines set in the display panel 110 may include a typical vertical line VLn set only in the normal area NA, a first vertical line VL1 that crosses both the first optical area OA1 and the normal area NA, and a second vertical line VL2 that crosses both the second optical area OA2 and the normal area NA.

[0169] The vertical lines provided in the display panel 110 may include data lines DL, driving voltage lines DVL, etc., and may also include reference voltage lines, initialization voltage lines, etc. That is to say, a typical vertical line VLn, a first vertical line VL1, and a second vertical line VL2 may include data lines DL, driving voltage lines DVL, etc., and may also include reference voltage lines, initialization voltage lines, etc.

[0170] In some implementations, it should be noted that the term "horizontal" in the second horizontal line HL2 may simply mean that the signal is carried from the left side to the right side (or from the right side to the left side) of the display panel, and may not mean that the second horizontal line HL2 extends only in a straight line in the exactly horizontal direction. For example, in Figure 5A and Figure 5B In the diagram, although the second horizontal line HL2 is shown as a straight line, one or more of the second horizontal lines HL2 may include lines that are parallel to each other. Figure 5A and Figure 5B The illustrated configuration may include one or more curved or bent sections. Similarly, one or more first horizontal lines HL1 may also include one or more curved or bent sections.

[0171] In some implementations, it should be noted that the term "vertical" in a typical vertical line VLn may simply mean that the signal is carried from the upper portion of the display panel to the lower portion (or from the lower portion to the upper portion), and may not mean that the typical vertical line VLn extends only in a straight line in the exactly vertical direction. For example, in Figure 5A and Figure 5BIn the diagram, although a typical vertical line VLn is shown as a straight line, one or more typical vertical lines VLn can include... Figure 5A and Figure 5B The diagram illustrates one or more curved or bent sections, each with its own distinct structure. Similarly, one or more of the first vertical lines VL1 and one or more of the second vertical lines VL2 may also include one or more curved or bent sections.

[0172] Reference Figure 5A The first optical region OA1 included in the first horizontal region HA1 may include, for example, Figure 4 The diagram shows the light-emitting region EA and the first transmission region TA1. Within the first optical region OA1, each outer region of the first transmission region TA1 may include the corresponding light-emitting region EA.

[0173] Reference Figure 5A In order to improve the transmittance of the first optical region OA1, the first horizontal line HL1 can pass through the first optical region OA1 while avoiding the first transmission region TA1 in the first optical region OA1.

[0174] Therefore, each first horizontal line HL1 traversing the first optical region OA1 may include one or more curved or bent portions extending around one or more corresponding outer edges of one or more first transmission regions TA1.

[0175] Therefore, the first horizontal line HL1 disposed in the first horizontal region HA1 and the second horizontal line HL2 disposed in the second horizontal display region HA2 can have different shapes or lengths. For example, the first horizontal line HL1 that crosses the first optical region OA1 and the second horizontal line HL2 that does not cross the first optical region OA1 can have different shapes or lengths.

[0176] In addition, in order to improve the transmittance of the first optical region OA1, the first vertical line VL1 can pass through the first optical region OA1 while avoiding the first transmission region TA1 in the first optical region OA1.

[0177] Therefore, each first vertical line VL1 traversing the first optical region OA1 may include one or more curved or bent portions extending around one or more corresponding outer edges of one or more first transmission regions TA1.

[0178] Therefore, the first vertical line VL1 that crosses the first optical region OA1 and the typical vertical line VLn that is set in the normal region NA but does not cross the first optical region OA1 can have different shapes or lengths.

[0179] Reference Figure 5AThe first transmission region TA1, which is included in the first optical region OA1 in the first horizontal region HA1, can be arranged in a diagonal direction.

[0180] Reference Figure 5A In the first optical region OA1 within the first horizontal region HA1, one or more light-emitting regions EA can be disposed between two horizontally adjacent first transmission regions TA1. In the first optical region OA1 within the first horizontal region HA1, one or more light-emitting regions EA can be disposed between two vertically adjacent first transmission regions TA1.

[0181] Reference Figure 5A Each first horizontal line HL1 in the first horizontal region HA1 (e.g., each first horizontal line HL1 traversing the first optical region OA1) may include one or more curved or bent portions extending around one or more corresponding outer edges of one or more transmission regions TA1.

[0182] Reference Figure 5B The second optical region OA2, included in the first horizontal region HA1, may include a light-emitting region EA and a second transmission region TA2. Within the second optical region OA2, each outer region of the second transmission region TA2 may include a corresponding light-emitting region EA.

[0183] In one embodiment, the light-emitting region EA and the second transmission region TA2 in the second optical region OA2 can have the same characteristics as... Figure 5A The light-emitting region EA and the first transmission region TA1 in the first optical region OA1 have basically the same position and arrangement.

[0184] In another embodiment, such as Figure 5B As shown, the light-emitting region EA and the second transmission region TA2 in the second optical region OA2 can have the same characteristics as... Figure 5A The first optical region OA1 has different positions and arrangements of the light-emitting region EA and the first transmission region TA1.

[0185] For example, refer to Figure 5B The second transmission regions TA2 in the second optical region OA2 can be arranged in a horizontal direction (from left to right or from right to left). In this example, the emitting region EA may not be located between two horizontally adjacent second transmission regions TA2. Furthermore, one or more emitting regions EA in the second optical region OA2 can be located between second transmission regions TA2 that are vertically adjacent (from top to bottom or from bottom to top). For example, one or more emitting regions EA can be located between two rows of second transmission regions.

[0186] In one embodiment, when the first horizontal line HL1 traverses the second optical region OA2 and the normal region NA adjacent to the second optical region OA2 within the first horizontal region HA1, the first horizontal line HL1 may have the same characteristics as... Figure 5A The arrangement is basically the same as the first horizontal line HL1.

[0187] In another embodiment, such as Figure 5B As shown, when the first horizontal line HL1 passes through the second optical region OA2 and the normal region NA adjacent to the second optical region OA2 within the first horizontal region HA1, the first horizontal line HL1 can have the same characteristics as... Figure 5A The first horizontal line HL1 has a different arrangement.

[0188] This is because Figure 5B The luminescent region EA and the second transmission region TA2 in the second optical region OA2 have the same characteristics as... Figure 5A The first optical region OA1 has different positions and arrangements of the light-emitting region EA and the first transmission region TA1.

[0189] Reference Figure 5B When the first horizontal line HL1 crosses the second optical region OA2 and the normal region NA adjacent to the second optical region OA2 in the first horizontal region HA1, the first horizontal line HL1 can extend in a straight line between the vertically adjacent second transmission regions TA2 without any curved or bent portions.

[0190] For example, a first horizontal line HL1 may have one or more curved or bent portions in a first optical region OA1, but may not have curved or bent portions in a second optical region OA2.

[0191] In order to improve the transmittance of the second optical region OA2, the second vertical line VL2 can pass through the second optical region OA2 while avoiding the second transmission region TA2 in the second optical region OA2.

[0192] Therefore, each second vertical line VL2 traversing the second optical region OA2 may include one or more curved or bent portions extending around one or more corresponding outer edges of one or more second transmission regions TA2.

[0193] Therefore, the second vertical line VL2 that crosses the second optical region OA2 and the typical vertical line VLn that is set in the normal region NA and does not cross the second optical region OA2 can have different shapes or lengths.

[0194] like Figure 5AAs shown, each or more of the first horizontal lines HL1 that traverse the first optical region OA1 may have one or more curved or bent portions extending around one or more corresponding outer edges of one or more first transmission regions TA1.

[0195] Therefore, the length of the first horizontal line HL1 that crosses the first optical region OA1 and the second optical region OA2 can be slightly longer than the length of the second horizontal line HL2 that is only set in the normal region NA and does not cross the first optical region OA1 and the second optical region OA2.

[0196] Therefore, the resistance of the first horizontal line HL1 that crosses the first optical region OA1 and the second optical region OA2 (referred to as the first resistance) can be slightly greater than the resistance of the second horizontal line HL2 that is only set in the normal region NA and does not cross the first optical region OA1 and the second optical region OA2 (referred to as the second resistance).

[0197] Reference Figure 5A and Figure 5B According to the exemplary light-transmitting structure, the first optical region OA1, which at least partially overlaps with the first optical electronics 11, includes a first transmission region TA1, while the second optical region OA2, which at least partially overlaps with the second optical electronics 12, includes a second transmission region TA2. Therefore, the number of sub-pixels per unit area in each of the first optical region OA1 and the second optical region OA2 can be less than the number of sub-pixels per unit area in the normal region NA.

[0198] Therefore, the number of sub-pixels connected to each or one or more of the first horizontal lines HL1 that cross the first optical region OA1 and the second optical region OA2 may be different from the number of sub-pixels connected to each or one or more of the second horizontal lines HL2 that are only set in the normal region NA and do not cross the first optical region OA1 and the second optical region OA2.

[0199] The number of sub-pixels connected to each or one or more of the first horizontal lines HL1 that cross the first optical region OA1 and the second optical region OA2 (referred to as the first number) may be less than the number of sub-pixels connected to each or one or more of the second horizontal lines HL2 that are only set in the normal region NA and do not cross the first optical region OA1 and the second optical region OA2 (referred to as the second number).

[0200] The difference between the first quantity and the second quantity can vary depending on the difference between the resolution of each of the first optical region OA1 and the second optical region OA2 and the resolution of the normal region NA. For example, as the difference between the resolution of each of the first optical region OA1 and the second optical region OA2 and the resolution of the normal region NA increases, the difference between the first quantity and the second quantity can increase.

[0201] As described above, since the number of sub-pixels connected to each or one or more of the first horizontal lines HL1 that cross the first optical region OA1 and the second optical region OA2 (the first number) is less than the number of sub-pixels connected to each or one or more of the second horizontal lines HL2 that are only set in the normal region NA and do not cross the first optical region OA1 and the second optical region OA2 (the second number), the area where the first horizontal line HL1 overlaps with one or more other electrodes or lines adjacent to the first horizontal line HL1 can be smaller than the area where the second horizontal line HL2 overlaps with one or more other electrodes or lines adjacent to the second horizontal line HL2.

[0202] Therefore, the parasitic capacitance formed between the first horizontal line HL1 and one or more other electrodes or lines adjacent to the first horizontal line HL1 (referred to as the first capacitance) can be much smaller than the parasitic capacitance formed between the second horizontal line HL2 and one or more other electrodes or lines adjacent to the second horizontal line HL2 (referred to as the second capacitance).

[0203] Considering the relationship between the first and second resistors (first resistor ≥ second resistor) and the relationship between the first and second capacitors (first capacitor << second capacitor), the resistance-capacitance (RC) value of the first horizontal line HL1 crossing the first optical region OA1 and the second optical region OA2 (referred to as the first RC value) can be much smaller than the RC value of the second horizontal line HL2, which is only set in the normal region NA and does not cross the first and second optical regions OA1 and OA2 (referred to as the second RC value). Therefore, in this example, the first RC value is much smaller than the second RC value (i.e., the first RC value << the second RC value).

[0204] Due to this difference between the first RC value of the first horizontal line HL1 and the second RC value of the second horizontal line HL2 (which is called the RC load difference), the signal transmission characteristics through the first horizontal line HL1 can be different from those through the second horizontal line HL2.

[0205] Figure 6 and Figure 7 This is an example cross-sectional view of the normal area, the first optical area, and the second optical area included in the display area of ​​a display panel according to aspects of this disclosure.

[0206] Figure 6 The example shown is a display panel 110 in which the touch sensor is implemented as a touch panel external to the display panel 110, and Figure 7 The display panel 110 is shown as an example in which the touch sensor TS is implemented inside the display panel 110.

[0207] Figure 6 and Figure 7 Each of the figures shows an exemplary cross-sectional view of the normal region NA, the first optical region OA1, and the second optical region OA2 included in the display region DA.

[0208] First, refer to Figure 6 and Figure 7 Describe the stacked structure of the normal region NA. Each luminescent region EA included in the first optical region OA1 and the second optical region OA2 may have the same stacked structure as the normal region NA or the luminescent region EA in the normal region NA.

[0209] Reference Figure 6 and Figure 7 The substrate SUB may include a first substrate SUB1, an interlayer insulating layer IPD, and a second substrate SUB2. The interlayer insulating layer IPD may be inserted between the first substrate SUB1 and the second substrate SUB2. Because the substrate SUB includes the first substrate SUB1, the interlayer insulating layer IPD, and the second substrate SUB2, the substrate SUB can prevent or reduce the penetration of moisture. The first substrate SUB1 and the second substrate SUB2 may be, for example, polyimide (PI) substrates. The first substrate SUB1 may be referred to as the main PI substrate, and the second substrate SUB2 may be referred to as the secondary PI substrate.

[0210] Reference Figure 6 and Figure 7 Various types of patterns such as ACT, SD1, GATE, various types of insulating layers MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, PAS0, and various types of metal patterns TM, GM, ML1, ML2, etc., for setting one or more transistors such as driving transistors DRT, can be set on or above the substrate SUB.

[0211] Reference Figure 6 and Figure 7 The multi-buffer layer MBUF can be disposed on the second substrate SUB2, and the first active buffer layer ABUF1 can be disposed on the multi-buffer layer MBUF.

[0212] The first metal layer ML1 and the second metal layer ML2 can be disposed on the first active buffer layer ABUF1. The first metal layer ML1 and the second metal layer ML2 can be, for example, a light-shielding layer LS for light blocking.

[0213] The second active buffer layer ABUF2 can be disposed on the first metal layer ML1 and the second metal layer ML2. The active layer ACT that drives the transistor DRT can be disposed on the second active buffer layer ABUF2.

[0214] The gate insulating layer GI can be configured to cover the active layer ACT.

[0215] The gate (GATE) of the driving transistor (DRT) can be disposed on the gate insulating layer (GI). Furthermore, at a location different from where the driving transistor (DRT) is disposed, the gate material layer (GM) can be disposed together with the gate (GATE) of the driving transistor (DRT) on the gate insulating layer (GI).

[0216] The first interlayer insulating layer ILD1 can be configured to cover the gate (GATE) and the gate material layer (GM). A metal pattern (TM) can be disposed on the first interlayer insulating layer ILD1. The metal pattern (TM) can be located at a different position than where the driving transistor (DRT) is formed. The second interlayer insulating layer ILD2 can be configured to cover the metal pattern (TM) on the first interlayer insulating layer ILD1.

[0217] Two first source-drain electrode patterns SD1 can be disposed on the second interlayer insulating layer ILD2. One of the two first source-drain electrode patterns SD1 can be the source node of the driving transistor DRT, and the other can be the drain node of the driving transistor DRT.

[0218] The two first source-drain electrode patterns SD1 can be electrically connected to the first and second sides of the active layer ACT through contact holes formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1 and the gate insulating layer GI, respectively.

[0219] The portion of the active layer ACT that overlaps with the gate GATE can be used as a channel region. One of the two first source-drain electrode patterns SD1 can be connected to the first side of the channel region of the active layer ACT, and the other of the two first source-drain electrode patterns SD1 can be connected to the second side of the channel region of the active layer ACT.

[0220] The passivation layer PAS0 can be configured to cover two first source-drain electrode patterns SD1. A planarization layer PLN can be disposed on the passivation layer PAS0. The planarization layer PLN may include a first planarization layer PLN1 and a second planarization layer PLN2.

[0221] The first planarization layer PLN1 can be set on the passivation layer PAS0.

[0222] The second source-drain electrode pattern SD2 can be disposed on the first planarization layer PLN1. The second source-drain electrode pattern SD2 can be connected to one of the two first source-drain electrode patterns SD1 (corresponding to) through contact holes formed in the first planarization layer PLN1 and the passivation layer PAS0. Figure 3 The second node N2 of the driving transistor DRT in the sub-pixel SP.

[0223] The second planarization layer PLN2 can be configured to cover the second source-drain electrode pattern SD2. The light-emitting element ED can be disposed on the second planarization layer PLN2.

[0224] According to the example stacked structure of the light-emitting element ED, the anode electrode AE ​​can be disposed on the second planarization layer PLN2. The anode electrode AE ​​can be electrically connected to the second source-drain electrode pattern SD2 through contact holes formed in the second planarization layer PLN2.

[0225] The dam can be configured to cover a portion of the anode electrode AE. The portion of the dam corresponding to the light-emitting area EA of the sub-pixel SP can be open.

[0226] A portion of the anode electrode AE ​​can be exposed through the opening (open portion) of the dam bank. The luminescent layer EL can be located on the side surface of the dam bank and within the opening (open portion) of the dam bank. All or at least a portion of the luminescent layer EL can be located between adjacent dams.

[0227] At the opening of the dam bank, the light-emitting layer EL can contact the anode electrode AE. The cathode electrode CE can be disposed on the light-emitting layer EL.

[0228] As described above, a light-emitting element ED can be formed by including an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE. The light-emitting layer EL may include a layer of organic material.

[0229] The encapsulation layer ENCAP can be placed on the stack of light-emitting elements (EDs).

[0230] The ENCAP encapsulation layer can have a single-layer structure or a multi-layer structure. For example, Figure 6 and Figure 7 As shown, the encapsulation layer ENCAP may include a first encapsulation layer PAS1, a second encapsulation layer PCL, and a third encapsulation layer PAS2.

[0231] The first encapsulation layer PAS1 and the third encapsulation layer PAS2 can be inorganic material layers, for example, and the second encapsulation layer PCL can be an organic material layer, for example. Among the first encapsulation layer PAS1, the second encapsulation layer PCL, and the third encapsulation layer PAS2, the second encapsulation layer PCL can be the thickest and is used as a planarization layer.

[0232] The first encapsulation layer PAS1 can be disposed on the cathode electrode CE and can be positioned closest to the light-emitting element ED. The first encapsulation layer PAS1 can include an inorganic insulating material that can be deposited using low-temperature deposition. For example, the first encapsulation layer PAS1 can include, but is not limited to, silicon nitride (SiN). x ), silicon dioxide (SiO) x Materials include silicon oxynitride (SiON), aluminum oxide (Al2O3), etc. Since the first encapsulation layer PAS1 can be deposited in a low-temperature atmosphere, it can prevent damage to the light-emitting layer EL, which includes organic materials susceptible to high-temperature atmospheres, during the deposition process.

[0233] The second encapsulation layer PCL can have a smaller area or size than the first encapsulation layer PAS1. For example, the second encapsulation layer PCL can be configured to expose the ends or edges of the first encapsulation layer PAS1. The second encapsulation layer PCL can serve as a buffer layer to alleviate stress between corresponding layers when the display device 100 is curved or bent, and can also be used to enhance planarization performance. For example, the second encapsulation layer PCL can include organic insulating materials such as acrylic resin, epoxy resin, polyimide, polyethylene, silicon-oxygen carbon (SiOC), etc. For example, an inkjet printing method can be used to configure the second encapsulation layer PCL.

[0234] A third encapsulation layer, PAS2, can be disposed above a substrate SUB on which a second encapsulation layer, PCL, is disposed, such that the third encapsulation layer, PAS2, covers the top and side surfaces of both the second encapsulation layer, PCL, and the first encapsulation layer, PAS1. The third encapsulation layer, PAS2, can minimize or prevent the penetration of external moisture or oxygen into the first encapsulation layer, PAS1, and the second encapsulation layer, PCL. For example, the third encapsulation layer, PAS2, may include an inorganic insulating material, such as silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), etc.

[0235] Reference Figure 7 In the example where the touch sensor TS is embedded in the display panel 110, the touch sensor TS can be disposed on the encapsulation layer ENCAP. The structure of the touch sensor will be described in detail below.

[0236] The touch buffer layer (T-BUF) can be placed on the encapsulation layer (ENCAP). The touch sensor (TS) can be placed on the touch buffer layer (T-BUF).

[0237] The touch sensor TS may include a touch sensor metal TSM located in different layers and at least one bridging metal BRG.

[0238] The interlayer insulating layer (T-ILD) can be placed between the touch sensor metal (TSM) and the bridging metal (BRG).

[0239] For example, the touch sensor metal TSM may include a first touch sensor metal TSM, a second touch sensor metal TSM, and a third touch sensor metal TSM disposed adjacent to each other. In an embodiment where the third touch sensor metal TSM is disposed between the first and second touch sensor metal TSMs, and the first and second touch sensor metal TSMs need to be electrically connected to each other, the first and second touch sensor metal TSMs can be electrically connected to each other through a bridging metal BRG located on different layers. The bridging metal BRG can be electrically insulated from the third touch sensor metal TSM through a touch layer interlayer insulating layer (T-ILD).

[0240] When the touch sensor TS is disposed on the display panel 110, chemical solutions (e.g., developers or etchants) used in the corresponding processes or external moisture may be generated or introduced. In some embodiments, by disposing the touch sensor TS on the touch buffer layer T-BUF, it is possible to prevent chemical solutions or moisture from penetrating into the light-emitting layer EL, which includes organic materials, during the manufacturing process of the touch sensor TS. Therefore, the touch buffer layer T-BUF can prevent damage to the light-emitting layer EL, which is susceptible to chemical solutions or moisture.

[0241] To prevent damage to the light-emitting layer EL, which contains organic materials susceptible to high temperatures, the touch buffer layer T-BUF can be formed at a low temperature below or equal to a predetermined temperature (e.g., 100 degrees Celsius (°C)) and is formed using an organic insulating material with a low dielectric constant of 1 to 3. For example, the touch buffer layer T-BUF may include acrylic-based materials, epoxy resin-based materials, or siloxane-based materials. When the display device 100 is bent, the encapsulation layer ENCAP may be damaged, and the touch sensor metal located on the touch buffer layer T-BUF may crack or break. However, in this application, even when the display device 100 is bent, the touch buffer layer T-BUF, as an organic insulating material with planarization properties, is able to prevent damage to the encapsulation layer ENCAP and / or cracking or breakage of the metal (TSM, BRG) included in the touch sensor TS.

[0242] The protective layer PAC can be configured to cover the touch sensor TS. The protective layer PAC can be, for example, an organic insulating layer.

[0243] Next, we will refer to Figure 6 and Figure 7 Describe the stacked structure of the first optical region OA1.

[0244] Reference Figure 6 and Figure 7 The emitting region EA of the first optical region OA1 can have the same stacked structure as the stacked structure in the normal region NA. Therefore, in the following discussion, the emitting region EA in the first optical region OA1 will not be described again, and the stacked structure of the first transmission region TA1 in the first optical region OA1 will be described in detail below.

[0245] In some embodiments, the cathode electrode CE may be disposed in the light-emitting region EA included in the normal region NA and the first optical region OA1, but may not be disposed in the first transmission region TA1 in the first optical region OA1. For example, the first transmission region TA1 in the first optical region OA1 may correspond to the opening of the cathode electrode CE.

[0246] Furthermore, in some embodiments, the light-shielding layer LS, which includes at least one of the first metal layer ML1 and the second metal layer ML2, may be disposed in the light-emitting region EA included in the normal region NA and the first optical region OA1, but may not be disposed in the first transmission region TA1 in the first optical region OA1. For example, the first transmission region TA1 in the first optical region OA1 may correspond to the opening of the light-shielding layer LS.

[0247] The substrate SUB and various types of insulating layers (MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, PAS0, PLN (PLN1, PLN2), BANK, ENCAP (PAS1, PCL, PAS2), T-BUF, T-ILD, PAC) disposed in the light-emitting region EA included in the normal region NA and the first optical region OA1 can be disposed in the first transmission region TA1 in the first optical region OA1 in a similar, substantially similar, or analogous manner.

[0248] However, in some embodiments, all or one or more of the one or more material layers (e.g., one or more metal material layers and / or one or more semiconductor layers) with electrical properties, other than insulating materials or layers, provided in the light-emitting region EA included in the normal region NA and the first optical region OA1 may not be provided in the first transmission region TA1 in the first optical region OA1.

[0249] For example, refer to Figure 6 and Figure 7 All or one or more of the metal material layers (ML1, ML2, GATE, GM, TM, SD1, SD2) associated with at least one transistor and semiconductor layer ACT may not be disposed in the first transmission region TA1.

[0250] In addition, refer to Figure 6 and Figure 7 In some embodiments, the anode electrode AE ​​and cathode electrode CE included in the light-emitting element ED may not be disposed in the first transmission region TA1. In some embodiments, the light-emitting layer EL of the light-emitting element ED may or may not be disposed in the first transmission region TA1, depending on design requirements.

[0251] In addition, refer to Figure 7 In some embodiments, the touch sensor metal TSM and bridging metal BRG included in the touch sensor TS may not be disposed in the first transmission region TA1 in the first optical region OA1.

[0252] Therefore, since the material layer with electrical properties (e.g., one or more metal material layers and / or one or more semiconductor layers) is not disposed in the first transmission region TA1 of the first optical region OA1, the light transmittance of the first transmission region TA1 in the first optical region OA1 can be provided or improved. As a result, the first optoelectronic device 11 can perform a predetermined function (e.g., image sensing) by receiving light transmitted through the first transmission region TA1.

[0253] In some embodiments, since all or one or more of the first transmission regions TA1 in the first optical region OA1 overlap with the first optical electronic device 11, enabling the first optical electronic device 11 to operate normally, it is desirable to further increase the transmittance of the first transmission regions TA1 in the first optical region OA1.

[0254] In order to achieve the above objective, in the display panel 110 of the display device 100 according to aspects of the present disclosure, a transmittance enhancement structure TIS can be provided to the first transmission region TA1 in the first optical region OA1.

[0255] Reference Figure 6 and Figure 7 The multiple insulating layers included in the display panel 110 may include at least one buffer layer (MBUF, ABUF1, ABUF2) between at least one substrate (SUB1, SUB2) and at least one transistor (DRT, SCT), at least one planarization layer (PLN1, PLN2) between the transistor DRT and the light-emitting element ED, at least one encapsulation layer ENCAP on the light-emitting element ED, etc.

[0256] Reference Figure 7 The multiple insulating layers included in the display panel 110 may also include a touch buffer layer T-BUF and a touch interlayer insulating layer T-ILD located on the encapsulation layer ENCAP.

[0257] Reference Figure 6 and Figure 7 The first transmission region TA1 in the first optical region OA1 may have the following structure: the first planarization layer PLN1 and the passivation layer PAS0 have recessed portions extending downward from their respective surfaces as a transmittance enhancement structure TIS.

[0258] Reference Figure 6 and Figure 7 Among the multiple insulating layers, the first planarization layer PLN1 may include at least one recess (e.g., groove, trench, recessed portion, protrusion, etc.). The first planarization layer PLN1 may be, for example, an organic insulating layer.

[0259] In an example where the first planarization layer PLN1 has a recessed portion extending downward from its surface, the second planarization layer PLN2 can be substantially used to provide planarization. In one embodiment, the second planarization layer PLN2 may also have a recessed portion extending downward from its surface. In this embodiment, the second encapsulation layer PCL can be substantially used to provide planarization.

[0260] Reference Figure 6 and Figure 7 The recessed portions of the first planarization layer PLN1 and the passivation layer PAS0 can pass through the insulating layer used to form the transistor DRT (such as the first interlayer insulating layer ILD, the second interlayer insulating layer ILD2, the gate insulating layer GI, etc.) and the buffer layer located below the insulating layer (such as the first active buffer layer ABUF1, the second active buffer layer ABUF2, the multi-buffer layer MBUF, etc.) and extend to the upper portion of the second substrate SUB2.

[0261] Reference Figure 6 and Figure 7 The substrate SUB may include at least one recessed or sunken portion as a transmittance enhancement structure (TIS). For example, in the first transmission region TA1, the upper portion of the second substrate SUB2 may be recessed or sunken downwards, or the second substrate SUB2 may be perforated.

[0262] Reference Figure 6 and Figure 7The first encapsulation layer PAS1 and the second encapsulation layer PCL included in the ENCAP encapsulation layer can also have a transmittance enhancement structure TIS, wherein the first encapsulation layer PAS1 and the second encapsulation layer PCL have recessed portions extending downward from their respective bottom surfaces. The second encapsulation layer PCL can be, for example, an organic insulating layer.

[0263] Reference Figure 7 To protect the touch sensor TS, the protective layer PAC can be configured to cover the touch sensor TS on the encapsulation layer ENCAP.

[0264] Reference Figure 7 The protective layer PAC may have at least one recess (e.g., groove, trench, recessed portion, protrusion, etc.) in the portion overlapping with the first transmission region TA1 as a transmittance-enhancing structure TIS. The protective layer PAC may be, for example, an organic insulating layer.

[0265] Reference Figure 7 The touch sensor TS may include one or more touch sensor metal TSMs having a mesh type. In the example where the touch sensor metal TSM is formed as a mesh type, multiple openings may be formed in the touch sensor metal TSM. Each of the multiple openings may be positioned to correspond to the light-emitting area EA of the sub-pixel SP.

[0266] In order to make the first optical region OA1 have a higher transmittance than the normal region NA, the area or size of the touch sensor metal TSM per unit area in the first optical region OA1 can be smaller than the area or size of the touch sensor metal TSM per unit area in the normal region NA.

[0267] Reference Figure 7 In some embodiments, the touch sensor TS may be located in the light-emitting area EA of the first optical area OA1, but may not be located in the first transmission area TA1 of the first optical area OA1.

[0268] Next, we will refer to Figure 6 and Figure 7 Describe the stacked structure of the second optical region OA2.

[0269] Reference Figure 6 and Figure 7 The emitting region EA of the second optical region OA2 can have the same stacked structure as the normal region NA. Therefore, in the following discussion, the emitting region EA in the second optical region OA2 will no longer be described again, but the stacked structure of the second transmission region TA2 in the second optical region OA2 will be described in detail.

[0270] In some embodiments, the cathode electrode CE may be disposed in the light-emitting region EA included in the normal region NA and the second optical region OA2, but may not be disposed in the second transmission region TA2 of the second optical region OA2. For example, the second transmission region TA2 in the second optical region OA2 may correspond to the opening of the cathode electrode CE.

[0271] Furthermore, in some embodiments, the light-shielding layer LS, which includes at least one of the first metal layer ML1 and the second metal layer ML2, may be disposed in the light-emitting region EA included in the normal region NA and the second optical region OA2, but may not be disposed in the second transmission region TA2 in the second optical region OA2. For example, the second transmission region TA2 in the second optical region OA2 may correspond to the opening of the light-shielding layer LS.

[0272] In an example where the transmittance of the second optical region OA2 is the same as that of the first optical region OA1, the stacked structure of the second transmission region TA2 in the second optical region OA2 can be the same as the stacked structure of the first transmission region TA1 in the first optical region OA1.

[0273] In another example where the transmittance of the second optical region OA2 is different from that of the first optical region OA1, the stacked structure of the second transmission region TA2 in the second optical region OA2 may be at least partially different from the stacked structure of the first transmission region TA1 in the first optical region OA1.

[0274] For example, such as Figure 6 and Figure 7 As shown, in some embodiments, when the transmittance of the second optical region OA2 is lower than that of the first optical region OA1, the second transmission region TA2 in the second optical region OA2 may not have a transmittance enhancement structure (TIS). As a result, the first planarization layer PLN1 and the passivation layer PAS0 may not be recessed or sunken. Furthermore, the width of the second transmission region TA2 in the second optical region OA2 may be smaller than the width of the first transmission region TA1 in the first optical region OA1.

[0275] The substrate SUB and various types of insulating layers (MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, PAS0, PLN (PLN1, PLN2), BANK, ENCAP (PAS1, PCL, PAS2), T-BUF, T-ILD, PAC) disposed in the light-emitting region EA included in the normal region NA and the second optical region OA2 can be disposed in the second transmission region TA2 in the second optical region OA2 in an equivalent, substantially equivalent, or similar manner.

[0276] However, in some embodiments, all or one or more of the electrically conductive layers (e.g., one or more metal material layers and / or optical region semiconductor layers) disposed in the light-emitting region EA, which is included in the normal region NA and the second optical region OA2, may not be disposed in the second transmission region TA2 in the second optical region OA2.

[0277] For example, refer to Figure 6 and Figure 7 All or one or more of the metal material layers (ML1, ML2, GATE, GM, TM, SD1, SD2) associated with at least one transistor and semiconductor layer ACT may not be disposed in the second transmission region TA2 in the second optical region OA2.

[0278] In addition, refer to Figure 6 and Figure 7 In some embodiments, the anode electrode AE ​​and cathode electrode CE included in the light-emitting element ED may not be disposed in the second transmission region TA2. In some embodiments, the light-emitting layer EL of the light-emitting element ED may or may not be disposed in the second transmission region TA2, depending on design requirements.

[0279] In addition, refer to Figure 7 In some embodiments, the touch sensor metal TSM and bridging metal BRG included in the touch sensor TS may not be disposed in the second transmission region TA2 in the second optical region OA2.

[0280] Therefore, since the material layer with electrical properties (e.g., one or more metal material layers, and / or one or more semiconductor layers) is not disposed in the second transmission region TA2 of the second optical region OA2, the light transmittance of the second transmission region TA2 in the second optical region OA2 can be provided or improved. As a result, the second optoelectronic device 12 can perform a predefined function (e.g., detecting an object or human body, or detecting external lighting) by receiving light transmitted through the second transmission region TA2.

[0281] Figure 8 This is an example cross-sectional view of the outer edge of the display panel according to aspects of this disclosure.

[0282] For the sake of brevity, Figure 8 The diagram illustrates a single substrate SUB comprising a first substrate SUB1 and a second substrate SUB2, and also illustrates, in a simplified manner, a layer or portion located below the embankment BANK. Similarly, Figure 8An example is shown of a single planarization layer PLN comprising a first planarization layer PLN1 and a second planarization layer PLN2, and a single interlayer insulating layer INS comprising a second interlayer insulating layer ILD2 and a first interlayer insulating layer ILD1 located below the planarization layer PLN.

[0283] Reference Figure 8 The first encapsulation layer PAS1 can be disposed on the cathode electrode CE and positioned closest to the light-emitting element ED. The second encapsulation layer PCL can have a smaller area or size than the first encapsulation layer PAS1. For example, the second encapsulation layer PCL can be configured to expose both ends or edges of the first encapsulation layer PAS1.

[0284] The third encapsulation layer PAS2 can be disposed above the substrate SUB on which the second encapsulation layer PCL is disposed, such that the third encapsulation layer PAS2 covers the top surface and side surface of the second encapsulation layer PCL and the first encapsulation layer PAS1 respectively.

[0285] The third encapsulation layer PAS2 can minimize or prevent external moisture or oxygen from penetrating into the first encapsulation layer PAS1 and the second encapsulation layer PCL.

[0286] Reference Figure 8 To prevent the encapsulation layer ENCAP from collapsing, the display panel 110 may include one or more dams (DAM1, DAM2) at or near the end or edge of the inclined surface SLP of the encapsulation layer ENCAP. One or more dams (DAM1, DAM2) may exist at or near the boundary point between the display area DA and the non-display area NDA.

[0287] One or more dams (DAM1, DAM2) may include DFP made of the same material as the embankment BANK.

[0288] Reference Figure 8 In one embodiment, the second encapsulation layer PCL, comprising organic material, may be located only inside the first dam DAM1, which is positioned closest to the inclined surface SLP of the encapsulation layer ENCAP. For example, the second encapsulation layer PCL may not be located on all dams (DAM1, DAM2). In another embodiment, the second encapsulation layer PCL, comprising organic material, may be located at least on the first dam DAM1 of the first dam DAM1 and the second dam DAM2.

[0289] For example, the second encapsulation layer PCL may extend to all or at least a portion of the upper portion of the first dam DAM1. In another embodiment, the second encapsulation layer PCL may extend beyond the upper portion of the first dam DAM1 and extend to all or at least a portion of the upper portion of the second dam DAM2.

[0290] Reference Figure 8 ,like Figure 2 The touch drive circuit 260 shown is electrically connected to a touch pad TP which can be disposed on a portion of the substrate SUB located outside one or more dams (DAM1, DAM2).

[0291] The touch line TL can electrically connect the touch sensor metal TSM or bridging metal BRG contained in the touch electrode set in the display area DA or used as the touch electrode to the touch pad TP.

[0292] One end or edge of the touch line TL can be electrically connected to the touch sensor metal TSM or the bridging metal BRG, and the other end or edge of the touch line TL can be electrically connected to the touch pad TP.

[0293] The touch line TL can extend downward along the inclined surface SLP of the ENCAP package layer, along the corresponding upper portion of the dam (DAM1, DAM2), and extend to the touch pad TP located on the outside of the dam (DAM1, DAM2).

[0294] Reference Figure 8 In one embodiment, the touch line TL can be a bridging metal BRG. In another embodiment, the touch line TL can be a touch sensor metal TSM.

[0295] Figure 9 An example pixel circuit of a display device 100 according to aspects of the present disclosure is illustrated.

[0296] Reference Figure 9 In some embodiments, the display device 100 may include a plurality of sub-pixels SP, and each sub-pixel SP may include a light-emitting element ED, a driving transistor DRT, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a storage capacitor Cst, etc.

[0297] Reference Figure 9 Describe the components included in the pixel circuit.

[0298] The light-emitting element ED may include an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE.

[0299] The driving transistor DRT may include a first node N1, a second node N2 and a third node N3, and may be a transistor used to drive a light-emitting element ED.

[0300] The first transistor T1 can be controlled by the first scan signal SCAN1, and control the connection between the first node N1 and the second node N2.

[0301] The second transistor T2 can be controlled by the second scan signal SCAN2, and it also controls the connection between the third node N3 and the data line DL. The data voltage Vdata can be applied to the data line DL.

[0302] The third transistor T3 can be controlled by the light emission control signal EM, which in turn controls the connection between the third node N3 and the drive voltage line DVL. The drive voltage ELVDD can be applied to the drive voltage line DVL.

[0303] The fourth transistor T4 can be controlled by the light emission control signal EM, and controls the connection between the anode electrode AE ​​and the second node N2.

[0304] The fifth transistor T5 can be controlled by the third scan signal SCAN3, which also controls the connection between the initialization signal line VINIL and the second node N2. The initialization voltage VINI, used to initialize the voltage of the second node N2 or the first node N1, can be applied to the initialization signal line VINIL.

[0305] The sixth transistor T6 controls the connection between the anode reset voltage line VARL and the anode electrode AE. The anode reset voltage VAR, used to reset the voltage of the anode electrode AE ​​of the light-emitting element ED, can be applied to the anode reset voltage line VARL.

[0306] The storage capacitor Cst can be connected between the first node N1 and the drive voltage line DVL.

[0307] Reference Figure 9 This will describe an example connection between pixel circuits and signal lines.

[0308] The first scan signal SCAN1 can be applied to the gate node of the first transistor T1 through the first scan line SCL1. For example, the gate node of the first transistor T1 can be electrically connected to the first scan line SCL1.

[0309] The second scan signal SCAN2 can be applied to the gate node of the second transistor T2 through the second scan line SCL2. The gate node of the second transistor T2 can be electrically connected to the second scan line SCL2.

[0310] The third scan signal SCAN3 can be applied to the gate node of the fifth transistor T5 through the third scan line SCL3. The gate node of the fifth transistor T5 can be electrically connected to the third scan line SCL3.

[0311] The light emission control signal EM can be applied together to the gate nodes of the third transistor T3 and the fourth transistor T4 via the light emission control line EML. For example, the gate nodes of the third transistor T3 and the fourth transistor T4 can be connected together to the light emission control line EML.

[0312] Reference Figure 9 A third scan signal SCAN3′, different from the third scan signal SCAN3 applied to the gate node of the fifth transistor T5, can be applied to the gate node of the sixth transistor T6 via another third scan line SCL3′. The gate node of the sixth transistor T6 can be electrically connected to the other third scan line SCL3′.

[0313] Another third scan signal SCAN3′ applied to the gate node of the sixth transistor T6 can be the third scan signal SCAN3 applied to the gate node of another fifth transistor T5 of another sub-pixel SP.

[0314] Another third scan line SCL3′ connected to the gate node of the sixth transistor T6 can be different from the third scan line SCL3 connected to the gate node of the fifth transistor T5. For example, another third scan signal SCAN3′ applied to the gate node of the sixth transistor T6 can be the third scan signal SCAN3 applied to the gate node of another fifth transistor T5 of another sub-pixel SP.

[0315] In one embodiment, all seven transistors (DRT and T1 to T6) included in each sub-pixel SP can be p-type transistors or n-type transistors. In another embodiment, at least one of the seven transistors (DRT and T1 to T6) can be a p-type transistor or an n-type transistor, and the remaining transistors can be n-type transistors or p-type transistors.

[0316] For example, such as Figure 9 As shown, among the seven transistors (DRT, T1 to T6), the first transistor T1 can be an n-type transistor, and the remaining six transistors (DRT, T2 to T6) can be p-type transistors.

[0317] Reference Figure 9 In the display device 100 according to aspects of the present disclosure, the display panel 110 may further include a shielding metal BSM disposed below the driving transistor DRT of each sub-pixel SP.

[0318] Reference Figure 9 The shielding metal BSM can be configured to avoid multiple first transmission regions TA1 in the first optical region OA1. This ensures that the transmittance of the multiple first transmission regions TA1 in the first optical region OA1 is not reduced and protects the channel of the driving transistor DRT.

[0319] Reference Figure 9 The shielding metal BSM can be electrically connected to the drive voltage line DVL. Therefore, it is possible to improve the driving stability of the drive transistor DRT, for example, stability related to the body effect.

[0320] Figure 9 The shielded metal BSM can correspond to Figure 6 and Figure 7 The light-shielding layer LS.

[0321] In the following description, an exemplary arrangement of a first horizontal line HL1 traversing a signal line passing through a first optical region OA1 will be described. The first horizontal line HL1 traversing the first optical region OA1 may also traverse a second optical region OA2. For ease of description, the arrangement of the first horizontal line in the first optical region OA1 will be described below. However, it should be noted that the arrangement of the first horizontal line in the first optical region OA1 can be applied substantially equivalently to the arrangement of the first horizontal line in the second optical region OA2. Therefore, it should be understood that the scope of this disclosure includes embodiments where the first horizontal line is arranged in the second optical region OA2.

[0322] Figure 10 An exemplary first optical region OA1 of a display device 100 according to aspects of the present disclosure is illustrated, as shown in the first optical region OA1 of the aforementioned figures.

[0323] As described above, the display panel 110 of the display device 100 according to aspects of the present disclosure may include a display area DA and a non-display area NDA, and includes a plurality of sub-pixels SP and a plurality of signal lines.

[0324] In addition, the display area DA of the display panel 110 may include a first optical area OA1 and a normal area NA located outside the first optical area OA1.

[0325] The first optical region OA1 may include multiple first transmission regions TA1.

[0326] In the first optical region OA1, multiple sub-pixels SP can be disposed in the region other than the multiple first transmission regions TA1. This can be represented as the first optical region OA1 including multiple light-emitting regions EA located outside the multiple first transmission regions TA1.

[0327] Multiple sub-pixels SP can be set in the normal area NA. Therefore, the normal area NA can include multiple emitting areas EA.

[0328] As described above, the first optical electronic device 11 may be located below or in the lower portion of the display panel 110 and overlap with at least a portion of the first optical region OA1 included in the display region DA.

[0329] Reference Figure 10For example, the first optical region OA1 may include an inner region IA and a border region BA. The border region BA may be an annular region surrounding the inner region IA. The border region BA may be the boundary between the inner region IA and the normal region NA.

[0330] Reference Figure 10 Multiple first transmission regions TA1 can exist in the border region BA and the inner region IA included in the first optical region OA1.

[0331] Reference Figure 10 In one implementation, the border region BA may have the same structure as the inner region IA (e.g., the same subpixel arrangement and / or the same line arrangement).

[0332] In another embodiment, the border region BA may have a different structure than the normal region NA and the inner region IA (e.g., a different subpixel arrangement, and / or a different line arrangement). For example, the border region BA may have a higher resolution (number of subpixels per unit area) than the inner region IA and a lower resolution than the normal region NA.

[0333] Reference Figure 10 An example region ROI, including a local region of the first optical region OA1 in the horizontal direction, may include an inner region IA, a first border region LBA as a border region BA located on the first side (left side) of the inner region IA, and a second border region RBA as a border region BA located on the second side (right side) of the inner region IA.

[0334] Reference Figure 10 The display area DA may also include one or more extended areas (ELOA1, EROA1) surrounding the first optical area OA1. The extended areas (ELOA1, EROA1) may be annular areas and may be included in the first optical area OA1 and / or the normal area NA.

[0335] The sub-pixels SP located in the extended regions (ELOA1, EROA1) can have the same or similar arrangement structure as the sub-pixels SP located in the normal region NA. In one embodiment, the number of sub-pixels per unit area in the extended regions (ELOA1, EROA1) can be substantially the same as the number of sub-pixels per unit area in the normal region NA.

[0336] In another embodiment, the sub-pixels SP located in the extended regions (ELOA1, EROA1) may have the same or similar arrangement structure as the sub-pixels SP located in the border regions BA (LBA, RBA) of the first optical region OA1. For example, the number of sub-pixels per unit area in the extended regions (ELOA1, EROA1) may be substantially the same as the number of sub-pixels per unit area in the border regions BA (LBA, RBA) of the first optical region OA1.

[0337] Reference Figure 10 The extended regions (ELOA1, EROA1) can be called extended border regions (ELBA, ERBA), and the border region BA is extended within the extended border regions (ELBA, ERBA).

[0338] In some embodiments, in the display panel 110 of the display device 100, the number of sub-pixels per unit area in the first optical region OA1 may be different from the number of sub-pixels per unit area in the normal region NA.

[0339] Each of one or more first horizontal lines HL1 that traverses the first optical region OA1 may include a portion disposed in the first optical region OA1 and a portion disposed in the normal region NA.

[0340] Because the number of sub-pixels per unit area in the first optical region OA1 differs from the number of sub-pixels per unit area in the normal region NA, the number of sub-pixels per unit area in the first optical region OA1 connected to a first horizontal line HL1 can be different from the number of sub-pixels per unit area in the normal region NA connected to a first horizontal line HL1. The number of sub-pixels per unit area in the first optical region OA1 connected to a first horizontal line HL1 can be less than the number of sub-pixels per unit area in the normal region NA connected to a first horizontal line HL1.

[0341] Furthermore, one or more first horizontal lines HL1 passing through the first optical region OA1 can be configured to avoid the first transmission region TA1 included in the first optical region OA1. Therefore, it is possible to prevent a reduction in the expected transmittance of the first transmission region TA1.

[0342] In some implementations, one or more first horizontal lines HL1 traversing the first optical region OA1 may be provided based on a specific arrangement structure designed with the above characteristics in mind.

[0343] Reference Figure 10In some embodiments, since one or more first horizontal lines HL1 traversing the first optical region OA1 are intended to be configured to avoid the first transmission region TA1 included in the first optical region OA1, the first horizontal lines HL1 can be curved according to the shape of the first transmission region TA1. In this way, one or more first horizontal lines HL1 in the first optical region OA1 may have one or more non-linear portions NLS. The non-linear portions NLS may have, for example, an arc shape or a curved shape.

[0344] Reference Figure 10 In some embodiments, since the first transmission region TA1 included in the first optical region OA1 is arranged diagonally, and the first horizontal line HL1 is arranged to avoid the first transmission region TA1, one or more non-straight sections NLS of each of the two first horizontal lines HL1 can be arranged in a zigzag pattern.

[0345] Reference Figure 10 In some embodiments, the display panel 110 may include a first sub-pixel SP1 and a second sub-pixel SP2 among a plurality of sub-pixels SP.

[0346] The first sub-pixel SP1 can be located near the left boundary of the first optical region OA1 (e.g., in...). Figure 10 (Example in the first extended border area of ​​ELBA).

[0347] The second sub-pixel SP2 can be located near the right boundary of the first optical region OA1 (e.g., in...). Figure 10 In the example of the second extended border region ERBA), it is positioned horizontally spaced from the first sub-pixel SP1.

[0348] Each of the multiple sub-pixels SP can receive S types of signals. Here, S can be a natural number of 2 or greater.

[0349] In some embodiments, the display panel 110 of the display device 100 may include multiple first horizontal lines HL1 that pass through the first optical region OA1 among a plurality of signal lines.

[0350] Reference Figure 10 In some embodiments, one or more of the multiple first horizontal lines HL1 traversing the first optical region OA1 may bypass (i.e., not connect to) one or more other sub-pixels between the first sub-pixel SP1 and the second sub-pixel SP2, while connecting to the first circuit portion SPC1 of the first sub-pixel SP1 and the second circuit portion SPC2 of the second sub-pixel SP2. Such a first horizontal line HL1_BP may be referred to as a bypass line HL1_BP.

[0351] For example, one or more bypass lines HL1_BP can be used to carry one or more specific signals. Specific signals could be, for example,... Figure 9 The second scan signal is SCAN2.

[0352] Reference Figure 10 In some implementations, one or more first horizontal lines HL1_NBP, which are different from the bypass lines HL1_BP among the multiple first horizontal lines HL1 traversing the first optical region OA1, can be connected to one or more sub-pixels SP within the first optical region OA1. Such one or more first horizontal lines HL1_NBP can be referred to as non-bypass lines HL1_NBP.

[0353] Reference Figure 10 In some embodiments, the display panel 110 of the display device 100 may further include a third sub-pixel SP3, a fourth sub-pixel SP4, a fifth sub-pixel SP5, and a sixth sub-pixel SP6 among a plurality of sub-pixels SP.

[0354] The third sub-pixel SP3 can be located near the left boundary of the first optical region OA1 (e.g., Figure 10 The example's first extended border region (ELBA) is positioned vertically spaced from the first sub-pixel SP1.

[0355] The fourth sub-pixel SP4 can be located near the right boundary of the first optical region OA1 (e.g., Figure 10 The example's second extended border region (ERBA) is positioned vertically spaced from the second sub-pixel SP2.

[0356] The fifth sub-pixel SP5 and the sixth sub-pixel SP6 can be located inside the first optical region OA1 and between the third sub-pixel SP3 and the fourth sub-pixel SP4.

[0357] Reference Figure 10 In some implementations, one or more first horizontal lines HL1_NBP, which are non-bypass lines, can be connected to the third circuit portion SPC3 of the third sub-pixel SP3, the fourth circuit portion SPC4 of the fourth sub-pixel SP4, the fifth circuit portion SPC5 of the fifth sub-pixel SP5, and the sixth circuit portion SPC6 of the sixth sub-pixel SP6.

[0358] Reference Figure 10 In one embodiment, in the display panel 110 of the display device 100, all of the multiple first horizontal lines HL1 can be located on the same layer.

[0359] In another embodiment, at least one of the plurality of first horizontal lines HL1 may be located in a different layer than the other first horizontal lines HL1.

[0360] Reference Figure 10 In some embodiments, multiple first horizontal lines HL1 may be provided in the display panel 110 of the display device 100 to avoid multiple first transmission regions TA1 of the first optical region OA1. For example, the direction or pattern of the multiple first horizontal lines HL1 that are constructed or provided in each of the multiple first horizontal lines HL1 to avoid multiple first transmission regions TA1 may alternate in a zigzag shape.

[0361] Each bypass route HL1_BP can bypass multiple first transmission regions TA1 by alternately bypassing the first transmission region TA1 in a first direction and a second direction opposite to each other. Each non-bypass route HL1_NBP can bypass multiple first transmission regions TA1 by bypassing the first transmission region TA1 in either the first direction or the second direction.

[0362] For example, the bypass route HL1_BP can avoid the first transmission region TA1 by alternating between the upper part of some first transmission regions TA1 and the lower part of the remaining first transmission regions TA1. The non-bypass route HL1_NBP can avoid the first transmission region TA1 by bypassing the upper part of some first transmission regions TA1 or the lower part of the remaining first transmission regions TA1.

[0363] For example, one or more non-straight sections NLS of each bypass route HL1_BP may include one or more first non-straight sections NLS that bypass one or more lower portions of one or more first transmission regions TA1 and / or one or more second non-straight sections NLS that bypass one or more upper portions of one or more first transmission regions TA1.

[0364] For example, one or more non-linear portions (NLS) of each bypass route HL1_BP can be positioned to be diagonally adjacent to each other. One or more non-linear portions (NLS) of each non-bypass route HL1_NBP can be positioned to be diagonally adjacent to each other.

[0365] Subpixels SP, located in the first optical region OA1, can be arranged adjacent to each other on a predetermined basis. Figure 10 In the example, four sub-pixels SP can be arranged adjacent to each other in the first optical region OA1. The light-emitting regions EA of the four adjacent sub-pixels SP in the first optical region OA1 can be arranged to be adjacent to each other in a diagonal direction, as described above. Figure 4As shown in the attached figures. In these examples, the region EA comprising the light-emitting area of ​​four adjacent sub-pixels SP can have a rhomboid shape. Therefore, the corresponding four anode electrodes AE of the four adjacent sub-pixels SP in the first optical region OA1 can be arranged to be adjacent to each other in a diagonal direction.

[0366] On the contrary, Figure 10 In the example, the circuit portions of each of the four adjacent sub-pixels SP in the first optical region OA1 can be arranged parallel in the horizontal direction. The circuit portion of each of the four sub-pixels SP can be configured with... Figure 9 The example includes the remaining components besides the light-emitting element ED (e.g., transistors (DRT and T1 to T6)) and the storage capacitor Cst.

[0367] In the following text, reference will be made to Figure 11 and Figure 12 describe Figure 9 Pixel circuits are applied to Figure 10 An example of a line layout structure.

[0368] Figure 11 An example arrangement of signal lines passing through a first optical region OA1 in a display device 100 according to an aspect of the present disclosure is illustrated.

[0369] Reference Figure 11 In some embodiments, the display panel 110 of the display device 100 may include one or more first sub-pixels SP1 located near the left boundary of the first optical region OA1 (e.g., the first extended border region ELBA) and one or more second sub-pixels SP2 located near the right boundary of the first optical region OA1 (e.g., the second extended border region ERBA) and spaced apart from the first sub-pixels SP1 in the horizontal direction.

[0370] Reference Figure 11 Each of the plurality of sub-pixels SP can receive S types of signals. Here, S can be a natural number of 2 or greater. In some embodiments, the display panel 110 of the display device 100 may include a plurality of first horizontal lines HL1 that traverse the first optical region OA1 among the signal lines.

[0371] Reference Figure 11 In some implementations, when the S types of signals provided to each of the plurality of sub-pixels SP are limited to signals provided from the horizontal line, five of the S types of signals can be defined as follows: Figure 9The pixel circuit includes the first to third scan signals (SCAN1, SCAN2, and SCAN3), the light emission control signal EM, and the initialization voltage VINI. In some embodiments, an additional signal among the S types of signals can be defined as... Figure 9 The anode reset voltage VAR in the pixel circuit.

[0372] Reference Figure 11 In some embodiments, the display panel 110 of the display device 100 may include K first horizontal lines HL1 that pass through the first optical region OA1 and are used to provide K types of signals of S types to the first sub-pixel SP1 and the second sub-pixel P2.

[0373] Here, K can be a natural number greater than 1 and less than S.

[0374] according to Figure 11 For example, among the S types of signals, K types of signals can be a single type of signal, such as the second scan signal SCAN2. In this example, a first horizontal line HL1 used to provide the second scan signal SCAN2, which is a K-type signal, to the first sub-pixel SP1 and the second sub-pixel SP2 can be the second scan line SCL2_BP.

[0375] For ease of description, in the following discussion, it is assumed that the S types of signals are the first scan signal to the third scan signal (e.g., Figure 9 In the example, the first scan signal to the third scan signal (SCAN1, SCAN2, SCAN3) and the light emission control signal (e.g., Figure 9 In the example, the light control signal EM), initialization voltage (e.g., Figure 9 The initialization voltage (VINI) and anode reset voltage (e.g., in the example) are shown. Figure 9 In the example, the anode reset voltage (VAR) is used, and the K types of signals are the second scan signals (e.g., Figure 9 The second scan signal in the example is SCAN2.

[0376] Therefore, in the following text, the S-type signal will be referred to as the 6-type gating signal (SCAN1, SCAN2, SCAN3, EM, VINI, and VAR), and the K-type signal will be referred to as the second scan signal SCAN2. Furthermore, the S first horizontal lines HL1 used to transmit the S-type signals will be referred to as the 6-type gating lines, namely, the first scan line to the third scan line (SCL1, SCL2_NBP / SCL2_BP, SCL3), the light emission control line EML, the initialization voltage line VINIL, and the anode voltage reset line VARL. The K first horizontal lines HL1 used to transmit the K-type signals will be referred to as the second scan lines (SCL2_BP, SCL2_NBP).

[0377] Reference Figure 11 In some embodiments, the anode voltage reset line VARL may include a first vertical anode voltage reset line VARL_LV extending in the vertical direction in the first non-display area NDA1, a second vertical anode voltage reset line VARL_RV extending in the vertical direction in the second non-display area NDA2, and a horizontal anode voltage reset line VARL_H extending in the horizontal direction in the display area DA.

[0378] Reference Figure 11 In some embodiments, the anode voltage reset line VARL may also include a third vertical anode voltage reset line VARL_IV extending in the vertical direction within the first optical region OA1.

[0379] Reference Figure 11 The second scan line SCL2_BP, which overlaps with the first sub-pixel SP1 and the second sub-pixel SP2 among the multiple first horizontal lines HL1 that traverse the first optical region OA1, can be a bypass line. This bypass line does not connect to one or more sub-pixels SP in the first optical region OA1 other than the first sub-pixel SP1 and the second sub-pixel SP2, and bypasses one or more sub-pixels SP between the first sub-pixel SP1 and the second sub-pixel SP2.

[0380] Reference Figure 11 In some embodiments, the display panel 110 of the display device 100 may further include a third sub-pixel SP3, a fourth sub-pixel SP4, a fifth sub-pixel SP5, and a sixth sub-pixel SP6 among a plurality of sub-pixels SP.

[0381] The third sub-pixel SP3 may be located near the left boundary of the first optical region OA1 (e.g., the first extended border region ELBA) and is positioned to be spaced apart from the first sub-pixel SP1 in the vertical direction.

[0382] The fourth sub-pixel SP4 may be located near the right boundary of the first optical region OA1 (e.g., the second extended border region ERBA) and is positioned to be spaced apart from the second sub-pixel SP2 in the vertical direction.

[0383] The fifth sub-pixel SP5 and the sixth sub-pixel SP6 can be located inside the first optical region OA1 and between the third sub-pixel SP3 and the fourth sub-pixel SP4.

[0384] Reference Figure 11 In some embodiments, the display panel 110 of the display device 100 may further include six types of gating lines (SCL1, SCL2_NBP, SCL3, EML, VINIL, and VARL) among the multiple first horizontal lines HL1 that traverse the first optical region OA1, which are used to provide six types of gating signals (SCAN1, SCAN2, SCAN3, EML, VINIL, and VAR) to the third sub-pixel SP3, the fifth sub-pixel SP5, the sixth sub-pixel SP6, and the fourth sub-pixel SP4.

[0385] For example, the six types of gate lines (SCL1, SCL2_NBP, SCL3, EML, VINIL, and VARL) that serve as the first horizontal line HL1 can be set to overlap with the third sub-pixel SP3, the fifth sub-pixel SP5, the sixth sub-pixel SP6, and the fourth sub-pixel SP4.

[0386] Reference Figure 11 In some implementations, the six types of gate lines (SCL1, SCL2_NBP, SCL3, EML, VINIL, and VARL) corresponding to the third sub-pixel SP3, the fifth sub-pixel SP5, the sixth sub-pixel SP6, and the fourth sub-pixel SP4 can be the first scan line SCL1, the second scan line SCL2_NBP, the third scan line SCL3, the light emission control line EML, the initialization voltage line VINIL, and the anode voltage reset line VARL.

[0387] In some implementations, five (SK, S=6, K=1) first horizontal lines (SCL1, SCL3, EML, VINIL, and VARL) of the six types of gating lines (SCL1, SCL2_NBP, SCL3, EML, VINIL, and VARL) traversing the first optical region OA1 may branch at a first point (e.g., a point to its left), thereby further including five (SK, S=6, K=1) first branch lines (SCL1_LB, SCL3_LB, EML_LB, VINIL_LB, and VARL_LB) for providing five (SK, S=6, K=1) types of gating signals (SCAN1, SCAN3, EM, VINI, VAR) to the first pixel SP1.

[0388] Reference Figure 11 In some implementations, five (SK, S=6, K=1) first horizontal lines (SCL1, SCL3, EML, VINIL, and VARL) of the six types of gating lines (SCL1, SCL2_NBP, SCL3, EML, VINIL, and VARL) traversing the first optical region OA1 may branch at a second point (e.g., a point to its right), thereby further including five (SK, S=6, K=1) second branch lines (SCL1_RB, SCL3_RB, EML_RB, VINIL_RB, and VARL_RB) for providing five (SK, S=6, K=1) types of gating signals (SCAN1, SCAN3, EM, VINI, VAR) to the second pixel SP2.

[0389] Here, the first point and the second point can be placed in or near the first optical region OA1. The second point can be located to the right of the display area compared to the first point, and can be a point that is relatively closer to the second non-display region NDA2 than the first point.

[0390] Reference Figure 11 In one embodiment, in the display panel 110 of the display device 100, the six types of gate lines (SCL1, SCL2_NBP / SCL2_BP, SCL3, EML, VINIL, VARL) that are the first horizontal lines HL1 can be located in the same layer.

[0391] Reference Figure 11 In another embodiment, in the display panel 110 of the display device 100, at least one of the six types of gate lines (SCL1, SCL2_NBP / SCL2_BP, SCL3, EML, VINIL, VARL) that are the S first horizontal lines HL1 can be located in a different layer from the other lines.

[0392] Reference Figure 11 In some embodiments, in the display panel 110 of the display device 100, the second scan line SCL2_BP, which is a bypass line, can be configured to avoid multiple first transmission regions TA1 of the first optical region OA1, and the second scan line SCL2_NBP, which is a non-bypass line, can also be configured to avoid multiple first transmission regions TA1 in the first optical region OA1.

[0393] The direction in which the second scan line SCL2_BP, as a bypass route, avoids the transmission region TA1 can be opposite to the direction in which the second scan line SCL2_NBP, as a non-bypass route, avoids the transmission region TA1.

[0394] Reference Figure 11 In some embodiments, the display panel 110 of the display device 100 may further include a third sub-pixel SP3 located near the left boundary ELBA of the first optical region OA1 and positioned vertically spaced from the first sub-pixel SP1, a fourth sub-pixel SP4 located near the right boundary ERBA of the first optical region OA1 and positioned vertically spaced from the second sub-pixel SP2, and a fifth sub-pixel SP5 located inside the first optical region OA1 and between the third sub-pixel SP3 and the fourth sub-pixel SP4.

[0395] The first sub-pixel SP1 and the second sub-pixel SP2 can be included in the first sub-pixel row. The third sub-pixel SP3, the fifth sub-pixel SP5, and the fourth sub-pixel SP4 can be included in the second sub-pixel row.

[0396] The S types of signals can include the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, and the light emission control signal EM.

[0397] In some embodiments, the display panel 110 of the display device 100 may further include a first scan line SCL1 for providing a first scan signal SCAN1 to the second sub-pixel row, a second scan line SCL2_NBP for providing a second scan signal SCAN2 to the second sub-pixel row, a third scan line SCL3 for providing a third scan signal SCAN3 to the second sub-pixel row, and a light emission control line EML for providing a light emission control signal EM to the second sub-pixel row.

[0398] In some embodiments, the plurality of first horizontal lines HL1 may further include a first scan branch line SCL1_LB that branches off at a first point of the first scan line SCL1 and provides a first scan signal SCAN1 to the first sub-pixel SP1 included in the first sub-pixel row; a third scan branch line SCL3_LB that branches off at a first point of the third scan line SCL3 and provides a third scan signal SCAN3 to the first sub-pixel SP1 included in the first sub-pixel row; and a light emission control branch line EML_LB that branches off at a first point of the light emission control line EML and provides a light emission control signal EM to the first sub-pixel SP1 included in the first sub-pixel row.

[0399] In some embodiments, the plurality of first horizontal lines HL1 may further include another first scan branch line SCL1_RB that branches off at the second point of the first scan line SCL1 and provides a first scan signal SCAN1 to the second sub-pixel SP2 included in the first sub-pixel row; another third scan branch line SCL3_RB that branches off at the second point of the third scan line SCL3 and provides a third scan signal SCAN3 to the second sub-pixel SP2 included in the first sub-pixel row; and another light emission control branch line EML_RB that branches off at the second point of the light emission control line EML and provides a light emission control signal EM to the second sub-pixel SP2 included in the first sub-pixel row.

[0400] In some embodiments, the display panel 110 of the display device 100 may further include another second scan line SCL2_BP among a plurality of first horizontal lines HL1, which is used to provide a second scan signal SCAN2 to the first sub-pixel row.

[0401] The second scan line SCL2_BP set in the first sub-pixel row can be a bypass line that bypasses other sub-pixels SP in the first optical region OA1 without connecting to those other sub-pixels SP.

[0402] Reference Figure 11 In some embodiments, the display panel 110 of the display device 100 may include a driving circuit connected to or disposed in the non-display area NDA.

[0403] The non-display area NDA may include a first non-display area NDA1 located on the first side of the display area DA and a second non-display area NDA2 located on the second side of the display area DA.

[0404] The driving circuit may include a first scan driving circuit SCD1 for outputting a first scan signal SCAN1, a second scan driving circuit SCD2 for outputting a second scan signal SCAN2, a third scan driving circuit SCD3 for outputting a third scan signal SCAN3, and a light emission control driving circuit EMD for outputting a light emission control signal EM.

[0405] Each of the first scan drive circuit SCD1, the third scan drive circuit SCD3, and the light emission control drive circuit EMD can be connected to one of the first non-display area NDA1 and the second non-display area NDA2, or can be located in one of the first non-display area NDA1 and the second non-display area NDA2.

[0406] The second scan drive circuit SCD2 can be connected to either the first non-display area NDA1 or the second non-display area NDA2, or can be located in either the first non-display area NDA1 or the second non-display area NDA2.

[0407] The second scan drive circuit SCD2 can output a corresponding second scan signal SCAN2 to each of the second scan line SCL2_BP (which is a bypass line) and the second scan line SCL2_NBP (which is a non-bypass line).

[0408] Reference Figure 11 In some embodiments, the display panel 110 of the display device 100 may further include an initialization signal line VINIL, an initialization branch line VINIL_LB and another initialization branch line VINIL_RB, which are among a plurality of first horizontal lines HL1 that pass through the first optical region OA1.

[0409] The initialization signal line VINIL can be set to correspond to the second sub-pixel row and can provide the initialization signal VINI to the second sub-pixel row.

[0410] The initialization branch line VINIL_LB can, for example, branch off at the first point of the initialization signal line VINIL, and can provide the initialization signal VINI to the first sub-pixel SP1 included in the first sub-pixel row.

[0411] Another initialization branch line, VINIL_RB, can branch off at the second point of the initialization signal line VINIL, and can provide the initialization signal VINI to the second sub-pixel SP2 included in the first sub-pixel row.

[0412] Reference Figure 11 In some embodiments, the display panel 110 of the display device 100 may include a drive circuit connected to or disposed in the non-display area NDA.

[0413] The non-display area NDA may include a first non-display area NDA1 located on the first side of the display area DA and a second non-display area NDA2 located on the second side of the display area DA.

[0414] The driving circuit may include an initialization driving circuit VINID for outputting an initialization signal VINI. The initialization driving circuit VINID may be connected to one of the first non-display area NDA1 and the second non-display area NDA2, or may be located in one of the first non-display area NDA1 and the second non-display area NDA2.

[0415] Figure 12 and Figure 13 A more specific example arrangement of the bypass line within the first optical region OA1 of the display device 100 according to aspects of the present disclosure is illustrated.

[0416] Reference Figure 12 In some embodiments, the second scan line SCL2_BP, which serves as a bypass path, and the second scan line SCL2_NBP, which serves as a non-bypass path, can be alternately arranged in the first optical region OA1.

[0417] The second scan line SCL2_BP, which serves as a bypass route, can be a signal line that is not connected to the circuit portion of the sub-pixel SP in the first optical region OA1. The second scan line SCL2_NBP, which is not a bypass route, can be a signal line that is connected to the circuit portion of the sub-pixel SP in the first optical region OA1.

[0418] As described above, although examples in which the second scan line SCL2_BP is set as a bypass line have been discussed, the embodiments of this disclosure are not limited thereto. For example, one or more of the six types of gate lines (SCL1, SCL2, SCL3, EML, VINIL, and VARL) other than the second scan line SCL2_BP can be set as bypass lines.

[0419] Figure 14 An example arrangement of touch sensor metal in each of the normal area NA and the first optical area OA1 of a display device 100 according to aspects of the present disclosure is illustrated. Figure 15 This is an enlarged view of an example of the arrangement structure of the touch sensor metal inside the first optical region OA1 of the display device 100 according to aspects of this disclosure.

[0420] As described above, in some embodiments, the display panel 110 of the display device 100 may further include: a cathode electrode CE disposed in a plurality of light-emitting regions EA included in the normal region NA and the first optical region OA1, but not disposed in a plurality of first transmission regions TA1 of the first optical region OA1; and an encapsulation layer ENCAP disposed on the cathode electrode CE.

[0421] As described above, the display device 100 according to aspects of this disclosure can provide touch sensing functionality. To provide this functionality, in an example where the touch sensor TS is embedded in the display panel 110, the display panel 110 can have, for example... Figure 7 The vertical structure is shown. In this example, for instance, the display panel 110 of the display device 100 may also include a touch sensor metal TSM with a mesh pattern and forming a touch sensor TS on the encapsulation layer ENCAP.

[0422] Reference Figure 14 In some embodiments, the touch sensor metal TSM can be arranged in a mesh pattern in the normal area NA, while avoiding the light-emitting area EA. Therefore, even when the touch sensor TS is embedded in the display panel 110, it is possible to prevent or at least reduce the reduction in luminous efficiency in the normal area NA.

[0423] Reference Figure 14 In some embodiments, in the first optical region OA1, the touch sensor metal TSM can be configured to avoid multiple light-emitting regions EA in the first optical region OA1, and further configured to avoid multiple first transmission regions TA1 in the first optical region OA1. As a result, touch sensing in the first optical region OA1 can be implemented normally, thereby preventing or at least reducing the reduction in luminous efficiency and transmittance in the first optical region OA1.

[0424] Reference Figure 14 In some embodiments, the density of the touch sensor metal TSM forming multiple mesh units in the first optical region OA1 can be less than the density of the touch sensor metal TSM forming multiple mesh units in the normal region NA.

[0425] However, the linewidth of at least a portion of the touch sensor metal TSM in the first optical region OA1 can be greater than the linewidth of the touch sensor metal TSM in the normal region NA. For example, the maximum linewidth of the touch sensor metal TSM in the first optical region OA1 can be greater than the maximum linewidth of the touch sensor metal TSM in the normal region NA.

[0426] Therefore, although the density of the touch sensor metal TSM forming mesh cells in the first optical region OA1 is lower than the density of the touch sensor metal TSM forming mesh cells in the normal region NA, the capacitance required for touch sensing through the touch sensor metal TSM in the first optical region OA1 can be made to be similar to the level required for touch sensing through the touch sensor metal TSM in the normal region NA. Therefore, the touch sensitivity of the first optical region OA1 can be improved.

[0427] Considering the difference between the density of the touch sensor metal TSM in the first optical region OA1 and the density of the touch sensor metal TSM in the normal region NA, such as Figure 14 As shown in cases 1, 2 and 3, the maximum linewidth of the touch sensor metal TSM in the first optical region OA1 can be adjusted in various ways.

[0428] Reference Figure 15 In the first optical region OA1, the touch sensor metal TSM may have, for example, a mesh pattern. According to this example, the touch sensor metal TSM in the first optical region OA1 may include a cross portion TSM_IP in the cross region IPA and a link portion TSM_LP in the link region LPA for connecting the cross portion TSM_IP.

[0429] Reference Figure 15 In the touch sensor metal TSM included in the first optical region OA1, the linewidth Wlp of each link portion TSM_LP can be greater than the linewidth Wip of each intersection portion TSM_IP.

[0430] This not only ensures that the touch sensor metal TSM in the first optical region OA1 avoids the light-emitting region EA and the first transmission region TA1 to the greatest extent possible, but also that the capacitance required for touch sensing through the touch sensor metal TSM in the first optical region OA1 is very similar to the capacitance required for touch sensing through the touch sensor metal TSM in the normal region NA. Therefore, the luminous performance and touch sensitivity of the first optical region OA1 can be maximized.

[0431] In some implementations, multiple first horizontal lines HL1 traversing the first optical region OA1 may partially overlap with the touch sensor metal TSM.

[0432] The above implementation method will be briefly described below.

[0433] According to an aspect of this disclosure, a display device includes: a display panel including a plurality of sub-pixels and a plurality of signal lines, the display panel defining a display area and a non-display area, the display area having a first optical area and a normal area located outside the first optical area, wherein the first optical area includes a plurality of light-emitting areas and a plurality of first transmissive areas, and the normal area includes a plurality of light-emitting areas.

[0434] The display panel may include multiple first horizontal lines among multiple signal lines arranged through a first optical area.

[0435] The first horizontal line may include a bypass line that connects to the sub-pixels at the two boundaries of the first optical region but does not connect to other sub-pixels inside the first optical region, as well as a non-bypass line that connects to the sub-pixels at the two boundaries of the first optical region and to the sub-pixels inside the first optical region.

[0436] The display device may also include a first optical electronic device located below the display panel and at a portion overlapping with at least a portion of the first optical region of the display area.

[0437] Bypass lines and non-bypass lines can be set alternately, and both bypass lines and non-bypass lines can carry the same type of signal.

[0438] Multiple first horizontal lines can be located on the same layer.

[0439] At least one of the multiple first horizontal lines can be located in a different layer from the other multiple first horizontal lines, such that at least one of the multiple first horizontal lines intersects the other multiple first horizontal lines perpendicularly.

[0440] Multiple first horizontal lines may not exist in multiple first transmission regions of the first optical region.

[0441] Each of the plurality of sub-pixels may include: a light-emitting element having an anode electrode, a light-emitting layer and a cathode electrode; and a driving transistor configured to drive the light-emitting element having a first node, a second node and a third node.

[0442] A first transistor configured to control the connection between a first node and a second node, the first transistor being controlled by a first scan signal; a second transistor configured to control the connection between a third node and a data line, the second transistor being controlled by a second scan signal; a third transistor configured to control the connection between a third node and a drive voltage line, the third transistor being controlled by a light emission control signal; a fourth transistor configured to control the connection between an anode electrode and a second node, the fourth transistor being controlled by a light emission control signal; a fifth transistor configured to control the connection between an initialization signal line and a second node, the fifth transistor being controlled by a third scan signal; a sixth transistor configured to control the connection between an anode reset voltage line and an anode electrode; and a storage capacitor connected between the first node and the drive voltage line.

[0443] The plurality of first horizontal lines may include a first scan line configured to provide a first scan signal, a second scan line configured to provide a second scan signal, a third scan line configured to provide a third scan signal, and a light emission control line configured to provide a light emission control signal.

[0444] The first horizontal line may include a bypass line that connects to the sub-pixels at the two boundaries of the first optical region but does not connect to other sub-pixels inside the first optical region, as well as a non-bypass line that connects to the sub-pixels at the two boundaries of the first optical region and to the sub-pixels inside the first optical region.

[0445] The bypass line can be configured to provide a second scan signal to the first sub-pixel of a plurality of sub-pixels.

[0446] The display device may also include an encapsulation layer on the cathode electrode and a touch sensor metal with a grid pattern on the encapsulation layer.

[0447] The metal of the touch sensor may not be present in multiple luminescent areas of the normal area.

[0448] The touch sensor metal may not be present in the multiple light-emitting areas and multiple first transmission areas of the first optical area.

[0449] The linewidth of the touch sensor metal portion in the first optical zone can be greater than the linewidth of the touch sensor metal portion in the normal zone.

[0450] The touch sensor metal may include intersecting portions and connecting portions that connect the intersecting portions, and the line width of the connecting portions may be greater than the line width of the intersecting portions.

[0451] Optical electronic devices may include cameras or sensors.

[0452] The display area may also have a second optical area, which is different from the first optical area and the normal area.

[0453] The display panel may also include a second optical electronic device located below the display panel and at a portion that overlaps with at least a portion of the second optical region of the display area.

[0454] The display panel may include driving circuitry disposed in a non-display area. The non-display area may include a first non-display area located on a first side of the display area and a second non-display area located on a second side of the display area.

[0455] The driving circuit may include: a first scanning driving circuit configured to provide a first scanning signal; a second scanning driving circuit configured to provide a second scanning signal; a third scanning driving circuit configured to provide a third scanning signal; and a light emission control driving circuit configured to provide a light emission control signal.

[0456] Each of the first scanning drive circuit, the third scanning drive circuit, and the light emission control drive circuit can be located in one of the first non-display area and the second non-display area, and the second scanning drive circuit can be located in both the first non-display area and the second non-display area.

[0457] The second scan drive circuit is configured to output a second scan signal to a second scan line that serves as a bypass path, and is also configured to output a second scan signal to a second scan line that serves as a non-bypass path.

[0458] The driving circuit may also include an initialization driving circuit configured to output an initialization signal, and the initialization driving circuit may be located in one of the first non-display area and the second non-display area.

[0459] The display panel may also include a shielding metal located below the driving transistor and not present in the plurality of first transmission regions, and the shielding metal may be electrically connected to the driving voltage line.

[0460] The display panel may also include a cathode electrode located in a plurality of light-emitting areas in the normal area and in a plurality of light-emitting areas in the first optical area, and not present in a plurality of first transmission areas in the first optical area.

[0461] The first optical electronic device can be a camera, and the second optical electronic device can be a sensor.

[0462] The transmittance of the first optical region can be greater than or equal to the transmittance of the second optical region.

[0463] The number of sub-pixels per unit area in the first optical region can be less than the number of sub-pixels per unit area in the normal region, and the number of sub-pixels per unit area in the second optical region can be greater than or equal to the number of sub-pixels per unit area in the first optical region, and less than the number of sub-pixels per unit area in the normal region.

[0464] According to an aspect of this disclosure, a display device is provided, comprising: a display panel including a display area and a non-display area, the display area including a first optical area and a normal area located outside the first optical area, and the display panel including a plurality of sub-pixels and a plurality of signal lines, the first optical area including a plurality of light-emitting areas and a plurality of first transmissive areas, and the normal area including a plurality of light-emitting areas; and a first optical electronic device located below and in a lower portion of the display panel, and overlapping at least a portion of the first optical area included in the display area.

[0465] The display panel may include multiple first horizontal lines that cross the first optical area, among multiple signal lines.

[0466] The display panel may include bypass lines and non-bypass lines among multiple first horizontal lines. The bypass lines are connected to the sub-pixels at the two boundaries of the first optical region but not to other sub-pixels inside the first optical region. The non-bypass lines are connected to the sub-pixels at the two boundaries of the first optical region and to the sub-pixels inside the first optical region.

[0467] Bypass lines and non-bypass lines can carry the same type of signal.

[0468] Bypass routes and non-bypass routes can be set alternately.

[0469] Multiple first horizontal lines can be located on the same layer.

[0470] One or more of the multiple first horizontal lines may overlap perpendicularly with one or more of the remaining first horizontal lines. In this example, at least one of the multiple first horizontal lines may be located in a different layer from the remaining first horizontal lines.

[0471] Multiple first horizontal lines can be configured to avoid multiple first transmission regions within the first optical region.

[0472] At least one bypass route among the plurality of first horizontal lines can avoid each of the plurality of first transmission regions by bypassing the first transmission region in a first direction. At least one bypass route among the plurality of first horizontal lines can avoid each of the plurality of first transmission regions by alternately bypassing the first transmission region in a first direction and a second direction that are opposite to each other. At least one non-bypass route among the plurality of first horizontal lines can avoid each of the plurality of first transmission regions by bypassing the first transmission region in either a first direction or a second direction.

[0473] Each of the plurality of sub-pixels may include: a light-emitting element comprising an anode electrode, a light-emitting layer, and a cathode electrode; a driving transistor for driving the light-emitting element, the driving transistor comprising a first node, a second node, and a third node; a first transistor for controlling the connection between the first node and the second node, the first transistor being controlled by a first scan signal; a second transistor for controlling the connection between the third node and a data line, the second transistor being controlled by a second scan signal; a third transistor for controlling the connection between the third node and a driving voltage line, the third transistor being controlled by a light-emitting control signal; a fourth transistor for controlling the connection between the anode electrode and the second node, the fourth transistor being controlled by a light-emitting control signal; a fifth transistor for controlling the connection between an initialization signal line and the second node, the fifth transistor being controlled by a third scan signal; a sixth transistor for controlling the connection between the anode reset voltage line and the anode electrode; and a storage capacitor connected between the first node and the driving voltage line.

[0474] In an example where each of the plurality of sub-pixels has the aforementioned pixel circuitry, the display panel may include a first scan line for providing a first scan signal, a second scan line for providing a second scan signal, a third scan line for providing a third scan signal, and a light emission control line for providing a light emission control signal, among a plurality of first horizontal lines.

[0475] At least one of the multiple first horizontal lines can be a second scan line used to provide a second scan signal to the first sub-pixel among the multiple sub-pixels.

[0476] At least one of the multiple first horizontal lines, not a side line, can be another second scan line used to provide another second scan signal to a second sub-pixel that is different from the first sub-pixel among the multiple sub-pixels.

[0477] The display panel may include driving circuitry connected to or disposed within a non-display area. The non-display area may include a first non-display area located on a first side of the display area and a second non-display area located on a second side of the display area.

[0478] The driving circuit may include a first scanning driving circuit for outputting a first scanning signal, a second scanning driving circuit for outputting a second scanning signal, a third scanning driving circuit for outputting a third scanning signal, and a light emission control driving circuit for outputting a light emission control signal.

[0479] Each of the first scanning drive circuit, the third scanning drive circuit, and the light emission control drive circuit can be connected to one of the first non-display area and the second non-display area, or can be located in one of the first non-display area and the second non-display area.

[0480] The second scanning drive circuit can be connected to either the first non-display area or the second non-display area, or can be located in either the first non-display area or the second non-display area.

[0481] The second scan drive circuit can output a corresponding second scan signal to each of the second scan line that serves as a bypass path and the second scan line that serves as a non-bypass path.

[0482] The driving circuit may further include an initialization driving circuit for outputting an initialization signal. The initialization driving circuit may be connected to one of the first non-display area and the second non-display area, or may be disposed in one of the first non-display area and the second non-display area.

[0483] The display panel may also include a shielding metal disposed below the driving transistor and configured to avoid multiple first transmission areas. The shielding metal may be electrically connected to the driving voltage lines.

[0484] The display panel may also include a cathode electrode disposed in a plurality of light-emitting regions included in the normal region and the first optical region, and not disposed in a plurality of first transmission regions of the first optical region.

[0485] The display panel may also include an encapsulation layer on the cathode electrode and a touch sensor metal with a mesh pattern on the encapsulation layer.

[0486] The touch sensor metal can be configured to avoid multiple light-emitting areas within the normal area. The touch sensor metal can also be configured to avoid multiple light-emitting areas and multiple first transmissive areas included within the first optical area.

[0487] The touch sensor metal in the first optical region may include a portion with a larger linewidth than the touch sensor metal in the normal region.

[0488] The touch sensor metal may include cross portions and link portions for connecting the cross portions, and the line width of each link portion may be greater than the line width of each cross portion.

[0489] Multiple first horizontal lines can partially overlap with the metal of the touch sensor.

[0490] The first optical electronic device can be a camera or a sensor, and the number of sub-pixels per unit area in the first optical region can be less than the number of sub-pixels per unit area in the normal region.

[0491] The display area may also include a second optical area that is different from the first optical area and the normal area.

[0492] The display device may further include a second optical electronic device located below the display panel, in the lower portion, and overlapping at least a portion of the second optical region. In this example, the normal region may be disposed between the first and second optical regions, or may not be disposed between the first and second optical regions.

[0493] The first optical electronic device can be a camera, the second optical electronic device can be a sensor, and the transmittance of the first optical region can be greater than or equal to the transmittance of the second optical region.

[0494] The number of sub-pixels per unit area in the first optical region can be less than the number of sub-pixels per unit area in the normal region.

[0495] The number of sub-pixels per unit area in the second optical region can be equal to or greater than the number of sub-pixels per unit area in the first optical region, but less than the number of sub-pixels per unit area in the normal region.

[0496] According to the embodiments described herein, a display panel and display device can be provided that can reduce the non-display area of ​​the display panel and prevent the optical electronics from being exposed on the front surface of the display panel by placing optical electronic devices such as cameras and / or sensors below or in the lower portion of the display area of ​​the display panel.

[0497] According to the embodiments described herein, a display panel and a display device can be provided having a light-transmitting structure for enabling optical electronics in the lower part or below the display area of ​​the display panel to properly receive light transmitted through the display panel.

[0498] According to the embodiments described herein, a display panel and a display device can be provided that are capable of performing display driving normally in the display area included in the display panel and in the optical area overlapping with the optical electronics.

[0499] According to the embodiments described herein, a display device can be provided that enables signal lines to pass through an optical region overlapping with an optical electronic device in a manner suitable for the characteristics of the optical region.

[0500] The above description is provided to enable those skilled in the art to implement and use the technical concepts of the present invention, and is offered in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The above description and drawings are provided as examples of the technical concepts of the invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the invention. Therefore, the scope of the invention is not limited to the illustrated embodiments, but is to be accorded the widest scope consistent with the claims. The scope of protection of the invention should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be interpreted as being included within the scope of the invention.

[0501] Cross-reference to related applications

[0502] This application claims priority to Korean Patent Application No. 10-2021-0154440, filed with the Korean Intellectual Property Office on November 11, 2021, which is incorporated herein by reference in its entirety.

Claims

1. A display device comprising: a display panel comprising a plurality of sub-pixels and a plurality of signal lines, the display panel defining a display area and a non-display area, the display area having a first optical area and a normal area located outside the first optical area, wherein the first optical area comprises a plurality of light-emitting areas and a plurality of first transmissive areas, and wherein the normal area comprises a plurality of light-emitting areas, wherein the display panel comprises, among the plurality of signal lines, a plurality of first horizontal lines disposed through the first optical area, wherein the first horizontal lines comprise bypass lines connected to sub-pixels at two boundaries of the first optical area and not connected to other sub-pixels inside the first optical area, and non-bypass lines connected to sub-pixels at the two boundaries of the first optical area and sub-pixels inside the first optical area, wherein the bypass lines comprise an arc-shaped first non-straight portion that bypasses one of the plurality of first transmissive areas in a first direction and an arc-shaped second non-straight portion that bypasses another of the plurality of first transmissive areas in a second direction opposite to the first direction, and wherein the non-bypass lines comprise an arc-shaped non-straight portion that bypasses the plurality of first transmissive areas in the first direction or the second direction.

2. The display device of claim 1, further comprising first optical electronics located below the display panel and at a portion overlapping at least a portion of the first optical area of the display area.

3. The display device according to claim 1, wherein the bypass lines are disposed alternately with the non-bypass lines, and wherein the bypass lines and the non-bypass lines carry the same type of signal.

4. The display device according to claim 1, wherein the plurality of first horizontal lines are located in a same layer.

5. The display device according to claim 1, wherein at least one of the plurality of first horizontal lines is located in a different layer from the remaining first horizontal lines of the plurality of first horizontal lines, such that the at least one of the plurality of first horizontal lines is vertically overlapped with the remaining first horizontal lines of the plurality of first horizontal lines.

6. The display device according to claim 1, wherein each of the plurality of sub-pixels comprises: a light-emitting element having an anode electrode, a light-emitting layer, and a cathode electrode; a drive transistor configured to drive the light-emitting element, the drive transistor having a first node, a second node, and a third node; a first transistor configured to control connection between the first node and the second node, the first transistor being configured to be controlled by a first scan signal; a second transistor configured to control connection between the third node and a data line, the second transistor being configured to be controlled by a second scan signal; a third transistor configured to control connection between the third node and a drive voltage line, the third transistor being configured to be controlled by a light-emitting control signal; a fourth transistor configured to control connection between the anode electrode and the second node, the fourth transistor configured to be controlled by the light emission control signal; a fifth transistor configured to control connection between an initialization signal line and the second node, the fifth transistor configured to be controlled by a third scan signal; a sixth transistor configured to control connection between an anode reset voltage line and the anode electrode; and a storage capacitor connected between the first node and the drive voltage line, wherein the plurality of first horizontal lines include a first scan line configured to provide the first scan signal, a second scan line configured to provide the second scan signal, a third scan line configured to provide the third scan signal, and a light emission control line configured to provide the light emission control signal.

7. The display device of claim 6, wherein, the first horizontal lines include bypass lines connected to sub-pixels at two boundaries of the first optical area and not connected to other sub-pixels inside the first optical area, and non-bypass lines connected to the sub-pixels at the two boundaries of the first optical area and the sub-pixels inside the first optical area, and wherein the bypass lines are configured to provide the second scan signal to first sub-pixels of the plurality of sub-pixels.

8. The display device of claim 1, further comprising an encapsulation layer on a cathode electrode, and a touch sensor metal having a mesh pattern on the encapsulation layer, wherein the touch sensor metal is absent from the plurality of light emitting regions of the normal area, and wherein the touch sensor metal is absent from the plurality of light emitting regions and the plurality of first transmissive regions of the first optical area.

9. The display device of claim 8, wherein, a line width of a portion of the touch sensor metal in the first optical area is greater than a line width of a portion of the touch sensor metal in the normal area.

10. The display device of claim 8, wherein, the touch sensor metal includes cross portions and link portions connecting the cross portions, and wherein a line width of the link portions is greater than a line width of the cross portions.

11. The display device according to claim 1, wherein the first optical electronic device includes a camera or a sensor.

12. The display device according to claim 1, wherein the display area further has a second optical area different from the first optical area and the normal area, and wherein the display panel further includes a second optical electronic device located below the display panel and at a portion overlapping at least a portion of the second optical area of the display area.

13. The display device of claim 6, wherein, the display panel includes a drive circuit disposed in the non-display area, wherein the non-display area includes a first non-display area located at a first side of the display area and a second non-display area located at a second side of the display area; wherein the drive circuit includes: a first scan drive circuit configured to provide the first scan signal; a second scan drive circuit configured to provide the second scan signal; a third scan driving circuit configured to provide the third scan signal; and a light emission control driving circuit configured to provide the light emission control signal, wherein each of the first scan driving circuit, the third scan driving circuit, and the light emission control driving circuit is disposed in one of the first non-display region and the second non-display region, and the second scan driving circuit is disposed in both the first non-display region and the second non-display region, and wherein the second scan driving circuit is configured to output the second scan signal to a second scan line that is the bypass line, and is configured to output the second scan signal to a second scan line that is the non-bypass line.

14. The display device of claim 13, wherein, The driving circuit further includes an initialization driving circuit configured to output the initialization signal, and the initialization driving circuit is disposed in one of the first non-display region and the second non-display region.

15. The display device of claim 6, wherein, The display panel further includes a shielding metal located below the driving transistor and not present in the plurality of first transmission regions, and wherein the shielding metal is electrically connected to the driving voltage line.

16. The display device of claim 1, wherein, The display panel further includes a cathode electrode located in the plurality of light emission regions of the normal region and the plurality of light emission regions of the first optical region and not present in the plurality of first transmission regions of the first optical region.

17. The display device of claim 12, wherein, The first optical electronic device is a camera, the second optical electronic device is a sensor, and wherein the transmittance of the first optical region is greater than or equal to the transmittance of the second optical region.

18. The display device of claim 12, wherein, The number of sub-pixels per unit area in the first optical region is less than the number of sub-pixels per unit area in the normal region, and wherein the number of sub-pixels per unit area in the second optical region is greater than or equal to the number of sub-pixels per unit area in the first optical region, and is less than the number of sub-pixels per unit area in the normal region. wherein the number of sub-pixels per unit area in the second optical region is greater than or equal to the number of sub-pixels per unit area in the first optical region, and is less than the number of sub-pixels per unit area in the normal region.

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