An adaptive compensation circuit and method

Abstract

The application provides an adaptive compensation circuit and method, which comprises the following steps: a common-source amplifier is arranged between an error amplifier and a load circuit; one end of a capacitor is connected with an output end of the error amplifier, and the other end of the capacitor is connected with one end of a second fixed resistor; the second fixed resistor and a common end of a first fixed resistor are connected with a control end of an adjustable resistance circuit; the other end of the first fixed resistor is connected with the other control end of the adjustable resistance circuit; a detection end of the adjustable resistance circuit is connected with the load circuit; and an output end of the adjustable resistance circuit is connected with the common-source amplifier and the load circuit; when the adjustable resistance circuit detects that the load of the load circuit jumps from light load to heavy load, or jumps from heavy load to light load, the proportion of the fixed resistor connected to the circuit is adjusted, so that a compensation zero point changing with the load is obtained, and the purpose of improving the load transient response capability of the LDO while ensuring the stability of the LDO is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and in particular to an adaptive compensation circuit and method. BACKGROUND

[0002] Low dropout regulator (LDO) is generally used in a wide load range, and the LDO needs to maintain stability in a wide load range. However, many application occasions also have certain requirements for the load transient response of the LDO, and it is hoped that the LDO can have good load transient response performance, at this time, the LDO needs a larger bandwidth to achieve the above requirements. However, a larger bandwidth will affect the stability of the LDO in a wide load range.

[0003] Therefore, the prior art faces the problem of how to ensure that the LDO maintains stability in a wide load range while having good load transient response capability. SUMMARY

[0004] Therefore, the present application provides an adaptive compensation circuit and method to achieve the purpose of ensuring that the LDO can maintain stability while having good load transient response capability.

[0005] To achieve the above purpose, the present application provides the following technical solutions:

[0006] The first aspect of the present application provides an adaptive compensation circuit, which comprises an error amplifier, a common-source amplifier, a load circuit and an adaptive zero compensation network.

[0007] The common-source amplifier is arranged between the error amplifier and the load circuit.

[0008] The adaptive zero compensation network comprises a first fixed resistor Rzs, a second fixed resistor Rzx, a capacitor Cc and an adjustable resistance circuit.

[0009] One end of the capacitor Cc is connected to the output end of the error amplifier, and the other end is connected to one end of the second fixed resistor Rzx.

[0010] The common end of the second fixed resistor Rzx and the first fixed resistor Rzs is connected to a control end of the adjustable resistance circuit, the other end of the first fixed resistor Rzs is connected to the other control end of the adjustable resistance circuit, the detection end of the adjustable resistance circuit is connected to the load circuit, and the output end of the adjustable resistance circuit is connected to the common-source amplifier and the load circuit.

[0011] When the adjustable resistance circuit detects the load change of the load circuit, the first fixed resistance Rzs and the second fixed resistance Rzx are adjusted to compensate the frequency change with the resistance value and the load change.

[0012] Optionally, the adjustable resistance circuit comprises a first power tube M1, a second power tube M2 and a control circuit.

[0013] The source stage of the second power tube M2 is connected to the common end of the second fixed resistance Rzx and the first fixed resistance Rzs, and the gate of the second power tube M2 is connected to the second control end of the control circuit.

[0014] One end of the drain of the second power tube M2 connected to the source stage of the first power tube M1 is connected to the other end of the first fixed resistance Rzs.

[0015] The gate of the first power tube M1 is connected to the first control end of the control circuit, and the drain of the first power tube M1 is connected to the common source amplifier and the load circuit.

[0016] The sampling end of the control circuit is connected to the load circuit to collect the load generated by the load circuit. If the load becomes smaller, the control circuit controls the first power tube M1, the first fixed resistance Rzs and the second fixed resistance Rzx to form a first zero adjustment resistance to obtain a low-frequency compensation zero point. If the load becomes larger, the control circuit controls the first power tube M1, the second power tube M2 and the second fixed resistance Rzx to form a second zero adjustment resistance to obtain a high-frequency compensation zero point.

[0017] Optionally, the control circuit comprises a third power tube M3, a fourth power tube M4, a fifth power tube M5, a sixth power tube M6, a sampling tube MS and a filter.

[0018] The gate of the sampling tube MS is connected to the load circuit, and the source stage is connected to the drain of the sixth power tube M6. The sampling tube M7 is used to sample the size of the load.

[0019] The sixth power tube M6 and the fifth power tube M5 form a mirror circuit with a common gate. The fifth power tube M5 and the sixth power tube M6 clamp the drain voltage of the sampling tube MS to be equal to the output voltage VOUT of the load circuit.

[0020] The gate and source stage of the fifth power tube M5 are short-circuited, and are connected to the drain of the third power tube M3.

[0021] The third power tube M3 and the fourth power tube M4 are connected in common gate to form a mirror circuit, the gate and the drain of the fourth power tube M4 are shorted, and the source of the fourth power tube M4 is connected to the source of the sixth power tube M6, and the drain of the fourth power tube M4 is used as the first control end of the control circuit;

[0022] The filter is connected to the common end, and the output end of the filter is used as the second control end of the control circuit.

[0023] Optionally, the filter comprises a resistor R1 and a capacitor C1.

[0024] The common end of the resistor R1 and the capacitor C1 is used as the second control end of the control circuit.

[0025] The other end of the resistor R1 is connected to the common end, and the other end of the capacitor C1 is connected to the ground.

[0026] Optionally, the first power tube M1, the second power tube M2, the third power tube M3 and the fourth power tube M4 are N-type MOS tubes.

[0027] The fifth power tube M5 and the sixth power tube M6 are P-type MOS tubes.

[0028] The sampling tube MS is a P-type MOS tube.

[0029] Optionally, the common-source amplifier comprises a seventh power tube M7 and a bias current source IB1.

[0030] The gate of the seventh power tube M7 is connected to the output end of the error amplifier, the drain of the seventh power tube M7 is connected to the power supply, the gate of the seventh power tube M7 is connected to the positive electrode of the bias current source IB1, and the negative electrode of the bias current source IB1 is connected to the ground.

[0031] The seventh power tube M7 is a P-type MOS tube.

[0032] Optionally, the load circuit comprises an eighth power tube M8, a first voltage dividing resistor RFB1, a second voltage dividing resistor RFB2, a load capacitor Cout and a load resistor Rout.

[0033] The common end of the first voltage dividing resistor RFB1 and the second voltage dividing resistor RFB2 is connected to the negative input end of the error amplifier.

[0034] The common end of the first voltage dividing resistor RFB1, the load capacitor Cout and the load resistor Rout is connected to the source of the eighth power tube M8.

[0035] The other end of the second voltage dividing resistor RFB2, the load capacitor Cout and the load resistor Rout is connected to the ground.

[0036] The gate of the eighth power tube M8 is connected with the output end of the common source amplifier and the sampling end of the adjustable resistance circuit, and the drain is connected with the power supply;

[0037] The eighth power tube M8 is a P-type MOS tube.

[0038] The second aspect of the embodiment of the application provides a self-adaptive compensation method, which is suitable for the self-adaptive compensation circuit provided by the first aspect of the embodiment of the application, and the method comprises the following steps:

[0039] When the adjustable resistance circuit detects the load change of the load circuit, the self-adaptive zero compensation network in the self-adaptive compensation circuit adjusts the mode of the first fixed resistor Rzs and the second fixed resistor Rzx connected to the self-adaptive compensation circuit, so as to obtain the compensation zero point changing with the resistance value and the load.

[0040] Optionally, when the adjustable resistance circuit detects the load change of the load circuit, the first power tube M1 in the adjustable resistance circuit is controlled to form the first zero adjustment resistor together with the first fixed resistor Rzs and the second fixed resistor Rzx, so as to obtain the compensation zero point of low frequency.

[0041] Optionally, when the adjustable resistance circuit detects the load change of the load circuit, the first power tube M1, the second power tube M2 and the second fixed resistor Rzx in the adjustable resistance circuit are controlled to form the second zero adjustment resistor, so as to obtain the compensation zero point of high frequency.

[0042] Based on the adaptive compensation circuit and method provided in the above embodiment of the present application, the adaptive compensation circuit comprises an error amplifier, a common-source amplifier, a load circuit and an adaptive zero compensation network; the common-source amplifier is arranged between the error amplifier and the load circuit; the adaptive zero compensation network comprises a first fixed resistor Rzs, a second fixed resistor Rzx, a capacitor Cc and an adjustable resistance circuit; one end of the capacitor Cc is connected with an output end of the error amplifier, and the other end is connected with one end of the second fixed resistor Rzx; the common end of the second fixed resistor Rzx and the first fixed resistor Rzs is connected with a control end of the adjustable resistance circuit, the other end of the first fixed resistor Rzs is connected with the other control end of the adjustable resistance circuit, a detection end of the adjustable resistance circuit is connected with the load circuit, and an output end of the adjustable resistance circuit is connected with the common-source amplifier and the load circuit; when the adjustable resistance circuit detects the load change of the load circuit, the first fixed resistor Rzs and the second fixed resistor Rzx are adjusted to obtain the compensation zero point changing with the load. In the present scheme, the change of the load in the load circuit is detected by the adjustable resistance circuit, and the proportion of the fixed resistance access circuit is adjusted, so that the compensation zero point changing with the resistance value and the load is obtained, and the purpose of improving the load transient response capability of the LDO while ensuring the stability of the LDO is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of the provided drawings.

[0044] Figure 1 The structural schematic diagram of the adaptive compensation circuit disclosed in the embodiment of the present application is shown in the figure.

[0045] Figure 2 The structural schematic diagram of another adaptive compensation circuit disclosed in the embodiment of the present application is shown in the figure.

[0046] Figure 3 The structural schematic diagram of the control circuit disclosed in the embodiment of the present application is shown in the figure.

[0047] Figure 4 The jump ratio comparison diagram of the fast control signal VF and the slow control signal VS disclosed in the embodiment of the present application is shown in the figure.

[0048] Figure 5 The structural schematic diagram of another adaptive compensation circuit disclosed in the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0050] In the present application, the terms "comprising", "containing" or any other variant thereof are intended to cover the non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitation, the element defined by the sentence "including a…" does not exclude the presence of other identical elements in the process, method, article or equipment including the element.

[0051] Based on the prior art, how to ensure that the LDO remains stable in a wide load range while having good load transient response capability is a problem. The embodiments of the present application disclose a self-adaptive compensation circuit and method, which can ensure that the LDO can remain stable while having good load transient response capability on the basis of ensuring the stability of the LDO and without introducing a complex transient response enhancement circuit. The specific embodiments are described in detail as follows.

[0052] As shown in FIG. 1, it is a structural schematic diagram of a self-adaptive compensation circuit disclosed by the embodiments of the present application. The self-adaptive compensation circuit mainly includes an error amplifier 10, a common-source amplifier 11, a load circuit 12 and a self-adaptive zero compensation network 13. Figure 1

[0053] The common-source amplifier 11 is arranged between the error amplifier 10 and the load circuit 12.

[0054] The positive input end of the error amplifier 10 inputs an external reference voltage VREF, and the negative input end receives a negative feedback voltage VFB output by the load circuit 12.

[0055] The self-adaptive zero compensation network 13 includes a first fixed resistor Rzs, a second fixed resistor Rzx, a capacitor Cc and an adjustable resistor circuit 14.

[0056] One end of the capacitor Cc is connected with the output end of the error amplifier 10, and the other end is connected with one end of the second fixed resistor Rzx.

[0057] ​The common end of the second fixed resistor Rzx and the first fixed resistor Rzs is connected to a control end of the adjustable resistance circuit 14, the other end of the first fixed resistor Rzs is connected to another control end of the adjustable resistance circuit 14, the detection end of the adjustable resistance circuit is connected to the load circuit 12, and the output end of the adjustable resistance circuit 14 is connected to the common-source amplifier 11 and the load circuit 12.

[0058] Based on the above embodiment of the present application Figure 1 The disclosed adaptive compensation circuit has a pole wp1 at EA_OUT, a pole wp2 at VOUT which changes with the load, and a pole wp3 at VGATE.

[0059] In the process of realizing the load range stability while ensuring that the system has good load transient response capability, the adaptive zero compensation network 13 detects the load change of the load circuit 12 through the adjustable resistance circuit 14, and when the adjustable resistance circuit 14 detects that the load of the load circuit 12 changes, the first fixed resistor Rzs and the second fixed resistor Rzx are adjusted to obtain a compensation zero wz1 whose frequency changes with the resistance value and the load.

[0060] In the process, specifically, the frequency of the compensation zero wz1 changes with the adjusted resistance value at the same time, thereby obtaining good load transient response.

[0061] In the process, specifically, the frequency of the compensation zero wz1 changes with the adjusted resistance value at the same time, thereby obtaining good load transient response.

[0062] Based on Figure 1 The disclosed adaptive compensation circuit, wherein the adjustable resistance circuit 14 can include: a first power tube M1, a second power tube M2, and a control circuit 15.

[0063] As Figure 2 As shown, the source level S of the second power tube M2 is connected to the common end of the second fixed resistor Rzx and the first fixed resistor Rzs, and the gate G of the second power tube M2 is connected to the second control end of the control circuit 15. The second control end is used to output a slow control signal VS.

[0064] The drain D of the second power tube M2 is connected to one end of the source level S of the first power tube M1, and the other end of the first fixed resistor Rzs is connected.

[0065] The gate G of the first power tube M1 is connected with the first control end of the control circuit 15, and the drain D of the first power tube M1 is connected with the common-source amplifier 11 and the load circuit 12. The first control end is used for outputting a fast control signal VF.

[0066] The sampling end of the control circuit 15 is connected with the load circuit 12, and is used for collecting the load generated by the load circuit 12.

[0067] The first power tube M1 is used as a fast adjustable resistance R_M1, and the second power tube M2 is used as a slow adjustable resistance R_M2.

[0068] In the specific implementation, if the load becomes small, that is, the adaptive compensation circuit is in light load, the fast adjustable resistance R_M1 and the slow adjustable resistance R_M2 are both large, at this time, the control circuit 15 controls the first power tube M1, the first fixed resistance Rzs and the second fixed resistance Rzx to form a first zero adjustment resistance, the resistance value of the first zero adjustment resistance is R_M1+Rzs+Rzx, and the compensation zero point of low frequency is obtained based on the first zero adjustment resistance.

[0069] If the load becomes large, that is, the adaptive compensation circuit is in heavy load, the fast adjustable resistance R_M1 and the slow adjustable resistance R_M2 are both small, at this time, the control circuit 15 controls the first power tube M1, the second power tube M2 and the second fixed resistance Rzx to form a second zero adjustment resistance, the resistance value of the second zero adjustment resistance is R_M1+R_M2+Rzx, and the compensation zero point of high frequency is obtained based on the second zero adjustment resistance.

[0070] In the adaptive compensation circuit disclosed in the embodiment of the present application, the first power tube M1, the second power tube M2, the first fixed resistance Rzs and the second fixed resistance Rzx are adjusted to form different zero adjustment resistances according to the load change, the compensation zero point of the corresponding frequency is determined based on the obtained zero adjustment resistance, and the pole wp2 is compensated through the compensation zero point, so that the adaptive compensation circuit can ensure that the LDO can maintain stability and has good load transient response capability on the basis of ensuring the stability of the LDO and without introducing a complex transient response enhancement circuit.

[0071] In the adaptive compensation circuit disclosed in the embodiment of the present application, the first power tube M1, the second power tube M2, the first fixed resistance Rzs and the second fixed resistance Rzx are adjusted to form different zero adjustment resistances according to the load change, the compensation zero point of the corresponding frequency is determined based on the obtained zero adjustment resistance, and the pole wp2 is compensated through the compensation zero point, so that the adaptive compensation circuit can ensure that the LDO can maintain stability and has good load transient response capability on the basis of ensuring the stability of the LDO and without introducing a complex transient response enhancement circuit. Figure 2 The specific structure of the control circuit 15 disclosed in the embodiment is as shown in the figure. Figure 3 The control circuit mainly includes a third power tube M3, a fourth power tube M4, a fifth power tube M5, a sixth power tube M6, a sampling tube MS and a filter 16.

[0072] The gate G of the sampling tube MS is connected with the load circuit, and the source stage S is connected with the drain D of the sixth power tube M6. The sampling tube MS is used for sampling the size of the load.

[0073] The sixth power transistor M6 and the fifth power transistor M5 are connected in common gate to form a mirror circuit, and the fifth power transistor M5 and the sixth power transistor M6 are clamped so that the drain voltage of the sampling transistor MS is equal to the output voltage VOUT of the load circuit.

[0074] The gate G and the source S of the fifth power transistor M5 are shorted, and the drain D of the third power transistor M3 is connected.

[0075] The third power transistor M3 and the fourth power transistor M4 are connected in common gate to form a mirror circuit, the gate G and the drain D of the fourth power transistor M4 are shorted, and the source S of the sixth power transistor M6 is connected, and the drain D of the fourth power transistor M4 is used as the first control terminal of the control circuit.

[0076] The common terminal is connected to the filter 16, and the output terminal of the filter 16 is used as the second control terminal of the control circuit.

[0077] In an embodiment, the filter 16 can be composed of a resistor R1 and a capacitor C1.

[0078] The common terminal connected to the resistor R1 and the capacitor C1 is used as the second control terminal of the control circuit.

[0079] The other terminal of the resistor R1 is connected to the common terminal, and the other terminal of the capacitor C1 is grounded.

[0080] The slow control signal VS output by the second control terminal is obtained by filtering the fast control signal VF through a filter composed of a resistor R1 and a capacitor C1, and the slow control signal VS has a response delay compared with the fast control signal VF. That is, when the load changes, the rising edge of the fast control signal VF is relatively steep, and the rising edge of the slow control signal VS is relatively slow. The specific jump ratio of the fast control signal VF and the slow control signal VS is shown in the following table. Figure 4

[0081] In combination with Figure 2 and Figure 3 ​It is explained that in the specific implementation, the sampling tube MS can be used to sample the load size of the load circuit. The fifth power tube M5 and the sixth power tube M6 clamp the drain voltage of the sampling tube MS to be equal to the output voltage VOUT of the load circuit. Based on this, the accuracy of the sampling current is ensured. When the load of the load circuit is larger, the sampling current of the sampling tube MS is also larger. The fast control signal VF and the slow control signal VS are also higher, and the fast adjustable resistor R_M1 and the slow adjustable resistor R_M2 controlled by the fast control signal VF and the slow control signal VS are also smaller, and the generated compensation zero point is also higher in frequency, and the pole wp2 to be offset at this time is also high in frequency. By compensating the pole wp2 with the current generated compensation zero point, the purpose of ensuring that the LDO can maintain stability while having good load transient response capability can be achieved.

[0082] It should be noted that the various power tubes disclosed in the above embodiments of the present application include but are not limited to: Figures 1 to 3

[0083] The first power tube M1, the second power tube M2, the third power tube M3 and the fourth power tube M4 are N-type MOS tubes.

[0084] The fifth power tube M5 and the sixth power tube M6 are P-type MOS tubes.

[0085] The sampling tube MS is a P-type MOS tube.

[0086] It should be noted that the resistance values of various resistors and the capacitance values of capacitors disclosed in the above embodiments of the present application can be designed and debugged by simulation tools according to the actual load jump rate.

[0087] In combination with the adaptive compensation circuit disclosed in the above embodiments of the present application Figure 1 and Figure 2 the control circuit disclosed. As Figure 3 shown is another structure of an adaptive compensation circuit disclosed in an embodiment of the present application. Figure 5

[0088] The overall architecture of the adaptive compensation circuit is a negative feedback LDO architecture composed of three-stage amplifiers.

[0089] The first stage is an error amplifier 10.

[0090] The second stage is a common-source amplifier 11.

[0091] The common-source amplifier 11 is arranged between the error amplifier 10 and the load circuit 12.

[0092] The common-source amplifier 11 includes a seventh power tube M7 and a bias current source IB1. The seventh power tube M7 can be a P-type MOS tube.​​

[0093] The third stage is a load circuit 12 and an adaptive zero compensation network 13.

[0094] The load circuit 12 comprises an eighth power tube M8, a first voltage dividing resistor RFB1, a second voltage dividing resistor RFB2, a load capacitor Cout and a load resistor Rout. The eighth power tube M8 is optionally a P-type MOS tube.

[0095] The eighth power tube M8 and the load resistor Rout form a common-source power amplifier, and the first voltage dividing resistor RFB1 and the second voltage dividing resistor RFB2 form a negative feedback circuit.

[0096] The adaptive zero compensation network 13 comprises a first fixed resistor Rzs, a second fixed resistor Rzx, a capacitor Cc, a first power tube M1, a second power tube M2, a third power tube M3, a fourth power tube M4, a fifth power tube M5, a sixth power tube M6, a sampling tube MS, a resistor R1 and a capacitor C1.

[0097] The first power tube M1, the second power tube M2, the third power tube M3 and the fourth power tube M4 are N-type MOS tubes.

[0098] The fifth power tube M5 and the sixth power tube M6 are P-type MOS tubes.

[0099] The sampling tube MS is a P-type MOS tube.

[0100] The third power tube M3, the fourth power tube M4, the fifth power tube M5, the sixth power tube M6, the sampling tube MS, the resistor R1 and the capacitor C1 form a control circuit and output a fast control signal VF and a slow control signal VS.

[0101] The N-type MOS tube M1 controlled by the fast control signal VF serves as a fast adjustable resistor R_M1, and the N-type MOS tube M2 controlled by the slow control signal VS serves as a slow adjustable resistor R_M2.

[0102] The specific connection mode of the above-mentioned three-stage amplifier is as follows:

[0103] The positive input end of the error amplifier 10 inputs a reference voltage VREF, and the negative input end is connected to the common end of the first voltage dividing resistor RFB1 and the second voltage dividing resistor RFB2 in series and receives a negative feedback voltage VFB.

[0104] The output end of the error amplifier 10 is connected to the gate G of the seventh power tube M7 and one end of the capacitor Cc, respectively.

[0105] The drain D of the seventh power transistor M7 is connected to the power supply VDD, and the source S is connected to the positive pole of the bias current source IB1, and the negative pole of the bias current source IB1 is grounded.

[0106] The source S of the seventh power transistor M7 is connected to the drain D of the first power transistor M1 and the gate G of the eighth power transistor M8.

[0107] The other end of the capacitor Cc is connected to one end of the second fixed resistor Rzx.

[0108] The common end of the second fixed resistor Rzx and the first fixed resistor Rzs is connected to the source S of the second power transistor M2, and the gate G of the second power transistor M2 is connected to the second control end of the control circuit 15. The second control end is used to output the slow control signal VS.

[0109] The other end of the first fixed resistor Rzs is connected to the drain D of the second power transistor M2 and the source S of the first power transistor M1.

[0110] The gate G of the first power transistor M1 is connected to the drain D of the fourth power transistor M4. The drain D of the fourth power transistor M4 outputs the fast control signal VF.

[0111] The drain D of the fourth power transistor M4 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the common end of the capacitor C1, which outputs the slow control signal VS. The other end of the capacitor C1 is grounded.

[0112] The fourth power transistor M4 and the third power transistor M3 are connected in common gate to form a mirror circuit. The gate G and the drain D of the fourth power transistor M4 are shorted, and the source S of the sixth power transistor M6 is connected.

[0113] The sixth power transistor M6 and the fifth power transistor M5 are connected in common gate to form a mirror circuit. The fifth power transistor M5 and the sixth power transistor M6 clamp the drain voltage of the sampling transistor MS to be equal to the output voltage VOUT of the load circuit.

[0114] The gate G and the source S of the fifth power transistor M5 are shorted, and the drain D of the third power transistor M3 is connected.

[0115] The drain D of the fifth power transistor M5 is connected to the output end of the load circuit 12.

[0116] The drain D of the sixth power transistor M6 is connected to the source S of the sampling transistor MS.

[0117] The drain D of the sampling transistor MS is connected to the power supply VDD.

[0118] The gate G of the sampling tube MS is connected with the gate G of the eighth power tube M8.

[0119] The drain D of the eighth power tube M8 is connected with the power supply VDD.

[0120] The source S of the eighth power tube M8 is connected with the common end of the second voltage dividing resistor RFB2, the load capacitor Cout and the load resistor Rout.

[0121] The other end of the first voltage dividing resistor RFB1, the load capacitor Cout and the load resistor Rout is grounded.

[0122] In the process of ensuring that the LDO can maintain stability and also has good load transient response capability:

[0123] The sampling tube MS is the sampling tube of the eighth power tube M8, and samples the information of the load size. In the process of the load jumping from light load to heavy load, the N-type MOS tube M1 rapidly decreases due to the fast control signal VF jumping from VF_L to VF_H, and the zero setting resistor is determined by R_M1+R_M2+Rzx to obtain a higher frequency compensation zero point. By tracking the compensation pole wp2, it is ensured that the main part of the circuit system is in a stable state. In this process, the N-type MOS tube M2 slowly jumps from VS_L to VS_H due to the slow control signal VS, and the zero setting resistor will experience a process of decreasing from R_M1+Rzs+Rzx to R_M1+R_M2+Rzx, thereby delaying the movement of the compensation zero point from low frequency to high frequency, and increasing the circuit system bandwidth in the jumping process, so that the LDO can maintain stability while obtaining good load transient response of light load jumping to heavy load.

[0124] In the process of the load jumping from heavy load to light load, the N-type MOS tube M1 rapidly increases due to the fast control signal VF jumping from VF_H to VF_L, and the N-type MOS tube M1 rapidly increases and dominates in the whole zero setting resistor, that is, R_M1+Rzs+Rzx, so that the LDO can maintain stability while the load transient response of heavy load jumping to light load is comparable to the traditional adaptive compensation scheme.

[0125] In the adaptive compensation circuit disclosed in the embodiment of the present application, the change of the load in the load circuit is detected through the adjustable resistance circuit, and the proportion of the fixed resistance circuit is adjusted in the process of the load jumping from light load to heavy load, or in the process of the load jumping from heavy load to light load, so as to obtain a compensation zero point varying with the load, and achieve the purpose of improving the load transient response capability of the LDO while ensuring the stability of the LDO.

[0126] Based on the adaptive compensation circuit disclosed in the above embodiment of the present application, the embodiment of the present application further discloses an adaptive compensation method, which is suitable for the aboveFigures 1 to 5 The adaptive compensation circuit is disclosed, and the method is specifically as follows:

[0127] The adaptive zero compensation network in the adaptive compensation circuit adjusts the way in which the first fixed resistor Rzs and the second fixed resistor Rzx are connected to the adaptive compensation circuit when the adjustable resistance circuit detects the load change of the load circuit, so as to obtain the compensation zero point that changes with the load.

[0128] Specifically, when the adjustable resistance circuit detects the load change of the load circuit, the first power tube M1 in the adjustable resistance circuit is controlled to form a first zero adjustment resistor together with the first fixed resistor Rzs and the second fixed resistor Rzx, so as to obtain a low-frequency compensation zero point.

[0129] When the adjustable resistance circuit detects the load change of the load circuit, the first power tube M1, the second power tube M2 and the second fixed resistor Rzx in the adjustable resistance circuit are controlled to form a second zero adjustment resistor, so as to obtain a high-frequency compensation zero point.

[0130] In the adaptive compensation circuit disclosed in the embodiment of the present application, the adjustable resistance circuit detects the load change in the load circuit, and the proportion of the fixed resistor connected to the circuit is adjusted during the process of the load jumping from light load to heavy load or during the process of the load jumping from heavy load to light load, so as to obtain a compensation zero point that changes with the load, thereby achieving the purpose of improving the load transient response capability of the LDO while ensuring the stability of the LDO.

[0131] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment mainly describes the difference from other embodiments. Especially, for the circuit or circuit embodiment, since it is basically similar to the method embodiment, it is described more simply, and the related parts can be referred to the part of the circuit embodiment. The above-described circuit structure and circuit embodiment are only schematic, and the units described as separate components can be or can not be physically separated, and the components displayed as units can be or can not be physical units, that is, they can be located in one place, or can be distributed on multiple network units. According to the actual needs, part or all of the modules can be selected to achieve the purpose of the embodiment scheme. Those skilled in the art can understand and implement it without creative labor.

[0132] The foregoing description of the disclosed embodiments enables a person skilled in the art to make or use the application. Modifications of these embodiments will occur to persons of skill in the art, and that the appended claims are intended to cover all such modifications that do not depart from the true spirit and scope of the application. Therefore, the application is not limited to the embodiments shown but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An adaptive compensation circuit, characterized by, The adaptive compensation circuit comprises an error amplifier, a common-source amplifier, a load circuit and an adaptive zero compensation network; The common-source amplifier is arranged between the error amplifier and the load circuit; The adaptive zero compensation network comprises a first fixed resistor Rzs, a second fixed resistor Rzx, a capacitor Cc and an adjustable resistance circuit; One end of the capacitor Cc is connected to an output terminal of the error amplifier, and the other end is connected to one end of the second fixed resistor Rzx; The common end of the second fixed resistor Rzx and the first fixed resistor Rzs is connected to a control terminal of the adjustable resistance circuit, the other end of the first fixed resistor Rzs is connected to the other control terminal of the adjustable resistance circuit, a detection terminal of the adjustable resistance circuit is connected to the load circuit, and an output terminal of the adjustable resistance circuit is connected to the common-source amplifier and the load circuit; When the adjustable resistance circuit detects a load change of the load circuit, the first fixed resistor Rzs and the second fixed resistor Rzx are adjusted to obtain a compensation zero point with a variable resistance and a variable load; The adjustable resistance circuit comprises a first power tube M1, a second power tube M2 and a control circuit; The source level of the second power tube M2 is connected to the common end of the second fixed resistor Rzx and the first fixed resistor Rzs, and the gate of the second power tube M2 is connected to the second control terminal of the control circuit; One end of the drain of the second power tube M2 connected to the source level of the first power tube M1 is connected to the other end of the first fixed resistor Rzs; The gate of the first power tube M1 is connected to the first control terminal of the control circuit, and the drain of the first power tube M1 is connected to the common-source amplifier and the load circuit; The sampling terminal of the control circuit is connected to the load circuit to collect the load generated by the load circuit, if the load becomes smaller, the control circuit controls the first power tube M1 and the first fixed resistor Rzs and the second fixed resistor Rzx to form a first zero adjustment resistance to obtain a low-frequency compensation zero point, if the load becomes larger, the control circuit controls the first power tube M1, the second power tube M2 and the second fixed resistor Rzx to form a second zero adjustment resistance to obtain a high-frequency compensation zero point.

2. The circuit of claim 1, wherein, The control circuit comprises a third power tube M3, a fourth power tube M4, a fifth power tube M5, a sixth power tube M6, a sampling tube MS and a filter; The gate of the sampling tube MS is connected to the load circuit, and the source level is connected to the drain of the sixth power tube M6, and the sampling tube M7 is used to sample the size of the load; The sixth power tube M6 and the fifth power tube M5 share a gate to form a mirror circuit, and the fifth power tube M5 and the sixth power tube M6 clamp so that the drain voltage of the sampling tube MS is equal to the output voltage VOUT of the load circuit; The gate and the source level of the fifth power tube M5 are short-circuited, and are connected to the drain of the third power tube M3. The third power tube M3 and the fourth power tube M4 are common-gate mirror circuits, the gate and the drain of the fourth power tube M4 are shorted, and the source of the fourth power tube M4 is connected to the sixth power tube M6, and the drain of the fourth power tube M4 is the first control end of the control circuit; The common end is connected to the filter, and the output end of the filter is the second control end of the control circuit.

3. The circuit of claim 2, wherein, The filter comprises a resistor R1 and a capacitor C1; The common end connected to the resistor R1 and the capacitor C1 is the second control end of the control circuit; The other end of the resistor R1 is connected to the common end, and the other end of the capacitor C1 is grounded.

4. The circuit of claim 3, wherein, The first power tube M1, the second power tube M2, the third power tube M3 and the fourth power tube M4 are N-type MOS tubes; The fifth power tube M5 and the sixth power tube M6 are P-type MOS tubes; The sampling tube MS is a P-type MOS tube.

5. The circuit of any one of claims 1 to 4, wherein, The common-source amplifier comprises a seventh power tube M7 and a bias current source IB1; The gate of the seventh power tube M7 is connected to the output end of the error amplifier, the drain is connected to the power supply, the gate is connected to the positive pole of the bias current source IB1, and the negative pole of the bias current source IB1 is grounded; The seventh power tube M7 is a P-type MOS tube.

6. The circuit of any one of claims 1 to 4, wherein, The load circuit comprises an eighth power tube M8, a first voltage dividing resistor RFB1, a second voltage dividing resistor RFB2, a load capacitor Cout and a load resistor Rout; The common end of the first voltage dividing resistor RFB1 and the second voltage dividing resistor RFB2 in series is connected to the negative input end of the error amplifier; The common end of the first voltage dividing resistor RFB1, the load capacitor Cout and the load resistor Rout is connected to the source of the eighth power tube M8; The other end of the second voltage dividing resistor RFB2, the load capacitor Cout and the load resistor Rout is grounded; The gate of the eighth power tube M8 is connected to the output end of the common-source amplifier and the sampling end of the adjustable resistance circuit, and the drain is connected to the power supply; The eighth power tube M8 is a P-type MOS tube.

7. A method of adaptive compensation, characterized by, The method is suitable for the adaptive compensation circuit in any one of claims 1 to 6, and the method comprises: When the adjustable resistance circuit detects the load change of the load circuit, the adaptive zero compensation network in the adaptive compensation circuit adjusts the way in which the first fixed resistor Rzs and the second fixed resistor Rzx are connected to the adaptive compensation circuit to obtain a compensation zero point that changes with the resistance value and the load; When the adjustable resistance circuit detects that the load of the load circuit decreases, the first power tube M1 in the adjustable resistance circuit and the first fixed resistor Rzs and the second fixed resistor Rzx form a first zero adjusting resistor to obtain a low-frequency compensation zero point; When the adjustable resistance circuit detects that the load of the load circuit increases, the first power tube M1, the second power tube M2 and the second fixed resistor Rzx in the adjustable resistance circuit form a second zero adjusting resistor to obtain a high-frequency compensation zero point.

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