Semiconductor structure and method of fabricating the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; performing decoupling plasma nitridation on the gate dielectric layer, wherein the gas used in the decoupling plasma nitridation comprises N x O y ; performing post-nitridation annealing on the gate dielectric layer; and forming a gate conductive layer on the gate dielectric layer. The gas used in the decoupling plasma nitridation of the gate dielectric layer of the application comprises N x O y , and N x O y plasma is used to replace conventional N2 plasma. The advantage is that the same nitrogen concentration can be achieved with a lower dose to improve the K value of the gate dielectric layer. Meanwhile, the oxygen in the N x O y plasma fills the oxygen vacancy defects in the gate dielectric layer, reduces the probability of defect generation, and thus improves the reliability of the device. In addition, the manufacturing method of the semiconductor structure of the application does not need to increase the raw materials and process steps, so as not to increase the production cost and process complexity.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor integrated circuits, and relates to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] The main semiconductor device of integrated circuits, especially very large scale integrated circuits, is a metal-oxide-semiconductor field-effect transistor (MOSFET). With the continuous development of integrated circuit manufacturing technology, the technology node of semiconductor devices is continuously reduced, and the geometric size of semiconductor devices is continuously reduced according to Moore's Law. When the size of semiconductor devices is reduced to a certain extent, various secondary effects caused by the physical limits of semiconductor devices appear in succession, and it becomes more and more difficult to scale down the characteristic size of semiconductor devices in proportion. Among them, the most challenging in the field of semiconductor manufacturing is how to solve the problem of large leakage current of semiconductor devices. The large leakage current of semiconductor devices is mainly caused by the continuous reduction of the thickness of the traditional gate dielectric layer.

[0003] With the development of semiconductor technology, high dielectric constant (high-K) materials are usually used in the gate structure of semiconductor devices of advanced process nodes instead of traditional silicon dioxide materials as gate dielectric layers, and metals are used as gate electrodes to form a high-K metal gate (HKMG) structure to avoid Fermi level pinning effect and boron penetration effect of high-K materials and traditional gate electrode materials, thereby reducing the leakage current of semiconductor devices.

[0004] Currently, in the decoupled plasma nitridation (DPN) and post nitridation anneal (PNA) processes of high-K metal gates, N is doped into the thin film by plasma dissociation, and then high-temperature annealing is performed to fix it. There are two purposes of doping N in the high-K dielectric layer: to reduce the effective oxide thickness (EOT) and to repair defects. Among them, doping N can increase the K value of the interface layer (IL), thereby reducing the EOT, and doping N can repair the oxygen vacancy defect problem of the high-K dielectric layer and the interface layer.

[0005] However, there is still room for improvement in the oxygen vacancy defect problem of the high-K dielectric layer in this process, so it is necessary to find a substitute material that can fill the oxygen vacancy defect problem and maintain the nitrogen concentration to improve the K value, to improve this problem.

[0006] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely describing the technical scheme of the present application and facilitating the understanding of the skilled in the art. The above technical scheme cannot be considered as known to the skilled in the art only because it is described in the background section of the present application. SUMMARY

[0007] In view of the above-mentioned disadvantages of the prior art, the present application aims to provide a semiconductor structure and a manufacturing method thereof, which can solve the problem that the K value and quality of the gate dielectric layer need to be improved in the prior art.

[0008] To achieve the above object and other related objects, the present application provides a manufacturing method of a semiconductor structure, comprising the following steps:

[0009] providing a semiconductor substrate, and forming a gate dielectric layer on the semiconductor substrate;

[0010] performing decoupled plasma nitridation treatment on the gate dielectric layer, wherein the gas used in the decoupled plasma nitridation treatment comprises N x O y , wherein x is the atomic component of N, y is the atomic component of O, x is greater than 0, and y is greater than 0;

[0011] performing post-nitridation annealing treatment on the gate dielectric layer;

[0012] forming a gate conductive layer on the gate dielectric layer.

[0013] Optionally, the gas used in the decoupled plasma nitridation treatment comprises one or more of N2O, N2O3, N2O4 and N2O5.

[0014] Optionally, only inert gas is used in at least one stage of the post-nitridation annealing treatment.

[0015] Optionally, the gas used in at least one stage of the post-nitridation annealing treatment comprises a reducing gas or an oxidizing gas.

[0016] Optionally, the gate dielectric layer comprises a high-K dielectric layer, and the gate conductive layer comprises a metal layer.

[0017] Optionally, the gate dielectric layer further comprises an interface layer, and the high-K dielectric layer is located on the interface layer.

[0018] Optionally, the high-K dielectric layer comprises a hafnium oxide layer or an aluminum oxide layer, and the gate conductive layer comprises a TiN layer.

[0019] Optionally, the gate dielectric layer comprises a silicon oxide layer, and the gate conductive layer comprises a polysilicon layer.

[0020] Optionally, a shallow trench isolation structure is formed in the semiconductor substrate.

[0021] The present application also provides a semiconductor structure comprising a semiconductor substrate, a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer is formed on the semiconductor substrate, and the gate conductive layer is formed on the gate dielectric layer, and the semiconductor structure is formed by the method for forming a semiconductor structure according to any one of the above.

[0022] As described above, the method for forming a semiconductor structure of the present application uses N x O y as the gas for decoupling plasma nitridation of the gate dielectric layer, which has the advantage of achieving the same nitrogen concentration with a lower dose to increase the K value of the gate dielectric layer, and the oxygen in the N x O y plasma fills the oxygen vacancy defects in the gate dielectric layer, reducing the probability of defect generation, thereby improving the reliability of the device. In addition, the method for forming a semiconductor structure of the present application does not require additional raw materials and process steps, thereby not increasing production costs and process complexity, and compared with conventional N2 raw gas, the N x O y plasma can reduce gas consumption, which is beneficial to reduce costs. x y BRIEF DESCRIPTION OF DRAWINGS

[0023] Fig. 1 A process flow chart of the method for forming a semiconductor structure of the present application is shown.

[0024] Fig. 2 A cross-sectional schematic view of the structure obtained after forming a gate dielectric layer on a semiconductor substrate by the method for forming a semiconductor structure of the present application is shown.

[0025] Fig. 3 A cross-sectional schematic view of a high-K metal gate structure formed by the method for forming a semiconductor structure of the present application is shown.

[0026] ELEMENT REFERENCE

[0027] S1-S4 steps

[0028] 1 semiconductor substrate

[0029] 2 shallow trench isolation structure

[0030] 3 interface layer

[0031] 4 high-K dielectric layer

[0032] 5 bottom barrier TiN layer​​

[0033] 6 bottom barrier TaN layer

[0034] 7 P-type work function TiN layer

[0035] 8 N-type work function TiAl layer

[0036] 9 top barrier TiN layer

[0037] 10 Al metal layer

[0038] 11 sidewall structure DETAILED DESCRIPTION

[0039] The present application is herein described, by way of example only, with reference to embodiments thereof. It is to be understood that variations and modifications will be apparent to those skilled in the art and that the scope of the application encompasses all such variations and modifications. The embodiments described herein are intended to be merely illustrative of the present application and not in limitation thereof. Accordingly, one of ordinary skill in the art would recognize the ingenuity thereof upon reading the specification, and it is intended to claim all modifications and alterations in the implementation of the present application which come within the scope of the following claims and the equivalents thereof.

[0040] Reference will now be made to the drawings, wherein Figs. 1 to 3 It is to be understood that the above-mentioned embodiments are only to illustrate the basic concept of the present application, and thus the drawings only show the components related to the present application, rather than the number, shape and size of the components in actual implementation. The actual implementation of the components can be arbitrarily changed in terms of shape, number and ratio, and the layout of the components can be more complex.

[0041] Embodiment One

[0042] The present embodiment provides a method for manufacturing a semiconductor structure, please refer to Fig. 1 , which is a process flow diagram of the method, including the following steps:

[0043] S1: providing a semiconductor substrate, and forming a gate dielectric layer on the semiconductor substrate;

[0044] S2: performing decoupled plasma nitridation treatment on the gate dielectric layer, the gas used in the decoupled plasma nitridation treatment includes N x O y , wherein x is the atomic component of N, y is the atomic component of O, x is greater than 0, and y is greater than 0;

[0045] S3: performing post-nitridation annealing treatment on the gate dielectric layer;

[0046] S4: forming a gate conductive layer on the gate dielectric layer.

[0047] First, the step S1 is performed: providing a semiconductor substrate, and forming a gate dielectric layer on the semiconductor substrate. Please refer toFig. 2 , which shows a cross-sectional schematic view of the structure obtained after performing the present step.

[0048] As an example, the semiconductor substrate includes a substrate layer 1 and a shallow trench isolation structure 2 pre-fabricated in the substrate layer 1, which divides an active region in the substrate layer 1.

[0049] As an example, the substrate layer 1 can be a Si substrate, a Ge substrate, a SiGe substrate, a SiC substrate, a III-V compound substrate or other suitable semiconductor substrate known in the art, and the substrate layer 1 can have P-well and / or N-well and other required structures pre-fabricated therein. In the present embodiment, the substrate layer 1 is a Si substrate.

[0050] As an example, one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition and oxidation can be used to form the gate dielectric layer on the semiconductor substrate.

[0051] As an example, the gate dielectric layer includes a high-K dielectric layer 4, which together with a subsequently formed gate conductive layer of metal material forms a high-K metal gate structure. High-K dielectric refers to a dielectric with a relative dielectric constant greater than that of silicon oxide. In the present embodiment, the high-K dielectric layer 4 includes a hafnium oxide layer or an aluminum oxide layer.

[0052] As an example, the gate dielectric layer further includes an interface layer 3, and the high-K dielectric layer 4 is located on the interface layer 3.

[0053] As an example, the material of the interface layer 3 includes at least one of SiO2, SiON and SiCO. The interface layer 3 serves to provide a good interface basis for the subsequent formation of the high-K dielectric layer 4 to improve the quality of the high-K dielectric layer 4, reduce the interface state density between the high-K dielectric layer 4 and the substrate layer 1, and avoid adverse effects caused by direct contact between the high-K dielectric layer 4 and the substrate layer 1. The thickness of the interface layer 3 can be reasonably set based on actual needs to meet the structure and performance requirements of the device. In the present embodiment, the interface layer 3 is formed by rapid thermal oxidation in an in-situ steam generation (ISSG) chamber, which can improve the interface performance between the interface layer 3 and the high-K dielectric layer 4.

[0054] After forming the high-K dielectric layer 4, the step S2 of performing decoupled plasma nitridation on the gate dielectric layer is performed. The gas used in the decoupled plasma nitridation includes N x O y , wherein x is the atomic component of N, y is the atomic component of O, x is greater than 0, and y is greater than 0.

[0055] As an example, the decoupled plasma nitridation process is performed in the ISSG chamber, and the gas used in the decoupled plasma nitridation process includes, but is not limited to, one or more of N2O, N2O3, N2O4, and N2O5.

[0056] Specifically, N2O is selected as the gas in the decoupled plasma nitridation process in the embodiment. x O y The decoupled plasma nitridation process on the gate dielectric layer can incorporate N into the gate dielectric layer to increase the K value of the gate dielectric layer, and on the other hand, the N x O y The oxygen in the plasma fills the oxygen vacancy defects in the gate dielectric layer, reduces the probability of defect generation, and thus helps to improve the reliability of the device. In the embodiment, the interface layer 3 (for example, the SiO2 layer) in the gate dielectric layer has a higher K value and a lower EOT due to the incorporation of N, and the oxygen vacancy defects in the interface layer 3 and the hafnium oxide layer or the aluminum oxide layer as the high-K dielectric layer are also filled.

[0057] In addition to the main purpose, compared with the conventional N2 raw gas, the N2O gas used in the embodiment can reduce the amount of gas used, that is, the same nitrogen concentration can be achieved with a lower dose to increase the K value of the gate dielectric layer, which not only does not increase the cost, but also helps to reduce the cost. x O y The gas can also reduce the amount of gas used, that is, the same nitrogen concentration can be achieved with a lower dose to increase the K value of the gate dielectric layer, which not only does not increase the cost, but also helps to reduce the cost.

[0058] In addition, the N2O gas used in the decoupled plasma nitridation process in the embodiment can reduce the amount of gas used, that is, the same nitrogen concentration can be achieved with a lower dose to increase the K value of the gate dielectric layer, which not only does not increase the cost, but also helps to reduce the cost. x O y The decoupled plasma nitridation process on the gate dielectric layer does not require additional process steps, and thus does not increase the process complexity.

[0059] After the decoupled plasma nitridation process on the gate dielectric layer, the step S3 of performing a post-nitridation annealing process on the gate dielectric layer is performed.

[0060] As an example, the post-nitridation annealing process is performed in the ISSG chamber.

[0061] As an example, only inert gas is used in at least one stage of the post-nitridation annealing process, including but not limited to one or more of nitrogen, argon, and helium, to densify the gate dielectric layer.

[0062] As an example, the gas used in at least one stage of the post-nitridation annealing process includes a reducing gas or an oxidizing gas, wherein the reducing gas includes but is not limited to hydrogen, and the oxidizing gas includes but is not limited to oxygen, which can be mixed with inert gas and introduced into the reaction chamber, which helps to further increase the K value of the gate dielectric layer and reduce the EOT.

[0063] After the post-nitridation annealing treatment of the gate dielectric layer, the step S4 is performed: forming a gate conductive layer on the gate dielectric layer.

[0064] In particular, the high-K metal gate structure is fabricated in the embodiment, and thus the gate conductive layer includes a metal layer, such as a TiN layer.

[0065] Generally, a work function layer is needed in the high-K metal gate, i.e., an N-type work function layer such as TiAl is used in an N-type semiconductor device, the work function of the N-type work function layer is close to the conduction band of a semiconductor substrate such as a silicon substrate, which is beneficial to reduce the threshold voltage of the N-type semiconductor device, and a P-type work function layer such as TiN is used in a P-type semiconductor device, the work function of the P-type work function layer is close to the valence band of a semiconductor substrate such as a silicon substrate, which is beneficial to reduce the threshold voltage of the P-type semiconductor device, i.e., the absolute value of the threshold voltage. Generally, the N-type semiconductor device and the P-type semiconductor device need to be integrated on the same semiconductor substrate.

[0066] As an example, refer to Fig. 3 , which is a cross-sectional schematic view of a high-K metal gate structure fabricated in the embodiment, wherein the gate conductive layer on the gate dielectric layer composed of the interface layer 3 and the high-K dielectric layer 4 includes, from bottom to top, a bottom barrier TiN layer 5, a bottom barrier TaN layer 6, a P-type work function TiN layer 7, an N-type work function TiAl layer 8, a top barrier TiN layer 9, and an Al metal layer 10. In the embodiment, the high-K metal gate structure further includes a sidewall structure 11 on both sides of the gate dielectric layer and the gate conductive layer, and the sidewall structure 11 can be a single layer or a stacked structure, such as one or more of SiO2, SiN, SiON, and SiCO.

[0067] It should be noted that the layer structure and material of the high-K metal gate structure described above are only an example, and are not limited thereto, and in actual production, the layer structure and material can be adjusted as needed, and the protection scope of the present application should not be excessively limited herein.

[0068] The gas used for the decoupled plasma nitridation treatment of the gate dielectric layer in the method for fabricating the semiconductor structure of the embodiment includes N x O y , wherein the N x O y plasma is used to replace the conventional N2 plasma, which has the advantage of achieving the same nitrogen concentration with a lower dose to increase the K value of the gate dielectric layer, and at the same time, the N x O yThe oxygen in the plasma fills the oxygen vacancy defects in the gate dielectric layer, reduces the probability of defect generation, and thus improves the reliability of the device. x O y The plasma can reduce the amount of gas used, which is conducive to reducing costs.

[0069] Embodiment two

[0070] The embodiment and embodiment one use basically the same technical solution, the difference is that the semiconductor structure made in embodiment one uses a high-K metal gate structure, while the semiconductor structure made in this embodiment uses a polysilicon gate structure.

[0071] As an example, in the polysilicon gate structure of the embodiment, the gate dielectric layer includes a silicon oxide layer, and the gate conductive layer includes a polysilicon layer, wherein the silicon oxide layer as the gate dielectric layer is doped with N after the decoupling plasma nitriding treatment, and is converted into a silicon oxynitride (SiON) layer, the K value is improved, the EOT value is low, and the oxygen vacancy defects are repaired.

[0072] Embodiment three

[0073] The embodiment provides a semiconductor structure, which includes a semiconductor substrate, a gate dielectric layer and a gate conductive layer, the gate dielectric layer is located on the semiconductor substrate, and the gate conductive layer is located on the gate dielectric layer, wherein the semiconductor structure is made by the semiconductor structure manufacturing method in embodiment one or embodiment two, that is, the gate dielectric layer is subjected to decoupling plasma nitriding treatment by using N x O y The decoupling plasma nitriding treatment of the plasma not only improves the K value of the gate dielectric layer, which is conducive to reducing the EOT, but also repairs the oxygen vacancy defects in the gate dielectric layer, thereby having higher device reliability.

[0074] In summary, the semiconductor structure manufacturing method of the embodiment uses N x O y , wherein the N x O y Plasma is used instead of conventional N2 plasma, which has the advantage that the same nitrogen concentration can be achieved with a lower dose to improve the K value of the gate dielectric layer, and at the same time, the N x O yThe oxygen in the plasma fills the oxygen vacancy defects in the gate dielectric layer, reduces the probability of defect generation, and thus improves the reliability of the device. In addition, the manufacturing method of the semiconductor structure does not need to increase raw materials and process steps, so as not to increase the production cost and process complexity, and compared with the conventional N2 raw gas, the N x O y The plasma can reduce the gas consumption, and is conducive to reducing the cost. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0075] The above examples only illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above examples without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method of fabricating a semiconductor structure, the method comprising: The method comprises the following steps: providing a semiconductor substrate, forming a gate dielectric layer on the semiconductor substrate, the gate dielectric layer comprising an interface layer and a high-K dielectric layer on the interface layer; The gate dielectric layer is subjected to a decoupling plasma nitridation process, the gas used in the decoupling plasma nitridation process including N x O y So that the oxygen vacancy defects in the high-K dielectric layer are filled, wherein x is the atomic component of N, y is the atomic component of O, x is greater than 0, and y is greater than 0. performing a post-nitridation annealing process on the gate dielectric layer; forming a gate conductive layer on the gate dielectric layer, the gate conductive layer comprising a metal layer.

2. The method of fabricating a semiconductor structure of claim 1, wherein: The decoupled plasma nitridation process uses a gas comprising one or more of N2O, N2O3, N2O4 and N2O5.

3. The method of claim 1, wherein: In at least one stage of the post-nitridation annealing process, only an inert gas is used.

4. The method of claim 1, wherein: In at least one stage of the post-nitridation annealing process, a reducing gas or an oxidizing gas is used.

5. The method of claim 1, wherein: The high-K dielectric layer comprises a hafnium oxide layer or an aluminum oxide layer, and the gate conductive layer comprises a TiN layer.

6. The method of claim 1, wherein: The semiconductor substrate has a shallow trench isolation structure formed therein.

7. A semiconductor structure comprising a semiconductor substrate, a gate dielectric layer and a gate conductive layer, the gate dielectric layer being on the semiconductor substrate, the gate conductive layer being on the gate dielectric layer, characterized in that: The semiconductor structure is formed by the method of any one of claims 1-6.

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