Fast recovery diode with low reverse recovery time and its fabrication method

Abstract

This invention discloses a fast recovery diode with low reverse recovery time and its fabrication method. The fabrication method includes providing a fast recovery diode substrate; sequentially thinning and etching the back side of the fast recovery diode substrate, with a thinning thickness of 40-80 μm and an etching thickness of 1-5 μm; doping the back side of the fast recovery diode substrate with gold; and after gold doping, sequentially thinning and evaporating the metal on the back side of the fast recovery diode substrate to form a back pad metal layer. By doping the substrate with more effective gold, the resulting fast recovery diode exhibits a lower reverse recovery time and superior other performance characteristics.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and specifically to a fast recovery diode with low reverse recovery time and its fabrication method. Background Technology

[0002] PN junction diodes, as the most basic semiconductor components, are widely used in switching, rectification, protection, and filtering. The reverse recovery time (Trr) of ordinary PN junction diodes is approximately in the microsecond range (1E-6S), which is no longer suitable for the increasingly demanding high-frequency applications. Fast recovery diodes and Schottky diodes, as representatives of high-frequency diodes, have rapidly gained dominance in the high-frequency field due to their lower TTr. However, with the development of high-frequency applications, higher requirements are being placed on the reverse recovery time of fast recovery diodes. Summary of the Invention

[0003] The primary objective of this invention is to provide a method for manufacturing a fast recovery diode with a low reverse recovery time. Compared with existing fast recovery diodes, the prepared fast recovery diode has a lower reverse recovery time and a higher frequency, meeting the higher requirements of the high-frequency field.

[0004] In a first aspect, the present invention provides a method for manufacturing a fast recovery diode with a low reverse recovery time, comprising:

[0005] Provide a fast recovery diode substrate;

[0006] The back side of the fast recovery diode substrate is subjected to thinning and etching processes in sequence, with a thinning thickness of 40-80 μm and an etching thickness of 1-5 μm.

[0007] Gold doping is performed on the back side of the fast recovery diode substrate;

[0008] After gold doping is completed, the back side of the fast recovery diode substrate is thinned and the metal is evaporated sequentially to form a back pad metal layer.

[0009] Using the above technical solution, firstly, by doping the fast recovery diode substrate with metallic gold, the carrier lifetime in the semiconductor is reduced, thereby reducing the reverse recovery time of the device. Secondly, through a combination of thinning and etching processes, a damage layer of a certain thickness is formed on the back side of the fast recovery diode substrate, and the resulting fast recovery diode has a certain stress. This is to regulate the diffusion effect of metallic gold in the fast recovery diode substrate, ultimately increasing the content of metallic gold in the fast recovery diode substrate, thereby reducing the carrier lifetime in the fast recovery diode and obtaining a lower reverse recovery time (Trr). Finally, the back side of the fast recovery diode substrate has a certain roughness, which can obtain a larger extension area, adsorb more metallic gold, further reduce the carrier lifetime in the fast recovery diode, and obtain an even lower reverse recovery time (Trr).

[0010] Secondly, the present invention provides a fast recovery diode with a low reverse recovery time, comprising a fast recovery diode substrate, wherein metallic gold is dispersed in the fast recovery diode substrate; a back pad metal layer is disposed on the back side of the fast recovery diode substrate; and the reverse recovery time of the fast recovery diode is 3.5 to 4.5 ns.

[0011] With the above technical solution, the fast recovery diode has a high content of gold metal, thus it has a low reverse recovery time of about 4nS (4E-9S), which meets the higher requirements of fast recovery diodes in the high frequency field.

[0012] The beneficial effects of this invention are:

[0013] Assuming the fast recovery diode substrate remains intact, a damaged layer with a certain thickness and roughness is obtained by thinning and etching the back side of the fast recovery diode substrate. This results in a fast recovery diode with a certain stress, which increases the adsorption rate of gold on the substrate surface and the diffusion rate within the substrate. This increases the gold content in the fast recovery diode substrate, thereby reducing the carrier lifetime of the fast recovery diode and achieving a lower reverse recovery time (Trr). Attached Figure Description

[0014] Figure 1 This is a structural diagram of the present invention after field oxygenation in an embodiment;

[0015] Figure 2 for Figure 1 Structure diagram of the substrate after AA etching;

[0016] Figure 3 for Figure 2 Structure diagram of the substrate after AA push-well;

[0017] Figure 4 for Figure 3The resulting substrate after XN etching is shown in the diagram.

[0018] Figure 5 for Figure 4 Structure diagram of the obtained substrate after XN push-well;

[0019] Figure 6 for Figure 5 Structure diagram of the substrate after ILD deposition;

[0020] Figure 7 for Figure 6 The resulting substrate structure after CT etching;

[0021] Figure 8 for Figure 7 The resulting substrate after back-side thinning;

[0022] Figure 9 for Figure 8 Structure diagram of the back side of the obtained substrate after etching;

[0023] Figure 10 for Figure 9 Structure diagram of the back side of the substrate after gold evaporation;

[0024] Figure 11 for Figure 10 The structure of the substrate after gold diffusion on the back side;

[0025] Figure 12 for Figure 11 Structure diagram of the substrate surface after etching;

[0026] Figure 13 for Figure 12 The resulting substrate after back-side thinning;

[0027] Figure 14 for Figure 13 Structure diagram of the substrate after metal evaporation on the back side;

[0028] Figure 15 This is a picture of the actual appearance of item number 1 after the back has been thinned.

[0029] Figure 16 This is a picture of the actual appearance of item number 2 after the back has been thinned.

[0030] Figure 17 This is a picture of the actual appearance of item number 3 after the back has been thinned.

[0031] Figure 18 This is a picture of the actual appearance of item number 4 after the back has been thinned.

[0032] Figure 19 This is a picture of the actual appearance of item number 5 after the back has been thinned.

[0033] Figure 20This is a picture of the actual appearance of item number 1 after the back has been etched.

[0034] Figure 21 This is a picture of the actual appearance of item number 2 after corrosion on the back.

[0035] Figure 22 This is a picture of the actual appearance of item number 3 after corrosion on the back.

[0036] Figure 23 This is a picture of the actual appearance of item number 4 after corrosion on the back.

[0037] Figure 24 This is a picture of the actual appearance of item number 5 after corrosion on the back.

[0038] Figure 25 Single-factor analysis plots for the new and old processes (VBR@IR=100uA);

[0039] Figure 26 Single-factor analysis plots for the new and old processes (IR@VR=80V);

[0040] Figure 27 Single-factor analysis plots for the new and old processes (IR@VR=110V);

[0041] Figure 28 Single-factor analysis plots for the new and old processes (VF@IF=1mA);

[0042] Figure 29 Single-factor analysis plots for the new and old processes (VF@IF=5mA);

[0043] Figure 30 Single-factor analysis plots for the new and old processes (VF@IF=10mA);

[0044] Figure 31 Single-factor analysis plots for the new and old processes (VF@IF=50mA);

[0045] Figure 32 Single-factor analysis plots for the new and old processes (VF@IF=150mA);

[0046] Figure 33 Single-factor analysis plots (reverse recovery time) for the new and old processes.

[0047] Wherein: 1-substrate; 2-oxide layer; 3-first ion implantation window; 4-trap region; 5-first impurity layer;

[0048] 6-Second ion implantation window; 7-Second impurity layer; 8-Terminal structure; 9-Insulating layer; 10-Third ion implantation window; 11-Damaged layer; 12-First gold metal layer; 13-Gold metal; 14-Backing metal layer. Detailed Implementation

[0049] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0050] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0052] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0053] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0054] In their pursuit of reducing the reverse recovery time of fast recovery diodes, the inventors discovered that doping the fast recovery diode substrate with heavy metals, such as gold, can reduce carrier lifetime, thereby lowering the reverse recovery time. Furthermore, they found that the higher the doping concentration of the heavy metal, the shorter the reverse recovery time. Therefore, how to increase the doping concentration of the heavy metal has become a pressing issue.

[0055] In the process of seeking to increase the doping amount of heavy metals, the inventors of this invention discovered that, while ensuring the integrity of the fast recovery diode substrate itself, by thinning and etching the back side of the fast recovery diode substrate, the fast recovery diode substrate can have a certain damage layer, a certain stress, and a certain roughness. The certain damage layer and the certain stress are conducive to the diffusion of metallic gold, and the certain roughness can obtain a larger extension area and adsorb more metallic gold.

[0056] In this invention, the "integrity of the fast recovery diode substrate itself" means that after the back side of the fast recovery diode substrate is thinned and etched, the fast recovery diode substrate does not crack, has no hidden cracks, or leak current.

[0057] In this invention, the "back side" refers to the surface of the fast recovery diode substrate without functional areas. The "front side" is the surface opposite the "back side".

[0058] As mentioned earlier, after thinning and etching the back side of the fast recovery diode substrate, it is also necessary to ensure the integrity of the fast recovery diode substrate itself. This places requirements on various parameters in the thinning and etching processes, such as: the thickness of the thinning, the thickness of the damaged layer after etching, the roughness of the damaged layer after etching, the selection of the etching solution, and the control of the etching time.

[0059] In a first aspect, the present invention provides a method for manufacturing a fast recovery diode with low reverse recovery time, comprising the following steps:

[0060] S1. Provide a fast recovery diode substrate;

[0061] In this step, the "fast recovery diode substrate" can be prepared by the following steps:

[0062] S1-1: Provide a substrate 1;

[0063] The substrate 1 can be a material commonly used in diode fabrication, such as silicon wafers.

[0064] S1-2: Field Oxygen

[0065] like Figure 1 As shown, the front side of the substrate 1 is oxidized to obtain an oxide layer 2; the oxide layer 2 covers the entire front side of the substrate 1.

[0066] S1-3: As Figure 2 As shown, the oxide layer 2 is etched to form the first ion implantation window 3;

[0067] In this step, the etching can be performed at any location on oxide layer 2, but it is generally performed in the middle of oxide layer 2. The etching method used in this step is AA etching.

[0068] S1-4: As Figure 3 As shown, the substrate 1 is pushed into a well region 4 and a first impurity layer 5 through the first ion implantation window 3; the pushing in this step uses an AA pushing method. The first impurity layer 5 connects the remaining oxide layer 2 into a single unit;

[0069] S1-5: As Figure 4 As shown, the oxide layer 2 is etched to form multiple second ion implantation windows 6;

[0070] This step primarily involves etching the edges of oxide layer 2. The etching method used in this step is XN etching.

[0071] S1-6: As Figure 5 As shown, the substrate 1 is pushed into a well through multiple second ion implantation windows 6 to form a terminal structure 8 and a second impurity layer 7; the push-in well in this step is an XN push-in well. The second impurity layer 7 fills in the removed edge oxide layer 2.

[0072] S1-7: As Figure 6 As shown, an insulating dielectric is deposited on the front side of the substrate 1 to form an insulating layer 9, which is used to cover the aforementioned oxide layer 2, the first impurity layer 5, and the second impurity layer 7.

[0073] S1-8: As Figure 7 As shown, the insulating layer 9 and the first impurity layer 5 are etched to form the third ion implantation window 10; CT etching is used in this step.

[0074] S2. The back side of the fast recovery diode substrate is subjected to thinning and etching processes in sequence, with a thinning thickness of 40-80 μm and an etching thickness of 1-5 μm;

[0075] like Figure 8 As shown, the equipment used in this step for thinning can be common grinding equipment in the art, such as thinning machines and thinning grinding wheels. Thinning can be performed multiple times using different types of grinding wheels or using grinding wheels of the same size. It is preferred to use different types of grinding wheels to obtain a wear layer of more ideal thickness.

[0076] Generally, two different types of grinding wheels are used for grinding: 360 grit for coarse grinding and 600 grit for fine grinding. The thickness reduction during coarse grinding is 30-50 μm, and the thickness reduction during fine grinding is 10-30 μm.

[0077] The grinding speed during the rough grinding process is generally: spindle speed 1500-2400 rpm; vacuum chuck speed 150-300 rpm.

[0078] The grinding speed during fine grinding is generally: spindle speed 2000-2400 rpm; vacuum chuck speed 200-260 rpm.

[0079] After the thinning process, the fast recovery diode substrate should meet the following requirements: stress of 400-1000 MPa, thickness of the damaged layer 11 of 3-6 μm, and roughness Ra of the damaged layer 11 of >0.3 μm.

[0080] like Figure 9 As shown, in this step, the corrosion treatment specifically involves using chemical substances for corrosion. These chemicals can be a mixture, applied sequentially, or used individually. Generally, multiple different chemicals are used sequentially. The chemicals are silicon etching solution and dilute hydrofluoric acid. The corrosion process is as follows: silicon etching solution 2–5 minutes → rinsing with water 5–10 minutes → DHF (dilute hydrofluoric acid) 1–5 minutes → rinsing with water 5–10 minutes. The corrosion temperature is generally controlled within 23±2℃.

[0081] The corrosion thickness in the corrosion treatment is generally 1 to 3 μm to release some of the thinning stress.

[0082] After the etching process, the fast recovery diode substrate should meet the following requirements: stress of 400–800 MPa, thickness of the damaged layer 11 of 2–3 μm, and roughness Ra of the damaged layer 11 > 0.2 μm. This is to obtain better adsorption and diffusion efficiency of metallic gold 13, ultimately reducing the reverse recovery time.

[0083] S3. Perform gold 13 doping on the back side of the fast recovery diode substrate;

[0084] This step specifically includes the evaporation of metallic gold 13 (e.g., Figure 10 (as shown) and diffusion (as shown) Figure 11 (As shown) Two steps: First, metallic gold 13 is evaporated onto the back side of the substrate to form a metallic gold 13 layer. Then, diffusion allows metallic gold 13 to enter the substrate and form a metallic gold 13 layer on the third ion implantation window 10. At the same time, the metallic gold 13 layer on the back side of the substrate disappears.

[0085] Since forming a metallic gold 13 layer on the third ion implantation window 10 is detrimental to the performance of the fast recovery diode, this metallic layer needs to be removed, such as... Figure 12 As shown, the surface corrosion method is used to remove it. The corrosion solution is a liquid that can dissolve metallic gold 13, such as hydrofluoric acid.

[0086] S4. After gold 13 doping is completed, the back side of the fast recovery diode substrate is sequentially thinned (e.g., ...). Figure 13 (as shown) and metal evaporation (e.g.) Figure 14 As shown), a backing metal layer 14 is formed.

[0087] The purpose of thinning in this step is to remove the damaged layer 11 on the back of the substrate, to prevent the damaged layer 11 from affecting the performance, and also to ensure that the backing metal layer 14 can be firmly deposited on the back of the substrate to protect the substrate.

[0088] Secondly, the present invention also discloses a fast recovery diode with low reverse recovery time prepared by the aforementioned manufacturing method. For example... Figure 14 As shown, the fast recovery diode with low reverse recovery time includes a fast recovery diode substrate, in which metallic gold 13 is dispersed; a back pad metal layer 14 is disposed on the back side of the fast recovery diode substrate, and the reverse recovery time of the fast recovery diode is 3.5 to 4.5 ns.

[0089] Wherein: the fast recovery diode substrate includes a substrate 1, on which a well region 4 and a termination structure 8 are disposed;

[0090] Two functional layers are provided on the front side of the substrate 1. Each functional layer includes a first impurity layer 5, an oxide layer 2 and a second impurity layer 7, all of which are bonded to the front side of the substrate 1. The oxide layer 2 is disposed between the first impurity layer 5 and the second impurity layer 7, and the second impurity layer 7 is close to the edge of the substrate 1.

[0091] Preferably, each of the functional layers is covered with an insulating layer 9.

[0092] Example

[0093] This embodiment discloses a method for manufacturing a fast recovery diode, including the following steps:

[0094] S1: Provide a silicon wafer as a substrate;

[0095] S2: Field Oxygen

[0096] like Figure 1 As shown, the front side of the silicon wafer is oxidized to obtain an oxide layer;

[0097] S3: As Figure 2 As shown, AA etching is used to etch the oxide layer to form the first ion implantation window;

[0098] S4: As Figure 3 As shown, the silicon wafer is subjected to AA push-in through the first ion implantation window to form a well region and a first impurity layer;

[0099] S5: As Figure 4As shown, the oxide layer is subjected to XN etching to form two second ion implantation windows;

[0100] S6: As Figure 5 As shown, the silicon wafer is subjected to XN push-well through two second ion implantation windows to form a terminal structure and a second impurity layer.

[0101] S7: As Figure 6 As shown, an insulating dielectric is deposited on the front side of the silicon wafer to form an insulating layer, which is used to cover the aforementioned oxide layer, first impurity layer and second impurity layer;

[0102] S8: As Figure 7 As shown, CT etching of the insulating layer and the first impurity layer forms the third ion implantation window;

[0103] S9: The back side of the silicon wafer is sequentially thinned and etched using a thinning grinding wheel. The thickness and stress of the silicon wafer after thinning, the thickness and roughness of the damaged layer are recorded. The etching thickness, post-etching stress, combined thinning and post-etching stress, and the thickness and roughness of the damaged layer after etching are also recorded, as shown in Tables 1 and 2. The etching process is as follows: silicon etching solution for 4 minutes → rinsing with water for 5 minutes → DHF (dilute hydrofluoric acid) for 1 minute → rinsing with water for 5 minutes. The etching temperature is generally controlled within 23±0.3℃.

[0104] S10: As Figure 10 As shown, metallic gold is evaporated from the back of the silicon wafer, and then... Figure 11 As shown, metallic gold diffusion is performed, allowing metallic gold to enter the silicon wafer and form a metallic gold layer on the third ion implantation window.

[0105] S11: As Figure 12 As shown, the silicon wafer surface is etched with hydrofluoric acid.

[0106] S13: As Figure 13 After the etching process is completed as shown, the damaged layer on the back side of the silicon wafer is thinned and removed sequentially, then as shown... Figure 14 As shown, the metal evaporates, forming a backing metal layer.

[0107] Comparative Example

[0108] Compared with the aforementioned embodiments, in this comparative example, the back side of the silicon wafer is not thinned or etched before the gold metal evaporates; otherwise, the process remains the same.

[0109] Table 1. Test data after silicon wafer backside thinning adjustment.

[0110]

[0111]

[0112] Table 2. Test data after adjusting the back etching of silicon wafers.

[0113]

[0114] The appearance of the five serial numbers after thinning in Table 1 is shown below. Figure 15-19 As shown, the stress all exhibited a trend of first decreasing and then increasing. The appearance images of the five serial numbers after corrosion in Table 2 are as follows. Figure 20-24 As shown, the forces all exhibit a trend of first increasing and then decreasing.

[0115] The performance of the five products prepared in the examples and the five products prepared in the comparative examples was tested, and the results are shown in Table 3.

[0116] Table 3

[0117]

[0118]

[0119] As shown in Table 3, when the back side of the silicon wafer is thinned and etched sequentially, and the process parameters of the thinning and etching processes are adjusted within a reasonable range, the resulting fast recovery diode has a lower reverse recovery time (Trr), with an average reduction of TTrr of about 0.17 ns, and no significant effect on the VR, IR, and VF parameters of the fast recovery diode.

[0120] One-way analysis of VRB / IR / VF parameters was performed on the five products prepared in the examples (referred to as the new process) and the five products prepared in the comparative examples (referred to as the old process). The results are as follows: Figure 25-33 As shown.

[0121] Depend on Figure 25-33 It can be seen that when the back side of the silicon wafer is thinned and etched sequentially, and the process parameters of the thinning and etching processes are adjusted within a reasonable range, the obtained fast recovery diode has a lower reverse recovery time (Trr), with an average reduction of TTrr of about 0.17 ns. There is no significant difference in VRB / IR / VF parameters, and the parameter levels are comparable.

[0122] In summary, this invention, by sequentially thinning and etching the back side of the substrate, not only facilitates the adsorption of metallic gold but also promotes its diffusion, resulting in a fast recovery diode containing more effective metallic gold. This reduces the reverse recovery time without significantly affecting other performance characteristics. Therefore, this fabrication method is worth promoting to obtain diodes with shorter reverse recovery times, meeting the performance requirements of diodes in future high-frequency applications.

[0123] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for manufacturing a fast recovery diode with low reverse recovery time, characterized in that, The manufacturing method includes: Provide a fast recovery diode substrate; The back side of the fast recovery diode substrate is subjected to thinning and etching processes in sequence, with a thinning thickness of 40-80 μm and an etching thickness of 1-5 μm. Gold doping is performed on the back side of the fast recovery diode substrate; After gold doping is completed, the back side of the fast recovery diode substrate is thinned and metal evaporated sequentially to form a back pad metal layer. The fast recovery diode substrate is prepared by the following method: Provide a substrate; The front side of the substrate is oxidized to obtain an oxide layer; The oxide layer is etched to form a first ion implantation window; The substrate is pushed into a well through the first ion implantation window to form a well region and a first impurity layer; The oxide layer is etched to form multiple second ion implantation windows; The substrate is pushed into a trap through multiple second ion implantation windows to form a terminal structure and a second impurity layer; An insulating dielectric is deposited on the front side of the substrate to form an insulating layer; The insulating layer and the first impurity layer are corroded to form the third ion implantation window.

2. The manufacturing method according to claim 1, characterized in that, After the thinning and etching processes, the stress of the fast recovery diode substrate is 400–800 MPa, the thickness of the damage layer on the back side of the fast recovery diode substrate is 2–3 μm, and the roughness Ra of the back side of the fast recovery diode substrate is >0.2 μm.

3. The manufacturing method according to claim 1 or 2, characterized in that, After the thinning process, the stress of the fast recovery diode substrate is 400-1000 MPa, the thickness of the damage layer on the back side of the fast recovery diode substrate is 3-6 μm, and the roughness Ra on the back side of the fast recovery diode substrate is >0.3 μm.

4. The manufacturing method according to claim 1, characterized in that, The thinning process includes coarse grinding thinning and fine grinding thinning. The thickness of coarse grinding thinning is 30-50 μm, and the thickness of fine grinding thinning is 10-30 μm.

5. The manufacturing method according to claim 1, characterized in that, The corrosion treatment is carried out at a temperature of 21–25°C, and the corrosion solution is a silicon corrosion solution and dilute hydrofluoric acid.

6. The manufacturing method according to claim 5, characterized in that, First, the silicon etching solution is used for etching, followed by dilute hydrofluoric acid. The etching time for the former is 2 to 5 minutes, and the etching time for the latter is 1 to 5 minutes.

7. The manufacturing method according to claim 6, characterized in that, Before etching with the dilute hydrofluoric acid, the fast recovery diode substrate is cleaned.

8. A fast recovery diode with low reverse recovery time, manufactured using the method described in claim 1, characterized in that, The fast recovery diode substrate is included, and the back side of the fast recovery diode substrate is sequentially thinned and etched. Metallic gold is dispersed in the fast recovery diode substrate. A back pad metal layer is provided on the back side of the fast recovery diode substrate; The reverse recovery time of the fast recovery diode is 3.5 to 4.5 ns.

9. The fast recovery diode according to claim 8, characterized in that, The fast recovery diode substrate includes a substrate on which a well region and a termination structure are disposed; Two functional layers are disposed on the front side of the substrate. Each functional layer includes a first impurity layer, an oxide layer, and a second impurity layer, all of which are bonded to the front side of the substrate. The oxide layer is disposed between the first impurity layer and the second impurity layer, and the second impurity layer is close to the edge of the substrate.

10. The fast recovery diode according to claim 9, characterized in that, Each of the functional layers is covered with an insulating layer.

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