A low-resistivity ohmic contact Ge n-type channel field-effect transistor structure and its fabrication method

Abstract

The application discloses a Gen type channel field effect transistor structure with low-resistance ohmic contact and a preparation method thereof. The structure comprises a p-type Ge substrate, n-type Ge source / drain regions arranged on both sides of the p-type Ge substrate, ultrathin oxide layers arranged on the n-type Ge source / drain regions, a gate passivation layer, a gate dielectric layer and a gate metal layer arranged from bottom to top between the n-type Ge source / drain regions and on the top of the p-type Ge substrate, and insulating side walls arranged on both sides of the gate metal layer. Source electrode adhesion layers, source electrodes and drain electrode adhesion layers and drain electrodes are arranged on the outside of the insulating side walls and on the ultrathin oxide layers. Gate electrode adhesion layers and gate electrodes are arranged between the insulating side walls and on the gate metal layer. The source electrodes and the drain electrodes are connected with the n-type Ge source / drain regions through conductive filament channels penetrating through the ultrathin oxide layers. The ultrathin oxide layer is embedded between the metal and the n-Ge semiconductor, and the oxide layer is broken through by using an electroforming process, so that the low-resistance ohmic contact is realized.

Description

Technical Field

[0001] This invention relates to the field of field-effect transistor technology, specifically to a low-resistivity ohmic contact Gen-type channel field-effect transistor structure and its fabrication method. Background Technology

[0002] As Moore's Law for Si materials gradually reaches its limit, Ge, with its high and symmetrical electron and hole mobility, low doping activation temperature, and high compatibility with CMOS and HKMG processes, has been widely studied as the most promising alternative to Si devices. Currently, due to the inherent Fermi level pinning effect of n-type Ge materials, it is difficult to form ohmic contacts or the ohmic contact resistance is high, which restricts the further development of Ge CMOS.

[0003] Methods for achieving low resistivity ohmic contact: Due to the inherent problem of the Fermi level pinning near the valence band, Ge materials cannot form good ohmic contacts with metals of different work functions.

[0004] The journal ISSN 1750-0443, in its paper titled "[Improving metal / n-Ge ohmic contact by inserting TiO2 deposited by PEALD]", proposes a method for achieving n-Ge ohmic contacts using an inserted oxide layer. However, the inserted oxide layer requires a relatively high thickness; a thin oxide layer cannot completely depin, while a thick oxide layer results in a conductivity mechanism dominated by a smaller tunneling current, limiting the on-state current of the device. Application number 201611072571.1, titled "A Method for Fabricating an N-type Ohmic Contact of Ge", proposes using a nickel-tin alloy metal alloyed with a germanium-based semiconductor to reduce the resistivity of the source-drain ohmic contact region. However, the method of using Ni or NiSn annealing to form NiGe or NiSnGe alloys has limited Fermi pinning deactivation capabilities. Summary of the Invention

[0005] In order to overcome the shortcomings of the prior art, the present invention aims to provide a Ge n-channel field-effect transistor structure with low resistivity ohmic contact and its fabrication method. By embedding an ultrathin oxide layer between a metal and an n-Ge semiconductor and using an electroforming process to break down the ultrathin oxide layer, a low resistivity ohmic contact is achieved.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A Ge n-type trench field effect transistor structure with low-resistivity ohmic contact, comprising a p-type Ge substrate 1. On both sides of the p-type Ge substrate 1, an n-type Ge source region 21 and an n-type Ge drain region 22 are respectively provided. A first ultra-thin oxide layer 71 is provided on the n-type Ge source region 21, and a second ultra-thin oxide layer 72 is provided on the n-type Ge drain region 22. Between the n-type Ge source region 21 and the n-type Ge drain region 22 and in the middle of the top of the p-type Ge substrate 1, a gate passivation layer 3, a gate dielectric layer 4 and a gate metal layer 5 are sequentially arranged from bottom to top. First insulating sidewalls 61 and second insulating sidewalls 62 are respectively provided on both sides of the gate passivation layer 3, the gate dielectric layer 4 and the gate metal layer 5; on the outside of the first insulating sidewall 61 and on the first ultra-thin oxide layer 71, a source electrode adhesion layer 81 and a source electrode 91 are sequentially arranged; on the outside of the second insulating sidewall 62 and on the second ultra-thin oxide layer 72, a drain electrode adhesion layer 82 and a drain electrode 92 are sequentially arranged; between the first insulating sidewall 61 and the second insulating sidewall 62 and on the gate metal layer 5, a gate electrode adhesion layer 83 and a gate electrode 93 are sequentially arranged. A substrate electrode 10 is provided at the bottom of the p-type Ge substrate 1. A first conductive filament channel 11 penetrates through the first ultra-thin oxide layer 71. One end of the first conductive filament channel 11 is electrically connected to the source electrode 91 through the source electrode adhesion layer 81, and the other end of the first conductive filament channel 11 is electrically connected to the n-type Ge source region 21; a second conductive filament channel 12 penetrates through the second ultra-thin oxide layer 72. One end of the second conductive filament channel 12 is electrically connected to the drain electrode 92 through the drain electrode adhesion layer 82, and the other end of the second conductive filament channel 12 is electrically connected to the n-type Ge drain region 22.

[0008] The first insulating sidewalls 61 and the second insulating sidewalls 62 are made of SiO2 material.

[0009] Both the first ultra-thin oxide layer 71 and the second ultra-thin oxide layer 72 are GeO

[0011] ,

[0010] , , , ,

[0013] , ,

[0012] N y , 1 < x < 2, 0 < y < 0.5, and the thicknesses are all 2 - 5 nm.

[0010] The present invention also provides a preparation method for the Ge n-type trench field effect transistor structure based on low-resistivity ohmic contact, comprising the following steps:

[0011] Step 1: Oxidize on the p-type Ge substrate 1 to generate GeOx, and then deposit SiO2;

[0012] Step 2: Prepare the n-type Ge source region 21 and the n-type Ge drain region 22 on both sides of the top of the p-type Ge substrate 1 processed in Step 1 through photolithography and ion implantation processes;

[0013] Step 3: Remove the GeOx and SiO2 from the surfaces of the p-type Ge substrate 1, n-type Ge source region 21 and n-type Ge drain region 22 after the treatment in Step 2. Then, deposit a passivation layer, a dielectric layer and a metal layer sequentially on top of the p-type Ge substrate 1. Remove the passivation layer, dielectric layer and metal layer deposited between the n-type Ge source region 21 and the n-type Ge drain region 22, except directly above the p-type Ge substrate 1, by photolithography and etching to form the gate passivation layer 3, the gate dielectric layer 4 and the gate metal layer 5.

[0014] Step 4: Deposit SiO2 insulating layers on the surfaces of the gate passivation layer 3, gate dielectric layer 4, gate metal layer 5, and n-type Ge source region 21 and n-type Ge drain region 22 formed in step 3. Then, remove the SiO2 insulating layers deposited above the n-type Ge source region 21 and n-type Ge drain region 22 and the SiO2 insulating layer deposited in the middle of the top of the gate metal layer 5 by photolithography and wet etching, forming the first insulating sidewall 61 and the second insulating sidewall 62, respectively. Next, form the first ultrathin oxide layer 71 and the second ultrathin oxide layer 72 above the n-type Ge source region 21 and n-type Ge drain region 22.

[0015] Step 5: Sequentially deposit source electrode adhesion layer 81 and source electrode 91 on the first ultrathin oxide layer 71; sequentially deposit drain electrode adhesion layer 82 and drain electrode 92 on the second ultrathin oxide layer 72; sequentially deposit gate electrode adhesion layer 83 and gate electrode 92 on the gate metal layer 5.

[0016] Step 6: Deposit Al on the bottom surface of the p-type Ge substrate 1 to form the substrate electrode 10;

[0017] Step 7: Apply a gradually increasing negative scanning voltage between the source electrode and the substrate electrode, and between the drain electrode and the substrate electrode. The current voltage test shows that the current suddenly increases at a certain voltage when scanning in the negative voltage direction, forming a conductive filament channel in the first ultrathin oxide layer 71 and the second ultrathin oxide layer 72, respectively connecting the source electrode 91 to the n-type Ge source region 21 and the drain electrode 92 to the n-type Ge drain region 22.

[0018] The specific method of step 1 is as follows: perform standard cleaning on p-type Ge substrate 1, use PEALD equipment to oxidize with ozone at 275-325°C for 15-30 min to form 3-5 nm GeOx, and use deposition equipment to deposit 10-15 nm SiO2.

[0019] The specific method of step 2 is as follows: P0 particles are implanted onto the top two sides of the p-type Ge substrate 1 after step 1 using photolithography and ion implantation processes. +Ions, with an energy of 25 keV - 35 keV, a dose of 5E14 - 1E15, and an angle of 6° - 8°, are then annealed at 575 - 625 °C for 25 - 35 s in a rapid annealing furnace under an N2 atmosphere to activate the doped ions, forming an n-type Ge source region 21 and an n-type Ge drain region 22;

[0020] The specific method of step 3 is as follows: Use diluted hydrofluoric acid of 2% - 20% to remove GeOx and SiO2 on the surfaces of the p-type Ge substrate 1, n-type Ge source region 21, and n-type Ge drain region 22 after the treatment in step 2. Then, use a PEALD device on the top of the p-type Ge substrate 1 to perform ozone oxidation at 275 - 325 °C for 15 - 30 min, deposit 5 - 10 nm of ZrO2, and then use a magnetron sputtering device to deposit 30 - 100 nm of TiN metal. The passivation layer, dielectric layer, and metal layer deposited outside the p-type Ge substrate 1 directly above between the n-type Ge source region 21 and n-type Ge drain region 22 are removed by photolithography and etching to form a gate passivation layer 3, a gate dielectric layer 4, and a gate metal layer 5;

[0021] The gate metal in step 3 is any one of titanium nitride and tantalum nitride; the dielectric layer can also be any one of HfZrO2, HfAlO2, HfO2, Al2O3, TiO2, and their mixtures.

[0022] The deposition in step 4 is carried out using a PECVD device, and the thickness of the deposited SiO2 insulating layer is 40 - 60 nm; the specific preparation methods of the first ultra-thin oxide layer 71 and the second ultra-thin oxide layer 72 are as follows: Use a RIE etcher to bombard the n-type Ge source region 21 and the n-type Ge drain region 22 in an O2 / Ar / N2 mixed plasma for 60 - 120 s, with a power of 200 - 400 W and O2, Ar, and N2 flow rates of 150 - 200 sccm, to form a GeO layer rich in oxygen vacancies on the n-type Ge source region 21 and the n-type Ge drain region 22, that is, the first ultra-thin oxide layer 71 and the second ultra-thin oxide layer 72; x N y layer, namely the first ultra-thin oxide layer 71 and the second ultra-thin oxide layer 72;

[0023] Both the first ultra-thin oxide layer 71 and the second ultra-thin oxide layer 72 in step 4 are GeO x N y , 1 < x < 2, 0 < y < 0.5, and the thicknesses are both 2 - 5 nm.

[0024] Step 5 involves depositing an electrode adhesion layer and an electrode layer on the first ultrathin oxide layer 71, the second ultrathin oxide layer 72, and the gate metal layer 5 using an electron beam evaporation apparatus, and removing the electrode adhesion layer and electrode layer outside the gate, source, and drain regions using a stripping process to expose the source electrode adhesion layer 81, the source electrode 91, the drain electrode adhesion layer 82, the drain electrode 92, the gate electrode adhesion layer 83, and the gate electrode 93.

[0025] The electrode adhesion layer is Ti with a thickness of 10-30 nm; the electrode layer is any one of Au, Al, Cu, and Ag with a thickness of 20-50 nm; the source electrode 91, drain electrode 92, and gate electrode 93 can all be made of any one of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

[0026] The specific method of step 6 is as follows: deposit 50-100 nm of Al on the bottom surface of the p-type Ge substrate 1 using magnetron sputtering to obtain the substrate electrode 10.

[0027] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0028] 1. Compared with traditional n-type field-effect transistors, this invention achieves low resistivity ohmic contact by embedding an ultrathin oxide layer between the metal and the semiconductor and using an electroforming process to break down the oxide layer.

[0029] 2. This invention employs an oxide layer with a thickness of 2-5 nm to alleviate Fermi level pinning between metal-induced bandgap energy levels, thereby achieving ohmic contact. Then, conductive filaments are formed through an electroforming process, i.e., a gradually increasing source / drain voltage to the Ge substrate is applied to cause the embedded oxide to break down. After breakdown, multiple oxygen vacancy conductive paths are generated inside the oxide, and the main conductivity mechanism becomes conductivity of the conductive filaments, thus achieving low resistivity ohmic contact.

[0030] 3. This invention incorporates a GeO layer with a thickness of 2-5 nm between the metal and the n-Ge semiconductor. x N y It also has the effect of passivating the Ge surface, which can better relieve Fermi level pinning by reducing the number of dangling bonds.

[0031] 4. This invention incorporates a GeO layer with a thickness of 2-5 nm between the metal and the n-Ge semiconductor. x N y It can be formed through a low-temperature plasma process, without thermal budget limitations, and without the need for additional photolithography steps for patterning.

[0032] 5. This invention incorporates a GeO layer with a thickness of 2-5 nm between the metal and the n-Ge semiconductor. x N y The reliability of unpinning layers is improved by incorporating nitrogen.

[0033] 6. The Ti material used in the adhesion layer of this invention has good adhesion, which can enhance the adhesion of the Au film and can bond Au to other materials well. It also has low contact resistance and can form a good ohmic contact with Au. Furthermore, the gold electrode used has extremely high corrosion resistance, good electrical conductivity and thermal conductivity, and other good properties. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the overall structure of the present invention.

[0035] Figure 2 This is a process flow diagram of the formation of the gate passivation layer 3, the gate dielectric layer 4, and the gate metal layer 5 of the present invention; wherein, Figure 2 (a) is a schematic diagram of the structure after GeOx is generated and SiO2 is deposited on the p-type Ge substrate 1. Figure 2 (b) is a schematic diagram of the structure of the n-type Ge source region 21 and the n-type Ge drain region 22. Figure 2 (c) is a schematic diagram of the structure after removing GeOx and SiO2. Figure 2 (d) is a schematic diagram of the passivation layer, dielectric layer and metal layer. Figure 2 (f) is a schematic diagram of the structure of gate passivation layer 3, gate dielectric layer 4, and gate metal layer 5.

[0036] Figure 3 This is a process flow diagram of the source / drain / gate electrode adhesion layer and the formation of the source / drain / gate electrodes according to the present invention; wherein, Figure 3 (a) is a schematic diagram of the structure of the SiO2 insulating layer. Figure 3 (b) is a structural schematic diagram of the first insulating sidewall 61 and the second insulating sidewall 62. Figure 3 (c) is a schematic diagram of the structure of the first ultrathin oxide layer 71 and the second ultrathin oxide layer 72. Figure 3 (d) is a schematic diagram of the structure of the source electrode adhesion layer 81, the drain electrode adhesion layer 82, the gate electrode adhesion layer 83, the source electrode 91, the drain electrode 92 and the gate electrode 93.

[0037] Figure 4 This is a schematic diagram of the substrate electrode 10.

[0038] Wherein: 1 - p-type Ge substrate; 21 - n-type Ge source region; 22 - n-type Ge drain region; 3 - gate passivation layer; 4 - gate dielectric layer; 5 - gate metal layer; 61 - first insulating sidewall; 62 - second insulating sidewall; 71 - first ultra-thin oxide layer; 72 - second ultra-thin oxide layer; 81 - source electrode adhesion layer; 82 - drain electrode adhesion layer; 83 - gate electrode adhesion layer; 91 - source electrode; 92 - drain electrode; 93 - gate electrode; 10 - substrate electrode; 11 - first conductive filament channel; 12 - second conductive filament channel. Detailed implementation manners

[0039] The implementation manners of the present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

[0040] A Ge n-type channel field effect transistor structure with low-resistivity ohmic contact includes a p-type Ge substrate 1. On both sides of the p-type Ge substrate 1, an n-type Ge source region 21 and an n-type Ge drain region 22 are respectively provided. A first ultra-thin oxide layer 71 is provided on the n-type Ge source region 21, and a second ultra-thin oxide layer 72 is provided on the n-type Ge drain region 22. Between the n-type Ge source region 21 and the n-type Ge drain region 22 and in the middle of the top of the p-type Ge substrate 1, a gate passivation layer 3, a gate dielectric layer 4, and a gate metal layer 5 are sequentially arranged from bottom to top. On both sides of the gate passivation layer 3, the gate dielectric layer 4, and the gate metal layer 5, a first insulating sidewall 61 and a second insulating sidewall 62 are respectively provided; on the outside of the first insulating sidewall 61 and on the first ultra-thin oxide layer 71, a source electrode adhesion layer 81 and a source electrode 91 are sequentially arranged; on the outside of the second insulating sidewall 62 and on the second ultra-thin oxide layer 72, a drain electrode adhesion layer 82 and a drain electrode 92 are sequentially arranged; between the first insulating sidewall 61 and the second insulating sidewall 62 and on the gate metal layer 5, a gate electrode adhesion layer 83 and a gate electrode 93 are sequentially arranged. A first conductive filament channel 11 penetrates through the first ultra-thin oxide layer 71. One end of the first conductive filament channel 11 is electrically connected to the source electrode 91 through the source electrode adhesion layer 81, and the other end of the first conductive filament channel 11 is electrically connected to the n-type Ge source region 21; a second conductive filament channel 12 penetrates through the second ultra-thin oxide layer 72. One end of the second conductive filament channel is electrically connected to the drain electrode through the drain electrode adhesion layer 82, and the other end of the second conductive filament channel 12 is electrically connected to the n-type Ge drain region 22.

[0041] The first insulating sidewall 61 and the second insulating sidewall 62 are made of SiO2 material.

[0042] A substrate electrode 10 is provided at the bottom of the p-type Ge substrate 1.

[0043] Both the first ultra-thin oxide layer 71 and the second ultra-thin oxide layer 72 are GeOx, where 1 < x < 2, 0 < y < 0.5, and the thickness of both is 2 - 5 nm. x N y , 1 < x < 2, 0 < y < 0.5, and the thickness of both is 2 - 5 nm.

[0044] This invention also provides a method for fabricating a Ge n-type channel field-effect transistor structure based on a low resistivity ohmic contact, comprising the following steps:

[0045] Step 1: Oxidize GeOx on p-type Ge substrate 1 to generate GeOx, and then deposit SiO2;

[0046] Step 2: An n-type Ge source region 21 and an n-type Ge drain region 22 are prepared on both sides of the top of the p-type Ge substrate 1 after the treatment in Step 1 by photolithography and ion implantation.

[0047] Step 3: Remove the GeOx and SiO2 from the surfaces of the p-type Ge substrate 1, n-type Ge source region 21 and n-type Ge drain region 22 after the treatment in Step 2. Then, deposit a passivation layer, a dielectric layer and a metal layer sequentially on top of the p-type Ge substrate 1. Remove the passivation layer, dielectric layer and metal layer deposited between the n-type Ge source region 21 and the n-type Ge drain region 22, except directly above the p-type Ge substrate 1, by photolithography and etching to form the gate passivation layer 3, the gate dielectric layer 4 and the gate metal layer 5.

[0048] Step 4: Deposit SiO2 insulating layers on the surfaces of the gate passivation layer 3, gate dielectric layer 4, gate metal layer 5, and n-type Ge source region 21 and n-type Ge drain region 22 formed in step 3. Then, remove the SiO2 insulating layers deposited above the n-type Ge source region 21 and n-type Ge drain region 22 and the SiO2 insulating layer deposited in the middle of the top of the gate metal layer 5 by photolithography and wet etching, forming the first insulating sidewall 61 and the second insulating sidewall 62, respectively. Next, form the first ultrathin oxide layer 71 and the second ultrathin oxide layer 72 above the n-type Ge source region 21 and n-type Ge drain region 22.

[0049] Step 5: Sequentially deposit source electrode adhesion layer 81 and source electrode 91 on the first ultrathin oxide layer 71; sequentially deposit drain electrode adhesion layer 82 and drain electrode 92 on the second ultrathin oxide layer 72; sequentially deposit gate electrode adhesion layer 83 and gate electrode 92 on the gate metal layer 5.

[0050] Step 6: Deposit Al on the bottom surface of the p-type Ge substrate 1 to form the substrate electrode 10;

[0051] Step 7: Apply a gradually increasing negative scanning voltage between the source electrode and the substrate electrode, and between the drain electrode and the substrate electrode. The current voltage test shows that the current suddenly increases at a certain voltage when scanning in the negative voltage direction, forming a conductive filament channel in the first ultrathin oxide layer 71 and the second ultrathin oxide layer 72, respectively connecting the source electrode 91 to the n-type Ge source region 21 and the drain electrode 92 to the n-type Ge drain region 22.

[0052] The specific method of step 1 is as follows: perform standard cleaning on p-type Ge substrate 1, use PEALD equipment to oxidize with ozone at 275-325℃ for 15-30 minutes to form 3-5nm GeOx, and use deposition equipment to deposit 10-15nm SiO2.

[0053] The specific method of step 2 is as follows: P0 particles are implanted onto the top two sides of the p-type Ge substrate 1 after step 1 using photolithography and ion implantation processes. + Ions with energies of 25keV-35keV, doses of 5E14-1E15, and angles of 6°-8° are used. Then, the doped ions are activated by annealing in a rapid annealing furnace at 575-625°C in a N2 atmosphere for 25-35 seconds to form an n-type Ge source region 21 and an n-type Ge drain region 22.

[0054] The specific method of step 3 is as follows: Use diluted hydrofluoric acid 2%-20% to remove GeOx and SiO2 from the surface of p-type Ge substrate 1, n-type Ge source region 21 and n-type Ge drain region 22 after step 2 treatment. Then, use a PEALD device to oxidize with ozone at 275-325℃ for 15-30 min on the top of p-type Ge substrate 1 to deposit 5-10 nm of ZrO2. Then, use a magnetron sputtering device to deposit 30-100 nm of TiN metal. The passivation layer, dielectric layer and metal layer deposited on the p-type Ge substrate 1 between n-type Ge source region 21 and n-type Ge drain region 22 are removed by photolithography and etching to form gate passivation layer 3, gate dielectric layer 4 and gate metal layer 5.

[0055] The gate metal in step 3 is any one of titanium nitride and tantalum nitride; the dielectric layer may also be any one of HfZrO2, HfAlO2, HfO2, Al2O3, TiO2 and mixtures thereof.

[0056] The deposition in step 4 is performed using a PECVD device, and the thickness of the deposited SiO2 insulating layer is 40-60 nm. The specific preparation methods for the first ultrathin oxide layer 71 and the second ultrathin oxide layer 72 are as follows: The n-type Ge source region 21 and the n-type Ge drain region 22 are bombarded for 60-120 seconds using a RIE etching machine under a mixed O2 / Ar / N2 plasma, with a power of 200-400 W and O2, Ar, and N2 flow rates of 150-200 sccm, forming an oxygen-vacancy-rich GeO layer in the n-type Ge source region 21 and the n-type Ge drain region 22. x N y The layers are the first ultrathin oxide layer 71 and the second ultrathin oxide layer 72.

[0057] In step 4, both the first ultrathin oxide layer 71 and the second ultrathin oxide layer 72 are GeO. x Ny , 1 < x < 2, 0 < y < 0.5, with a thickness of 2 - 5 nm.

[0058] Step 5 is to use an electron beam evaporation device to deposit an electrode adhesion layer and an electrode layer on the first ultra-thin oxide layer 71, the second ultra-thin oxide layer 72, and the gate metal layer 5 respectively, and use a lift-off process to remove the electrode adhesion layer and the electrode layer outside the source-drain-gate regions, and lead out the source electrode adhesion layer 81, the source electrode 91, the drain electrode adhesion layer 82, the drain electrode 92, and the gate electrode adhesion layer 83, the gate electrode 93.

[0059] The electrode adhesion layer is Ti with a thickness of 10 - 30 nm; the electrode layer is any one of Au, Al, Cu, Ag with a thickness of 20 - 50 nm; the metals of the source electrode 91, the drain electrode 92, and the gate electrode 93 can be any one of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

[0060] The specific method of Step 6 is: using magnetron sputtering to deposit 50 - 100 nm of Al on the bottom surface of the p-type Ge substrate 1 to obtain the substrate electrode 10.

[0061] Example

[0062] Such as Figure 1As shown in the figure, a Ge n-type field effect transistor structure with a low-resistivity ohmic contact includes a p-type Ge substrate 1. On both sides of the p-type Ge substrate 1, there are an n-type Ge source region 21 and an n-type Ge drain region 22 respectively. A first ultra-thin oxide layer 71 is provided on the n-type Ge source region 21, and a second ultra-thin oxide layer 72 is provided on the n-type Ge drain region 22. Between the n-type Ge source region 21 and the n-type Ge drain region 22 and in the middle of the top of the p-type Ge substrate 1, a gate passivation layer 3, a gate dielectric layer 4, and a gate metal layer 5 are sequentially arranged from bottom to top. First insulating sidewalls 61 and second insulating sidewalls 62 are provided on both sides of the gate passivation layer 3, the gate dielectric layer 4, and the gate metal layer 5 respectively; on the outside of the first insulating sidewall 61 and on the first ultra-thin oxide layer 71, a source electrode adhesion layer 81 and a source electrode 91 are sequentially arranged; on the outside of the second insulating sidewall 62 and on the second ultra-thin oxide layer 72, a drain electrode adhesion layer 82 and a drain electrode 92 are sequentially arranged; between the first insulating sidewall 61 and the second insulating sidewall 62 and on the gate metal layer 5, a gate electrode adhesion layer 83 and a gate electrode 93 are sequentially arranged. A first conductive filament channel 11 penetrates through the first ultra-thin oxide layer 71. One end of the first conductive filament channel 11 is electrically connected to the source electrode 91 through the source electrode adhesion layer 81, and the other end of the first conductive filament channel 11 is electrically connected to the n-type Ge source region 21; a second conductive filament channel 12 penetrates through the second ultra-thin oxide layer 72. One end of the second conductive filament channel 12 is electrically connected to the drain electrode 92 through the drain electrode adhesion layer 82, and the other end of the second conductive filament channel 12 is electrically connected to the n-type Ge drain region 22.

[0063] The first insulating sidewalls 61 and the second insulating sidewalls 62 are made of SiO2 material.

[0064] A substrate electrode 10 is provided at the bottom of the p-type Ge substrate 1.

[0065] Both the first ultra-thin oxide layer 71 and the second ultra-thin oxide layer 72 are GeO x N y where 1 < x < 2, 0 < y < 0.5, and the thicknesses are both 2 - 5 nm.

[0066] Both the first ultra-thin oxide layer 71 and the second ultra-thin oxide layer 72 play a role in alleviating the metal-induced band-to-band energy level unlocking and Fermi level pinning.

[0067] The present invention also provides a preparation method for a Ge n-type field effect transistor structure based on a low-resistivity ohmic contact, including the following steps:

[0068] As Figure 2 (a) shown, Step 1: Perform standard cleaning on the p-type Ge substrate 1, use a PEALD device to perform ozone oxidation at 300 °C for 15 min to form 3 nm of GeOx, and use a deposition device to deposit 10 nm of SiO2;

[0069] like Figure 2 As shown in (b), step 2: P-type Ge substrate 1 after step 1 is implanted on both sides of the top using photolithography and ion implantation processes. + Ions with an energy of 30keV, a dose of 1E15, and an angle of 7° were used. Then, the doped ions were activated by annealing at 600°C in a N2 atmosphere for 30 seconds using a rapid annealing furnace to form an n-type Ge source region 21 and an n-type Ge drain region 22.

[0070] like Figure 2 (c) As shown, step 3: Use diluted 2% hydrofluoric acid to remove GeOx and SiO2 from the surfaces of the p-type Ge substrate 1, n-type Ge source region 21, and n-type Ge drain region 22 after the treatment in step 2, as follows: Figure 2 As shown in (d), a 10 nm thick ZrO2 layer was deposited on top of the p-type Ge substrate 1 using a PEALD device at 300 °C with ozone oxidation for 15 min. Following this, a 100 nm thick TiN metal layer was deposited using a magnetron sputtering device. Figure 2 As shown in (f), the passivation layer, dielectric layer and metal layer deposited above the p-type Ge substrate 1 between the n-type Ge source region 21 and the n-type Ge drain region 22 are removed by photolithography and etching to form the gate passivation layer 3, the gate dielectric layer 4 and the gate metal layer 5.

[0071] The gate metal in step 3 is any one of titanium nitride and tantalum nitride; the dielectric layer may also be any one of HfZrO2, HfAlO2, HfO2, Al2O3, TiO2 and mixtures thereof;

[0072] like Figure 3 As shown in (a), step 4: A 50 nm thick SiO2 insulating layer is deposited on the top and sides of the gate passivation layer 3, gate dielectric layer 4, and gate metal layer 5 formed in step 3, as well as on the n-type Ge source region 21 and n-type Ge drain region 22, using a PECVD device. Then, as... Figure 3 As shown in (b), the SiO2 insulating layer deposited above the n-type Ge source region 21 and the n-type Ge drain region 22, as well as the SiO2 insulating layer deposited in the middle of the top of the gate metal layer 5, are removed by photolithography and wet etching, forming the first insulating sidewall 61 and the second insulating sidewall 62, respectively; Figure 3 As shown in (c), the n-type Ge source region 21 and n-type Ge drain region 22 were bombarded for 120 s using a RIE etching machine under a mixed plasma of O2 / Ar / N2. The power was 400 W, and the flow rates of O2, Ar, and N2 were 200 sccm, respectively, forming a layer of GeO rich in oxygen vacancies in the n-type Ge source region 21 and the n-type Ge drain region 22. x N yThe layers are 5 nm thick, forming a first ultrathin oxide layer 71 and a second ultrathin oxide layer 72.

[0073] like Figure 3 As shown in (d), in step 5: using an electron beam evaporation apparatus, a Ti electrode adhesion layer with a thickness of 25 nm and an Au electrode layer with a thickness of 50 nm are deposited sequentially on the first ultrathin oxide layer 71, the second ultrathin oxide layer 72 and the gate metal layer 5, respectively. The electrode adhesion layer and electrode layer outside the gate, source and drain regions are removed using a stripping process, and the source electrode adhesion layer 81, source electrode 91, drain electrode adhesion layer 82, drain electrode 92 and gate electrode adhesion layer 83 and gate electrode 93 are brought out.

[0074] The Ti material used has good adhesion, which enhances the adhesion of the Au film and can bond Au to other materials well. It also has low contact resistance, which can form a good ohmic contact with Au. Furthermore, the gold electrode has extremely high corrosion resistance, good electrical conductivity, and thermal conductivity, among other good properties.

[0075] The source electrode 91, drain electrode 92, and gate electrode 93 can all be made of any one of the following metals: tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

[0076] like Figure 4 As shown, step 6: deposit 100 nm of Al on the bottom surface of the p-type Ge substrate 1 using magnetron sputtering to obtain the substrate electrode 10.

[0077] like Figure 1 As shown, in step 7: a gradually increasing negative scanning voltage is applied between the source electrode and the substrate electrode and between the drain electrode and the substrate electrode. The current voltage test shows that the current suddenly increases at a certain voltage when scanning in the negative voltage direction, forming a conductive filament channel in the first ultrathin oxide layer 71 and the second ultrathin oxide layer 72, respectively connecting the source electrode 91 and the n-type Ge source region 21, and the drain electrode 92 and the n-type Ge drain region 22.

[0078] This invention addresses the problem of difficult formation of ohmic contacts and high ohmic contact resistance in n-channel Ge field-effect transistors due to the Fermi pinning effect in n-type Ge materials. It proposes a Ge n-channel field-effect transistor structure with low resistivity ohmic contact and a method for fabricating it, which is highly compatible with CMOS. By embedding an ultrathin oxide layer between the metal and the n-Ge semiconductor and using an electroforming process to break down the oxide layer, a low resistivity ohmic contact is achieved.

Claims

1. A low-resistivity ohmic contact Ge n-channel field-effect transistor structure, comprising a p-type Ge substrate (1), characterized in that: The p-type Ge substrate (1) has an n-type Ge source region (21) and an n-type Ge drain region (22) on both sides. The n-type Ge source region (21) has a first ultrathin oxide layer (71), and the n-type Ge drain region (22) has a second ultrathin oxide layer (72). Between the n-type Ge source region (21) and the n-type Ge drain region (22), and located at the top center of the p-type Ge substrate (1), a gate passivation layer (3), a gate dielectric layer (4), and a gate metal layer (5) are arranged sequentially from bottom to top. The gate passivation layer (3), the gate dielectric layer (4), and the gate metal layer (5) have a first insulating sidewall (61) and a second insulating sidewall (62) on both sides. A source electrode adhesion layer (81) and a source electrode (91) are arranged sequentially on the outside of the first insulating sidewall (61) and on the first ultrathin oxide layer (71). A drain electrode is arranged sequentially on the outside of the second insulating sidewall (62) and on the second ultrathin oxide layer (72). Electrode adhesion layer (82), drain electrode (92); gate electrode adhesion layer (83) and gate electrode (93) are sequentially disposed between the first insulating sidewall (61) and the second insulating sidewall (62) and on the gate metal layer (5). The bottom of the p-type Ge substrate (1) is provided with a substrate electrode (10). A first conductive filament channel (11) is passed through the first ultrathin oxide layer (71). One end of the first conductive filament channel (11) is electrically connected to the source electrode (91) through the source electrode adhesion layer (81), and the other end of the first conductive filament channel (11) is electrically connected to the n-type Ge source region (21). A second conductive filament channel (12) is passed through the second ultrathin oxide layer (72). One end of the second conductive filament channel (12) is electrically connected to the drain electrode (92) through the drain electrode adhesion layer (82), and the other end of the second conductive filament channel (12) is electrically connected to the n-type Ge drain region (22).

2. The low resistivity ohmic contact Gen-type channel field-effect transistor structure according to claim 1, characterized in that: The first insulating sidewall (61) and the second insulating sidewall (62) are made of SiO2 material.

3. The low resistivity ohmic contact Gen-type channel field-effect transistor structure according to claim 1, characterized in that: Both the first ultra-thin oxide layer (71) and the second ultra-thin oxide layer (72) are GeO x N y , where 1 < x < 2, 0 < y < 0.5, and both have a thickness of 2 - 5 nm.

4. A method for fabricating a Gen n-type channel field-effect transistor structure based on a low resistivity ohmic contact, characterized in that: Includes the following steps: Step 1: Oxidize GeOx on a p-type Ge substrate (1) to generate GeOx, and then deposit SiO2; Step 2: On the top two sides of the p-type Ge substrate (1) after step 1, n-type Ge source region (21) and n-type Ge drain region (22) are prepared by photolithography and ion implantation. Step 3: Remove GeOx and SiO2 from the surfaces of the p-type Ge substrate (1), n-type Ge source region (21) and n-type Ge drain region (22) after the treatment in Step 2. Then, deposit a passivation layer, a dielectric layer and a metal layer on top of the p-type Ge substrate (1) in sequence. Remove the passivation layer, dielectric layer and metal layer deposited between the n-type Ge source region (21) and the n-type Ge drain region (22) from the p-type Ge substrate (1) outside the area directly above it by photolithography and etching to form a gate passivation layer (3), a gate dielectric layer (4) and a gate metal layer (5). Step 4: Deposit SiO2 insulating layers on the surfaces of the gate passivation layer (3), gate dielectric layer (4), gate metal layer (5), and n-type Ge source region (21) and n-type Ge drain region (22) formed in Step 3. Then, remove the SiO2 insulating layers deposited above the n-type Ge source region (21) and n-type Ge drain region (22) and the SiO2 insulating layer deposited in the middle of the top of the gate metal layer (5) by photolithography and wet etching to form the first insulating sidewall (61) and the second insulating sidewall (62), respectively. Then, form the first ultrathin oxide layer (71) and the second ultrathin oxide layer (72) above the n-type Ge source region (21) and n-type Ge drain region (22). Step 5: Sequentially deposit source electrode adhesion layer (81) and source electrode (91) on the first ultrathin oxide layer (71); sequentially deposit drain electrode adhesion layer (82) and drain electrode (92) on the second ultrathin oxide layer (72); sequentially deposit gate electrode adhesion layer (83) and gate electrode (93) on the gate metal layer (5); Step 6: Deposit Al on the bottom surface of the p-type Ge substrate (1) to form a substrate electrode (10); Step 7: Apply gradually increasing negative scanning voltage between the source electrode and the substrate electrode and between the drain electrode and the substrate electrode. The current voltage test shows that the current suddenly increases at a certain voltage when scanning in the negative voltage direction, forming conductive filament channels in the first ultrathin oxide layer (71) and the second ultrathin oxide layer (72), respectively connecting the source electrode (91) and the n-type Ge source region (21), and the drain electrode (92) and the n-type Ge drain region (22).

5. The method for fabricating a Gen-type channel field-effect transistor structure based on a low-resistivity ohmic contact according to claim 4, characterized in that: The specific method of step 1 is as follows: the p-type Ge substrate (1) is cleaned according to standard, and ozone is oxidized at 275-325℃ for 15-30 minutes using PEALD equipment to form 3-5nm GeOx, and 10-15nm SiO2 is deposited using deposition equipment. The specific method of step 2 is as follows: P is implanted into the top two sides of the p-type Ge substrate (1) after step 1 using photolithography and ion implantation processes. + Ions with energies of 25keV-35keV, doses of 5E14-1E15, and angles of 6°-8° are used. Then, the doped ions are activated in a rapid annealing furnace at 575-625°C in a N2 atmosphere for 25-35s to form an n-type Ge source region (21) and an n-type Ge drain region (22). The specific method of step 3 is as follows: use diluted hydrofluoric acid 2%-20% to remove GeOx and SiO2 from the surface of the p-type Ge substrate (1), n-type Ge source region (21) and n-type Ge drain region (22) after step 2 treatment. Then, use PEALD equipment to oxidize with ozone at 275-325℃ for 15-30 min on the top of the p-type Ge substrate (1) to deposit 5-10 nm of ZrO2. Then, use magnetron sputtering equipment to deposit 30-100 nm of TiN metal. The passivation layer, dielectric layer and metal layer deposited between the n-type Ge source region (21) and n-type Ge drain region (22) of the p-type Ge substrate (1) are removed by photolithography and etching to form the gate passivation layer (3), gate dielectric layer (4) and gate metal layer (5). The gate metal in step 3 is any one of titanium nitride and tantalum nitride; the dielectric layer may also be any one of HfZrO2, HfAlO2, HfO2, Al2O3, TiO2 and mixtures thereof.

6. The method for fabricating a Gen-type channel field-effect transistor structure based on a low-resistivity ohmic contact according to claim 4, characterized in that: The deposition in step 4 is performed using a PECVD device, and the thickness of the deposited SiO2 insulating layer is 40-60 nm. The specific preparation methods of the first ultrathin oxide layer (71) and the second ultrathin oxide layer (72) are as follows: the n-type Ge source region (21) and the n-type Ge drain region (22) are bombarded for 60-120 s using a RIE etching machine under O2 / Ar / N2 mixed plasma, with a power of 200-400 W and an O2, Ar and N2 flow rate of 150-200 sccm, to form an oxygen-vacancy-rich GeO layer in the n-type Ge source region (21) and the n-type Ge drain region (22). x N y The layers are the first ultrathin oxide layer (71) and the second ultrathin oxide layer (72).

7. The method for fabricating a Gen-type channel field-effect transistor structure based on a low-resistivity ohmic contact according to claim 4 or 6, characterized in that: The first ultra-thin oxide layer (71) and the second ultra-thin oxide layer (72) in the step 4 are both GeO x N y , where 1 < x < 2, 0 < y < 0.5, and the thicknesses are both 2 - 5 nm.

8. The method for fabricating a Gen-type channel field-effect transistor structure based on a low-resistivity ohmic contact according to claim 4, characterized in that: Step 5 involves depositing an electrode adhesion layer and an electrode layer on the first ultrathin oxide layer (71), the second ultrathin oxide layer (72), and the gate metal layer (5) using an electron beam evaporation apparatus. The electrode adhesion layer and electrode layer outside the gate source drain region are removed using a stripping process, and the source electrode adhesion layer (81), source electrode (91), drain electrode adhesion layer (82), drain electrode (92), gate electrode adhesion layer (83), and gate electrode (93) are brought out.

9. The method for fabricating a Gen-type channel field-effect transistor structure based on a low-resistivity ohmic contact according to claim 8, characterized in that: The electrode adhesion layer is Ti with a thickness of 10-30 nm; the electrode layer is any one of Au, Al, Cu, and Ag with a thickness of 20-50 nm; the source electrode (91), drain electrode (92), and gate electrode (93) can all be made of any one of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

10. The method for fabricating a Gen-type channel field-effect transistor structure based on a low-resistivity ohmic contact according to claim 4, characterized in that: The specific method of step 6 is as follows: deposit 50-100 nm of Al on the bottom surface of a p-type Ge substrate (1) using magnetron sputtering to obtain a substrate electrode (10).

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