An overcurrent protection circuit for half-bridge isolation converter

Abstract

The present invention belongs to the technical field of power management integrated circuits, and specifically relates to an overcurrent protection circuit for a half-bridge isolation converter. After the half-bridge converter triggers the overcurrent protection, the circuit will still immediately turn off the upper tube to avoid further aggravation of the overcurrent, but in the next cycle, the upper tube will not be turned on for only a minimum time like the traditional overcurrent protection mechanism, but will be turned on for the same time as the previous cycle, so that the main side of the transformer is guaranteed to be charged in the opposite direction for the same time in the two cycles before and after the overcurrent period, effectively avoiding the magnetic saturation problem that may occur in the main side of the transformer. If the overcurrent phenomenon still continues, it is guaranteed that the upper tube is turned on according to the minimum conduction time in the next even number of cycles, which not only ensures the effectiveness of the overcurrent protection, but also ensures that the main side transformer does not have magnetic saturation.

Description

Technical Field

[0001] The invention belongs to the technical field of power management integrated circuits, and in particular relates to an overcurrent protection circuit for a half-bridge isolation converter. Background Art

[0002] In today's society, with the continuous development of Internet of Things technology, a large number of new electronic devices have emerged in various application scenarios. Under the requirements of various application scenarios, the safety, stability and reliability of the power management system in various electronic devices have been put forward higher and higher requirements. Among various types of power management products, isolated converters have great advantages in safety and reliability because of their electrical isolation characteristics, and have now become a must-have solution in many occasions. Among various isolated converters, half-bridge converters are a common type. In medium-power application scenarios, all indicators are relatively balanced, so it is currently a popular topology. The power IC that controls the half-bridge converter, like the mainstream power IC on the current market, usually has an overcurrent protection circuit to deal with possible overcurrent behavior in the system. In a common power IC, once an overcurrent is detected, the upper tube will be immediately turned off to stop charging the output, and only a minimum upper tube opening time will be maintained in each cycle in the following several cycles until the overcurrent phenomenon disappears before the chip resumes normal operation. However, for the half-bridge converter topology, this approach may bring some problems. After detecting overcurrent and shutting down the upper tube, if the minimum opening time is maintained in the next cycle according to the traditional solution, the half-bridge converter will charge the main transformer in both positive and negative directions alternately, which will cause the charging time of the transformer main side in the two cycles to be inconsistent. Because people cannot determine the time point when the overcurrent event may occur, the two charging times may differ greatly, which will cause magnetic bias or even magnetic saturation on the transformer main side. For the control IC of the half-bridge converter, the general overcurrent protection circuit cannot solve this hidden danger. Summary of the invention

[0003] In view of the above-mentioned difficulties in the design of overcurrent protection for half-bridge converters, the present invention designs a circuit specifically for solving the magnetic saturation problem that may occur in the overcurrent protection stage of the half-bridge converter. After the half-bridge converter triggers the overcurrent protection, the circuit will still immediately turn off the upper tube to avoid further aggravation of the overcurrent, but in the next cycle, the upper tube will not be turned on for only a minimum time like the traditional overcurrent protection mechanism, but will be turned on for the same time as the previous cycle, so that the main side of the transformer is still charged in the opposite direction for the same time in the two cycles before and after the overcurrent period, effectively avoiding the magnetic saturation problem that may occur in the main side of the transformer. If the overcurrent phenomenon still continues, it is ensured that the upper tube is turned on according to the minimum conduction time in the next even number of cycles, which not only ensures the effectiveness of the overcurrent protection, but also ensures that the main side transformer does not have magnetic saturation.

[0004] The purpose of the present invention is to solve the magnetic saturation problem that may occur when a conventional power supply IC overcurrent protection circuit is applied to a half-bridge converter. An additional overcurrent protection mechanism suitable for the characteristics of a half-bridge converter is added to the traditional overcurrent protection behavior mechanism. This better solves the protection problem when an overcurrent phenomenon occurs in a half-bridge converter.

[0005] The technical solution of the present invention is:

[0006] An overcurrent protection circuit for a half-bridge isolation converter, comprising a clock generating circuit, an overcurrent clock generating circuit, and an overcurrent signal output circuit;

[0007] The clock generating circuit comprises a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a first NMOS tube MN1, a first capacitor C1, a frequency determining resistor RCLK, a first operational amplifier OP1, a second operational amplifier OP2, a first inverter INV1, a second inverter INV2, a third inverter INV3, a first NOR gate NOR1, a second NOR gate NOR2, and a first delay buffer Buffer1; the positive end of the first operational amplifier OP1 is connected to a first reference voltage VREF1, the negative end is connected to an output end, and the output is connected through one end of the frequency determining resistor RCLK and the gates of the first PMOS tube MP1 and the second PMOS tube MP2; the source of the first PMOS tube MP1 is connected to a power supply; the source of the second PMOS tube is connected to a power supply, and its drain is connected to the source of the third PMOS tube; the gate of the third PMOS tube is connected to the first clock signal, and its drain is connected to the drain of the first NMOS tube, one end of the first capacitor C1, the second operational amplifier OP1, and the third PMOS tube. 2; the gate of the first NMOS tube MN1 is connected to the first clock signal, the source of the first NMOS tube MN1, the other end of the first capacitor C1, and the other end of the frequency determining resistor RCLK are grounded; the negative end of the second operational amplifier OP2 is connected to the second reference voltage, and the output end thereof is connected to an input end of the second NOR gate NOR2; the other input end of the second NOR gate NOR2 is connected to the output end of the first NOR gate NOR1; one input end of the first NOR gate NOR1 is connected to the output end of the second NOR gate NOR2, and the other input end of the first NOR gate is connected to the output end of the first inverter INV1; the input end of the first inverter INV1 is connected to the output end of the first delay buffer Buffer1; the input end of the second inverter INV2 is connected to the output end of the first NOR gate NOR1, and the output end of the second inverter INV2 is connected to the input end of the third inverter INV3 and the input end of the first delay buffer Buffer1; the output end of the third inverter INV3 outputs the first clock signal;

[0008] The overcurrent clock generating circuit part includes a fourth PMOS tube MP4, a fifth PMOS tube MP5, a second NMOS tube MN2, a second capacitor C2, a third operational amplifier OP3, a fourth inverter INV4, a fifth inverter INV5, a third NOR gate NOR3, a fourth NOR gate NOR4, a first NAND gate NAND1, and a second delay buffer Buffer2; the source of the fourth PMOS tube MP4 is connected to the power supply, and the gate thereof is connected to the output end of the first operational amplifier OP1; the source of the fifth PMOS tube MP5 is connected to the drain of the fourth PMOS tube MP4, the gate of the fifth PMOS tube MP5 is connected to the second clock signal, the drain of the fifth PMOS tube is connected to the drain of the second NMOS tube, one end of the second capacitor C2, and the positive end of the third operational amplifier OP3; the gate of the second NMOS tube MN2 is connected to the second clock signal, and the source thereof is grounded with the other end of the second capacitor C2; The negative terminal of the three operational amplifiers OP3 is connected to the second reference voltage, and the output terminal thereof is connected to an input terminal of the fourth NOR gate NOR4; the other input terminal of the fourth NOR gate NOR4 is connected to the output terminal of the third NOR gate NOR3; one input terminal of the third NOR gate NOR3 is connected to the output terminal of the fourth NOR gate NOR4, and the other input terminal of the third NOR gate NOR3 is connected to the output terminal of the fourth inverter INV4; the input terminal of the fourth inverter INV4 is connected to the output terminal of the second delay buffer Buffer2; the input terminal of the fifth inverter INV5 is connected to the output terminal of the third NOR gate NOR3, and the output terminal of the fifth inverter INV5 is connected to the input terminal of the second delay buffer Buffer2 and an input terminal of the first NAND gate NAND1, the other input terminal of the first NAND gate NAND1 is connected to the overcurrent signal output circuit, and the output terminal of the first NAND gate NAND1 outputs the second clock signal;

[0009] The overcurrent signal output circuit includes a first trigger Trigger1, a first delayed inverter TD1, a second delayed inverter TD2, a fifth NOR gate NOR5, a sixth NOR gate NOR6, a seventh NOR gate NOR7, an eighth NOR gate NOR8, and a first AND gate AND1; the clock terminal of the first trigger Trigger1 is connected to the first clock signal, which is positive edge triggered, and its reset signal is connected to the second overcurrent detection signal, which is valid at a low level, and the two output terminals OUT and! of the first trigger Trigger1 are connected to the first clock signal, which is positive edge triggered, and the reset signal of the first trigger Trigger1 is connected to the second overcurrent detection signal, which is valid at a low level, and the two output terminals OUT and! OUT outputs the first trigger signal and the second trigger signal respectively, which are high level and low level respectively in the reset stage; the input end of the first delay inverter TD1 and one input end of the fifth NOR gate NOR5 are connected to the second trigger signal, the output end of the fifth NOR gate NOR5 is connected to one input end of the sixth NOR gate NOR6, the other input end of the sixth NOR gate NOR6 is connected to the output end of the seventh NOR gate NOR7, and the output end of the sixth NOR gate NOR6 outputs the second over-current detection signal; one input end of the seventh NOR gate NOR7 is connected to the output end of the sixth NOR gate NOR6, and the other input end of the seventh NOR gate NOR7 is connected to the first over-current detection signal; the first AND gate AND 1, one input end of the first AND gate AND1 is connected to the first trigger signal, and the output end of the first AND gate outputs the first overcurrent signal; the input end of the second delay inverter TD2 and one input end of the eighth NOR gate NOR8 are connected to the second clock signal, the output end of the second delay inverter TD2 is connected to the other input end of the eighth NOR gate NOR8, and the output end of the eighth NOR gate NOR8 outputs the second overcurrent signal; the first overcurrent detection signal is the overcurrent signal detected in the half-bridge isolation converter; the first overcurrent signal and the second overcurrent signal are both used to control the shutdown of the upper tube in the half-bridge isolation converter, and both are valid at high level.

[0010] The beneficial effect of the present invention is that the clock cycle is controlled by resistor programming, and the recording of the cycle when overcurrent occurs is controlled, so that when overcurrent occurs, the upper tube opening time of the next cycle can be guaranteed to correspond to the upper tube opening time of the overcurrent occurrence cycle. While the system is protected from overcurrent, the primary side of the transformer can always maintain magnetic balance. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 The present invention provides a specific overcurrent protection circuit suitable for a half-bridge converter.

[0012] Figure 2 Schematic diagram of the clock waveform generated by the circuit proposed in the present invention.

[0013] Figure 3 The specific waveform effect of the circuit proposed by the present invention when applied. DETAILED DESCRIPTION

[0014] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings:

[0015] The technical solution of the present invention comprises: a clock generating circuit part, an overcurrent clock generating circuit part, and an overcurrent signal output circuit part, which are composed of three parts. The specific circuit structure is as follows: Figure 1 As shown:

[0016] The clock generation circuit part includes a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a first NMOS tube MN1, a first capacitor C1, a frequency determining resistor RCLK, a first operational amplifier OP1, a second operational amplifier OP2, a first inverter INV1, a second inverter INV2, a third inverter INV3, a first NOR gate NOR1, a second NOR gate NOR2, and a first delay buffer Buffer1. The specific link relationship is: the operational amplifier OP1 is connected in a buffer form, the positive terminal input potential VREF1, the output is connected to RCLK to the ground, the output is connected to the diode-connected MP1, the gate of MP1 is VG, and VG is connected to the gate of MP2 as a current mirror. MP2, MP3, MN1, MP3 and MN1 are connected in sequence from the power supply to the ground, and the gates of MP3 and MN1 are connected to the CLK signal. The drain end of MN1 is connected to the ground by C1 and connected to the positive end of OP2, the negative end of OP2 is connected to VREF2, and the output signal is VTA1. Here, OP1 and OP2 can be replaced by general operational amplifiers. In the digital part, NOR1 and NOR2 are connected to form an RS latch. The VTA2 signal is connected to INV1 and then to the input of NOR1. The VTA1 signal is connected to the input of NOR2. The output of NOR1 is used as the output of the RS latch and then connected to INV2. The output of INV2 is connected in parallel to two lines, which are respectively connected to INV3 to output the CLK signal and to Buffer1 to output the VTA2 signal.

[0017] The overcurrent clock generating circuit includes the fourth PMOS tube MP4, the fifth PMOS tube MP5, the second NMOS tube MN2, the second capacitor C2, the third operational amplifier OP3, the fourth inverter INV4, the fifth inverter INV5, the third NOR gate NOR3, the fourth NOR gate NOR4, the first NAND gate NAND1, and the second delay buffer Buffer2. The specific link relationship is: MP4, MP5, MN2 are connected in sequence from the power supply to the ground, the gate of MP4 is connected to the VG potential, and the gates of MP5 and MN2 are connected to the CLK_OC signal. The drain end of MN2 is connected to the ground by C2 and connected to the positive end of OP3, the negative end of OP3 is connected to VREF2, and the output signal is VTB1. Here, OP3 can be replaced by a general operational amplifier. In the digital part, NOR3 and NOR4 are connected to form an RS latch. The VTB2 signal is connected to INV4 and then to the input of NOR3. The VTB1 signal is connected to the input of NOR4. The output of NOR3 is used as the output of the RS latch and then connected to INV5. The output of INV5 is connected in parallel to two lines, which are connected to one end of NAND1 and output CLK_OC signal and connected to Buffer2 to output VTB2 signal. The other input of NAND1 is connected to OC_C.

[0018] The overcurrent signal output circuit includes the first trigger Trigger1, the first delay inverter TD1, the second delay inverter TD2, the fifth NOR gate NOR5, the sixth NOR gate NOR6, the seventh NOR gate NOR7, the eighth NOR gate NOR8, and the first AND gate AND1. The specific link relationship is: the clock terminal of the first trigger Trigger1 is connected to the CLK signal, which is triggered by the positive edge, the reset signal is connected to the OC_C signal, and the low level is valid. The two outputs OUT and !OUT are connected to the A1 and A2 signals respectively, which are high and low levels in the reset stage. NOR6 and NOR7 form an RS latch, and the signal obtained by the A2 signal through TD1 and the A2 signal itself are used as the input of NOR5. The output terminal of NOR5 is connected to the input of one side of the RS latch NOR6. The output of NOR6 is used as the output of the entire RS latch to output the OC_C signal, and the input of one side of NOR7 is the OC signal. The OC and A1 signals are input to AND1, and AND1 outputs the OC_OUT1 signal. The signal obtained by the CLK_OC signal passing through TD2 and the CLK_OC signal itself are used as the input of NOR8, and NOR8 outputs the OC_OUT2 signal.

[0019] In the first part of the clock generation circuit, op amp OP1 is clamped to allow a specific current to flow through RCLK. This current can be adjusted by controlling the size of RCLK. This current flows through MP1 and then through the current mirror MP2. The size of this current controls the speed of charging capacitor C1. During the period of charging capacitor C1, VTA1 remains low until the potential on C1 increases to a certain level and then VTA1 turns high. After VTA1 turns to a high level, it triggers CLK to be high, and also triggers VTA2 to be low after a short period of time. After becoming low, VTA2 will trigger the RS latch again to make CLK low, thus forming a complete clock cycle, in which CLK is the clock signal, and its low level time is the charging time of the current capacitor C1, which is longer; and the high level time is the delay time of Buffer1, which is shorter. The specific clock waveform obtained is Figure 2 displayed in.

[0020] Next is the overcurrent clock generation circuit in the second part, which is mainly used to generate an overcurrent indication signal with the same delay as the previously generated clock cycle. Under normal circumstances, the OC_C signal remains low, which makes the CLK_OC signal remain high, and this part of the circuit does not work. When overcurrent occurs, OC_C remains high, indicating that the overcurrent state continues, and CLK_OC is low, activating the entire system to start working. At this time, the system will go through the same working process as the previous clock generation circuit. If the parameters of each circuit are kept the same, CLK_OC will experience a clock cycle that is first low and then high, and this clock cycle is the same as the cycle of the previously generated CLK signal. The end of the clock cycle is marked by CLK_OC turning low, and this action will have an effect on the shutdown of the upper tube in the next cycle. It will be described in the third part.

[0021] The third part of the circuit is responsible for converting the previously generated signal into a flag signal to shut down the upper tube in each cycle. The most original overcurrent signal is OC. The high OC indicates that an overcurrent condition has occurred in the external system. At this time, OC_C turns high, indicating the persistence of the overcurrent condition. At the same time, OC_OUT1 immediately turns high and is sent to the subsequent logic circuit to control the upper tube to shut down, so as to avoid further deterioration of the overcurrent condition. This means that the upper tube is shut down for the first time due to overcurrent. In this clock cycle, the upper tube has been turned off. After the next clock cycle, because CLK has a high process, A1 will turn low through the trigger, locking OC_OUT1 and no longer turning high. At the same time, the falling edge of CLK_OC generated in the second part of the circuit will trigger OC_OUT2 to turn high. Because the falling edge of CLK_OC is exactly one clock cycle away from the time when the first overcurrent occurs, when OC_OUT2 turns high, the upper tube turn-on time in the second clock cycle will also be the same as the upper tube turn-on time in the first clock cycle. At this time, OC_OUT2 happens to turn high, which makes the upper tube turn-on time of this pair of cycles the same. After the next clock cycle arrives, CLK has a high-level pulse again, which causes A2 to turn low through the trigger. A2 turning low generates a high-level pulse that acts on the RS trigger formed by NOR6 and NOR7, turning OC_C low, and this pair of overcurrent cycles ends. If it is still in an overcurrent state in the next cycle, because the overcurrent is detected at the beginning, the next pair of cycles will be a cycle in which the upper tube only maintains the minimum turn-on time until the circuit returns to normal. The effect of overcurrent protection is Figure 3 Displayed in.

[0022] In summary, the use of this new overcurrent protection circuit can provide normal overcurrent protection for the circuit while ensuring the consistency of the upper tube opening time in two cycles, ensuring that the primary transformer will not have magnetic bias. It is very suitable for use in the control IC of the half-bridge converter.

Claims

1. An overcurrent protection circuit for a half-bridge isolation converter, characterized in that: It includes a clock generating circuit, an overcurrent clock generating circuit, and an overcurrent signal output circuit; The clock generating circuit comprises a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a first NMOS tube MN1, a first capacitor C1, a frequency determining resistor RCLK, a first operational amplifier OP1, a second operational amplifier OP2, a first inverter INV1, a second inverter INV2, a third inverter INV3, a first NOR gate NOR1, a second NOR gate NOR2, and a first delay buffer Buffer1; the positive end of the first operational amplifier OP1 is connected to a first reference voltage VREF1, the negative end is connected to an output end, and the output is connected to one end of the frequency determining resistor RCLK and the gates of the first PMOS tube MP1 and the second PMOS tube MP2; the source of the first PMOS tube MP1 is connected to a power supply; the source of the second PMOS tube is connected to a power supply, and its drain is connected to the source of the third PMOS tube; the gate of the third PMOS tube is connected to the first clock signal, and its drain is connected to the drain of the first NMOS tube, one end of the first capacitor C1, and the second operational amplifier OP2. The positive end of the first NMOS tube MN1 is connected to the first clock signal, and the source of the first NMOS tube MN1, the other end of the first capacitor C1, and the other end of the frequency determining resistor RCLK are grounded; the negative end of the second operational amplifier OP2 is connected to the second reference voltage, and the output end thereof is connected to an input end of the second NOR gate NOR2; the other input end of the second NOR gate NOR2 is connected to the output end of the first NOR gate NOR1; one input end of the first NOR gate NOR1 is connected to the output end of the second NOR gate NOR2, and the other input end of the first NOR gate is connected to the output end of the first inverter INV1; the input end of the first inverter INV1 is connected to the output end of the first delay buffer Buffer1; the input end of the second inverter INV2 is connected to the output end of the first NOR gate NOR1, and the output end of the second inverter INV2 is connected to the input end of the third inverter INV3 and the input end of the first delay buffer Buffer1; the output end of the third inverter INV3 outputs the first clock signal; The overcurrent clock generating circuit part includes a fourth PMOS tube MP4, a fifth PMOS tube MP5, a second NMOS tube MN2, a second capacitor C2, a third operational amplifier OP3, a fourth inverter INV4, a fifth inverter INV5, a third NOR gate NOR3, a fourth NOR gate NOR4, a first NAND gate NAND1, and a second delay buffer Buffer2; the source of the fourth PMOS tube MP4 is connected to the power supply, and the gate thereof is connected to the output end of the first operational amplifier OP1; the source of the fifth PMOS tube MP5 is connected to the drain of the fourth PMOS tube MP4, the gate of the fifth PMOS tube MP5 is connected to the second clock signal, the drain of the fifth PMOS tube is connected to the drain of the second NMOS tube, one end of the second capacitor C2, and the positive end of the third operational amplifier OP3; the gate of the second NMOS tube MN2 is connected to the second clock signal, and the source thereof is grounded with the other end of the second capacitor C2; The negative terminal of the three operational amplifiers OP3 is connected to the second reference voltage, and the output terminal thereof is connected to an input terminal of the fourth NOR gate NOR4; the other input terminal of the fourth NOR gate NOR4 is connected to the output terminal of the third NOR gate NOR3; one input terminal of the third NOR gate NOR3 is connected to the output terminal of the fourth NOR gate NOR4, and the other input terminal of the third NOR gate NOR3 is connected to the output terminal of the fourth inverter INV4; the input terminal of the fourth inverter INV4 is connected to the output terminal of the second delay buffer Buffer2; the input terminal of the fifth inverter INV5 is connected to the output terminal of the third NOR gate NOR3, and the output terminal of the fifth inverter INV5 is connected to the input terminal of the second delay buffer Buffer2 and an input terminal of the first NAND gate NAND1, the other input terminal of the first NAND gate NAND1 is connected to the overcurrent signal output circuit, and the output terminal of the first NAND gate NAND1 outputs the second clock signal; The overcurrent signal output circuit includes a first trigger Trigger1, a first delayed inverter TD1, a second delayed inverter TD2, a fifth NOR gate NOR5, a sixth NOR gate NOR6, a seventh NOR gate NOR7, an eighth NOR gate NOR8, and a first AND gate AND1; the clock terminal of the first trigger Trigger1 is connected to the first clock signal, which is positive edge triggered, and its reset signal is connected to the second overcurrent detection signal, which is valid at a low level, and the two output terminals OUT and! of the first trigger Trigger1 are connected to the first clock signal, which is positive edge triggered, and the reset signal of the first trigger Trigger1 is connected to the second overcurrent detection signal, which is valid at a low level, and the two output terminals OUT and! OUT outputs the first trigger signal and the second trigger signal respectively, which are high level and low level respectively in the reset stage; the input end of the first delay inverter TD1 and one input end of the fifth NOR gate NOR5 are connected to the second trigger signal, the output end of the fifth NOR gate NOR5 is connected to one input end of the sixth NOR gate NOR6, the other input end of the sixth NOR gate NOR6 is connected to the output end of the seventh NOR gate NOR7, and the output end of the sixth NOR gate NOR6 outputs the second over-current detection signal; one input end of the seventh NOR gate NOR7 is connected to the output end of the sixth NOR gate NOR6, and the other input end of the seventh NOR gate NOR7 is connected to the first over-current detection signal; the first AND gate AND 1, one input end of the first AND gate AND1 is connected to the first trigger signal, and the output end of the first AND gate outputs the first overcurrent signal; the input end of the second delay inverter TD2 and one input end of the eighth NOR gate NOR8 are connected to the second clock signal, the output end of the second delay inverter TD2 is connected to the other input end of the eighth NOR gate NOR8, and the output end of the eighth NOR gate NOR8 outputs the second overcurrent signal; the first overcurrent detection signal is the overcurrent signal detected in the half-bridge isolation converter; the first overcurrent signal and the second overcurrent signal are both used to control the shutdown of the upper tube in the half-bridge isolation converter, and both are valid at high level.

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