A turn-off time generation circuit and a chip

Abstract

The present application provides a turn-off time generation circuit and a chip. The turn-off time generation circuit is applied to a DC-DC converter and includes a non-inverting input voltage generation module, an inverting input voltage generation module, and a comparator module. The input end of the non-inverting input voltage generation module receives the voltage of the SW terminal from the DC-DC converter. The non-inverting input voltage generation module is configured to generate a first comparison voltage proportional to the output voltage of the DC-DC converter. The input end of the inverting input voltage generation module receives the input voltage from the DC-DC converter. The inverting input voltage generation module is configured to generate a second comparison voltage proportional to the input voltage by discharging a load capacitor. The comparator module is configured to receive the first comparison voltage and the second comparison voltage, and output an output signal of the turn-off time generation circuit based on the result of comparing the first comparison voltage and the second comparison voltage.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit technology, and particularly to a turn-off time generation circuit and a chip. Background Art

[0002] With the development of portable electronic products, the direct current-direct current converter (DC-DC converter) has become an essential power supply component for various electronic products such as computers and mobile phones due to its high conversion efficiency. After years of development, the DC-DC loop control technology has also evolved from fixed-frequency control technology to variable-frequency control technology. The typical fixed-frequency control technologies include voltage-mode and current-mode control technologies, and the variable-frequency control technology is the currently popular ripple control loop technology, mainly including the constant on time (COT) mode, the constant off time (COF) mode, and the hysteresis mode control technology.

[0003] In the existing constant off-time mode, the off-time T of each cycle is kept off unchanged, and the on-time T is changed on to adjust the BUCK power supply system. For example, when the load suddenly changes, resulting in a decrease in the output voltage V OUT , the system will keep T off unchanged and extend T on to adjust V OUT ; or when the input voltage V IN increases, the system will keep T off unchanged and shorten T on to ensure the correct duty cycle.

[0004] In the existing constant off-time mode, when the input voltage V IN or the output voltage V OUT changes, it will cause the switching cycle of the BUCK power supply system to change. Excessive changes in the cycle will make the on-off control frequency of the BUCK power supply system unstable, which is not conducive to the control development of the system. Summary of the Invention

[0005] Aiming at the above problems of the prior art, the purpose of this application is to provide a turn-off time generation circuit and a chip with a simple circuit structure, which can adaptively adjust the turn-off time according to the changes in the input voltage and the output voltage, so as to maintain the relative stability of the switching frequency.

[0006] To solve the above problems, the present application provides a turn-off time generation circuit, which is applied to a DC-DC converter. The turn-off time generation circuit includes a non-inverting input voltage generation module, an inverting input voltage generation module, and a comparator module;

[0007] The input terminal of the non-inverting input voltage generation module receives the voltage of the SW terminal from the DC-DC converter; the non-inverting input voltage generation module is used to generate a first comparison voltage proportional to the output voltage of the DC-DC converter;

[0008] The input terminal of the inverting input voltage generation module receives the input voltage from the DC-DC converter; the inverting input voltage generation module is used to generate a second comparison voltage proportional to the input voltage by discharging a load capacitor;

[0009] The comparator module is used to receive the first comparison voltage and the second comparison voltage, and output an output signal of the turn-off time generation circuit based on the result of comparing the first comparison voltage and the second comparison voltage.

[0010] In some embodiments, the non-inverting input voltage generation module includes an SW terminal voltage voltage division module;

[0011] The input terminal of the SW terminal voltage voltage division module receives the SW terminal voltage, and the SW terminal voltage voltage division module is used to divide the SW terminal voltage to obtain a first divided voltage and output it.

[0012] In some embodiments, the SW terminal voltage voltage division module includes a first voltage division resistor and a second voltage division resistor connected in series;

[0013] One end of the first voltage division resistor not connected to the second voltage division resistor is connected to the SW terminal voltage, and one end of the second voltage division resistor not connected to the first voltage division resistor is grounded.

[0014] In some embodiments, the non-inverting input voltage generation module includes a first comparison voltage generation module;

[0015] The input terminal of the first comparison voltage generation module receives the SW terminal voltage, or receives the first divided voltage output by the SW terminal voltage voltage division module in the non-inverting input voltage generation module;

[0016] The first comparison voltage generation module is used to filter the SW terminal voltage or the first divided voltage through an RC filter circuit to generate a first comparison voltage proportional to the output voltage of the DC-DC converter.

[0017] In some embodiments, the first comparison voltage generation module includes a filter resistor and a filter capacitor;

[0018] The first end of the filtering resistor is connected to the voltage of the SW terminal or the output terminal of the voltage dividing module of the SW terminal, and the second end of the filtering resistor is connected to the upper plate of the filtering capacitor;

[0019] The upper plate of the filtering capacitor is also connected to the positive input terminal of the comparator module, and the lower plate of the filtering capacitor is grounded.

[0020] In some embodiments, the inverting input voltage generating module includes an input voltage dividing module and a second comparison voltage generating module;

[0021] The input terminal of the input voltage dividing module receives the input voltage, and the input voltage dividing module is used to divide the input voltage to obtain a second divided voltage and output it to the second comparison voltage generating module;

[0022] The input terminal of the second comparison voltage generating module receives the second divided voltage, and the second comparison voltage generating module is used to discharge the load capacitor in the second comparison voltage generating module by using a current proportional to the second divided voltage to generate a second comparison voltage proportional to the input voltage;

[0023] Wherein, the second comparison voltage has an inverse correlation with the discharge time of the load capacitor.

[0024] In some embodiments, the input voltage dividing module includes a third dividing resistor and a fourth dividing resistor connected in series;

[0025] One end of the third dividing resistor that is not connected to the fourth dividing resistor is connected to the input voltage, and one end of the fourth dividing resistor that is not connected to the third dividing resistor is grounded;

[0026] The input terminal of the second comparison voltage generating module is connected to the common terminal of the third dividing resistor and the fourth dividing resistor.

[0027] In some embodiments, the second comparison voltage generating module includes an operational amplifier, a load resistor, a first NMOS transistor, a first PMOS transistor, a second PMOS transistor, a second NMOS transistor, a third NMOS transistor, and a load capacitor;

[0028] The positive input terminal of the operational amplifier is connected to the common terminal of the third dividing resistor and the fourth dividing resistor, the inverting input terminal of the operational amplifier is connected to the first end of the load resistor, and the output terminal of the operational amplifier is connected to the gate of the first NMOS transistor;

[0029] The first end of the load resistor is also connected to the source of the first NMOS transistor, and the second end of the load resistor is grounded;

[0030] The drain of the first NMOS transistor is connected to the drain and gate of the first PMOS transistor, and the gate of the second PMOS transistor respectively;

[0031] The gate of the first PMOS transistor is also connected to the gate of the second PMOS transistor, the drain of the first PMOS transistor is also connected to the gate of the second PMOS transistor, and the source of the first PMOS transistor is connected to the input voltage;

[0032] The drain of the second PMOS transistor is connected to the drain and gate of the second NMOS transistor, and the gate of the third NMOS transistor respectively, and the source of the second PMOS transistor is connected to the input voltage;

[0033] The gate of the second NMOS transistor is also connected to the gate of the third NMOS transistor, and the source of the second NMOS transistor is grounded;

[0034] The source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the lower plate of the load capacitor;

[0035] The lower plate of the load capacitor is also connected to the inverting input terminal of the comparator module, and the upper plate of the load capacitor is connected to the input voltage.

[0036] In some embodiments, the second comparison voltage generating module includes an operational amplifier, a load resistor, a first NMOS transistor, a first PMOS transistor, a second PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a load capacitor;

[0037] The non-inverting input terminal of the operational amplifier is connected to the common terminal of the third voltage dividing resistor and the fourth voltage dividing resistor, the inverting input terminal of the operational amplifier is connected to the first end of the load resistor, and the output terminal of the operational amplifier is connected to the gate of the first NMOS transistor and the gate of the fourth NMOS transistor respectively;

[0038] The first end of the load resistor is also connected to the source of the first NMOS transistor, and the second end of the load resistor is grounded;

[0039] The drain of the first NMOS transistor is connected to the drain and gate of the first PMOS transistor, and the gate of the second PMOS transistor respectively;

[0040] The gate of the first PMOS transistor is also connected to the gate of the second PMOS transistor, the drain of the first PMOS transistor is also connected to the gate of the second PMOS transistor, and the source of the first PMOS transistor is respectively connected to the source of the second PMOS transistor and the drain of the fourth NMOS transistor;

[0041] The drain of the second PMOS transistor is respectively connected to the drain and gate of the second NMOS transistor, and the gate of the third NMOS transistor;

[0042] The gate of the second NMOS transistor is also connected to the gate of the third NMOS transistor, and the source of the second NMOS transistor is grounded;

[0043] The source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the lower plate of the load capacitor;

[0044] The source of the fourth NMOS transistor is connected to the upper plate of the load capacitor, and the lower plate of the load capacitor is also connected to the inverting input terminal of the comparator module.

[0045] In some embodiments, the comparator module includes a comparator, a second inverter, and a third inverter;

[0046] The output terminal of the non-inverting input voltage generation module is connected to the non-inverting input terminal of the comparator, and the output terminal of the inverting input voltage generation module is connected to the inverting input terminal of the comparator; the comparator is configured to receive the first comparison voltage and the second comparison voltage, compare the first comparison voltage and the second comparison voltage, and generate an output signal of the turn-off time generation circuit based on the comparison result;

[0047] The input terminal of the second inverter receives the output signal of the turn-off time generation circuit, the output terminal of the second inverter is connected to the input terminal of the third inverter, and the output terminal of the third inverter is used to output the output signal of the turn-off time generation circuit.

[0048] In some embodiments, the comparator is a rail-to-rail comparator.

[0049] In a second aspect, an embodiment of the present application provides a chip applied to a DC-DC converter, and the chip includes the turn-off time generation circuit as described above.

[0050] Due to the above technical solutions, the present application has the following beneficial effects:

[0051] The turn-off time generation circuit according to the embodiments of the present application generates a first comparison voltage proportional to the output voltage through a positive-phase input voltage generation module. The inverting input voltage generation module generates a second comparison voltage proportional to the input voltage by discharging the load capacitor. The comparator module outputs a turn-off time pulse signal that is adaptively adjusted according to the comparison results of the first comparison voltage and the second comparison voltage, so that the switching period and switching frequency of the overall system are kept relatively stable. The turn-off time generation circuit according to the embodiments of the present application has the advantages of simpler circuit structure, reliable performance, and low design and development costs, and thus can simplify the design complexity and cost of the DC-DC converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0053] Figure 1 The schematic diagram of the turn-off time generation circuit provided according to some embodiments is shown;

[0054] Figure 2 The schematic diagram of the voltage relationship between the voltage at the SW terminal and the output voltage Vout provided according to some embodiments is shown;

[0055] Figure 3 The schematic diagram of the voltage relationship between the voltage at the SW terminal and the equivalent voltage Vox of the output voltage provided according to some embodiments is shown;

[0056] Figure 4 The timing diagram of the turn-off time signal Toff_over provided according to some embodiments is shown;

[0057] Figure 5 The schematic diagram of the turn-off time generation circuit provided according to an embodiment of the present application is shown;

[0058] Figure 6 The schematic diagram of the turn-off time generation circuit provided according to another embodiment of the present application is shown;

[0059] Figure 7 The structural diagram of the turn-off time generation circuit provided according to an embodiment of the present application is shown;

[0060] Figure 8 The structural diagram of the turn-off time generation circuit provided according to another embodiment of the present application is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0061] To enable those skilled in the art to better understand the solution of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application.

[0062] It should be noted that the terms "first", "second", etc. in the specification, claims and above-mentioned drawings of this application are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of this application described here can be implemented in an order different from those illustrated or described here. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, device, product or equipment including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or equipment.

[0063] The turn-off time generation circuit provided in the embodiments of this application can be but is not limited to being applied to the Buck power supply system of the COF architecture in a DC-DC converter. In the existing COF mode, when the input voltage Vin or the output voltage Vout changes, the switching frequency of the system will change, and generally it is desired that the switching frequency of the overall system is fixed. Therefore, it is necessary to design a circuit that can change the Toff time in proportion according to the ratio of Vin and Vout, so as to maintain the relative stability of the switching frequency. That is, Toff = k * (Vin - Vout) / Vin, where k is a proportionality coefficient.

[0064] It should be noted that the above application to the DC-DC converter is only an example, and the turn-off time generation circuit provided in the embodiments of this application can also be applied to other scenarios, and the embodiments of this application do not limit this.

[0065] Refer to the accompanying Figure 1 drawings, which show the schematic diagram of a turn-off time generation circuit provided according to some embodiments. As Figure 1 shown, the turn-off time generation circuit mainly consists of five parts: Vin voltage division circuit, SW voltage division and filtering circuit, Vn generation circuit, Vp generation circuit and comparator circuit.

[0066] Regarding Figure 1The Vin voltage dividing circuit therein. Specifically, the Vin voltage dividing circuit includes a voltage dividing resistor R4 and a voltage dividing resistor R5 connected in series with each other, and an operational amplifier. One end of R4 that is not connected to R5 is connected to the input voltage Vin, and one end of R5 that is not connected to R4 is grounded (connected to the ground wire GND); the non-inverting input terminal of the operational amplifier is connected to the common terminal of R4 and R5, the inverting input terminal of the operational amplifier is connected to the first end of the load resistor Rx in the Vp generation circuit, and the output terminal of the operational amplifier is connected to the gate of the N-channel (N-Channel) metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOS) (abbreviated as NMOS transistor) Q4 in the Vp generation circuit. The Vin voltage dividing circuit is mainly used to divide the voltage of Vin to generate a voltage of Vix = Vin * K1, where K1 = R5 / (R4 + R5). The purpose of generating the Vix voltage is to generate a current Iix = Vix / Rx that is proportional to Vin.

[0067] Regarding Figure 1 The Vp generation circuit therein. Specifically, the Vp generation circuit includes a load resistor Rx, an NMOS transistor Q4, a P-channel (P-Channel) metal-oxide-semiconductor field-effect transistor (abbreviated as PMOS transistor) Q5, a PMOS transistor Q6, a PMOS transistor Q11, an NMOS transistor Q12, and a load capacitor Cx. The first end of the load resistor Rx is also connected to the source of the NMOS transistor Q4, and the second end of the load resistor Rx is grounded; the drain of the NMOS transistor Q4 is respectively connected to the drain and gate of the PMOS transistor Q5, the gate of the PMOS transistor Q6, and the gate of the PMOS transistor Q11. Then, a current Iix = Vix / Rx that is proportional to Vin can be generated in the load resistor Rx in the Vp generation circuit.

[0068] The gate of the PMOS transistor Q5 is also respectively connected to the gate of the PMOS transistor Q6 and the gate of the PMOS transistor Q11, the drain of the PMOS transistor Q5 is also connected to the gate of the PMOS transistor Q6 and the gate of the PMOS transistor Q11, and the source of the PMOS transistor Q5 is respectively connected to the source of the PMOS transistor Q6 and the source of the PMOS transistor Q11; the drain of the PMOS transistor Q6 is connected to the load resistor R6 in the Vn generation circuit, so as to introduce the generated current Iix into the Vn generation circuit to generate a voltage related to Vin - Vout.

[0069] The drain of PMOS transistor Q11 is connected to the drain and gate of NMOS transistor Q12, and the upper plate of load capacitor Cx. The source of NMOS transistor Q12 is connected to GND through a switching transistor. The upper plate of load capacitor Cx is also connected to the positive input terminal of the comparator circuit, and the lower plate of load capacitor Cx is grounded. That is to say, when an input voltage Vin is applied, the Iix current passes through the Vp generation circuit, and the load capacitor Cx can be charged, thereby generating a voltage Vp = Vgs + Iix*t / Cx = Vgs + K1*Vin*t / (Rx*Cx), where Vgs is the initial voltage.

[0070] In Figure 1 the illustrated embodiment, in order to generate a voltage value Vn related to Vin - Vout, it is necessary to first generate an equivalent voltage Vox of Vout. Figure 1 The purpose of the SW voltage division and filtering circuit in the illustrated embodiment is to generate an equivalent voltage Vox of Vout = Vout*K2, where K2 = R2 / (R1 + R2).

[0071] In practical applications, for the entire Buck power supply system, when it is operating normally, the relationship between the voltage at the SW terminal and the output voltage Vout is as Figure 2 shown. From Figure 2 it can be seen that after the voltage VSW at the SW terminal passes through the LC filter circuit, Vout can be obtained, and the average voltage Vout_avg of Vout = Vin*Ton / (Ton + Toff) = Vin*D, where Ton represents the conduction time and Toff represents the turn-off time.

[0072] When the integrated circuit (IC) does not have a Vout pin, an equivalent voltage Vox close to Vout can be generated through an RC filter circuit. Specifically, the relationship between the voltage at the SW terminal and Vox is as Figure 3 shown. From Figure 3 it can be seen that after the voltage VSW at the SW terminal passes through the RC filter circuit, the equivalent voltage Vox of Vout can be obtained, and the average voltage Vox_avg of Vox = Vin*Ton / (Ton + Toff) = Vin*D.

[0073] It can be seen that both the LC filter circuit and the RC filter circuit can obtain the average voltage of the voltage at the SW terminal. Therefore, through the RC filter circuit, the equivalent value Vox of Vout can be obtained. If the voltage at the SW terminal is applied to the RC filter circuit after passing through a voltage division resistor, then Vox can be equivalent to the voltage division of the same ratio of Vout.

[0074] Regarding Figure 1The SW voltage division and filtering circuit therein. Specifically, the SW voltage division and filtering circuit includes a voltage division resistor R1 and a voltage division resistor R2 connected in series with each other, as well as a filtering resistor R3 and a filtering capacitor C1. One end of R1 that is not connected to R2 is connected to the SW terminal, and one end of R2 that is not connected to R1 is grounded; the first end of the filtering resistor R3 is connected to the common terminal of R1 and R2, and the other end is connected to the non-inverting input terminal of the operational amplifier in the Vn generation circuit; the upper plate of the filtering capacitor C1 is connected to the non-inverting input terminal of the operational amplifier in the Vn generation circuit, and the lower plate is grounded.

[0075] Since the IC itself often does not have a Vout pin, but the IC needs to generate a Toff time related to Vout, the Vout voltage can be equivalently generated through the SW filtering circuit. If the voltage at the SW terminal is divided and then passes through the filtering circuit, it can be equivalent to a proportional voltage division of Vout, and finally a voltage of Vox = Vout * K2 = Vout * R2 / (R1 + R2) is obtained.

[0076] Regarding Figure 1 The Vn generation circuit therein. Specifically, the Vn generation circuit includes an operational amplifier, a load resistor Rx, an NMOS transistor Q1, a PMOS transistor Q2, a PMOS transistor Q3, an NMOS transistor Q7, a load resistor R6, an NMOS transistor Q8, an NMOS transistor Q9, and a PMOS transistor Q10. The inverting input terminal of the operational amplifier is connected to the first end of the load resistor Rx, and the output terminal is connected to the gate of the NMOS transistor Q1; the first end of the load resistor Rx is also connected to the source of the NMOS transistor Q1, and the second end of the load resistor Rx is grounded; the drain of the NMOS transistor Q1 is respectively connected to the drain and gate of the PMOS transistor Q2, the gate of the PMOS transistor Q3, and the gate of the PMOS transistor Q10.

[0077] The gate of PMOS transistor Q2 is also connected to the gates of PMOS transistor Q3 and PMOS transistor Q10 respectively. The drain of PMOS transistor Q2 is also connected to the gates of PMOS transistor Q3 and PMOS transistor Q10. The source of PMOS transistor Q2 is connected to the sources of PMOS transistor Q3 and PMOS transistor Q10 respectively. The drain of PMOS transistor Q3 is connected to the drain of NMOS transistor Q7. The drain of NMOS transistor Q7 is also connected to the first end of load resistor R6. The gate of NMOS transistor Q7 is also connected to the first end of load resistor R6. The source of NMOS transistor Q7 is grounded. The drain of PMOS transistor Q10 is connected to the gates, the gate and the drain of NMOS transistors Q8 and Q9 respectively. The sources of NMOS transistors Q8 and Q9 are both grounded. The drain of NMOS transistor Q8 is connected to the second end of load resistor R6. The second end of load resistor R6 is connected to the drain of PMOS transistor Q6 in the Vp generation circuit, and the second end of load resistor R6 is also connected to the inverting input terminal of the comparator circuit.

[0078] The purpose of the Vn generation circuit is to generate a voltage related to Vin - Vout. Since the Vox voltage proportional to Vout has been generated based on the SW voltage division and filtering circuit, a current Iox = Vox / Rx proportional to Vout can be generated in the load resistor Rx in the Vn generation circuit, and then subtracted from Iix to obtain the current difference Iix - Iox = Vix / Rx - Vox / Rx. That is to say, when the input voltage Vin is applied, the Iix current and the Iox current pass through the Vn generation circuit, and a voltage Vn = Vgs + R6*(Iix - Iox) = Vgs + R6*(Vix / Rx - Vox / Rx) = Vgs + R6*(K1*Vin - K2*Vout) / Rx can be generated, where Vgs is the initial voltage.

[0079] In practical applications, the resistance values of R1, R2, R4, and R5 can be selected such that K1 = K2 = K. Therefore, Vn = Vgs + R6*K*(Vin - Vout) / Rx can be obtained. Similarly, Vp = Vgs + K*Vin*t / (Rx*Cx) can be obtained.

[0080] Regarding Figure 1 the comparator circuit in, specifically, the comparator circuit includes a comparator, a first inverter, and a second inverter. The comparator is used to receive the Vp and Vn voltages and compare Vp and Vn. When Vp > Vn, the turn-off time signal flips to H, and the turn-off time ends. As Figure 4 shown, Figure 4The timing diagram of the turn-off time signal Toff_over provided according to some embodiments is shown. It can be seen that when Vp > Vn, Toff_over changes from low to high. Therefore, when Vp = Vn:

[0081] Vgs + K*Vin*t / (Rx*Cx) = Vgs + R6*K*(Vin - Vout) / Rx

[0082] Further derivation gives:

[0083] Toff = R6*Cx(Vin - Vout) / Vin = R6*Cx(1 - D)

[0084] where D = Vout / Vin, and then the switching period T = Toff / (1 - D) = R6*Cx. It can be seen that the switching period T is only related to R6 and Cx, and has nothing to do with Vin and Vout. Therefore, the switching frequency Fsw = 1 / T also has nothing to do with Vin and Vout and can remain basically stable.

[0085] Since Figure 1 the purpose of the Vn generation circuit in the turn-off time generation circuit is to generate a voltage related to Vin - Vout. Therefore, there is a process of subtracting the Vout-related current Iox from the Vin-related current Iix. Such an idea inevitably requires generating Iox, which leads to a relatively complex circuit structure, especially the Vn generation circuit, with a high development cost, and may also cause certain safety risks in the system due to the complex circuit structure.

[0086] To solve the above problems, the embodiments of the present application provide a turn-off time generation circuit that does not need to generate the Vout-related current Iox, avoids using the Vn generation circuit, makes the circuit simpler and more efficient, and reduces the safety risk of the overall system to a certain extent.

[0087] Referring to the attached Figure 5 to the specification, it shows the schematic diagram of a turn-off time generation circuit provided by the embodiments of the present application. This turn-off time generation circuit can be applied to a DC-DC converter, such as Figure 5As shown, the turn-off time generation circuit may include a non-inverting input voltage generation module 510, an inverting input voltage generation module 520, and a comparator module 530. The input end of the non-inverting input voltage generation module 510 receives the SW terminal voltage VSW from the DC-DC converter, and the output end of the non-inverting input voltage generation module 510 is connected to the non-inverting input terminal of the comparator module 530; the non-inverting input voltage generation module 510 can be used to generate a first comparison voltage Vp proportional to the output voltage Vout of the DC-DC converter. The input end of the inverting input voltage generation module 520 receives the input voltage Vin from the DC-DC converter, and the output end of the inverting input voltage generation module 520 is connected to the inverting input terminal of the comparator module 530; the inverting input voltage generation module 520 can be used to generate a second comparison voltage Vn proportional to the input voltage Vin by discharging the load capacitor.

[0088] The non-inverting input terminal of the comparator module 530 receives the first comparison voltage Vp output by the non-inverting input voltage generation module 510, and the inverting input terminal receives the second comparison voltage Vn output by the inverting input voltage generation module 520; the comparator module 530 can be used to output the output signal Toff of the turn-off time generation circuit through the output terminal based on the comparison result of the first comparison voltage Vp and the second comparison voltage Vn.

[0089] According to the turn-off time generation circuit of the embodiment of the present application, the non-inverting input voltage generation module generates a first comparison voltage proportional to the output voltage, the inverting input voltage generation module generates a second comparison voltage proportional to the input voltage by discharging the load capacitor, and the comparator module outputs a turn-off time pulse signal that is adaptively adjusted according to the comparison result of the first comparison voltage and the second comparison voltage, so that the switching period and switching frequency of the overall system are kept relatively stable. The turn-off time generation circuit of the embodiment of the present application has the advantages of simpler circuit structure, reliable performance, and low design and development cost, etc., and thus can simplify the design complexity and cost of the DC-DC converter, and reduce the safety risk of the overall system to a certain extent.

[0090] In an embodiment of the present application, referring to the attached drawings of the specification Figure 6 , the non-inverting input voltage generation module 510 may include a first comparison voltage generation module 512. The input end of the first comparison voltage generation module 512 receives the SW terminal voltage VSW, and the output end of the first comparison voltage generation module 512 is connected to the non-inverting input terminal of the comparator module 530.

[0091] During operation, the voltage VSW at the SW terminal of the DC-DC converter is input to the first comparison voltage generation module 512. The first comparison voltage generation module 512 can filter the received voltage VSW at the SW terminal through an RC filter circuit to generate a first comparison voltage Vp proportional to the output voltage Vout of the DC-DC converter, and output it to the comparator module 530.

[0092] In another embodiment of the present application, as Figure 6 shown by the dashed line in, the positive-phase input voltage generation module 510 may further include a voltage division module 511 for the voltage at the SW terminal. The input terminal of the voltage division module 511 for the voltage at the SW terminal receives the voltage VSW at the SW terminal, and the output terminal of the voltage division module 511 for the voltage at the SW terminal is connected to the input terminal of the first comparison voltage generation module 512. The voltage division module 511 for the voltage at the SW terminal can be used to divide the voltage VSW at the SW terminal to obtain a first divided voltage and output it to the first comparison voltage generation module 512.

[0093] In this embodiment, the input terminal of the first comparison voltage generation module 512 can receive the first divided voltage output by the voltage division module 511 for the voltage at the SW terminal, and the output terminal of the first comparison voltage generation module 512 is connected to the positive-phase input terminal of the comparator module 530.

[0094] During operation, the voltage VSW at the SW terminal of the DC-DC converter is input to the voltage division module 511 for the voltage at the SW terminal. The voltage division module 511 for the voltage at the SW terminal divides the voltage VSW at the SW terminal to obtain a first divided voltage and output it to the first comparison voltage generation module 512. The first comparison voltage generation module 512 can filter the received first divided voltage through an RC filter circuit to generate a first comparison voltage Vp proportional to the output voltage Vout of the DC-DC converter, and output it to the comparator module 530.

[0095] It can be understood that in the embodiment of the present application, by filtering the received voltage at the SW terminal through an RC filter circuit, or filtering the divided voltage obtained by dividing the voltage at the SW terminal, a voltage proportional to the output voltage of the DC-DC converter can be generated. The circuit structure is simple, the performance is reliable, and the design and development cost is low.

[0096] As Figure 6As shown, the inverting input voltage generation module 520 may include an input voltage divider module 521 and a second comparison voltage generation module 522. The input terminal of the input voltage divider module 521 receives the input voltage Vin. The input voltage divider module 521 may be configured to divide the input voltage Vin to obtain a second divided voltage and output it to the second comparison voltage generation module 522. The input terminal of the second comparison voltage generation module 522 receives the second divided voltage output by the input voltage divider module 521, and the output terminal of the second comparison voltage generation module 522 is connected to the inverting input terminal of the comparator module 530.

[0097] During operation, the input voltage Vin of the DC-DC converter is input to the input voltage divider module 521. The input voltage divider module 521 divides the input voltage Vin to obtain a first divided voltage and outputs it to the second comparison voltage generation module 522. The second comparison voltage generation module 522 may discharge the load capacitor in the second comparison voltage generation module 522 using a current proportional to the second divided voltage to generate a second comparison voltage Vn proportional to the input voltage Vin and output it to the comparator module 530. Among them, the second comparison voltage Vn has an inverse correlation with the discharge time of the load capacitor.

[0098] It can be understood that in the embodiment of the present application, by discharging the load capacitor, a voltage proportional to the input voltage is generated. Then, by subtracting this voltage from the voltage proportional to the output voltage, a voltage proportional to the Vin-Vout voltage can be directly generated, eliminating the need to separately design a Vin-Vout circuit and greatly simplifying the circuit structure.

[0099] As Figure 6 shown, after receiving the first comparison voltage Vp and the second comparison voltage Vn, the comparator module 530 may compare the first comparison voltage Vp and the second comparison voltage Vn, and based on the comparison result, output the output signal Toff of the off-time generation circuit from the output terminal.

[0100] In a specific embodiment of the present application, referring to the attached Figure 7 drawing of the specification, the non-inverting input voltage generation module 510 may include a first comparison voltage generation module 512. The first comparison voltage generation module 512 may include a filter resistor R3 and a filter capacitor C1. The first end of the filter resistor R3 may be connected to the SW terminal voltage VSW of the DC-DC converter through a load resistor R1, and the second end of the filter resistor R3 is connected to the upper plate of the filter capacitor C1. The upper plate of the filter capacitor C1 is also connected to the non-inverting input terminal of the comparator module 530, and the lower plate of the filter capacitor C1 is grounded.

[0101] During operation, the voltage VSW at the SW terminal of the DC-DC converter can generate a first comparison voltage Vp = Vout equivalent to the output voltage Vout of the DC-DC converter through the RC filter circuit in the first comparison voltage generation module 512, and output it to the comparator module 530.

[0102] It can be understood that in the embodiment of the present application, by filtering the received voltage at the SW terminal through the RC filter circuit, a voltage equivalent to the output voltage of the DC-DC converter can be generated, and the circuit structure is simple.

[0103] As Figure 7 shown, the inverting input voltage generation module 520 may include an input voltage voltage division module 521 and a second comparison voltage generation module 522. The input voltage voltage division module 521 includes a third voltage division resistor R4 and a fourth voltage division resistor R5 connected in series. One end of the third voltage division resistor R4 that is not connected to the fourth voltage division resistor R5 is connected to the input voltage Vin, and one end of the fourth voltage division resistor R5 that is not connected to the third voltage division resistor R4 is grounded. The input end of the second comparison voltage generation module 522 is connected to the common end of the third voltage division resistor R4 and the fourth voltage division resistor R5.

[0104] During operation, the third voltage division resistor R4 and the fourth voltage division resistor R5 can divide the input voltage Vin to generate a voltage of Vix = K1 * Vin, where K1 = R5 / (R4 + R5), and output it to the second comparison voltage generation module 522. The purpose of generating the Vix voltage is to generate a current Iix = Vix / Rx proportional to the input voltage Vin.

[0105] As Figure 7 shown, the second comparison voltage generation module 522 includes an operational amplifier, a load resistor Rx, a first NMOS transistor Q1, a first PMOS transistor Q2, a second PMOS transistor Q3, a second NMOS transistor Q4, a third NMOS transistor Q5, and a load capacitor Cx.

[0106] Among them, the non-inverting input terminal of the operational amplifier is connected to the common end of the third voltage division resistor R4 and the fourth voltage division resistor R5 in the input voltage voltage division module 521. The inverting input terminal of the operational amplifier is connected to the first end of the load resistor Rx, and the output terminal of the operational amplifier is connected to the gate of the first NMOS transistor Q1. The first end of the load resistor Rx is also connected to the source of the first NMOS transistor Q1, and the second end of the load resistor Rx is grounded. Then during operation, a current Iix = Vix / Rx proportional to the input voltage Vin can be generated in the load resistor Rx of the second comparison voltage generation module 522.

[0107] Among them, the drain of the first NMOS transistor Q1 is respectively connected to the drain and gate of the first PMOS transistor Q2, and the gate of the second PMOS transistor Q3. The gate of the first PMOS transistor Q2 is also connected to the gate of the second PMOS transistor Q3, the drain of the first PMOS transistor Q2 is also connected to the gate of the second PMOS transistor Q3, and the source of the first PMOS transistor Q2 is connected to the input voltage Vin; the drain of the second PMOS transistor Q3 is respectively connected to the drain and gate of the second NMOS transistor Q4, and the gate of the third NMOS transistor Q5, and the source of the second PMOS transistor Q3 is connected to the input voltage Vin.

[0108] Among them, the gate of the second NMOS transistor Q4 is also connected to the gate of the third NMOS transistor Q5, and the source of the second NMOS transistor Q4 is grounded; the source of the third NMOS transistor Q5 is grounded, and the drain of the third NMOS transistor Q5 is connected to the lower plate of the load capacitor Cx; the lower plate of the load capacitor Cx is also connected to the inverting input terminal of the comparator module 530, and the upper plate of the load capacitor Cx is connected to the input voltage Vin.

[0109] In practical applications, reverse thinking can be adopted. Changing the charging of the load capacitor Cx to discharging the load capacitor Cx, grounding the load capacitor Cx to connecting it to the power supply, raising the initial state of Vn to the input voltage Vin, and discharging the load capacitor Cx with a current Iix proportional to the input voltage can generate a second comparison voltage Vn that is proportional to the input voltage Vin and has an inverse correlation with the discharge time of the load capacitor Cx.

[0110] During operation, the initial state of Vn can be raised to the input voltage Vin, and the load capacitor Cx can be discharged with a current Iix proportional to the input voltage Vin, thereby generating a second comparison voltage Vn = Vin - K1 * Vin * t / (Rx * Cx) that is proportional to the input voltage Vin and has an inverse correlation with the discharge time of the load capacitor Cx, and output it to the comparator module 530.

[0111] It should be noted that the resistance values of the voltage dividing resistors R4 and R5 in the embodiments of the present application can be selected according to actual situations, and the embodiments of the present application do not limit this.

[0112] It can be understood that the second comparison voltage generating module of the embodiment of the present application can generate the difference voltage Vin-K1*Vin*t / (Rx*Cx) between the input voltage and the discharge voltage as the second comparison voltage by discharging the load capacitor. The Vin-Vout voltage can be directly generated by subtracting the initial voltage Vin in the second comparison voltage from the first comparison voltage generated by the first comparison voltage generating module and equivalent to the output voltage Vout. There is no need to design a separate Vin-Vout circuit, which greatly simplifies the circuit structure.

[0113] like Figure 7 As shown, the comparator module 530 includes a comparator, a second inverter and a third inverter. The non-inverting input terminal of the comparator is connected to the output terminal of the non-inverting input voltage generating module 510, that is, connected to the upper plate of the filter capacitor C1 in the first comparison voltage generating module 512; the inverting input terminal of the comparator is connected to the output terminal of the inverting input voltage generating module 520, that is, connected to the lower plate of the load capacitor Cx in the second comparison voltage generating module 522; the output terminal of the comparator is connected to the input terminal of the second inverter. The output terminal of the second inverter is connected to the input terminal of the third inverter, and the output terminal of the third inverter is used to output the output signal of the off time generating circuit.

[0114] Among them, when the first comparison voltage Vp=Vout is greater than the preset threshold, the comparator can be a rail-to-rail comparator; when the first comparison voltage Vp=Vout is less than or equal to the preset threshold, the comparator can be other types of comparators. The preset threshold can be set according to actual conditions, and the embodiments of the present application are not limited to this. In other words, the comparator is preferably a rail-to-rail comparator.

[0115] In operation, the comparator can be used to receive the first comparison voltage Vp output by the first comparison voltage generating module 512 and the second comparison voltage Vn output by the second comparison voltage generating module 522, compare the first comparison voltage Vp and the second comparison voltage Vn, and generate an output signal of the off-time generating circuit based on the comparison result. The input end of the second inverter receives the output signal of the off-time generating circuit, and the output signal is output from the output end of the third inverter after passing through the second inverter and the third inverter.

[0116] Specifically, when the comparator determines that Vp>Vn, the off-time signal turns H and the off-time ends. Therefore, it can be obtained that when Vp=Vn:

[0117] Vout=Vin-K1*Vin*t / (Rx*Cx)

[0118] Further deduction yields:

[0119] Toff = Rx * Cx * (Vin - Vout) / (K1 * Vin) = Rx * Cx * (1 - D) / K1

[0120] Where D = Vout / Vin, and then the switching period T = Toff / (1 - D) = Rx * Cx / K1 can be obtained. It can be seen that the switching period T is only related to Rx, Cx, and K1, and has nothing to do with Vin and Vout. Therefore, the switching frequency Fsw = 1 / T = K1 / Rx * Cx is also only related to Rx, Cx, and K1, and has nothing to do with Vin and Vout, which can ensure the stability of the switching frequency.

[0121] It can be understood that the embodiment of the present application can implement a turn-off time pulse signal Toff = k * (Vin - Vout) / Vin related to the ratio (Vin - Vout) / Vin of Vin and Vout. This pulse signal can change the turn-off time Toff in proportion according to the ratio of Vin and Vout, so as to maintain the relative stability of the switching frequency.

[0122] Since in Figure 7 the shown embodiment, when the first comparison voltage Vp = Vout is relatively large, even close to the input voltage Vin, a rail-to-rail comparator needs to be used in the comparator module 530. Therefore, in order to improve the versatility, it can be further improved to obtain the turn-off time generation circuit as shown in Figure 8 . In this turn-off time generation circuit, a rail-to-rail comparator is not required, and the following is a detailed description.

[0123] In another specific embodiment of the present application, referring to the attached Figure 8 to the specification, the positive-phase input voltage generation module 510 may include a SW terminal voltage voltage division module 511 and a first comparison voltage generation module 512. The SW terminal voltage voltage division module 511 may include a first voltage division resistor R1 and a second voltage division resistor R2 connected in series; the first comparison voltage generation module 512 may include a filter resistor R3 and a filter capacitor C1.

[0124] Among them, one end of the first voltage division resistor R1 that is not connected to the second voltage division resistor R2 is connected to the SW terminal voltage VSW, and one end of the second voltage division resistor R2 that is not connected to the first voltage division resistor R1 is grounded. The first end of the filter resistor R3 is connected to the output terminal of the SW terminal voltage voltage division module 511, that is, connected to the common terminal of the first voltage division resistor R1 and the second voltage division resistor R2; the second end of the filter resistor R3 is connected to the upper plate of the filter capacitor C1; the upper plate of the filter capacitor C1 is also connected to the positive-phase input terminal of the comparator module 530, and the lower plate of the filter capacitor C1 is grounded.

[0125] During operation, the first voltage dividing resistor R1 and the second voltage dividing resistor R2 in the SW terminal voltage dividing module 511 can divide the SW terminal voltage VSW, generate a first divided voltage, and output it to the first comparison voltage generating module 512. The first divided voltage generated by the SW terminal voltage dividing module 511 can generate a first comparison voltage Vp = K2 * Vout proportional to the output voltage Vout of the DC-DC converter through the RC filter circuit in the first comparison voltage generating module 512, where K2 = R2 / (R1 + R2), and output it to the comparator module 530.

[0126] It can be understood that in the embodiment of the present application, the voltage obtained by dividing the SW terminal voltage is filtered through the RC filter circuit, and a voltage proportional to the output voltage of the DC-DC converter can be generated, and the circuit structure is simple.

[0127] As Figure 8 shown, the inverting input voltage generating module 520 may include an input voltage dividing module 521 and a second comparison voltage generating module 522. The input voltage dividing module 521 includes a third voltage dividing resistor R4 and a fourth voltage dividing resistor R5 connected in series; one end of the third voltage dividing resistor R4 not connected to the fourth voltage dividing resistor R5 is connected to the input voltage Vin, and one end of the fourth voltage dividing resistor R5 not connected to the third voltage dividing resistor R4 is grounded; the input end of the second comparison voltage generating module 522 is connected to the common end of the third voltage dividing resistor R4 and the fourth voltage dividing resistor R5.

[0128] During operation, the third voltage dividing resistor R4 and the fourth voltage dividing resistor R5 can divide the input voltage Vin, generate a voltage of Vix = K1 * Vin, K1 = R5 / (R4 + R5), and output it to the second comparison voltage generating module 522. The purpose of generating the Vix voltage is to generate a current Iix = Vix / Rx proportional to Vin.

[0129] As Figure 8 shown, the second comparison voltage generating module 522 includes an operational amplifier, a load resistor Rx, a first NMOS transistor Q1, a first PMOS transistor Q2, a second PMOS transistor Q3, a second NMOS transistor Q4, a third NMOS transistor Q5, a fourth NMOS transistor Q6, and a load capacitor Cx.

[0130] Among them, the non-inverting input terminal of the operational amplifier is connected to the common terminal of the third voltage-dividing resistor R4 and the fourth voltage-dividing resistor R5 in the input voltage voltage-dividing module 521. The inverting input terminal of the operational amplifier is connected to the first end of the load resistor Rx. The output terminal of the operational amplifier is respectively connected to the gate of the first NMOS transistor Q1 and the gate of the fourth NMOS transistor Q6. The first end of the load resistor Rx is also connected to the source of the first NMOS transistor Q1, and the second end of the load resistor Rx is grounded. Then, during operation, a current Iix = Vix / Rx proportional to the input voltage Vin can be generated in the load resistor Rx in the second comparison voltage generation module 522.

[0131] Among them, the drain of the first NMOS transistor Q1 is respectively connected to the drain and gate of the first PMOS transistor Q2, and the gate of the second PMOS transistor Q3. The gate of the first PMOS transistor Q2 is also connected to the gate of the second PMOS transistor Q3. The drain of the first PMOS transistor Q2 is also connected to the gate of the second PMOS transistor Q3. The source of the first PMOS transistor Q2 is respectively connected to the source of the second PMOS transistor Q3 and the drain of the fourth NMOS transistor Q6. The drain of the second PMOS transistor Q3 is respectively connected to the drain and gate of the second NMOS transistor Q4, and the gate of the third NMOS transistor Q5.

[0132] Among them, the gate of the second NMOS transistor Q4 is also connected to the gate of the third NMOS transistor Q5, and the source of the second NMOS transistor Q4 is grounded; the source of the third NMOS transistor Q5 is grounded, and the drain of the third NMOS transistor Q5 is connected to the lower plate of the load capacitor Cx; the source of the fourth NMOS transistor Q6 is connected to the upper plate of the load capacitor Cx, and the lower plate of the load capacitor Cx is also connected to the inverting input terminal of the comparator module 530.

[0133] In practical applications, in order to avoid using a rail-to-rail comparator, an NMOS transistor Q6 can be added. Its gate is connected to the output terminal of the operational amplifier, its drain is connected to the source of the first PMOS transistor Q2, and its source is connected to the upper plate of the load capacitor Cx. When the input voltage Vin is applied, a low dropout (LDO) voltage Vldo = K1*Vin can be generated, where K1 = R5 / (R4 + R5). In this way, the load capacitor Cx is not connected to the input voltage Vin but to Vldo.

[0134] During operation, the initial state of Vn is raised to the input voltage Vin, so the initial voltage of the load capacitor Cx is Vldo. The load capacitor Cx is discharged using a current Iix that is proportional to the input voltage Vin, thereby generating a second comparison voltage Vn = K1*Vin - K1*Vin*t / (Rx*Cx) that is proportional to the input voltage Vin and has an inverse correlation with the discharge time of the load capacitor Cx, and outputting it to the comparator module 530.

[0135] It should be noted that the resistance values of the voltage-dividing resistors R1, R2, R4, and R5 in the embodiments of the present application can be selected according to actual situations. Only the resistance values of R1, R2, R4, and R5 need to be selected such that K1 = K2 = K, and the embodiments of the present application do not limit this. Therefore, Vp = K*Vout can be obtained, and similarly, Vn = K*Vin - K*Vin*t / (Rx*Cx) can be obtained.

[0136] It can be understood that in the second comparison voltage generation module of the embodiments of the present application, by adding an NMOS transistor Q6, an LDO voltage Vldo = K*Vin can be generated. At the same time, by discharging the load capacitor, a differential voltage Vldo - K*Vin*t / (Rx*Cx) between the LDO voltage and the discharge voltage can be generated as the second comparison voltage. By subtracting the LDO voltage Vldo in the second comparison voltage from the first comparison voltage Vp = K*Vout generated by the first comparison voltage generation module and proportional to the output voltage Vout, a voltage proportional to Vin - Vout can be directly generated, eliminating the need to separately design a Vin - Vout circuit and greatly simplifying the circuit structure.

[0137] It should be noted that the above-described embodiment of generating the LDO voltage by adding an NMOS transistor Q6 is only an example. In practical applications, the method of generating the LDO voltage can include but is not limited to the above embodiment, that is, other methods can also be used to generate the LDO voltage. For example, by designing an LDO voltage generation circuit to generate an LDO voltage of Vldo = K1*Vin. The embodiments of the present application do not make specific limitations here and can be determined according to specific situations, all within the protection scope of the present application.

[0138] It should be noted that the specific structure of the comparator module 530 in the embodiments of the present application can refer to Figure 7 the embodiment shown. The embodiments of the present application will not be elaborated here. Among them, the comparator in the comparator module 530 can be various types of comparators, including but not limited to rail-to-rail comparators, and the embodiments of the present application do not make specific limitations on this.

[0139] Specifically, when the comparator determines that Vp > Vn, the turn-off time signal flips to H, and the turn-off time ends. Therefore, when Vp = Vn:

[0140] K * Vout = K * Vin - K * Vin * t / (Rx * Cx)

[0141] Further derivation gives:

[0142] Toff = Rx * Cx * (Vin - Vout) / Vin = Rx * Cx * (1 - D)

[0143] Where D = Vout / Vin, and then the switching period T = Toff / (1 - D) = Rx * Cx. It can be seen that the switching period T is only related to Rx and Cx, and has nothing to do with Vin and Vout. Therefore, the switching frequency Fsw = 1 / T = 1 / Rx * Cx is also only related to Rx and Cx, and has nothing to do with Vin and Vout, which can ensure the stability of the switching frequency.

[0144] It can be understood that the embodiment of the present application can implement a turn-off time pulse signal Toff = k * (Vin - Vout) / Vin related to the ratio (Vin - Vout) / Vin of Vin and Vout. This pulse signal can change the turn-off time Toff proportionally according to the ratio of Vin and Vout, so as to maintain the relative stability of the switching frequency.

[0145] An embodiment of the present application further provides a chip, which can be applied to a DC-DC converter. The chip can include the turn-off time generation circuit provided by any one of the embodiments as Figures 5 to 8 shown.

[0146] It should be noted that the various embodiments in this specification are described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the methods disclosed in the embodiments, since they correspond to the systems disclosed in the embodiments, the description is relatively simple, and the relevant points can be referred to the description of the system part.

[0147] It should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising said element.

[0148] The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A turn-off time generation circuit, applied to a DC-DC converter, characterized in that, The turn-off time generating circuit includes a non-inverting input voltage generating module, an inverting input voltage generating module, and a comparator module; The input end of the non-inverting input voltage generating module receives the voltage of the SW terminal from the DC-DC converter; the non-inverting input voltage generating module is used to generate a first comparison voltage proportional to the output voltage of the DC-DC converter; The input end of the inverting input voltage generating module receives the input voltage from the DC-DC converter; the inverting input voltage generating module is used to generate a second comparison voltage proportional to the input voltage by discharging the load capacitor; The comparator module is used to receive the first comparison voltage and the second comparison voltage, and output the output signal of the turn-off time generating circuit based on the result of comparing the first comparison voltage and the second comparison voltage; Among them, the non-inverting input voltage generating module includes a SW terminal voltage dividing module and a first comparison voltage generating module; The input end of the SW terminal voltage dividing module receives the SW terminal voltage, and the SW terminal voltage dividing module is used to divide the SW terminal voltage to obtain a first divided voltage and output it; The input end of the first comparison voltage generating module receives the SW terminal voltage, or receives the first divided voltage output by the SW terminal voltage dividing module in the non-inverting input voltage generating module; the first comparison voltage generating module is used to filter the SW terminal voltage or the first divided voltage through an RC filter circuit to generate a first comparison voltage proportional to the output voltage of the DC-DC converter; The inverting input voltage generating module includes an input voltage dividing module and a second comparison voltage generating module; The input end of the input voltage dividing module receives the input voltage, and the input voltage dividing module is used to divide the input voltage to obtain a second divided voltage and output it to the second comparison voltage generating module; The input end of the second comparison voltage generating module receives the second divided voltage, and the second comparison voltage generating module is used to discharge the load capacitor in the second comparison voltage generating module with a current proportional to the second divided voltage to generate a second comparison voltage proportional to the input voltage; Among them, the second comparison voltage has an inverse correlation with the discharge time of the load capacitor.

2. The turn-off time generation circuit according to claim 1, characterized in that, The SW terminal voltage dividing module includes a first dividing resistor and a second dividing resistor connected in series; One end of the first dividing resistor that is not connected to the second dividing resistor is connected to the SW terminal voltage, and one end of the second dividing resistor that is not connected to the first dividing resistor is grounded.

3. The turn-off time generation circuit according to claim 1, characterized in that, The first comparison voltage generating module includes a filtering resistor and a filtering capacitor; The first end of the filtering resistor is connected to the SW terminal voltage, or connected to the output end of the SW terminal voltage dividing module, and the second end of the filtering resistor is connected to the upper plate of the filtering capacitor; The upper plate of the filtering capacitor is also connected to the non-inverting input terminal of the comparator module, and the lower plate of the filtering capacitor is grounded.

4. The turn-off time generation circuit according to claim 1, characterized in that, The input voltage dividing module includes a third voltage dividing resistor and a fourth voltage dividing resistor connected in series; One end of the third voltage dividing resistor that is not connected to the fourth voltage dividing resistor is connected to the input voltage, and one end of the fourth voltage dividing resistor that is not connected to the third voltage dividing resistor is grounded; The input end of the second comparison voltage generating module is connected to the common end of the third voltage dividing resistor and the fourth voltage dividing resistor.

5. The turn-off time generation circuit according to claim 4, characterized in that, The second comparison voltage generating module includes an operational amplifier, a load resistor, a first NMOS transistor, a first PMOS transistor, a second PMOS transistor, a second NMOS transistor, a third NMOS transistor, and a load capacitor; The non-inverting input end of the operational amplifier is connected to the common end of the third voltage dividing resistor and the fourth voltage dividing resistor, the inverting input end of the operational amplifier is connected to the first end of the load resistor, and the output end of the operational amplifier is connected to the gate of the first NMOS transistor; The first end of the load resistor is also connected to the source of the first NMOS transistor, and the second end of the load resistor is grounded; The drain of the first NMOS transistor is respectively connected to the drain and gate of the first PMOS transistor, and the gate of the second PMOS transistor; The gate of the first PMOS transistor is also connected to the gate of the second PMOS transistor, the drain of the first PMOS transistor is also connected to the gate of the second PMOS transistor, and the source of the first PMOS transistor is connected to the input voltage; The drain of the second PMOS transistor is respectively connected to the drain and gate of the second NMOS transistor, and the gate of the third NMOS transistor, and the source of the second PMOS transistor is connected to the input voltage; The gate of the second NMOS transistor is also connected to the gate of the third NMOS transistor, and the source of the second NMOS transistor is grounded; The source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the lower plate of the load capacitor; The lower plate of the load capacitor is also connected to the inverting input end of the comparator module, and the upper plate of the load capacitor is connected to the input voltage.

6. The turn-off time generation circuit according to claim 4, characterized in that, The second comparison voltage generating module includes an operational amplifier, a load resistor, a first NMOS transistor, a first PMOS transistor, a second PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a load capacitor; The non-inverting input end of the operational amplifier is connected to the common end of the third voltage dividing resistor and the fourth voltage dividing resistor, the inverting input end of the operational amplifier is connected to the first end of the load resistor, and the output end of the operational amplifier is respectively connected to the gate of the first NMOS transistor and the gate of the fourth NMOS transistor; The first end of the load resistor is also connected to the source of the first NMOS transistor, and the second end of the load resistor is grounded; The drain of the first NMOS transistor is respectively connected to the drain and gate of the first PMOS transistor, and the gate of the second PMOS transistor; The gate of the first PMOS transistor is also connected to the gate of the second PMOS transistor, the drain of the first PMOS transistor is also connected to the gate of the second PMOS transistor, and the source of the first PMOS transistor is respectively connected to the source of the second PMOS transistor and the drain of the fourth NMOS transistor; The drain of the second PMOS transistor is respectively connected to the drain and gate of the second NMOS transistor, and the gate of the third NMOS transistor; The gate of the second NMOS transistor is also connected to the gate of the third NMOS transistor, and the source of the second NMOS transistor is grounded; The source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the lower plate of the load capacitor; The source of the fourth NMOS transistor is connected to the upper plate of the load capacitor, and the lower plate of the load capacitor is also connected to the inverting input terminal of the comparator module.

7. The turn-off time generation circuit according to claim 1, wherein, The comparator module includes a comparator, a second inverter, and a third inverter; The output terminal of the non-inverting input voltage generating module is connected to the non-inverting input terminal of the comparator, and the output terminal of the inverting input voltage generating module is connected to the inverting input terminal of the comparator; the comparator is configured to receive the first comparison voltage and the second comparison voltage, compare the first comparison voltage and the second comparison voltage, and generate an output signal of the turn-off time generating circuit based on the comparison result; The input terminal of the second inverter receives the output signal of the turn-off time generating circuit, the output terminal of the second inverter is connected to the input terminal of the third inverter, and the output terminal of the third inverter is used to output the output signal of the turn-off time generating circuit.

8. The turn-off time generation circuit according to claim 7, wherein, The comparator is a rail-to-rail comparator.

9. A chip applied to a DC-DC converter, wherein, The chip includes the turn-off time generating circuit according to any one of claims 1-8.

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