A pulse width modulation chip and modulation method based on microstep phase shift

Abstract

This invention discloses a pulse width modulation (PWM) chip and modulation method based on micro-step phase shifting, relating to the field of digital pulse width modulation (PWM) technology. In the chip, the output of a first delay unit chain is connected to the first input of a first selector, and the output of the first selector is connected to the input of a phase comparator. The output of the phase comparator is connected to the input of a logic control unit, and the output of the logic control unit is connected to the inputs of both the first and second selectors. The inputs of a second delay unit chain and the first input of a phase fine-tuning logic unit are both used to input the PWM signal to be adjusted. The output of the second delay unit chain is connected to the first input of a second selector. The output of the second selector is connected to the second input of the phase fine-tuning logic unit. The output of the phase fine-tuning logic unit is used to output the adjusted PWM signal. This invention can improve the accuracy of digital pulse width modulation without changing the CPU's operating mode.

Description

Technical Field

[0001] This invention relates to the field of digital pulse width modulation technology, and in particular to a pulse width modulation chip and modulation method based on microstep phase shift. Background Technology

[0002] Digital pulse width modulation (DPWM) technology is widely used in modern electronic applications and is receiving increasing attention from the industry, with applications in measurement, communication, and industrial control. However, as the required accuracy of frequency changes becomes increasingly demanding, traditional DPWM technology struggles to meet the requirements of complex application scenarios. Simply increasing the CPU's operating frequency is not a preferred solution, as it not only increases power consumption but may also fail to meet the design requirements of the scenario. How to improve the accuracy of DPWM without changing the CPU's operating mode is a task that urgently needs to be addressed. Summary of the Invention

[0003] The purpose of this invention is to provide a pulse width modulation chip and modulation method based on microstep phase shift, which can improve the accuracy of digital pulse width modulation without changing the CPU's operating mode.

[0004] To achieve the above objectives, the present invention provides the following solution:

[0005] A pulse width modulation chip based on micro-step phase shifting includes:

[0006] Calibration circuit, application circuit, and logic control unit;

[0007] The calibration circuit includes a phase comparator, a first selector, and a first delay unit chain; the application circuit includes a second delay unit chain, a second selector, and a phase fine-tuning logic unit; the first delay unit chain and the second delay unit chain have the same structure;

[0008] The input terminal of the first delay unit chain and the first input terminal of the phase comparator are both connected to the output terminal of the calibration clock. The output terminal of the first delay unit chain is connected to the first input terminal of the first selector, and the output terminal of the first selector is connected to the second input terminal of the phase comparator. The output terminal of the phase comparator is connected to the input terminal of the logic control unit, and the first output terminal of the logic control unit is connected to the second input terminal of the first selector.

[0009] The input terminal of the second delay unit chain and the first input terminal of the phase fine-tuning logic unit are both used to input the pulse width modulation signal to be adjusted. The output terminal of the second delay unit chain is connected to the first input terminal of the second selector. The second output terminal of the logic control unit is connected to the second input terminal of the second selector. The output terminal of the second selector is connected to the second input terminal of the phase fine-tuning logic unit. The output terminal of the phase fine-tuning logic unit is used to output the adjusted pulse width modulation signal.

[0010] Optionally, both the first delay unit chain and the second delay unit chain include multiple delay units connected in series;

[0011] The output of each delay unit in the first delay unit chain is connected to the first input of the first selector;

[0012] The output of each delay unit in the second delay unit chain is connected to the first input of the second selector.

[0013] A pulse width modulation method based on micro-step phase shift is applied to the aforementioned pulse width modulation chip based on micro-step phase shift. The method includes:

[0014] The first delay unit chain delays the calibration clock to obtain a delayed clock, and then transmits the delayed clock to the first selector;

[0015] The phase comparator determines whether the phase of the calibration clock is aligned with the phase of the delayed clock based on the phase of the calibration clock and the phase of the delayed clock.

[0016] If there is no alignment, the logic control unit sends a control signal to the first selector;

[0017] The first selector adjusts the first delay unit chain according to the control signal until the phase of the calibration clock is aligned with the phase of the delay clock, thus obtaining the adjusted first delay unit chain;

[0018] The logic control unit adjusts the second delay unit chain according to the adjusted first delay unit chain to obtain the adjusted second delay unit chain, and transmits the microstep delay unit duration corresponding to the obtained first delay unit chain to the second selector.

[0019] The adjusted second delay unit chain delays the pulse width modulation signal to be adjusted to obtain the delayed pulse width modulation signal to be adjusted;

[0020] The second selector obtains the phase shift signal based on the delayed pulse width modulation signal to be adjusted and the duration of the microstep delay unit;

[0021] The phase fine-tuning logic unit obtains the adjusted pulse width modulation signal based on the phase shift signal and the pulse width modulation signal to be adjusted.

[0022] According to specific embodiments provided by the present invention, the following technical effects are disclosed: the input terminal of the first delay unit chain and the first input terminal of the phase comparator are both connected to the output terminal of the calibration clock; the output terminal of the first delay unit chain is connected to the first input terminal of the first selector; the output terminal of the first selector is connected to the second input terminal of the phase comparator; the output terminal of the phase comparator is connected to the input terminal of the logic control unit; the first output terminal of the logic control unit is connected to the second input terminal of the first selector; the input terminal of the second delay unit chain and the first input terminal of the phase fine-tuning logic unit are both used to input the pulse width modulation signal to be adjusted; the output terminal of the second delay unit chain is connected to the first input terminal of the second selector; the second output terminal of the logic control unit is connected to the second input terminal of the second selector; the output terminal of the second selector is connected to the second input terminal of the phase fine-tuning logic unit; the output terminal of the phase fine-tuning logic unit is used to output the adjusted pulse width modulation signal. By employing micro-step phase shift technology, the accuracy of digital pulse width modulation is improved without changing the CPU's operating mode. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a block diagram of a pulse width modulation chip structure based on microstep phase shift, provided for an embodiment of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] Microstep phase shifting is a reliable frequency division multiplexing technique. By connecting customized delay units in series, waveforms with arbitrary phase shifts can be output according to decoding rules, thereby improving the accuracy of digital pulse width modulation and meeting the needs of applications with fast frequency changes. Based on this, this invention provides a pulse width modulation chip based on microstep phase shifting, such as... Figure 1 As shown, the pulse width modulation chip based on micro-step phase shifting includes:

[0028] The system comprises a calibration circuit, an application circuit, and a logic control unit. The calibration circuit includes a phase comparator, a first selector, and a first delay unit chain. The application circuit includes a second delay unit chain, a second selector, and a phase fine-tuning logic unit. The first and second delay unit chains have identical structures. The calibration circuit's function is to measure the precise delay of each delay unit by comparing the phase of the input calibration clock TBCLK and the delayed clock TBCLK_delayed, based on subtle changes in ambient temperature, operating voltage, and corresponding manufacturing process parameters. The application circuit's function is to calculate, based on the delay units fed back from the calibration circuit, how many delay units should be inserted to obtain a micro-step phase shift waveform for different application scenarios. Finally, the phase fine-tuning logic circuit outputs a high-precision pulse width modulation signal that meets the requirements.

[0029] The input terminals of the first delay unit chain and the first input terminal of the phase comparator are both connected to the output terminal of the calibration clock. The output terminal of the first delay unit chain is connected to the first input terminal of the first selector, and the output terminal of the first selector is connected to the second input terminal of the phase comparator. The output terminal of the phase comparator is connected to the input terminal of the logic control unit, and the first output terminal of the logic control unit is connected to the second input terminal of the first selector. The phase comparator is the core unit of the calibration circuit. The function of the phase comparator is to accurately capture two signals that are completely in phase. When there is a phase deviation, it can actively adjust the position of the delay units to make the phase deviation smaller and smaller until the phases are perfectly matched.

[0030] The input terminals of the second delay unit chain and the first input terminal of the phase fine-tuning logic unit are both used to input the pulse width modulation signal to be adjusted. The output terminal of the second delay unit chain is connected to the first input terminal of the second selector, and the second output terminal of the logic control unit is connected to the second input terminal of the second selector. The output terminal of the second selector is connected to the second input terminal of the phase fine-tuning logic unit. The output terminal of the phase fine-tuning logic unit is used to output the adjusted pulse width modulation signal. The logic control unit transmits the microstep delay unit duration HRPWM STEP obtained from the calibration circuit to the application circuit. Based on this information, the application circuit extracts the required microstep phase shift signal for different application scenarios. The logic control unit also gradually reduces the phase difference between the extracted microstep phase shift signal and the standard signal based on the information fed back from the phase comparator until the two are synchronized.

[0031] The function of the phase fine-tuning logic unit is to synthesize the required high-precision pulse width modulation signal HRPWM_OUT from the pulse width modulation signal ePWM_IN that needs fine-tuning and the phase shift signal ePWM_IN_phase_shift that has been calculated for the fine-tuning steps, through digital logic calculations. Generally, there are three types of fine-tuning requirements: synthesis of rising edge, falling edge, and rising / falling edge phase shift signals. The phase shift steps can be dynamically configured with corresponding registers according to the specific application.

[0032] In practical applications, both the first delay unit chain and the second delay unit chain include multiple delay units connected in series, specifically 2. n Each delay unit is customized according to the target manufacturing process, with the aim of ensuring that its delay duration does not change drastically when the application environment changes.

[0033] The output of each delay unit in the first delay unit chain is connected to the first input of the first selector.

[0034] The output of each delay unit in the second delay unit chain is connected to the first input of the second selector.

[0035] The calibration circuit in the above chip works as follows: The logic control unit outputs DLL Code to the first selector. At any given time, it selects a point in the first delay unit chain, i.e., the TBCLK_delayed clock to be verified. TBCLK and TBCLK_delayed are transmitted to the phase comparator for phase comparison. If the phase of TBCLK_delayed is ahead of the phase of TBCLK, the Up / Down Indicator informs the logic control unit to adjust the DLL Code to the first selector to select a point in the first delay unit chain backward for re-comparison; otherwise, it selects a point in the first delay unit chain forward. Finally, a point is found that aligns the phases of TBCLK and TBCLK_delayed, and the DLL Code at this time is recorded. The working principle of the application circuit is as follows: The delay unit chain of the calibration circuit is completely replicated, meaning the length and unit parameters are identical. By dividing the required delay time in the target scenario by the delay time of a single unit, the control logic unit rounds down to determine how many delay units (HRPWM STEP) should be inserted or activated in the application circuit. Then, the ePWM_IN signal from the application circuit and the phase shift signal ePWM_IN_phase_shift selected according to the HRPWM STEP are sent to the phase fine-tuning logic circuit to modulate the rising edge, falling edge, and upper and lower edge delay waveforms. One of these three is output according to the needs of the control logic. Based on this, this embodiment of the invention provides a pulse width modulation method based on micro-step phase shift applied to the aforementioned pulse width modulation chip based on micro-step phase shift. The method includes:

[0036] The first delay unit chain delays the calibration clock TBCLK to obtain the delayed clock TBCLK_delayed, and then transmits the delayed clock to the first selector.

[0037] The phase comparator determines whether the phase of the calibration clock is aligned with the phase of the delay clock based on the phase of the calibration clock and the phase of the delay clock.

[0038] If there is no alignment, the logic control unit sends a control signal to the first selector.

[0039] The first selector adjusts the first delay unit chain according to the control signal until the phase of the calibration clock is aligned with the phase of the delay clock, thus obtaining the adjusted first delay unit chain.

[0040] The logic control unit adjusts the second delay unit chain according to the adjusted first delay unit chain to obtain the adjusted second delay unit chain, and transmits the microstep delay unit duration HRPWM STEP corresponding to the obtained first delay unit chain to the second selector.

[0041] The adjusted second delay unit chain delays the pulse width modulation signal ePWM_IN to be adjusted to obtain the delayed pulse width modulation signal to be adjusted.

[0042] The second selector obtains the phase shift signal ePWM_IN_phase_shift based on the delayed pulse width modulation signal to be adjusted and the duration of the microstep delay unit.

[0043] The phase fine-tuning logic unit obtains the adjusted pulse width modulation signal HRPWM_OUT based on the phase shift signal and the pulse width modulation signal to be adjusted.

[0044] The present invention has the following advantages:

[0045] 1. Improved reusability of SoC chips and reduced chip area. Regardless of how many ePWM modules are integrated into the SoC chip, only one calibration circuit needs to be integrated. The calibration information can be shared among various ePWM modules without affecting accuracy.

[0046] 2. Improved stability of measurement accuracy. Because each individual delay unit in the chip is custom-developed based on parameters from a standard process library, the duration of a single delay does not change drastically with variations in process, voltage, and temperature.

[0047] 3. Increased flexibility in dynamic measurement. Although the delay duration of each unit is customized during the design phase, unit delays can be combined in specific applications. This expands the flexibility of measurement; for example, measurement accuracy from 150ps to 200ps can be adjusted during the design phase according to the application scenario.

[0048] 4. Improve the accuracy of digital pulse width modulation without changing the CPU's operating mode.

[0049] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0050] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A pulse width modulation chip based on micro-step phase shifting, characterized in that, include: Calibration circuit, application circuit, and logic control unit; The calibration circuit includes a phase comparator, a first selector, and a first delay unit chain; the application circuit includes a second delay unit chain, a second selector, and a phase fine-tuning logic unit; the first delay unit chain and the second delay unit chain have the same structure; The input terminal of the first delay unit chain and the first input terminal of the phase comparator are both connected to the output terminal of the calibration clock. The output terminal of the first delay unit chain is connected to the first input terminal of the first selector, and the output terminal of the first selector is connected to the second input terminal of the phase comparator. The output terminal of the phase comparator is connected to the input terminal of the logic control unit, and the first output terminal of the logic control unit is connected to the second input terminal of the first selector. The input terminal of the second delay unit chain and the first input terminal of the phase fine-tuning logic unit are both used to input the pulse width modulation signal to be adjusted. The output terminal of the second delay unit chain is connected to the first input terminal of the second selector. The second output terminal of the logic control unit is connected to the second input terminal of the second selector. The output terminal of the second selector is connected to the second input terminal of the phase fine-tuning logic unit. The output terminal of the phase fine-tuning logic unit is used to output the adjusted pulse width modulation signal.

2. The pulse width modulation chip based on micro-step phase shift according to claim 1, characterized in that, Both the first delay unit chain and the second delay unit chain include multiple delay units connected in series; The output of each delay unit in the first delay unit chain is connected to the first input of the first selector; The output of each delay unit in the second delay unit chain is connected to the first input of the second selector.

3. A pulse width modulation method based on microstep phase shift, characterized in that, The method, applied to the pulse width modulation chip based on microstep phase shift as described in any one of claims 1-2, comprises: The first delay unit chain delays the calibration clock to obtain a delayed clock, and then transmits the delayed clock to the first selector; The phase comparator determines whether the phase of the calibration clock is aligned with the phase of the delayed clock based on the phase of the calibration clock and the phase of the delayed clock. If there is no alignment, the logic control unit sends a control signal to the first selector; The first selector adjusts the first delay unit chain according to the control signal until the phase of the calibration clock is aligned with the phase of the delay clock, thus obtaining the adjusted first delay unit chain; The logic control unit adjusts the second delay unit chain according to the adjusted first delay unit chain to obtain the adjusted second delay unit chain, and transmits the microstep delay unit duration corresponding to the obtained first delay unit chain to the second selector. The adjusted second delay unit chain delays the pulse width modulation signal to be adjusted to obtain the delayed pulse width modulation signal to be adjusted; The second selector obtains the phase shift signal based on the delayed pulse width modulation signal to be adjusted and the duration of the microstep delay unit; The phase fine-tuning logic unit obtains the adjusted pulse width modulation signal based on the phase shift signal and the pulse width modulation signal to be adjusted.

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