Semiconductor structure and method of forming the same

Abstract

Embodiments of the present application provide a semiconductor structure and a forming method thereof. The method comprises: providing a semiconductor substrate, the semiconductor substrate comprising a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals along a first direction; the bit line isolation trenches extending along a second direction, the first direction being perpendicular to the second direction; forming a bit line isolation layer in the bit line isolation trenches; wherein a gap is provided between the bit line isolation layer and the bit line isolation trenches, the gap being located at a bottom corner of the bit line isolation trench and extending along the second direction, and the gap exposing part of the bottom of the bit line isolation trench; etching the first semiconductor pillars along the first direction through the gap to form a bit line trench; and forming a bit line in the bit line trench.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and relates to but is not limited to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] A semiconductor device usually includes a plurality of transistors, for example, in a memory device such as Dynamic Random Access Memory (DRAM), a memory cell includes a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Generally, in a MOSFET, a source / drain region is formed at a surface of a semiconductor substrate, and under such an arrangement, a planar channel is formed between the source region and the drain region.

[0003] As the integration of memory devices continues to increase, MOSFET manufacturing will reach a physical limit, and as the size of MOSFETs continues to shrink, memory devices maintain performance on data more and more poor. In this case, a Vertical Channel Transistor (VCT) emerges as the times require. In a VCT, a source region and a drain region are formed at respective end portions of a pillar, and any one of the source region and the drain region can be connected with a bit line, which is formed by being buried in a trench defined between semiconductor pillars, and is therefore referred to as a Buried Bit Line (BBL).

[0004] In the related art, the bit line is completely buried at the bottom of the channel, on the one hand, the bit line resistance, bit line voltage and bit line current are all relatively large; on the other hand, since the bit line is in contact with the semiconductor pillar, a large parasitic capacitance is generated between adjacent bit lines. SUMMARY

[0005] Therefore, the embodiments of the present application provide a semiconductor structure and a forming method thereof.

[0006] In a first aspect, the embodiments of the present application provide a forming method of a semiconductor structure, and the method comprises:

[0007] providing a semiconductor substrate, the semiconductor substrate comprising a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals along a first direction; the bit line isolation trenches extend along a second direction, and the first direction is perpendicular to the second direction;

[0008] forming a bit line isolation layer in the bit line isolation trench; wherein the bit line isolation layer and the bit line isolation trench have a gap therebetween, the gap is located at a bottom corner of the bit line isolation trench and extends along the second direction, and the gap exposes part of the bottom of the bit line isolation trench;

[0009] etching the first semiconductor pillar along the first direction through the gap, to form a bit line trench;

[0010] forming a bit line in the bit line trench.

[0011] In some embodiments, forming a bit line isolation layer in the bit line isolation trench comprises:

[0012] forming an initial bit line isolation layer in the bit line isolation trench;

[0013] removing part of the initial bit line isolation layer to form the bit line isolation layer and the gap.

[0014] In some embodiments, forming an initial bit line isolation layer in the bit line isolation trench comprises:

[0015] forming a first initial isolation layer and a second initial isolation layer in the bit line isolation trench in sequence;

[0016] etching and removing part of the second initial isolation layer and part of the first initial isolation layer in sequence along a third direction to form a first etching recess; wherein the first etching recess exposes a first sidewall of the bit line isolation trench and part of the bottom of the bit line isolation trench; the third direction is a depth direction of the bit line isolation trench;

[0017] filling an isolation material in the first etching recess to form a third initial isolation layer;

[0018] the remaining first initial isolation layer, the remaining second initial isolation layer, and the third initial isolation layer constitute the initial bit line isolation layer.

[0019] In some embodiments, removing part of the initial bit line isolation layer to form the bit line isolation layer and the gap comprises:

[0020] etching the remaining second initial isolation layer and the remaining first initial isolation layer in sequence along the third direction at an end of the bit line isolation trench to form at least one opening;

[0021] removing the remaining first initial isolation layer in the initial bit line isolation layer through the opening to form the bit line isolation layer and the gap.

[0022] In some embodiments, the etching the first semiconductor pillar along the first direction through the gap to form a bit line trench comprises:

[0023] partially etching the first semiconductor pillar along the first direction through the gap to form a second etching recess; wherein a dimension of the second etching recess in the third direction is equal to a dimension of the gap in the third direction, and a dimension of the second etching recess in the first direction is less than a dimension of the first semiconductor pillar in the first direction;

[0024] the second etching recess and the gap jointly form the bit line trench.

[0025] In some embodiments, the etching the first semiconductor pillar along the first direction through the gap to form a bit line trench comprises:

[0026] completely etching the first semiconductor pillar along the first direction through the gap to form a third etching recess; wherein a dimension of the third etching recess in the third direction is equal to a dimension of the gap in the third direction, and a dimension of the third etching recess in the first direction is equal to a dimension of the first semiconductor pillar in the first direction;

[0027] the third etching recess and the gap jointly form the bit line trench.

[0028] In some embodiments, before forming the bit line, the method further comprises:

[0029] etching and removing the remaining second initial isolation layer along the third direction to form a fourth etching recess; wherein the fourth etching recess exposes a second sidewall of the bit line isolation trench and the gap;

[0030] forming the bit line in the bit line trench through the fourth etching recess.

[0031] In some embodiments, the forming the bit line in the bit line trench through the fourth etching recess comprises:

[0032] forming an initial bit line layer in the fourth etching recess and the bit line trench;

[0033] performing etch-back on the initial bit line layer to remove the initial bit line layer in the fourth etching recess to form the bit line.

[0034] In some embodiments, after forming the bit line, the method further comprises:

[0035] filling an insulating material in the fourth etching recess to form an insulating layer;

[0036] wherein a top surface of the insulating layer is flush with a top surface of the third initial isolation layer.

[0037] In some embodiments, after forming the insulating layer, the method further comprises:

[0038] forming a plurality of word line trenches in the first semiconductor pillars, the word line trenches extending along the first direction;

[0039] forming a word line in the word line trench.

[0040] In some embodiments, the forming a plurality of word line trenches in the first semiconductor pillars comprises:

[0041] etching the first semiconductor pillars along the third direction to form a plurality of the word line trenches and second semiconductor pillars spaced along the second direction;

[0042] wherein a bottom of the word line trench is beyond a top of the bit line.

[0043] In some embodiments, the forming a word line in the word line trench comprises:

[0044] forming a gate insulating layer on sidewalls of the word line trench;

[0045] forming, in the word line trench with the gate insulating layer, a bottom initial barrier layer, an initial word line layer and a top initial barrier layer in sequence;

[0046] etching part of the top initial barrier layer, part of the initial word line layer and part of the bottom initial barrier layer in sequence along the third direction to form a word line isolation trench in a center of the word line trench, the remaining initial word line layer constituting the word line;

[0047] wherein a bottom of the word line isolation trench retains part of the bottom initial barrier layer.

[0048] In some embodiments, after forming the word line, the method further comprises:

[0049] filling an insulating material in the word line isolation trench to form a word line isolation layer.

[0050] In a second aspect, embodiments of the present application provide a semiconductor structure, comprising at least:

[0051] a semiconductor substrate; the semiconductor substrate comprising a plurality of semiconductor pillars spaced along a first direction and a bit line isolation trench; the bit line isolation trench extending along a second direction, the first direction being perpendicular to the second direction;

[0052] a bit line isolation layer in the bit line isolation trench.

[0053] a bit line, a portion of the bit line is buried at a bottom of the semiconductor pillar, and another portion of the bit line is buried at a bottom corner between the bit line isolation layer and the bit line isolation trench.

[0054] In some embodiments, the semiconductor substrate further comprises a plurality of word line trenches and second semiconductor pillars arranged along a second direction; and the semiconductor structure further comprises:

[0055] a gate insulating layer located on a sidewall of the word line trench;

[0056] a word line isolation layer located at a center of the word line trench, and a top surface of the word line isolation layer is flush with a top surface of the second semiconductor pillar; a dimension of the word line isolation layer in a third direction is smaller than a dimension of the word line trench in the third direction; the third direction is a depth direction of the word line trench;

[0057] a top blocking layer located between the gate insulating layer at a top of the word line trench and the corresponding word line isolation layer;

[0058] a word line located between the gate insulating layer at a middle of the word line trench and the corresponding word line isolation layer;

[0059] a bottom blocking layer located at a bottom of the word line trench in which the gate insulating layer is formed, and the bottom blocking layer is in contact with the word line and a portion of the word line isolation layer.

[0060] In some embodiments, the semiconductor structure further comprises a channel.

[0061] The channel is located between two adjacent gate insulating layers, and the channel is a region of the second semiconductor pillar between the two adjacent gate insulating layers corresponding to the word line.

[0062] The semiconductor structure and the forming method thereof provided by the embodiments of the present application, wherein the forming method of the semiconductor structure comprises: providing a semiconductor substrate, the semiconductor substrate comprising a plurality of first semiconductor pillars and bit line isolation trenches arranged along a first direction; the bit line isolation trenches extending along a second direction; forming a bit line isolation layer in the bit line isolation trenches, the bit line isolation layer having a gap with the bit line isolation trench, the gap being located at a bottom corner of the bit line isolation trench and extending along the second direction; etching the first semiconductor pillars along the first direction through the gap to form a bit line trench; and forming a bit line in the bit line trench. The semiconductor structure formed by the forming method of the semiconductor structure provided by the embodiments of the present application, a portion of the bit line is buried in the bit line isolation trench, and another portion of the bit line is buried at a bottom of the first semiconductor pillar, so that the bit line resistance, voltage and current of the formed semiconductor structure can be reduced, the parasitic capacitance between adjacent bit lines is reduced, and the performance of the semiconductor structure is improved. Attached Figure Description

[0063] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0064] Figure 1 A schematic diagram of an optional process for forming a semiconductor structure provided in an embodiment of this application;

[0065] Figures 2a-2t 3a to 3h are schematic diagrams of the semiconductor structure formation process provided in the embodiments of this application;

[0066] Figure 4a An optional top view of the semiconductor structure provided in an embodiment of this application;

[0067] Figures 4b-4d Cross-sectional views of the semiconductor structure provided in the embodiments of this application along different directions;

[0068] Explanation of reference numerals in the attached figures:

[0069] 20 - Semiconductor substrate; 201 - Bit line isolation trench; 201-1 - First sidewall of the bit line isolation trench; 201-2 - Second sidewall of the bit line isolation trench; 202 - First semiconductor pillar; 203a - First initial isolation layer; 203 - Remaining first initial isolation layer 203; 204a - Second initial isolation layer; 204 - Remaining second initial isolation layer; 205 - Third initial isolation layer; 206a - Initial bit line isolation layer; 206 / 404 - Bit line isolation layer; 207a - Initial bit line layer; 207 / 402 - Bit line; 208 - Insulating layer; 301 / 405 - Second semiconductor Pillar; 302 - Word line trench; 303 / 406 - Gate insulating layer; 304a - Bottom initial barrier layer; 304 / 409 - Bottom barrier layer; 305a - Initial word line layer; 305 / 403 - Word line; 306a - Top initial barrier layer; 306 / 408 - Top barrier layer; 307a - Word line isolation trench; 307 / 407 - Word line isolation layer; 40 - Semiconductor structure; 401 - Semiconductor pillar; 410 - Channel; A - First etched groove; B - Opening; C - Void; D - Second etched groove; D' - Third etched groove; E / E' - Bit line trench; F - Fourth etched groove. Detailed Implementation

[0070] Exemplary embodiments of the present application will be described herein below with reference to the accompanying drawings. While exemplary embodiments of the present application are illustrated, it will be understood that the present application can be carried out in various ways without being limited to the particular embodiments set forth herein. Conversely, additional embodiments of the present application can from time to time be set forth, of which the person of ordinary skill in the art will avail himself / herself by virtue of the conceptual description of the application as set forth herein.

[0071] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one of ordinary skill in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail so as not to unnecessarily obscure the present application.

[0072] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numerals can represent like elements throughout the several figures.

[0073] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms since such terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section.

[0074] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting thereof. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of associated items.

[0075] Based on the problems in the related art, the embodiments of the present application provide a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the following steps: providing a semiconductor substrate, the semiconductor substrate comprising a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals along a first direction; the bit line isolation trenches extending along a second direction; forming a bit line isolation layer in the bit line isolation trenches, the bit line isolation layer and the bit line isolation trenches having a gap therebetween, the gap being located at a bottom corner of the bit line isolation trenches and extending along the second direction; etching the first semiconductor pillars along the first direction through the gap to form a bit line trench; and forming a bit line in the bit line trench. The semiconductor structure formed by the forming method of the semiconductor structure provided by the embodiments of the present application has the bit line partially buried in the bit line isolation trench and another part of the bit line buried at the bottom of the first semiconductor pillar, so that the resistance, voltage and current of the bit line of the formed semiconductor structure can be reduced, the parasitic capacitance between adjacent bit lines is reduced, and the performance of the semiconductor structure is improved.

[0076] The embodiments of the present application provide a forming method of a semiconductor structure, as shown in the following schematic view: Figure 1 The forming method of the semiconductor structure comprises the following steps:

[0077] In step S101, a semiconductor substrate is provided, the semiconductor substrate comprising a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals along a first direction.

[0078] The bit line isolation trenches extend along a second direction, and the first direction is perpendicular to the second direction.

[0079] The semiconductor substrate can be a silicon substrate, and can also include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InP), or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP), or a combination thereof.

[0080] The semiconductor substrate can include a top surface at a front surface and a bottom surface at a back surface opposite to the front surface; a third direction is defined as a direction perpendicular to the top surface and the bottom surface of the semiconductor substrate, ignoring flatness of the top surface and the bottom surface. In the direction of the top surface and the bottom surface of the semiconductor substrate (i.e., the plane in which the semiconductor substrate is located), a first direction and a second direction intersecting each other (e.g., perpendicular to each other) are defined, for example, the arrangement direction of the plurality of bit line isolation trenches can be defined as the first direction, and the extension direction of the bit line isolation trenches can be defined as the second direction, and the plane direction of the semiconductor substrate can be determined based on the first direction and the second direction. Here, the first direction, the second direction, and the third direction are perpendicular to each other. In an embodiment of the present application, the first direction is defined as the X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is defined as the Z-axis direction.

[0081] In an embodiment of the present application, the bit line isolation trench is used to fill isolation material to isolate the finally formed bit line. The first semiconductor column is the semiconductor substrate located between two adjacent bit line isolation trenches after etching the semiconductor substrate to form a plurality of bit line isolation trenches. The bit line isolation trench and the first semiconductor column are arranged along the first direction.

[0082] In an embodiment of the present application, the bit line isolation trench is used to fill isolation material to isolate the finally formed bit line. The first semiconductor column is the semiconductor substrate located between two adjacent bit line isolation trenches after etching the semiconductor substrate to form a plurality of bit line isolation trenches. The bit line isolation trench and the first semiconductor column are arranged along the first direction.

[0083] In an embodiment of the present application, the bit line isolation trench is used to fill isolation material to isolate the finally formed bit line. The first semiconductor column is the semiconductor substrate located between two adjacent bit line isolation trenches after etching the semiconductor substrate to form a plurality of bit line isolation trenches. The bit line isolation trench and the first semiconductor column are arranged along the first direction.

[0084] Here, etching the first semiconductor column along the first direction through the gap can be etching part of the first semiconductor column in the first direction, or etching all of the first semiconductor column in the first direction.

[0085] Step S104, forming a bit line in the bit line trench.

[0086] Figures 2a-2t , 3a-3h are structure schematic diagrams of the semiconductor structure formation process provided by the embodiments of the present application. Next, please refer to Figures 2a-2t , 3a-3h further specifically describe the forming method of the semiconductor structure provided by the embodiments of the present application.

[0087] Firstly, please refer to Figures 2a to 2e Step S101, providing a semiconductor substrate, the semiconductor substrate comprising a plurality of first semiconductor pillars arranged along a first direction at intervals and a bit line isolation trench.

[0088] In some embodiments, the step S101 can comprise the following steps:

[0089] Step S1011, providing a semiconductor substrate.

[0090] Step S1012, forming a patterned photoresist layer on the surface of the semiconductor substrate.

[0091] Step S1013, etching the semiconductor substrate through the patterned photoresist layer to form a plurality of first semiconductor pillars arranged along a first direction at intervals and a bit line isolation trench.

[0092] As shown in Figure 2a and 2b , the semiconductor substrate 20 is etched along the Z-axis direction to form the bit line isolation trench 201 and the first semiconductor pillar 202 arranged along the X-axis direction at intervals, and the bit line isolation trench 201 extends along the Y-axis direction. Figure 2c is a top view of the semiconductor pillar after etching, Figure 2d and 2e are cross-sectional views along the a-a', b-b' and c-c' directions in Figure 2c respectively, it can be seen that the bottom of the bit line isolation trench 201 still retains a part of the thickness of the semiconductor substrate.

[0093] Next, please refer to Figures 2f to 2j Step S102, forming a bit line isolation layer in the bit line isolation trench; wherein the bit line isolation layer and the bit line isolation trench have a gap therebetween, the gap is located at the bottom corner of the bit line isolation trench and extends along the second direction, and the gap exposes part of the bottom of the bit line isolation trench.

[0094] In some embodiments, the step S102 can be formed by the following steps:

[0095] Step S1021, forming an initial bit line isolation layer in the bit line isolation trench.

[0096] In some embodiments, the initial bit line isolation layer can be formed by the following steps:

[0097] Step S10, sequentially forming a first initial isolation layer and a second initial isolation layer in the bit line isolation trench.

[0098] The materials of the first initial isolation layer and the second initial isolation layer can be any suitable insulating material, but the first initial isolation layer is different from the second initial isolation layer. Illustratively, the first initial isolation layer can be a silicon oxide layer, and the second initial isolation layer can be a silicon nitride layer.

[0099] In the embodiments of the present application, the first initial isolation layer and the second initial isolation layer can be formed by any suitable deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, or a coating process.

[0100] It should be noted that when the second initial isolation layer is formed, due to the influence of the process, the second initial isolation layer will often cover the top surface of the first semiconductor pillar, at this time, dry etching treatment or chemical mechanical polishing (CMP) treatment needs to be performed on the second initial isolation layer to expose the top surface of the first semiconductor pillar, therefore, in the embodiments of the present application, the top surface of the second initial isolation layer is flush with the top surface of the first semiconductor pillar.

[0101] As shown in FIG. 2B, the first initial isolation layer 203a and the second initial isolation layer 204a are sequentially formed in the bit line isolation trench, and the top surface of the second initial isolation layer 204a is flush with the top surface of the first semiconductor pillar 202. Figure 2f

[0102] Step S11, etching and removing part of the second initial isolation layer and part of the first initial isolation layer along a third direction to form a first etching groove; wherein the first etching groove exposes the first side wall of the bit line isolation trench and part of the bottom of the bit line isolation trench; the third direction is the depth direction of the bit line isolation trench.

[0103] In the embodiments of the present application, dry etching process can be used to remove part of the second initial isolation layer and part of the first initial isolation layer, for example, plasma etching process, reactive ion etching process or ion milling process.

[0104] As shown in FIG. 2C, the first etching groove 205 is formed by etching and removing part of the second initial isolation layer 204a and part of the first initial isolation layer 203a along the third direction, and the first etching groove 205 exposes the first side wall of the bit line isolation trench and part of the bottom of the bit line isolation trench.​Figure 2g As shown, along the Z-axis, the second initial isolation layer 204a and the first initial isolation layer 203a are etched sequentially, removing a portion of the second initial isolation layer 204a and a portion of the first initial isolation layer 203a, exposing the first sidewall 201-1 of the bit line isolation trench and a portion of the bottom of the bit line isolation trench, forming the first etched groove A. After the first etched groove A is formed, the remaining first initial isolation layer 203 and the remaining second initial isolation layer 204 are retained in the bit line isolation trench.

[0105] In this embodiment, removing a portion of the second initial isolation layer 204a and a portion of the first initial isolation layer 203a may involve removing half of the second initial isolation layer 204a and half of the first initial isolation layer 203a in each line isolation trench. In other embodiments, other proportions of the second and first initial isolation layers may be removed, for example, removing 3 / 5 of the second and first initial isolation layers.

[0106] Step S12: Fill the first etched groove with isolation material to form a third initial isolation layer.

[0107] In some embodiments, the insulating material can be any insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the insulating material is the same as the constituent material of the second initial insulating layer.

[0108] It should be noted that, during the formation of the third initial isolation layer, due to the influence of the process, the third initial isolation layer often covers the top surface of the first semiconductor pillar and the second initial isolation layer. In this case, the third initial isolation layer needs to be subjected to dry etching or CMP treatment to expose the top surface of the first semiconductor pillar and the second initial isolation layer. Therefore, in the embodiments of this application, the top surface of the third initial isolation layer is flush with the top surface of the first semiconductor pillar and the remaining second initial isolation layer.

[0109] like Figure 2h As shown, an isolation material is filled in the first etched groove A to form a third initial isolation layer 205. The top surface of the third initial isolation layer is flush with the top surfaces of the first semiconductor pillar 202 and the remaining second initial isolation layer 204. The remaining first initial isolation layer 203, the remaining second initial isolation layer 204, and the third initial isolation layer 205 constitute the initial bit line isolation layer 206a.

[0110] Step S1022: Remove part of the initial bit line isolation layer to form the bit line isolation layer and the gap.

[0111] In some embodiments, the bit line isolation layer and the gap can be formed by the following steps:

[0112] Step S13: At the end of the bit line isolation trench, along the third direction, the remaining second initial isolation layer and the remaining first initial isolation layer are etched sequentially to form at least one opening.

[0113] Here, the process of forming the opening can be achieved through a dry etching process.

[0114] like Figure 2i As shown, at any one or both ends of the bit line isolation trench, along the Z-axis direction, the remaining second initial isolation layer 204 and the remaining first initial isolation layer 203 are sequentially etched to form one or two openings B, the bottom of which is located inside the remaining first initial isolation layer 203.

[0115] Step S14: Remove the remaining first initial isolation layer in the initial bit line isolation layer through the opening to form the bit line isolation layer and the gap.

[0116] like Figure 2j As shown, a wet etching process is used, in which an etchant, such as a phosphoric acid solution (H3PO4), a sulfuric acid solution, or a hydrofluoric acid solution, is injected into the opening B to remove the remaining first initial isolation layer 203 in the initial bit line isolation layer 206a, forming a bit line isolation layer 206 and a void C, which extends along the Y-axis direction.

[0117] Next, you can refer to Figure 2k and 2l In step S103, the first semiconductor pillar is etched along the first direction through the gap to form a bit line trench.

[0118] In this embodiment, the process of etching the first semiconductor pillar through the gap is a wet etching process, which may include the following two etching processes:

[0119] The first etching process involves partially etching the first semiconductor pillar along the first direction through the gap to form a second etched groove. The dimension of the second etched groove in the third direction is equal to the dimension of the gap in the third direction, and the dimension of the second etched groove in the first direction is smaller than the dimension of the first semiconductor pillar in the first direction. The second etched groove and the gap together constitute the bit line trench.

[0120] like Figure 2kAs shown, the first semiconductor pillar 202 is partially etched along the X-axis through the gap C, forming a second etched groove D. The dimension h1 of the second etched groove D in the Z-axis direction is equal to the dimension h2 of the gap C in the Z-axis direction, and the dimension w1 of the second etched groove D in the Y-axis direction is smaller than the dimension w2 of the gap C in the Y-axis direction. In this embodiment, the second etched groove D and the gap C together constitute the bit line trench E.

[0121] The second etching process involves etching the entire first semiconductor pillar along the first direction through the gap to form a third etched groove. The dimension of the third etched groove in the third direction is equal to the dimension of the gap in the third direction, and the dimension of the third etched groove in the first direction is equal to the dimension of the first semiconductor pillar in the first direction. The third etched groove and the gap together constitute the bit line trench.

[0122] like Figure 2l As shown, the first semiconductor pillar 202 is completely etched along the X-axis through the gap C, forming a third etched groove D'. The dimension h3 of the third etched groove D' in the Z-axis direction is equal to the dimension h2 of the gap C in the Z-axis direction, and the dimension w3 of the third etched groove D' in the Y-axis direction is equal to the dimension w2 of the gap C in the Y-axis direction. In this embodiment, the third etched groove D' and the gap C together constitute a bit line trench E'.

[0123] Next, you can refer to Figures 2m to 2t Step S104 is executed to form a bit line in the bit line trench.

[0124] In some embodiments, prior to forming the bit line, the method further includes:

[0125] Step S15: Etch away the remaining second initial isolation layer along the third direction to form a fourth etched groove; wherein the fourth etched groove exposes the void and the second sidewall of the bit line isolation trench.

[0126] In this embodiment, a dry etching process can be used to etch away the remaining second initial isolation layer to form the fourth etched groove.

[0127] like Figure 2m and 2n As shown, along the Z-axis, the remaining second initial isolation layer 204 is etched away to form a fourth etched groove F. The fourth etched groove F exposes the void C and the second sidewall 201-2 of the bit line isolation trench.

[0128] Step S16: The bit line is formed in the bit line trench through the fourth etching groove.

[0129] In some embodiments, step S16 can be implemented by the following steps:

[0130] Step S161, forming an initial bit line layer in the fourth etching groove and the bit line trench.

[0131] As shown in Figure 2o and 2p , an initial bit line layer 207a is formed in the fourth etching groove F and the bit line trench E or the bit line trench E' by using any suitable deposition process.

[0132] Step S162, etching back the initial bit line layer to remove the initial bit line layer in the fourth etching groove, thereby forming the bit line.

[0133] As shown in Figure 2q and 2r , the initial bit line layer 207a is etched back to remove the initial bit line layer in the fourth etching groove F, thereby forming the bit line 207.

[0134] In the embodiments of the present application, the material of the initial bit line layer or the bit line includes tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide or any combination thereof.

[0135] In some embodiments, after the bit line is formed, the method for forming the semiconductor structure further includes:

[0136] Step S17, filling an insulating material in the fourth etching groove to form an insulating layer.

[0137] Here, the insulating material forming the insulating layer can be the same as or different from the material of the third initial isolation layer.

[0138] As shown in Figure 2s and 2t , the fourth etching groove F is filled with an insulating material to form an insulating layer 208, wherein the top surface of the insulating layer 208 is flush with the top surface of the third initial isolation layer 205.

[0139] In some embodiments, after the insulating layer is formed, the method for forming the semiconductor structure further includes the following steps, which are described below by taking the partial etching of the first semiconductor pillar in the first direction (i.e., the bit line trench E) as an example in combination with Figures 3a to 3h the subsequent formation process.

[0140] Step S18, forming a plurality of word line trenches in the first semiconductor pillar; the word line trenches extend along the first direction.

[0141] In this embodiment, the word line groove is used to form word lines and word line isolation structures.

[0142] In some embodiments, step S18 can be formed by the following steps:

[0143] Step S181: Etch the first semiconductor pillar along the third direction to form a plurality of word line trenches and second semiconductor pillars spaced apart along the second direction.

[0144] like Figure 3a As shown, along the Z-axis direction, the first semiconductor pillar is etched to form a plurality of second semiconductor pillars 301 and word line trenches 302 arranged at intervals along the Y-axis direction, and the word line trenches 302 extend along the X-axis direction. Figure 3b This is a top view of the etched semiconductor pillar. Figure 3c and 3d respectively along Figure 3b The cross-sectional views along the a-a', b-b', c-c', and d-d' directions show that the bottom of the word line groove 302 extends beyond the top of the bit line 206.

[0145] Step S19: Form character lines in the character line groove.

[0146] In some embodiments, the process of forming word lines may include the following steps:

[0147] Step S191: Form a gate insulating layer on the sidewall of the word line trench.

[0148] Step S192: In the word line trench where the gate insulating layer is formed, a bottom initial barrier layer, an initial word line layer and a top initial barrier layer are formed sequentially.

[0149] The gate insulating layer can be made of any insulating material, such as silicon oxide. The bottom initial barrier layer and the top initial barrier layer can be made of the same or different materials; for example, both the bottom and top initial barrier layers can be made of silicon nitride. The initial word line layer can be made of tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, titanium nitride, or any combination thereof.

[0150] In this embodiment, the gate insulating layer, bottom initial barrier layer, initial word line layer and top initial barrier layer can be formed by any suitable deposition process.

[0151] like Figure 3e As shown, a gate insulating layer 303 is formed on the sidewall of the word line trench 302, and a bottom initial barrier layer 304a, an initial word line layer 305a and a top initial barrier layer 306a are sequentially formed in the word line trench where the gate insulating layer 303 is formed.

[0152] Step S193, etching part of the top initial barrier layer, part of the initial word line layer and part of the bottom initial barrier layer in sequence along the third direction to form a word line isolation trench in the center of the word line trench, and the remaining initial word line layer constitutes the word line; wherein the bottom of the word line isolation trench remains part of the bottom initial barrier layer.

[0153] As shown in FIG. 3, the top initial barrier layer 306a, the initial word line layer 305a and the bottom initial barrier layer 304a are etched in sequence along the Z-axis direction to form a word line isolation trench 307a in the center of the word line trench, and the remaining initial word line layer constitutes the word line 305, and the remaining top initial barrier layer constitutes the top barrier layer 306 of the semiconductor structure, and the remaining bottom initial barrier layer constitutes the bottom barrier layer 304 of the semiconductor structure. Figure 3f As shown in FIG. 3, the top initial barrier layer 306a, the initial word line layer 305a and the bottom initial barrier layer 304a are etched in sequence along the Z-axis direction to form a word line isolation trench 307a in the center of the word line trench, and the remaining initial word line layer constitutes the word line 305, and the remaining top initial barrier layer constitutes the top barrier layer 306 of the semiconductor structure, and the remaining bottom initial barrier layer constitutes the bottom barrier layer 304 of the semiconductor structure.

[0154] In some embodiments, after the word line is formed, the method for forming the semiconductor structure further comprises:

[0155] Step S20, filling the word line isolation trench with an insulating material to form a word line isolation layer.

[0156] As shown in FIG. 3, an insulating material is deposited in the word line isolation trench 307a by using any suitable deposition process to form a word line isolation layer 307. The word line isolation layer is used to isolate adjacent word lines 305. Figure 3g 3h It should be noted that the method for forming the semiconductor structure provided in the embodiments of the present application can be applied to any vertical gate-all-around (VGAA) semiconductor device, such as a dynamic random access memory (DRAM).

[0157] The semiconductor structure formed by the method for forming the semiconductor structure provided in the embodiments of the present application comprises a buried word line and a buried bit line, wherein part of the bit line is buried in a bit line isolation trench, and another part of the bit line is buried at the bottom of a first semiconductor pillar. In this way, the resistance, voltage and current of the bit line of the formed semiconductor structure can be reduced, and the parasitic capacitance between adjacent bit lines is reduced, thereby improving the performance of the semiconductor structure.

[0158] In addition, the embodiments of the present application also provide a semiconductor structure formed by the method for forming the semiconductor structure provided in the above embodiments.

[0159] In addition, the embodiments of the present application also provide a semiconductor structure formed by the method for forming the semiconductor structure provided in the above embodiments. Figure 4a ​An optional top view of the semiconductor structure provided in the embodiments of the present application, Figures 4b-4d are sectional views of the semiconductor structure along different directions, respectively, as Figures 4a-4d As shown, the semiconductor structure 40 includes a semiconductor substrate, bit lines 402 and word lines 403.

[0160] The semiconductor substrate includes a plurality of semiconductor pillars 401 (corresponding to the first semiconductor pillars after the second semiconductor pillars are etched in the above embodiment) and bit line isolation trenches arranged along a first direction, and the bit line isolation trenches are filled with bit line isolation layers 404. In the embodiments of the present application, the bit line isolation trenches extend along a second direction, i.e., the bit line isolation layers 404 extend along the second direction, and the first direction is perpendicular to the second direction.

[0161] In the embodiments of the present application, the first direction is defined as the X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is defined as the Z-axis direction.

[0162] The bit lines 402 are partially buried in the bottom of the semiconductor pillars 401, and another part of the bit lines 402 is buried in the bottom corner between the bit line isolation layers 404 and the bit line isolation trenches, and the bit lines 402 extend along the Y-axis direction.

[0163] In some embodiments, the semiconductor substrate further includes a plurality of word line trenches and second semiconductor pillars 405 arranged along the Y-axis direction, the first semiconductor pillars 401 include the second semiconductor pillars 405, and the semiconductor structure 40 further includes: gate insulating layers 406 located on the sidewalls of the word line trenches; word line isolation layers 407 located in the centers of the word line trenches, and the top surfaces of the word line isolation layers 407 are flush with the top surfaces of the second semiconductor pillars 405; the size h4 of the word line isolation layers in the third direction is smaller than the size h5 of the word line trenches in the third direction; and the third direction is the depth direction of the word line trenches.

[0164] In some embodiments, the word lines 403 are located between the gate insulating layers 406 and the corresponding word line isolation layers 407 in the middle of the word line trenches; the semiconductor structure 40 further includes: top blocking layers 408 located between the gate insulating layers 406 and the corresponding word line isolation layers 407 at the top of the word line trenches; and bottom blocking layers 409 located at the bottom of the word line trenches in which the gate insulating layers 406 are formed, and the bottom blocking layers 409 are in contact with the word lines 403 and part of the word line isolation layers 407.

[0165] In some embodiments, the semiconductor structure further comprises: a channel 410; the channel 401 is located between two adjacent gate insulating layers 406, and the channel 401 is a second semiconductor pillar region between the two adjacent gate insulating layers 406 corresponding to the word line 403.

[0166] In other embodiments, the semiconductor structure can further comprise: a functional device such as a storage capacitor or a variable resistor, which will not be described in detail here.

[0167] The semiconductor structure in the embodiments of the present application is similar to the forming method of the semiconductor structure in the above-described embodiments. For technical features not described in detail in the embodiments of the present application, please refer to the above-described embodiments for understanding, which will not be described here.

[0168] The semiconductor structure provided by the embodiments of the present application can reduce the resistance, voltage and current of the bit line of the formed semiconductor structure, and reduce the parasitic capacitance between adjacent bit lines, and improve the performance of the semiconductor structure, because the bit line is partially buried in the bit line isolation trench and partially buried in the bottom of the semiconductor pillar.

[0169] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling between the displayed or discussed components.

[0170] The units described above as separate components can or can not be physically separated, and the components displayed as units can or can not be physical units, that is, they can be located in one place or distributed on multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0171] The features disclosed in several method or device embodiments provided in the present application can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

[0172] The above is only some embodiments of the embodiments of the present application, but the protection scope of the embodiments of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application should be subject to the protection scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: A semiconductor substrate is provided, the semiconductor substrate including a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals along a first direction; the bit line isolation trenches extend along a second direction, the first direction being perpendicular to the second direction; A bitline isolation layer is formed in the bitline isolation trench; wherein, there is a gap between the bitline isolation layer and the bitline isolation trench, the gap is located at the bottom corner of the bitline isolation trench and extends along the second direction, and the gap exposes part of the bottom of the bitline isolation trench; The first semiconductor pillar is etched along the first direction through the gap to form a bit line trench. Bit lines are formed in the bit line trenches.

2. The method according to claim 1, characterized in that, A bit line isolation layer is formed in the bit line isolation trench, including: An initial bit line isolation layer is formed in the bit line isolation trench; A portion of the initial bit line isolation layer is removed to form the bit line isolation layer and the void.

3. The method according to claim 2, characterized in that, Forming an initial bit line isolation layer in the bit line isolation trench includes: A first initial isolation layer and a second initial isolation layer are sequentially formed in the bit line isolation trench; Along a third direction, a portion of the second initial isolation layer and a portion of the first initial isolation layer are sequentially etched away to form a first etched groove; wherein, the first etched groove exposes the first sidewall of the bit line isolation trench and a portion of the bottom of the bit line isolation trench; the third direction is the depth direction of the bit line isolation trench; The first etched groove is filled with an isolation material to form a third initial isolation layer; The remaining first initial isolation layer, the remaining second initial isolation layer, and the third initial isolation layer constitute the initial bit line isolation layer.

4. The method according to claim 3, characterized in that, The step of removing a portion of the initial bit line isolation layer to form the bit line isolation layer and the gap includes: At the end of the bit line isolation trench, along the third direction, the remaining second initial isolation layer and the remaining first initial isolation layer are etched sequentially to form at least one opening; The remaining first initial isolation layer in the initial bit line isolation layer is removed through the opening to form the bit line isolation layer and the gap.

5. The method according to claim 4, characterized in that, The step of etching the first semiconductor pillar along the first direction through the gap to form a bit line trench includes: Through the gap, along the first direction, the first semiconductor pillar is partially etched to form a second etched groove; wherein, the size of the second etched groove in the third direction is equal to the size of the gap in the third direction, and the size of the second etched groove in the first direction is smaller than the size of the first semiconductor pillar in the first direction; The second etched groove and the void together constitute the bit line trench.

6. The method according to claim 4, characterized in that, The step of etching the first semiconductor pillar along the first direction through the gap to form a bit line trench includes: The first semiconductor pillar is completely etched through the gap along the first direction to form a third etched groove; wherein the dimension of the third etched groove in the third direction is equal to the dimension of the gap in the third direction, and the dimension of the third etched groove in the first direction is equal to the dimension of the first semiconductor pillar in the first direction; The third etched groove and the void together constitute the bit line groove.

7. The method according to claim 5 or 6, characterized in that, Before forming the bit line, the method further includes: Along the third direction, the remaining second initial isolation layer is etched away to form a fourth etched groove; wherein the fourth etched groove exposes the void and the second sidewall of the bit line isolation trench; The bit line is formed in the bit line trench through the fourth etched groove.

8. The method according to claim 7, characterized in that, The bit line is formed in the bit line trench through the fourth etched groove, including: An initial bit line layer is formed in the fourth etched groove and the bit line trench; The initial bit line layer is etched back to remove the initial bit line layer located in the fourth etch groove, thus forming the bit line.

9. The method according to claim 8, characterized in that, After forming the bit line, the method further includes: An insulating material is filled into the fourth etched groove to form an insulating layer; The top surface of the insulating layer is flush with the top surface of the third initial insulating layer.

10. The method according to claim 9, characterized in that, After forming the insulating layer, the method further includes: A plurality of word line trenches are formed in the first semiconductor pillar, and the word line trenches extend along the first direction; Character lines are formed in the character line groove.

11. The method according to claim 10, characterized in that, The formation of multiple word line trenches in the first semiconductor pillar includes: Along the third direction, the first semiconductor pillar is etched to form a plurality of word line trenches and second semiconductor pillars arranged at intervals along the second direction; The bottom of the word line groove extends beyond the top of the bit line.

12. The method according to claim 11, characterized in that, The process of forming character lines in the character line groove includes: A gate insulating layer is formed on the sidewall of the word line trench; In the word line trench where the gate insulating layer is formed, a bottom initial barrier layer, an initial word line layer and a top initial barrier layer are formed sequentially. Along the third direction, a portion of the top initial blocking layer, a portion of the initial word line layer, and a portion of the bottom initial blocking layer are sequentially etched to form a word line isolation trench located at the center of the word line trench, and the remaining initial word line layer constitutes the word line; The bottom of the word line isolation trench retains a portion of the initial bottom blocking layer.

13. The method according to claim 12, characterized in that, After forming the word lines, the method further includes: Insulating material is filled into the word line isolation trench to form a word line isolation layer.

14. A semiconductor structure, characterized in that, At least including: Semiconductor substrate; The semiconductor substrate includes a plurality of semiconductor pillars and bit line isolation trenches arranged at intervals along a first direction; The bit line isolation trench extends along a second direction, and the first direction is perpendicular to the second direction; Bit line isolation layer, located in the bit line isolation trench; Bit lines, a portion of which is buried at the bottom of the semiconductor pillar, and another portion of which is buried at the bottom corner between the bit line isolation layer and the bit line isolation trench; The semiconductor substrate further includes a plurality of word line trenches and a second semiconductor pillar arranged at intervals along the second direction; The semiconductor structure also includes: A gate insulating layer is located on the sidewall of the word line trench; A word line isolation layer is located at the center of the word line trench, and the top surface of the word line isolation layer is flush with the top surface of the second semiconductor pillar; the dimension of the word line isolation layer in a third direction is smaller than the dimension of the word line trench in the third direction; the third direction is the depth direction of the word line trench; A top blocking layer is located between the gate insulating layer and the corresponding word line isolation layer at the top of the word line trench; Word lines are located between the gate insulating layer and the corresponding word line isolation layer in the middle of the word line trench. A bottom barrier layer is located at the bottom of the word line trench where the gate insulating layer is formed, and the bottom barrier layer is in contact with the word line and a portion of the word line isolation layer.

15. The semiconductor structure according to claim 14, characterized in that, The semiconductor structure further includes: a channel; The channel is located between two adjacent gate insulating layers, and the channel is a second semiconductor pillar region corresponding to the word line and located between two adjacent gate insulating layers.

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