Method of fabricating a columnar capacitor array structure and semiconductor structure

Abstract

The application provides a preparation method of a columnar capacitor array structure and a semiconductor structure. The preparation method adjusts the thickness of the mask layer of the peripheral area and the thickness of the mask layer of the array area to be the same by using the filling of the photoresist layer before removing the mask layer, thereby avoiding the influence of the different thicknesses of the mask layers on the thickness of the top support layer and causing the loss of the top support layer. In addition, the preparation method of the application further forms a third sacrificial layer and an auxiliary layer to double-protect the top support layer, prevent the top support layer from being thinned in the subsequent process, increase the supporting force of the top support layer, and further avoid the tilting of the columnar capacitor caused by the insufficient supporting force of the top support layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a columnar capacitor array structure and a semiconductor structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor storage device in computers, consisting of many repeating memory cells. In DRAM manufacturing processes below 20nm, DRAM mostly adopts a stacked capacitor structure, where the capacitors are vertical cylindrical capacitors with a high aspect ratio.

[0003] Because the cylindrical capacitor has a high aspect ratio, a support layer is usually required to support it and increase its stability. A drawback of existing cylindrical capacitor manufacturing methods is that the top support layer is easily worn away, and insufficient support may cause the cylindrical capacitor to tilt or even peel off, affecting its performance.

[0004] Therefore, it is necessary to provide a method for fabricating a columnar capacitor array structure to solve problems such as the easy loss of the top support layer in the prior art. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for fabricating a columnar capacitor array structure and a semiconductor structure, which can avoid the loss of the top support layer, thereby ensuring the thickness and support strength of the top support layer, preventing the columnar capacitor from tilting, improving the performance of the columnar capacitor array structure, and thus improving the yield of the memory.

[0006] To address the above problems, this invention provides a method for fabricating a columnar capacitor array structure, comprising:

[0007] A substrate is provided, in which a plurality of conductive pads are disposed. A first sacrificial layer, an intermediate support layer, a second sacrificial layer, a top support layer, and a mask layer are stacked on the substrate. The substrate is divided into an array region and a peripheral region. The thickness of the mask layer in the array region is less than the thickness of the mask layer in the peripheral region. In the array region, a plurality of capacitor vias penetrate the mask layer, the top support layer, the second sacrificial layer, the intermediate support layer, and the first sacrificial layer, exposing the conductive pads. A photoresist layer is formed, which fills the capacitor vias and covers the mask layer in the array region. In the peripheral region, a portion of the mask layer is removed, and the remaining upper surface of the mask layer in the peripheral region is flush with the upper surface of the mask layer in the array region. The surface of the mask layer is then removed. The photoresist layer is etched, and the mask layer is etched using the top support layer as an etch stop layer; a third sacrificial layer is formed, which covers the top support layer; the photoresist layer is removed; conductive material is filled into the capacitor hole to form a lower electrode, which is electrically connected to the conductive pad; an auxiliary layer is formed, which covers the third sacrificial layer and the lower electrode; the auxiliary layer, the third sacrificial layer, and the top support layer are patterned, and the third sacrificial layer and the second sacrificial layer are removed; the intermediate support layer is patterned, and the first sacrificial layer and the auxiliary layer are removed; a dielectric layer is formed, which covers the exposed surfaces of the substrate, the lower electrode, the intermediate support layer, and the top support layer; an upper electrode is formed, which covers the surface of the dielectric layer. The step of forming a photoresist layer, wherein the photoresist layer fills the capacitor hole and covers the mask layer of the array region, further includes: forming a photoresist material layer, wherein the photoresist material layer fills the capacitor hole and covers the mask layer of the array region and the peripheral region; and etching back the photoresist material layer to expose the mask layer of the peripheral region to form the photoresist layer.

[0008] In one embodiment, the step of forming a photoresist layer that fills the capacitor holes and covers the mask layer of the array region further includes: forming a photoresist material layer that fills the capacitor holes and covers the mask layer of the array region and the peripheral region; and etching back the photoresist material layer to expose the mask layer of the peripheral region to form the photoresist layer.

[0009] In one embodiment, the upper surface of the photoresist layer is flush with the upper surface of the mask layer in the peripheral region.

[0010] In one embodiment, the photoresist layer on the surface of the mask layer is removed, and the top support layer is used as the etching stop layer. In the step of etching the mask layer, the etching rate of the etching material on the mask layer is greater than the etching rate on the top support layer.

[0011] In one embodiment, the mask layer is a polysilicon layer and the top support layer is a silicon nitride layer.

[0012] In one embodiment, the step of forming a third sacrificial layer that covers the top support layer is performed by a spin-coating deposition process.

[0013] In one embodiment, the third sacrificial layer is an oxide layer.

[0014] In one embodiment, the step of forming a third sacrificial layer that covers the top support layer further includes: forming a third sacrificial material layer that covers the top support layer and the photoresist layer; and thinning the third sacrificial material layer to expose the photoresist layer to form the third sacrificial layer.

[0015] In one embodiment, the step of filling the capacitor hole with conductive material to form a lower electrode, and electrically connecting the lower electrode to the conductive pad, further includes: forming a lower electrode material layer, the lower electrode material layer filling the capacitor hole and covering the third sacrificial layer; thinning the lower electrode material layer to expose the third sacrificial layer to form the lower electrode.

[0016] In one embodiment, the step of patterning the auxiliary layer, the third sacrificial layer, and the top support layer, and removing the third sacrificial layer and the second sacrificial layer further includes: patterning the auxiliary layer, the third sacrificial layer, and the top support layer to form a first opening, the first opening exposing the third sacrificial layer and the second sacrificial layer; and removing the third sacrificial layer and the second sacrificial layer along the first opening to expose the intermediate support layer.

[0017] In one embodiment, the step of patterning the intermediate support layer and removing the first sacrificial layer and the auxiliary layer further includes: patterning the intermediate support layer to form a second opening; removing the first sacrificial layer along the second opening to expose the substrate; and removing the auxiliary layer.

[0018] In one embodiment, the first opening corresponds to the position of the second opening.

[0019] In one embodiment, a bottom support layer is further included, which covers the substrate and exposes the conductive pad. The bottom support layer is exposed after the steps of patterning the intermediate support layer and removing the first sacrificial layer.

[0020] The present invention also provides a semiconductor structure comprising: a substrate having a plurality of conductive pads disposed therein, the substrate being divided into an array region and a peripheral region; a first sacrificial layer, an intermediate support layer, a second sacrificial layer, a top support layer, and a third sacrificial layer stacked on the substrate, wherein the surface of the top support layer located in the array region is flush with the surface of the top support layer located in the peripheral region; a lower electrode disposed in the array region and penetrating the third sacrificial layer, the top support layer, the second sacrificial layer, the intermediate support layer, and the first sacrificial layer, and electrically connected to the conductive pads; and an auxiliary layer covering the third sacrificial layer and the lower electrode.

[0021] The fabrication method of the columnar capacitor array structure of the present invention utilizes photoresist filling before removing the mask layer to adjust the thickness of the mask layer in the peripheral region to be the same as that in the array region. This avoids the influence of different mask layer thicknesses on the thickness of the top support layer, thus preventing loss of the top support layer. Furthermore, the fabrication method of the present invention also forms a third sacrificial layer and an auxiliary layer to provide double protection for the top support layer, preventing it from being thinned in subsequent processes. This increases the support strength of the top support layer, further preventing the columnar capacitor from tilting due to insufficient support strength. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figures 1A to 1D This is a cross-sectional schematic diagram of the semiconductor structure corresponding to the main process of forming the lower electrode of the columnar capacitor array structure provided in the first embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of the steps in the fabrication method of the columnar capacitor array structure provided in the second embodiment of the present invention;

[0025] Figures 3A to 3L This is a schematic cross-sectional view of the main semiconductor structure formed by the preparation method provided in an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical means, and effects of this application clearer, the following description, in conjunction with the accompanying drawings, will further illustrate this application. It should be understood that the embodiments described herein are merely some embodiments of this application, not all embodiments, and are not intended to limit this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0027] Figures 1A to 1D This is a cross-sectional schematic diagram of the semiconductor structure corresponding to the main process of forming the lower electrode of the columnar capacitor array structure provided in the first embodiment of the present invention.

[0028] Please see Figure 1A A substrate 100 is provided. A plurality of conductive pads 101 are disposed within the substrate 100. A first sacrificial layer 110, an intermediate support layer 120, a second sacrificial layer 130, a top support layer 140, and a mask layer 150 are stacked on the substrate 100. The substrate 100 is divided into an array region 100A and a peripheral region 100B. The thickness of the mask layer 150 located in the array region 100A is less than the thickness of the mask layer 150 located in the peripheral region 100B. In the array region 100A, a plurality of capacitor vias 160 penetrate the mask layer 150, the top support layer 140, the second sacrificial layer 130, the intermediate support layer 120, and the first sacrificial layer 110, exposing the conductive pads 101.

[0029] Please see Figure 1B The mask layer 150 is then removed. In this step, since the thickness of the mask layer 150 located in the peripheral region 100B is greater than the thickness of the mask layer 150 located in the array region 100A, completely removing the mask layer 150 in the peripheral region 100B would result in the loss of the top support layer 140 in the array region 100A, making it thinner than in the peripheral region 100B.

[0030] Please see Figure 1C Conductive material 170 is then filled in. The conductive material 170 fills the capacitor holes 160 and covers the surface of the top support layer 140. In this step, the thickness of the conductive material 170 deposited in the peripheral region 100B is greater than the thickness of the conductive material deposited in the array region 100A.

[0031] Please see Figure 1DThe conductive material 170 on the surface of the top support layer 140B is removed, and the lower electrode 180 is formed within the capacitor hole 160. In this step, since the thickness of the conductive material 170 deposited in the peripheral region 100B is greater than the thickness of the conductive material deposited in the array region 100A, completely removing the conductive material in the peripheral region 100B would further thin the thickness of the top support layer 140 in the array region 100A, or even completely remove it. This would result in insufficient support at the top of the subsequently formed columnar capacitors, making them prone to tilting, affecting the performance of the columnar capacitor array structure, and consequently affecting the performance of the memory and reducing the memory yield.

[0032] To address the aforementioned technical problems, the second embodiment of this invention also provides a method for fabricating a columnar capacitor array structure. This method avoids loss of the top support layer, ensures the thickness and support strength of the top support layer, prevents tilting, improves the performance of the columnar capacitor, and thus improves the yield of the memory. Specifically, the method for fabricating the columnar capacitor array structure of this invention uses a photoresist layer to fill the area before removing the mask layer, adjusting the thickness of the mask layer in the peripheral region to be the same as that in the array region. This avoids the impact of different mask layer thicknesses on the thickness of the top support layer, thus preventing loss of the top support layer. Furthermore, the method also forms a third sacrificial layer and an auxiliary layer to provide double protection for the top support layer, preventing it from being thinned in subsequent processes. This increases the support strength of the top support layer, further preventing tilting of the columnar capacitor due to insufficient support strength.

[0033] Figure 2 This is a schematic diagram illustrating the steps of the fabrication method of the columnar capacitor array structure provided in the second embodiment of the present invention. Please refer to [link / reference]. Figure 2The fabrication method includes the following steps: Step S20, providing a substrate, wherein a plurality of conductive pads are disposed within the substrate, and a first sacrificial layer, an intermediate support layer, a second sacrificial layer, a top support layer, and a mask layer are stacked on the substrate. The substrate is divided into an array region and a peripheral region. The thickness of the mask layer located in the array region is less than the thickness of the mask layer located in the peripheral region. In the array region, a plurality of capacitor holes penetrate the mask layer, the top support layer, the second sacrificial layer, the intermediate support layer, and the first sacrificial layer, exposing the conductive pads; Step S21, forming a photoresist layer, wherein the photoresist layer fills the capacitor holes and covers the mask layer in the array region; Step S22, in the peripheral region, removing a portion of the mask layer, wherein the remaining upper surface of the mask layer in the peripheral region is flush with the upper surface of the mask layer in the array region; Step S23, removing the photoresist layer from the surface of the mask layer. Step S23: Using the top support layer as an etching stop layer, etch the mask layer; Step S24: Form a third sacrificial layer, which covers the top support layer; Step S25: Remove the photoresist layer; Step S26: Fill the capacitor hole with conductive material to form a lower electrode, which is electrically connected to the conductive pad; Step S27: Form an auxiliary layer, which covers the third sacrificial layer and the lower electrode; Step S28: Pattern the auxiliary layer, the third sacrificial layer, and the top support layer, and remove the third sacrificial layer and the second sacrificial layer; Step S29: Pattern the intermediate support layer, and remove the first sacrificial layer and the auxiliary layer; Step S30: Form a dielectric layer, which covers the exposed surfaces of the substrate, the lower electrode, the intermediate support layer, and the top support layer; Step S31: Form an upper electrode, which covers the surface of the dielectric layer.

[0034] Figures 3A to 3L This is a schematic cross-sectional view of the main semiconductor structure formed by the preparation method provided in the second embodiment of the present invention.

[0035] Step S20, please refer to Figure 3A A substrate 300 is provided. A plurality of conductive pads 301 are disposed within the substrate 300. A first sacrificial layer 310, an intermediate support layer 320, a second sacrificial layer 330, a top support layer 340, and a mask layer 350 are stacked on the substrate 300. The substrate 300 is divided into an array region 300A and a peripheral region 300B. The thickness of the mask layer 350 located in the array region 300A is less than the thickness of the mask layer 350 located in the peripheral region 300B. In the array region 300A, a plurality of capacitor vias 360 penetrate the mask layer 350, the top support layer 340, the second sacrificial layer 330, the intermediate support layer 320, and the first sacrificial layer 310, exposing the conductive pads 301.

[0036] The substrate 300 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc. The substrate 300 may also be a substrate containing other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. The substrate 300 may also be a stacked structure, such as a silicon / germanium-silicon stack, etc. Furthermore, the substrate 300 may be an ion-doped substrate, which may be P-type doped or N-type doped. Multiple peripheral devices, such as field-effect transistors, capacitors, inductors, and / or pn junction diodes, may also be formed in the substrate 300. In this embodiment, the substrate 300 is a silicon substrate, which also includes other device structures, such as bit line structures and transistor structures, but these are not shown as they are not relevant to this invention.

[0037] In this embodiment, the materials of the first sacrificial layer 310 and the second sacrificial layer 330 can be oxides, such as silicon oxide, and the materials of the intermediate support layer 320 and the top support layer 340 can be nitrides, such as silicon nitride. The material of the mask layer 350 can be polycrystalline silicon.

[0038] In this embodiment, a bottom support layer 370 is further disposed on the substrate 300. The bottom support layer 370 covers the substrate 300 and exposes the conductive pad 301, and the first sacrificial layer 310 covers the bottom support layer 370. The material of the bottom support layer 370 can be a nitride, such as silicon nitride.

[0039] Step S21, please refer to Figure 3B A photoresist layer 380 is formed, which fills the capacitor hole 360 ​​and covers the mask layer 350 of the array region 300A. In this embodiment, the upper surface of the photoresist layer 380 is flush with the upper surface of the mask layer 350 of the peripheral region 300B.

[0040] In this step, a photoresist layer 380 is used to fill the capacitor hole 360 ​​and protect the mask layer 350 of the array region 300A. In some embodiments, a photoresist material layer is first formed, and then the photoresist material layer is etched back to form the photoresist layer 380. Specifically, a photoresist material layer is formed, which fills the capacitor hole 360 ​​and covers the mask layer 350 of the array region 300A and the peripheral region 300B; the photoresist material layer is etched back to expose the mask layer 350 of the peripheral region 300B, and the remaining photoresist material layer serves as the photoresist layer 380.

[0041] Step S22, please refer to Figure 3CIn the peripheral region 300B, a portion of the mask layer 350 is removed, and the upper surface of the remaining mask layer 350 in the peripheral region 300B is flush with the upper surface of the mask layer 350 in the array region 300A.

[0042] In this step, the photoresist layer 380 serves as a shielding layer for the mask layer 350 of the array region 300A. Since the mask layer 350 of the peripheral region 300B is not shielded by the photoresist layer 380, the mask layer 3500 of the peripheral region 300B can be etched and thinned, making the remaining upper surface of the mask layer 350 of the peripheral region 300B flush with the upper surface of the mask layer 350 of the array region 300A. In some embodiments of the present invention, due to limitations in actual processes, when removing the mask layer 350 of the peripheral region 300B, the photoresist layer 380 is also partially removed, i.e., the photoresist layer 380 is also thinned.

[0043] In this step, the etching rate of the etching material on the mask layer 350 is greater than the etching rate on the photoresist layer 380, to avoid the photoresist layer 380 being completely etched. For example, at least one of HBr and NF3 is used as the etching gas to perform dry etching on the mask layer 350, where the etching rate of the HBr and NF3 etching gases on the mask layer 350 is greater than the etching rate on the photoresist layer 380.

[0044] The purpose of this step is to eliminate the height difference between the mask layer 350 of the peripheral region 300B and the array region 300A. The remaining mask layer 350 of the peripheral region 300B has the same thickness as the mask layer 350 of the array region 300A, ensuring that during subsequent removal of the mask layer 350, there is no loss of the top support layer 340 of the array region 300A due to the need to completely remove the mask layer 350 of the peripheral region 300B (e.g., Figure 1B As shown, this is to avoid the thickness of the top support layer 340 of the array region 300A being less than the thickness of the top support layer 340 of the outer region 300B.

[0045] Step S23, please refer to Figure 3D Remove the photoresist layer 380 on the surface of the mask layer 350, and etch the mask layer 350 using the top support layer 340 as the etching stop layer.

[0046] In this step, the photoresist layer 380 on the surface of the mask layer 350 is removed to expose the mask layer 350, and then the mask layer 350 is etched until the top support layer 340 is exposed.

[0047] In this step, a dry etching process is used to remove the mask layer 350. The etching rate of the etchant on the mask layer 350 is greater than the etching rate on the photoresist layer 380 and the top support layer 340, to avoid etching the photoresist layer 380 and the top support layer 340. In this embodiment, the mask layer 350 is a polysilicon mask layer, and the top support layer 340 is a silicon nitride layer. At least one of HBr and NF3 can be used as the etching gas to dry etch the mask layer 350 to remove it. The etching rate of HBr and NF3 on polysilicon is greater than the etching rate on silicon nitride.

[0048] In this step, since the remaining mask layer 350 of the peripheral region 300B has the same thickness as the mask layer 350 of the array region 300A, the top support layer 340 of the peripheral region 300B and the array region 300A are thinned to the same degree, so that after this step, the thickness of the exposed top support layer 340 of the peripheral region 300B and the array region 300A is also the same.

[0049] Step S24, please refer to Figure 3E A third sacrificial layer 390 is formed, which covers the top support layer 340.

[0050] In this step, the third sacrificial layer 390 is deposited on the surface of the top support layer 340. The deposition method can be atomic layer deposition, chemical vapor deposition, spin coating, etc. In some embodiments, limited by the actual process, the third sacrificial layer 390 not only covers the surface of the top support layer 340 but also covers the top of the photoresist layer 380. The third sacrificial layer 390 can be an oxide layer, such as a silicon oxide layer, and the material of the third sacrificial layer 390 can be the same as that of the first sacrificial layer 310 and the second sacrificial layer 330.

[0051] In some embodiments, the method for forming the third sacrificial layer 390 includes the following steps: forming a third sacrificial material layer, the third sacrificial material layer covering the top support layer 340 and the photoresist layer 380; thinning the third sacrificial material layer to expose the photoresist layer 380, thereby forming the third sacrificial layer 390. The method for forming the third sacrificial material layer may be atomic layer deposition, chemical vapor deposition, spin coating, etc.

[0052] Step S25, please refer to Figure 3F Remove the photoresist layer 380.

[0053] Since the third sacrificial layer 390 also covers the top of the photoresist layer 380, in this step, the third sacrificial layer 390 is first thinned to expose the photoresist layer 380, and then the photoresist layer 380 is removed. An ashing process can be used to remove the photoresist layer 380.

[0054] Step S26, please refer to Figure 3G Conductive material is filled into the capacitor hole 360 ​​to form a lower electrode 400, which is electrically connected to the conductive pad 301.

[0055] The conductive material can be titanium nitride or other materials suitable for use as the lower electrode of a columnar capacitor. In this step, the conductive material can be deposited using atomic layer deposition (ALD) to form the lower electrode 400. In some embodiments, due to limitations in the actual process, the conductive material not only fills the capacitor hole 360 ​​but also covers the surface of the third sacrificial layer 390 of the array region 300A and the peripheral region 300B. In this case, the step further includes: forming a lower electrode material layer that not only fills the capacitor hole 360 ​​but also covers the third sacrificial layer 390; thinning the lower electrode material layer to expose the third sacrificial layer 390, with the remaining lower electrode material layer serving as the lower electrode 400. The method for thinning the lower electrode material layer can be etching back to expose the third sacrificial layer 390, retaining only the conductive material located within the capacitor hole 360 ​​to form the lower electrode 400.

[0056] Step S27, please refer to Figure 3H An auxiliary layer 410 is formed, which covers the third sacrificial layer 390 and the lower electrode 400.

[0057] In this step, an auxiliary layer 410 is deposited on the surface of the third sacrificial layer 390 and on top of the lower electrode 400. The auxiliary layer 410 may be a nitride layer, such as a silicon nitride layer. The auxiliary layer 410 and the third sacrificial layer 390 serve as a dual protective layer for the top support layer 340, preventing the top support layer 340 from being thinned in subsequent processes. In addition, the auxiliary layer 410 also protects the lower electrode 400 from damage in subsequent processes.

[0058] Step S28, please refer to Figure 3I The auxiliary layer 410, the third sacrificial layer 390 and the top support layer 340 are patterned, and the third sacrificial layer 390 and the second sacrificial layer 330 are removed.

[0059] Specifically, in this step, the auxiliary layer 410, the third sacrificial layer 390, and the top support layer 340 are patterned to form a first opening 341; the third sacrificial layer 390 and the second sacrificial layer 330 are removed along the first opening 341 to expose the intermediate support layer 320. The process of patterning the auxiliary layer 410, the third sacrificial layer 390, and the top support layer 340 can be photolithography and dry etching, and the method of removing the third sacrificial layer 390 and the second sacrificial layer 330 can be wet etching.

[0060] Step S29, please refer to Figure 3J The intermediate support layer 320 is patterned, and the first sacrificial layer 310 and the auxiliary layer 410 are removed.

[0061] Specifically, in this step, the intermediate support layer 320 is patterned to form a second opening 321. The second opening 321 corresponds in position to the first opening 341. The first sacrificial layer 310 is removed along the second opening 321, exposing the substrate 300. The process for patterning the intermediate support layer 320 can be photolithography and dry etching, and the method for removing the first sacrificial layer 310 can be wet etching.

[0062] In this step, the intermediate support layer 320 and the auxiliary layer 410 are made of the same material. Therefore, in the step of patterning the intermediate support layer 320, the auxiliary layer 410 can be removed simultaneously to expose the top of the lower electrode 400.

[0063] In this embodiment, the bottom support layer 370 is exposed after the first sacrificial layer 310 is removed.

[0064] Step S30, please refer to Figure 3K A dielectric layer 420 is formed, which covers the exposed surfaces of the substrate 300, the lower electrode 400, the intermediate support layer 320, and the top support layer 340.

[0065] The dielectric layer 420 can be a high-k dielectric layer to improve the performance of the cylindrical capacitor. For example, Al2O3, HfO2, Ta2O5, ZrO2 can be formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), or metal-organic chemical vapor deposition (MOCVD) processes.

[0066] Step S31, please refer to Figure 3L An upper electrode 430 is formed, which covers the surface of the dielectric layer 420.

[0067] In this embodiment, the upper electrode 430 fills the gap between the bottom support layer 370, the middle support layer 320, and the top support layer 340, and covers the top support layer 340. The upper electrode 430, the dielectric layer 420, and the lower electrode 400 constitute a columnar capacitor. A plurality of columnar capacitor arrays are arranged to form a columnar capacitor array structure.

[0068] The fabrication method of the columnar capacitor array structure of the present invention utilizes a photoresist layer 380 to fill the area before removing the mask layer, adjusting the thickness of the mask layer 350 in the peripheral region 300B to be the same as that in the array region 300A. This avoids the influence of different mask layer 350 thicknesses on the thickness of the top support layer 340. Furthermore, the fabrication method of the present invention also forms a third sacrificial layer 390 and an auxiliary layer 410 to provide double protection for the top support layer 340, preventing it from being thinned in subsequent processes. This increases the support strength of the top support layer 340, further preventing the columnar capacitor from tilting due to insufficient support strength.

[0069] This invention also provides a semiconductor structure. Please refer to [link / reference]. Figure 3H The semiconductor structure includes a substrate 300, in which a plurality of conductive pads 301 are disposed, and the substrate is divided into an array region 300A and a peripheral region 300B.

[0070] The substrate 300 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc. The substrate 300 may also be a substrate containing other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. The substrate 300 may also be a stacked structure, such as a silicon / germanium-silicon stack, etc. Furthermore, the substrate 300 may be an ion-doped substrate, which may be P-type doped or N-type doped. Multiple peripheral devices, such as field-effect transistors, capacitors, inductors, and / or pn junction diodes, may also be formed in the substrate 300. In this embodiment, the substrate 300 is a silicon substrate, which also includes other device structures, such as bit line structures and transistor structures, but these are not shown as they are not relevant to this invention.

[0071] A first sacrificial layer 310, an intermediate support layer 320, a second sacrificial layer 330, a top support layer 340, and a third sacrificial layer 390 are stacked on the substrate 300. The surface of the top support layer 340 located in the array region 300A is flush with the surface of the top support layer 340 located in the peripheral region 300B.

[0072] In this embodiment, the materials of the first sacrificial layer 310, the second sacrificial layer 330, and the third sacrificial layer 390 can be oxides, such as silicon oxide. The materials of the intermediate support layer 320 and the top support layer 340 can be nitrides, such as silicon nitride.

[0073] In this embodiment, a bottom support layer 370 is further disposed on the substrate 300. The bottom support layer 370 covers the substrate 300 and exposes the conductive pad 301, and the first sacrificial layer 310 covers the bottom support layer 370. The material of the bottom support layer 370 can be a nitride, such as silicon nitride.

[0074] The lower electrode 400 is disposed in the array region 300A and penetrates the third sacrificial layer 390, the top support layer 340, the second sacrificial layer 330, the intermediate support layer 320, and the first sacrificial layer 310, and is electrically connected to the conductive pad 301. The lower electrode 400 may be a titanium nitride electrode. The top of the lower electrode 390 may be flush with the surface of the third sacrificial layer 390.

[0075] The auxiliary layer 410 covers the third sacrificial layer 390 and the lower electrode 400. The auxiliary layer 410 may be a nitride layer, such as a silicon nitride layer. The auxiliary layer 410 and the third sacrificial layer 390 serve as a dual protective layer for the top support layer 340, preventing the top support layer 340 from being thinned in subsequent processes. In addition, the auxiliary layer 410 also protects the lower electrode 400 from damage during subsequent processes.

[0076] In the semiconductor structure of the present invention, the surface of the top support layer 340 located in the array region 300A is flush with the surface of the top support layer 340 located in the peripheral region 300B. The auxiliary layer 410 and the third sacrificial layer 390 serve as a double protective layer for the top support layer 340, preventing the top support layer 340 from being thinned in subsequent processes, ensuring the thickness and support strength of the top support layer 340, and preventing the columnar capacitors formed based on the semiconductor structure from tilting, thereby improving the performance of the subsequently formed memory.

[0077] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a columnar capacitor array structure, characterized in that, include: A substrate is provided, in which a plurality of conductive pads are disposed. A first sacrificial layer, an intermediate support layer, a second sacrificial layer, a top support layer, and a mask layer are stacked on the substrate. The substrate is divided into an array region and a peripheral region. The thickness of the mask layer located in the array region is less than the thickness of the mask layer located in the peripheral region. In the array region, a plurality of capacitor holes penetrate the mask layer, the top support layer, the second sacrificial layer, the intermediate support layer, and the first sacrificial layer to expose the conductive pads. A photoresist layer is formed, which fills the capacitor holes and covers the mask layer of the array region; In the peripheral region, a portion of the mask layer is removed, and the upper surface of the remaining mask layer in the peripheral region is flush with the upper surface of the mask layer in the array region. Remove the photoresist layer from the surface of the mask layer, and etch the mask layer using the top support layer as the etching stop layer; A third sacrificial layer is formed, which covers the top support layer; Remove the photoresist layer; A conductive material is filled into the capacitor hole to form a lower electrode, and the lower electrode is electrically connected to the conductive pad. An auxiliary layer is formed, which covers the third sacrificial layer and the lower electrode; Pattern the auxiliary layer, the third sacrificial layer, and the top support layer, and remove the third sacrificial layer and the second sacrificial layer; Pattern the intermediate support layer and remove the first sacrificial layer and the auxiliary layer; A dielectric layer is formed, which covers the exposed surfaces of the substrate, the lower electrode, the intermediate support layer, and the top support layer; An upper electrode is formed, which covers the surface of the dielectric layer.

2. The method for fabricating the columnar capacitor array structure according to claim 1, characterized in that, The step of forming a photoresist layer, wherein the photoresist layer fills the capacitor holes and covers the mask layer of the array region, further includes: A photoresist material layer is formed, which fills the capacitor hole and covers the mask layer of the array region and the peripheral region; The photoresist material layer is etched back to expose the mask layer of the peripheral region in order to form the photoresist layer.

3. The method for fabricating the columnar capacitor array structure according to claim 2, characterized in that, The upper surface of the photoresist layer is flush with the upper surface of the mask layer in the peripheral region.

4. The method for fabricating the columnar capacitor array structure according to claim 1, characterized in that, In the step of removing the photoresist layer on the surface of the mask layer and using the top support layer as the etching stop layer, the etching rate of the etching material on the mask layer is greater than the etching rate on the top support layer.

5. The method for fabricating the columnar capacitor array structure according to claim 4, characterized in that, The mask layer is a polycrystalline silicon layer, and the top support layer is a silicon nitride layer.

6. The method for fabricating the columnar capacitor array structure according to claim 1, characterized in that, In the step of forming a third sacrificial layer that covers the top support layer, the third sacrificial layer is formed using a spin-coating deposition process.

7. The method for fabricating the columnar capacitor array structure according to claim 6, characterized in that, The third sacrificial layer is an oxide layer.

8. The method for fabricating the columnar capacitor array structure according to claim 1, characterized in that, The step of forming a third sacrificial layer, wherein the third sacrificial layer covers the top support layer, further includes: A third sacrificial material layer is formed, which covers the top support layer and the photoresist layer; The third sacrificial material layer is thinned to expose the photoresist layer in order to form the third sacrificial layer.

9. The method for fabricating the columnar capacitor array structure according to claim 1, characterized in that, The step of filling the capacitor hole with conductive material to form a lower electrode, and electrically connecting the lower electrode to the conductive pad, further includes: A lower electrode material layer is formed, which fills the capacitor hole and covers the third sacrificial layer; The lower electrode material layer is thinned to expose the third sacrificial layer in order to form the lower electrode.

10. The method for fabricating the columnar capacitor array structure according to claim 1, characterized in that, The step of patterning the auxiliary layer, the third sacrificial layer, and the top support layer, and removing the third sacrificial layer and the second sacrificial layer, further includes: The auxiliary layer, the third sacrificial layer, and the top support layer are patterned to form a first opening, which exposes the third sacrificial layer and the second sacrificial layer. The third sacrificial layer and the second sacrificial layer are removed along the first opening to expose the intermediate support layer.

11. The method for fabricating the columnar capacitor array structure according to claim 10, characterized in that, The step of patterning the intermediate support layer and removing the first sacrificial layer and the auxiliary layer further includes: patterning the intermediate support layer to form a second opening; The first sacrificial layer is removed along the second opening to expose the substrate; Remove the auxiliary layer.

12. The method for fabricating the columnar capacitor array structure according to claim 11, characterized in that, The first opening corresponds to the position of the second opening.

13. The method for fabricating the columnar capacitor array structure according to claim 1, characterized in that, It also includes a bottom support layer that covers the substrate and exposes the conductive pad, the bottom support layer being exposed after the steps of patterning the intermediate support layer and removing the first sacrificial layer.

14. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the preparation method according to any one of claims 1-13, comprising: A substrate having a plurality of conductive pads disposed therein, the substrate being divided into an array region and a peripheral region; A first sacrificial layer, an intermediate support layer, a second sacrificial layer, a top support layer, and a third sacrificial layer are stacked on the substrate, with the surface of the top support layer located in the array region being flush with the surface of the top support layer located in the peripheral region. The lower electrode is disposed in the array region and penetrates the third sacrificial layer, the top support layer, the second sacrificial layer, the intermediate support layer and the first sacrificial layer, and is electrically connected to the conductive pad; An auxiliary layer covers the third sacrificial layer and the lower electrode.

15. The semiconductor structure according to claim 14, characterized in that, The surface of the lower electrode is flush with the surface of the third sacrificial layer.

16. The semiconductor structure according to claim 14, characterized in that, The semiconductor structure further includes a bottom support layer that covers the substrate and exposes the conductive pad, and the first sacrificial layer covers the bottom support layer.

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