Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present application relates to the field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprising: a substrate, the substrate having a plurality of spaced-apart word lines, and a groove between adjacent word lines; a bit line contact layer, the bottom surface of the bit line contact layer being in contact with the bottom surface of the groove, and the bit line contact layer having a non-planar contact portion in a direction away from the bottom surface of the groove; and a conductive layer, the conductive layer being in contact with the non-planar contact portion of the bit line contact layer. The embodiment of the present application is at least beneficial to reduce the resistance of the bit line itself comprising the bit line contact layer and the conductive layer, thereby being beneficial to improve the electrical performance of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory in computers, which is composed of a plurality of repeated memory cell devices. DRAM usually takes a storage capacitor and a transistor as a memory cell device to form a two-dimensional matrix, wherein the gate of the transistor is connected with a word line for controlling the conduction or closing of the transistor, and the source and drain of the transistor are connected with a bit line and a storage capacitor respectively, and data is read or stored in the storage capacitor through the bit line.

[0003] However, at present, the bit line usually includes a bit line contact layer and a conductive layer arranged in a stack. With the improvement of the integration of DRAM, the physical size of the bit line is further reduced, and the contact area between the bit line contact layer and the conductive layer is further reduced, which leads to the increase of the contact resistance between the bit line contact layer and the conductive layer, and the decrease of the conductivity of the bit line itself, thereby affecting the electrical performance and access speed of the DRAM.

[0004] Therefore, how to reduce the conductivity of the bit line itself to improve the electrical performance of the DRAM is a technical problem to be solved at present. SUMMARY

[0005] Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which at least have the advantages of reducing the resistance of the bit line including a bit line contact layer and a conductive layer, thereby improving the electrical performance of the semiconductor structure.

[0006] According to some embodiments of the present application, the embodiments of the present application provide a semiconductor structure, comprising: a substrate, the substrate has a plurality of spaced-apart word lines, and a groove is arranged between adjacent word lines; a bit line contact layer, the bottom surface of the bit line contact layer is in contact with the bottom surface of the groove, and the bit line contact layer has a non-planar contact portion in the direction away from the bottom surface of the groove; and a conductive layer, the conductive layer is in contact with the non-planar contact portion of the bit line contact layer.

[0007] According to some embodiments of the present application, the embodiments of the present application further provide a manufacturing method of a semiconductor structure, comprising: providing a substrate, the substrate has a plurality of spaced-apart word lines; forming a groove in the substrate between adjacent word lines; forming a bit line contact layer, the bottom surface of the bit line contact layer is in contact with the bottom surface of the groove, and the bit line contact layer has a non-planar contact portion in the direction away from the bottom surface of the groove; and forming a conductive layer, the conductive layer is in contact with the non-planar contact portion of the bit line contact layer.

[0008] The technical scheme provided by the embodiment of the application has at least the following advantages:

[0009] Since the bit line contact layer has a non-planar contact portion in the direction away from the bottom surface of the trench, the conductive layer is in contact with the non-planar contact portion. On the one hand, the conductive layer and the bit line contact layer are in a mutual embedding relationship, the contact surface between the bit line contact layer and the conductive layer is no longer a plane, but is composed of surfaces in different directions, so that in the plane perpendicular to the direction in which the bit line contact layer points to the conductive layer, the cross-sectional area of the bit line contact layer and the conductive layer in the plane is small (that is, the physical size of the bit line including the bit line contact layer and the conductive layer is small), while the contact area between the bit line contact layer and the conductive layer is increased, thereby reducing the resistance of the bit line including the bit line contact layer and the conductive layer. On the other hand, the conductivity of the bit line contact layer is generally lower than that of the conductive layer, and when the bit line contact layer has a non-planar contact portion and the conductive layer is embedded in the non-planar contact portion, the proportion of the bit line contact layer in the bit line is reduced, thereby improving the overall conductivity of the bit line. The above two aspects are both conducive to reducing the resistance of the bit line itself, thereby improving the electrical performance of the semiconductor structure to improve the access speed of the semiconductor structure. In addition, the second protrusion is embedded in the groove, which is conducive to improving the stability of the connection between the bit line contact layer and the conductive layer. BRIEF DESCRIPTION OF DRAWINGS

[0010] One or more embodiments are illustrated by way of example in the figures that form a part of this disclosure and which are not intended to limit the scope of the embodiments, unless otherwise specifically indicated, the drawings shown in the figures are not to scale.

[0011] Figure 1 A cross-sectional structure schematic diagram of a semiconductor structure provided in an embodiment of the application;

[0012] Figure 2 A cross-sectional structure schematic diagram of a conductive layer in the semiconductor structure shown; Figure 1

[0013] Figure 3 A cross-sectional structure schematic diagram of a bit line contact layer in the semiconductor structure shown; Figure 1

[0014] A cross-sectional structure schematic diagram of a first protrusion and a groove in the semiconductor structure provided in an embodiment of the application; Figures 4 to 12

[0015] A cross-sectional structure schematic diagram of another six cross-sectional structures of the semiconductor structure provided in an embodiment of the application; Figures 13 to 18

[0016] Figures 19 to 22 ​​The manufacturing method of the semiconductor structure provided in another embodiment of the present application includes the steps corresponding to the cross-sectional structure diagrams. DETAILED DESCRIPTION

[0017] As known from the background, the conductivity of the bit line and the electrical performance of the semiconductor structure need to be improved.

[0018] It is found through analysis that the bit line usually includes a bit line contact layer and a conductive layer arranged in a stack. With the improvement of the integration of DRAM, the physical size of the bit line is further reduced. On the one hand, the contact area between the bit line contact layer and the conductive layer is further reduced, which increases the contact resistance between the bit line contact layer and the conductive layer and reduces the conductivity of the bit line itself. On the other hand, the contact area between the bit line contact layer and the substrate is also further reduced, which increases the contact resistance between the bit line and the substrate. On the other hand, the conductivity of the bit line contact layer is usually lower than that of the conductive layer. The greater the proportion of the bit line contact layer in the bit line, the greater the resistance of the bit line as a whole.

[0019] The present application provides a semiconductor structure and a manufacturing method thereof. In the semiconductor structure, the conductive layer is in contact with the non-planar contact portion in the direction away from the bottom surface of the trench, that is, the conductive layer and the bit line contact layer are in a mutual embedding relationship. On the one hand, in the plane perpendicular to the direction in which the bit line contact layer points to the conductive layer, the cross-sectional area of the bit line contact layer and the conductive layer in the plane is small, which is conducive to increasing the contact area between the bit line contact layer and the conductive layer, thereby reducing the resistance of the bit line itself including the bit line contact layer and the conductive layer. On the other hand, the conductive layer is embedded in the non-planar contact portion of the bit line contact layer, which is conducive to reducing the proportion of the bit line contact layer in the bit line, thereby improving the conductivity of the bit line as a whole. The above two aspects are both conducive to reducing the resistance of the bit line itself, thereby improving the electrical performance of the semiconductor structure and the access speed of the semiconductor structure. In addition, the second protrusion is embedded in the groove, which is conducive to improving the stability of the connection between the bit line contact layer and the conductive layer.

[0020] The embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that in the embodiments of the present application, many technical details are proposed in order to make the reader better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0021] Reference Figures 1 to 3 , wherein, Figure 2 is Figure 1 a cross-sectional structure diagram of the conductive layer in the semiconductor structure shown in FIG. 1; Figure 3 is Figure 1 a cross-sectional structure diagram of the bit line contact layer in the semiconductor structure shown in FIG. 1.

[0022] The semiconductor structure comprises: a substrate 100, the substrate 100 has a plurality of spaced-apart word lines 101 therein, and a trench is formed between adjacent word lines 101; a bit line contact layer 112, the bottom surface of the bit line contact layer 112 is in contact with the bottom surface b of the trench, and the bit line contact layer 112 has a non-planar contact portion 132 in a direction away from the bottom surface b of the trench; and a conductive layer 122, the conductive layer 122 is in contact with the non-planar contact portion 132 of the bit line contact layer 112.

[0023] The substrate 100 can include, but is not limited to, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate, or a sapphire substrate. In addition, when the substrate 100 is a single crystal substrate or a polycrystalline substrate, it can also be an intrinsic silicon substrate or a doped silicon substrate. Further, it can be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.

[0024] In some embodiments, the substrate 100 is doped to form a doped region 120 and an undoped non-doped region 110 on the substrate 100, and the word line 101 passes through the doped region 120. The doping ions can be P ions, As ions, or B ions, etc. In other embodiments, the substrate can be entirely a doped region.

[0025] In some embodiments, the word line 101 comprises a metal layer 111 and a diffusion barrier layer 121, the diffusion barrier layer 121 is located at most of the peripheral region of the metal layer 111, which is beneficial to avoid the diffusion of the metal material in the metal layer 111 to the structure adjacent to the word line 101. In addition, the top surface of the word line 101 is covered with a gate insulating layer 141, and the other periphery of the word line 101 is surrounded by a gate oxide layer 131. The diffusion barrier layer 121 can act as an adhesive to make the metal layer 111 and the gate oxide layer 131 have better adhesion. The gate oxide layer 131 and the gate insulating layer 141 are used together to realize the insulation between the word line 101 and other structures in the substrate 100. The material of the metal layer 111 can be at least one of tungsten, aluminum, copper, or titanium, etc. The material of the diffusion barrier layer 121 can be titanium nitride. The material of the gate oxide layer 131 and the material of the gate insulating layer 141 can be at least one of silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0026] In some embodiments, the bit line contact layer 112 and the conductive layer 122 are both components of the bit line 102. The material of the bit line contact layer 112 can be polycrystalline silicon, and the material of the conductive layer 122 can be at least one of tungsten, aluminum, copper, or titanium, etc.

[0027] In some embodiments, the non-planar contact portion 132 of the bit line contact layer 112 has a first protrusion 142 and at least one groove a surrounded by the first protrusion 142, and the conductive layer 122 has a second protrusion 152 at a position corresponding to the groove a, and the second protrusion 152 is embedded in the groove a.

[0028] Since the second protrusion 152 is embedded in the groove a, on the one hand, the bottom surface and the side surface of the groove a are both in contact with the second protrusion 152, which increases the total contact area of the bit line contact layer 112 and the conductive layer 122, and is conducive to reducing the resistance of the bit line 102 while ensuring that the bit line 102 has a small structure size; on the other hand, the bit line contact layer 112 has the groove a, and the second protrusion 152 of the conductive layer 122 fills the groove a, which is conducive to reducing the proportion of the bit line contact layer 112 in the bit line 102, thereby improving the overall conductivity of the bit line 102. The above two aspects are both conducive to reducing the resistance of the bit line 102, thereby improving the electrical performance of the semiconductor structure, and improving the access speed of the semiconductor structure. In addition, the second protrusion 152 is embedded in the groove a, which increases the total contact area of the bit line contact layer 112 and the conductive layer 122, thereby facilitating the increase of the contact force between the bit line contact layer 112 and the conductive layer 122, for example, the side surface of the groove a and the side surface of the second protrusion 152 abut, which hinders the relative sliding between the bit line contact layer 112 and the conductive layer 122 in a direction perpendicular to the side surface of the groove a, thereby improving the stability of the connection between the bit line contact layer 112 and the conductive layer 122.

[0029] In some embodiments, the bottom surface of the conductive layer 122 is higher than the top surface of the word line 101, and the same conductive layer 122 is in contact with at least two non-planar contact portions 132.

[0030] It should be noted that generally, the bit line 102 is located above a plurality of word lines 101, and the extension direction of the bit line 102 is different from the extension direction of the word line 101, and the bit line 102 and the word line 101 are insulated by an insulating material. Figure 1 Taking the bottom surface of the bit line contact layer 112 closest to the bottom surface of the groove lower than the top surface of the word line 101 closest to the conductive layer 122 as an example, when the conductive layer 122 is located above a plurality of word lines 101, the bit line contact layer 112 is only located in the groove between adjacent word lines 101, so as to avoid the case that the bit line contact layer 112 is in contact with the word line 101 along the extension direction of the conductive layer 122, wherein the extension direction of the conductive layer 122 is the extension direction of the bit line 102. Therefore, the same conductive layer 122 is in contact with at least two non-planar contact portions 132 of the bit line contact layer 112, that is, the same bit line 102 includes one conductive layer 122 and at least two bit line contact layers 112.

[0031] In other embodiments, the bottom surface of the bit line contact layer closest to the bottom surface of the trench can be no lower than the top surface of the word line closest to the conductive layer, and in this case the same conductive layer can be in contact with the end portions of at least two bit line contact layers, i.e., the same bit line can include one conductive layer and at least two bit line contact layers. In addition, when the bottom surface of the bit line contact layer closest to the bottom surface of the trench is higher than the top surface of the word line closest to the conductive layer, the bit line contact layer can not only be located in the trench between adjacent word lines, but also be located above a plurality of word lines, and in this case the bit line contact layer and the conductive layer can have the same extension direction, i.e., the same bit line can include one conductive layer and one bit line contact layer. In actual applications, the height relationship between the bottom surface of the bit line contact layer closest to the bottom surface of the trench and the top surface of the word line closest to the conductive layer is not limited.

[0032] In addition, it should be noted that, Figure 1 In the embodiment, the side surface of the trench is formed by the gate oxide layer 131, and in actual applications, the side surface of the trench can also be formed by the substrate.

[0033] The semiconductor structure can further include a protection layer 103 located on the surface formed by the substrate 100 and the gate oxide layer 131, so as to avoid the surface of the substrate 100 being exposed. In some embodiments, the top surface of the first protrusion 142 away from the bottom surface b of the trench is flush with the top surface of the protection layer 103 away from the substrate 100. In other embodiments, the top surface of the first protrusion away from the bottom surface of the trench can also be flush with the surface of the substrate, and it should be noted that in actual applications, the positional relationship between the top surface of the first protrusion away from the bottom surface of the trench and the adjacent structure is not limited. The material of the protection layer 103 can be at least one of silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0034] In some embodiments, referring to Figures 4 to 8 , the number of the first protrusions 142 is 1, and the orthographic projection of the first protrusion 142 on the substrate 100 (referring to Figure 1 ) is an axisymmetric figure.

[0035] Since the orthographic projection of the first protrusion 142 on the substrate 100 is an axisymmetric figure, the central axis of the first protrusion 142 can coincide with the central axis of the cross section of the bit line 102 as shown in Figure 1 , so that the first protrusions 142 are uniformly distributed in the non-planar contact portion 132 of the bit line contact layer 112, and the recesses a surrounded by the first protrusions 142 are also uniformly distributed in the non-planar contact portion 132 of the bit line contact layer 112. In addition, the second protrusions 152 (referring to Figure 2) and the recess a interfit, the central axis of the second protrusion 152 also coincides with the central axis of the recess a. When the bit line 102 is affected by stress and the bit line contact layer 112 and the conductive layer 122 have a tendency of relative sliding, the interaction force between the second protrusion 152 and the first protrusion 142 is evenly distributed on the first protrusion 142 and the second protrusion 152, preventing the deformation of the first protrusion 142 and the second protrusion 152, thereby improving the stability of the connection between the bit line contact layer 112 and the conductive layer 122.

[0036] Wherein, the specific distribution of the first protrusion 142 and the recess a on the non-planar contact part 132 of the bit line contact layer 112 will be described below in combination with Figures 4 to 8 , Figures 4 to 8 Fig. 5 is a schematic diagram of five sectional structures of the first protrusion 142 and the recess a in an embodiment of the present application. It should be noted that, in order to highlight the first protrusion 142 and the recess a, only the first protrusion 142 is pattern filled.

[0037] In some examples, referring to Figure 4 and Figure 5 , the orthographic projection of the first protrusion 142 on the substrate 100 (referring to Figure 1 ) is annular. Wherein, referring to Figure 4 , the orthographic projection of the first protrusion 142 on the substrate 100 is circular, and the orthographic projection of the recess a on the substrate 100 is also circular; or, referring to Figure 5 , the orthographic projection of the first protrusion 142 on the substrate 100 is rectangular, and the orthographic projection of the recess a on the substrate 100 is also rectangular.

[0038] In other examples, referring to Figure 6 , the orthographic projection of the first protrusion 142 on the substrate 100 (referring to Figure 1 ) is cruciform. And the side surfaces of the groove between the first protrusion 142 and the adjacent word line 101 together enclose four recesses a.

[0039] In yet other examples, referring to Figure 7 , the orthographic projection of the outer edge of the first protrusion 142 on the substrate 100 (referring to Figure 1 ) encloses a rectangular pattern, and the orthographic projection of the recess a enclosed by the first protrusion 142 on the substrate 100 is circular.

[0040] In still other examples, referring to Figure 8 , the orthographic projection of the outer edge of the first protrusion 142 on the substrate 100 (referring to Figure 1 ) encloses a circular pattern, and the orthographic projection of the recess a enclosed by the first protrusion 142 on the substrate 100 is rectangular.

[0041] It should be noted that in actual applications, the shape of the pattern surrounded by the orthographic projection of the outer edge of the first protrusion on the substrate is not limited, and the shape of the orthographic projection of the groove surrounded by the first protrusion on the substrate is also not limited, that is, in other embodiments, the orthographic projection of the first protrusion on the substrate can also be an axisymmetric pattern. In addition, in the above examples, the positions of the first protrusion and the groove can be interchanged, as long as the second protrusion corresponding to the groove in the conductive layer is spliced with the first protrusion to form the bit line.

[0042] In other embodiments, referring to Figures 9 to 12 , the number of the first protrusions 142 is at least two, and the combined structure formed by the at least two first protrusions 142 has an axisymmetric pattern in the orthographic projection on the substrate 100 (referring to Figure 1 ). The orthographic projection of the groove a on the substrate 100 is also an axisymmetric pattern.

[0043] Since the combined structure formed by the at least two first protrusions 142 has an axisymmetric pattern in the orthographic projection on the substrate 100, the at least two first protrusions 142 are uniformly distributed in the non-planar contact part 132 of the bit line contact layer 112, and the orthographic projection of the groove a on the substrate 100 is also an axisymmetric pattern, that is, the groove a is also uniformly distributed in the non-planar contact part 132 of the bit line contact layer 112. Therefore, when the second protrusion 152 (referring to Figure 2 ) is spliced with the groove a, and the bit line 102 is affected by stress and has a tendency of relative sliding between the bit line contact layer 112 and the conductive layer 122, the interaction force between the second protrusion 152 and the first protrusion 142 is uniformly distributed on the first protrusion 142 and the second protrusion 152, preventing the deformation of the first protrusion 142 and the second protrusion 152, thereby improving the stability of the connection between the bit line contact layer 112 and the conductive layer 122.

[0044] In the above examples, the specific distribution of the at least two first protrusions 142 and the groove a in the non-planar contact part 132 of the bit line contact layer 112 will be described below in combination with Figures 9 to 12 , Figures 9 to 12 , which are schematic diagrams of four other cross-sectional structures of the first protrusion 142 and the groove a in an embodiment of the present application. It should be noted that, in order to highlight the first protrusion 142 and the groove a, only the first protrusion 142 is pattern-filled.

[0045] In some examples, referring to Figure 9 and Figure 10 , the non-planar contact part 132 of the bit line contact layer 112 has two first protrusions 142, and the orthographic projection of the groove a on the substrate 100 is a ring shape or a cross shape. In the above examples, the specific distribution of the at least two first protrusions 142 and the groove a in the non-planar contact part 132 of the bit line contact layer 112 will be described below in combination with Figure 9, the first protrusions 142 at the outermost edge have a circular ring shape in the projection on the substrate 100, the first protrusions 142 at the center have a circular shape in the projection on the substrate 100, and the groove a has a circular ring shape in the projection on the substrate 100; or, referring to Figure 10 , the first protrusions 142 at the outermost edge have a square ring shape in the projection on the substrate 100, the first protrusions 142 at the center have a rectangular shape in the projection on the substrate 100, and the groove a has a square ring shape in the projection on the substrate 100.

[0046] In other examples, referring to Figure 11 , the non-planar contact portion 132 of the bit line contact layer 112 has four first protrusions 142, and the groove a surrounded by the four first protrusions 142 has a cross shape in the projection on the substrate 100.

[0047] In yet other examples, referring to Figure 12 , the non-planar contact portion 132 of the bit line contact layer 112 has six first protrusions 142, and the first protrusions 142 are arranged in an array, and the first protrusions 142 and the trench side surfaces together form the groove a. Figure 12 In the example in which three first protrusions 142 form a row, and the six first protrusions 142 together form two columns, each first protrusion 142 has a circular shape in the projection on the substrate 100. In actual applications, the number of rows and the number of columns of the plurality of first protrusions, the number of first protrusions included in each row or each column, and the shape of the projection of the first protrusions on the substrate are not limited.

[0048] In addition, it should be noted that, in actual applications, the shape of the projection on the substrate of the combined structure formed by the at least two first protrusions is not limited, and the shape of the projection on the substrate of the groove surrounded by the at least two first protrusions is also not limited. In other embodiments, the projection on the substrate of the combined structure formed by the at least two first protrusions can also not be an axisymmetric figure. In addition, in the above examples, the positions of the first protrusions and the groove can be transposed, as long as the second protrusions corresponding to the groove in the conductive layer are spliced with the first protrusions to form the bit line.

[0049] In the above various embodiments, on the one hand, referring to Figure 1 and Figure 13 , in the direction perpendicular to the surface of the substrate 100, the bottom surface of a single groove a can have at least two regions with different depths.

[0050] Since the bottom surface of a single groove a can have at least two regions with different depths, it is beneficial to further increase the second protrusions 152 (referring to Figure 2) and the total contact area at the contact between the groove a and the second protrusion 152 (refer to FIG. 1C), on one hand, is conducive to reducing the contact resistance between the bit line contact layer 112 and the conductive layer 122, so as to reduce the resistance of the bit line 102 itself, thereby improving the electrical performance and access speed of the semiconductor structure; on the other hand, is conducive to increasing the contact force between the bit line contact layer 112 and the conductive layer 122, so as to avoid the relative sliding between the bit line contact layer 112 and the conductive layer 122, thereby improving the stability of the connection between the bit line contact layer 112 and the conductive layer 122.

[0051] In the present application, the specific shape of the bottom surface of the single groove a will be described below in combination with Figure 1 and Figures 13 to 14 . Figure 1 and Figures 13 to 14 are three cross-sectional structure schematic diagrams of the specific shape of the bottom surface of the single groove a in an embodiment of the present application.

[0052] In some examples, continuing to refer to Figure 1 , the bottom surface of the groove a can be a concave surface recessed towards the substrate 100. In this way, it is conducive to further reducing the volume of the bit line contact layer 112, thereby reducing the proportion of the bit line contact layer 112 in the bit line 102, so as to improve the conductivity of the bit line 102 itself, thereby facilitating the improvement of the electrical performance and access speed of the semiconductor structure.

[0053] In other examples, referring to Figure 13 , the bottom surface of the groove a can be in a wavy shape. In this way, it is conducive to further increasing the total contact area at the contact between the groove a and the second protrusion 152 (refer to Figure 2 ) and the groove a, thereby reducing the contact resistance between the bit line contact layer 112 and the conductive layer 122, so as to reduce the resistance of the bit line 102 itself, thereby improving the electrical performance and access speed of the semiconductor structure.

[0054] In yet other embodiments, referring to Figure 14 , the non-planar contact part 132 (refer to Figure 3 ) is located in the groove, and the non-planar contact part 132 is a convex surface protruding away from the bottom surface b of the groove. In this way, it is also conducive to increasing the total contact area at the contact between the bit line contact layer 112 and the conductive layer 122, thereby reducing the contact resistance between the bit line contact layer 112 and the conductive layer 122, so as to reduce the resistance of the bit line 102 itself, thereby improving the electrical performance and access speed of the semiconductor structure.

[0055] In other embodiments, the bottom surface of the groove can be in a stepped shape, and correspondingly, the second protrusion mutually jointed with the groove is also in a stepped shape, which is conducive to increasing the volume of the conductive layer, so as to increase the proportion of the conductive layer in the bit line, thereby facilitating the reduction of the resistance of the bit line itself, thereby facilitating the improvement of the electrical performance and access speed of the semiconductor structure. In other embodiments, the bottom surface of the groove can be in a stepped shape, and correspondingly, the second protrusion mutually jointed with the groove is also in a stepped shape, which is conducive to increasing the volume of the conductive layer, so as to increase the proportion of the conductive layer in the bit line, thereby facilitating the reduction of the resistance of the bit line itself, thereby facilitating the improvement of the electrical performance and access speed of the semiconductor structure.

[0056] It should be noted that, in combination with reference to Figure 3 , Figure 1 and Figures 13 to 14 , it is exemplified that the first protrusion 142 has a region with the same width in the direction perpendicular to the sidewall of the trench at the end away from the substrate 100. In actual applications, the width of the first protrusion can gradually decrease in the direction away from the substrate in the direction perpendicular to the sidewall of the trench.

[0057] In the above various embodiments, on the other hand, reference is made to Figure 15 and Figure 16 . The non-planar contact portion 132 (reference is made to Figure 3 ) can have at least two grooves a arranged at intervals. In this way, it is beneficial to further increase the contact force between the bit line contact layer 112 and the conductive layer 122, avoid the relative sliding between the bit line contact layer 112 and the conductive layer 122, and thus improve the stability of the connection between the bit line contact layer 112 and the conductive layer 122.

[0058] In which, the specific arrangement of the depth of the at least two grooves a will be described below in combination with Figure 15 and Figure 16 , Figure 15 and Figure 16 are two cross-sectional structure diagrams of the specific arrangement of the depth of the at least two grooves a in an embodiment of the present application.

[0059] In some examples, reference is made to Figure 15 . The non-planar contact portion 132 can have four grooves a arranged at intervals, and the depth of each groove a is the same in the direction Z perpendicular to the surface of the substrate 100. It should be noted that Figure 15 four is exemplified, and in actual applications, the number of grooves a is not limited, and the arrangement of the plurality of grooves a is not limited.

[0060] In other examples, reference is made to Figure 16 . The non-planar contact portion 132 can have four grooves a arranged at intervals, and the depth of each groove a is different in the direction Z perpendicular to the surface of the substrate 100. In actual applications, the depth of some grooves can be the same, and the depth of some grooves can be different.

[0061] In addition, on the basis of the above various embodiments, reference is made to Figure 17 and Figure 18In the direction perpendicular to the surface of the substrate 100, the bottom surface b of the trench can have at least two regions with different depths. In this way, the contact area of the substrate 100 below the bottom surface b of the trench and the bit line contact layer 112 is increased, so as to reduce the contact resistance between the bit line contact layer 112 and the substrate 100 below the bottom surface b of the trench, thereby improving the electrical performance and access speed of the semiconductor structure.

[0062] In the following, the specific shape of the bottom surface b of the trench will be described in detail with reference to Figure 17 and Figure 18 . Figure 17 and Figure 18 are schematic diagrams of two cross-sectional structures of the specific shape of the bottom surface of the trench in an embodiment of the present application.

[0063] In some examples, with reference to Figure 17 , the bottom surface b of the trench can be a convex surface protruding towards the bit line contact layer 112. In this way, the volume of the bit line contact layer 112 is further reduced, so as to further reduce the proportion of the bit line contact layer 112 in the bit line 102, thereby reducing the resistance of the bit line 102 itself, and improving the electrical performance and access speed of the semiconductor structure.

[0064] In other examples, with reference to Figure 18 , the bottom surface b of the trench can be wavy. In other examples, the bottom surface of the trench can also be stepped.

[0065] It should be noted that in actual applications, the substrate below the bottom surface of the trench can have a third protrusion corresponding to the second protrusion of the conductive layer, i.e. various shapes included in the second protrusion can be applied to the third protrusion. In addition, the end of the bit line contact layer in contact with the bottom surface of the trench can have a fourth protrusion corresponding to the first protrusion, i.e. various shapes included in the first protrusion can be applied to the fourth protrusion

[0066] In summary, the second protrusion 152 is embedded in the groove a, on one hand, in a plane perpendicular to the bit line contact layer 112 and pointing to the conductive layer 122, the cross-sectional area of the bit line contact layer 112 and the conductive layer 122 in the plane is small, and the contact area between the bit line contact layer 112 and the conductive layer 122 is increased, thereby reducing the resistance of the bit line 102 itself; on the other hand, the bit line contact layer 112 has a groove a, and the second protrusion 152 of the conductive layer 122 fills the groove a, which is conducive to reducing the proportion of the bit line contact layer 112 in the bit line 102, thereby improving the overall conductivity of the bit line 102. The above two aspects are conducive to reducing the resistance of the bit line 102 itself, thereby improving the electrical performance of the semiconductor structure to improve the access speed of the semiconductor structure. In addition, the second protrusion 152 is embedded in the groove a, which is conducive to improving the stability of the connection between the bit line contact layer 112 and the conductive layer 122.

[0067] Another embodiment of the present application also provides a manufacturing method of a semiconductor structure, which can be used to manufacture the semiconductor structure provided in the above embodiments. The manufacturing method of the semiconductor structure provided in another embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0068] Figures 19 to 22 The manufacturing method of the semiconductor structure provided in another embodiment of the present application includes the following steps.

[0069] Reference Figures 19 to 22 The manufacturing method of the semiconductor structure includes the following process steps:

[0070] Reference Figure 19 A substrate 100 is provided, and the substrate 100 has a plurality of spaced-apart word lines 101; a groove c is formed in the substrate 100 between adjacent word lines 101.

[0071] In some embodiments, the substrate 100 includes a doped region 120 and an undoped non-doped region 110; the word line 101 includes a metal layer 111 and a diffusion barrier layer 121; the top surface of the word line 101 is covered with a gate insulating layer 141, and the other periphery of the word line 101 is surrounded by a gate oxide layer 131; the bit line contact layer 112 and the conductive layer 122 are both components of the bit line 102; the semiconductor structure can also include a protective layer 103 on the surface formed by the substrate 100 and the gate oxide layer 131. The details of the above structures are the same as those of the previous embodiments and will not be repeated here.

[0072] It should be noted that, Figure 19 For example, etching the substrate 100 to expose part of the sidewall of the gate oxide layer 131, in actual application, the sidewall of the groove formed in the step of etching the substrate to form the groove can also be composed of the substrate.

[0073] In combination with reference to Figure 3 and Figures 20 to 22 , a bit line contact layer 112 is formed, the bottom surface of the bit line contact layer 112 is in contact with the bottom surface b of the trench, and the bit line contact layer 112 has a non-planar contact portion 132 in a direction away from the bottom surface b of the trench.

[0074] In some embodiments, forming the bit line contact layer 112 can include the following process steps:

[0075] In combination with reference to Figure 20 , an initial bit line contact layer 162 is formed to fill the trench c (refer to Figure 19 ). When the surface of the substrate 100 has the protective layer 103, the initial bit line contact layer 162 is flush with the top surface of the protective layer 103 away from the top surface of the substrate 100. In other embodiments, when the surface of the substrate is exposed, the initial bit line contact layer can be flush with the surface of the substrate away from the top surface of the substrate.

[0076] In combination with reference to Figure 21 , a mask layer 104 is formed on the surface formed by the substrate 100 and the initial bit line contact layer 162, and the mask layer 104 has an opening exposing at least part of the surface of the initial bit line contact layer 162. It should be noted that the number of openings in the mask layer 104 can be one or at least two, and the shape of the orthographic projection of the plurality of openings in the mask layer 104 on the substrate 100 and the arrangement of the plurality of openings are not limited by the embodiments of the present application.

[0077] The material of the mask layer 104 includes at least one of a hard mask material such as silicon nitride, silicon oxide, or silicon oxynitride, and the method of forming the mask layer 104 includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0078] In combination with reference to Figure 3 and Figures 21 to 22 , the initial bit line contact layer 162 is etched to form the bit line contact layer 112 using the mask layer 104 as a mask, and the mask layer 104 is removed.

[0079] In some embodiments, the non-planar contact portion 132 has a first protrusion 142 and at least one groove a surrounded by the first protrusion 142, and the subsequently formed conductive layer has a second protrusion at a position corresponding to the groove a, and the second protrusion is embedded in the groove a. In some embodiments, the material of the initial bit line contact layer 162 is polysilicon, the method of etching the initial bit line contact layer 162 includes a dry etching process, and the etching gas includes carbon tetrafluoride and argon.

[0080] With the dry etching process, the depth of the groove a gradually deepens in the direction Z perpendicular to the surface of the substrate 100. The etching gas first contacts the sidewall of the groove a and then reaches the bottom surface of the groove a. The probability of the etching gas reacting with the sidewall of the groove a is greater than that of reacting with the bottom surface of the groove a, so that the bottom surface of the groove a is recessed towards the bottom surface b of the trench.

[0081] The ratio of the gas flow of the carbon tetrafluoride to the gas flow of the argon is 3-6. For example, the ratio of the gas flow of the carbon tetrafluoride to the gas flow of the argon is 5, which is conducive to ensuring that the formed bit line contact layer 112 has high dimensional accuracy and the etching rate of the substrate 100 is high, thereby improving the efficiency of forming the bit line contact layer 112.

[0082] In some embodiments, the material of the mask layer 104 is silicon nitride, and the silicon nitride can be etched and removed by hot phosphoric acid. In other embodiments, the material of the mask layer 104 is silicon oxide, and the silicon nitride can be etched and removed by dilute hydrofluoric acid, for example, the ratio of hydrofluoric acid to water is 1:300.

[0083] In addition, the depth of the groove a in the direction Z perpendicular to the surface of the substrate 100 is 3-7 nm. It should be noted that the depth of the groove a refers to the distance between the groove a closest to the bottom surface b of the trench and the top surface of the bit line contact layer 112 away from the substrate 100. For example, the depth of the groove a can be 5 nm to ensure that the subsequently formed bit line has a suitable size.

[0084] In other embodiments, after the initial groove is etched to form the initial groove with the mask layer as the mask, the initial groove can be etched again to form a groove with a wavy, stepped or other shape bottom surface.

[0085] In some examples, after forming the trenches, the substrate exposed by the trenches can be processed to form a substrate with a local region protruding towards the opening direction of the trenches before forming the initial bit line contact layer. For example, a first mask layer is formed on the bottom surface and sidewall of the trenches, and the first mask layer surrounds a through hole; a second mask layer is formed to fill the through hole; the first mask layer is etched to expose part of the substrate by taking the second mask layer as a mask; the part of the substrate is etched, and then the second mask layer is removed, so as to form a substrate with a local region protruding towards the opening direction of the trenches. It should be noted that the above description is only an exemplary description of how to form a substrate with a local region protruding towards the opening direction of the trenches, and the embodiments of the present application do not limit the method of forming a substrate with a local region protruding towards the opening direction of the trenches.

[0086] Reference Figures 1 to 3 The conductive layer 122 is formed, the conductive layer 122 is in contact with the non-planar contact part 132 of the bit line contact layer 112, and the conductive layer 122 has a second protrusion 152 corresponding to the position of the groove a, and the second protrusion 152 is embedded in the groove a.

[0087] The material of the conductive layer 122 can be at least one of tungsten, aluminum, copper or titanium, and the bit line contact layer 112 and the conductive layer 122 are both components of the bit line 102.

[0088] In summary, by forming the bit line contact layer 112 with the first protrusion 142 and the groove a, and the conductive layer 122 with the second protrusion 152, the second protrusion 152 is embedded in the groove a. On the one hand, in the plane perpendicular to the direction of the bit line contact layer 112 pointing to the conductive layer 122, it is ensured that the cross-sectional area of the bit line contact layer 112 and the conductive layer 122 in the plane is small, and it is beneficial to increase the contact area between the bit line contact layer 112 and the conductive layer 122, thereby reducing the resistance of the bit line 102 itself; on the other hand, the bit line contact layer 112 has the groove a, and the second protrusion 152 of the conductive layer 122 fills the groove a, which is beneficial to reduce the proportion of the bit line contact layer 112 in the bit line 102, thereby improving the overall conductivity of the bit line 102. The above two aspects are both beneficial to reduce the resistance of the bit line 102 itself, thereby improving the electrical performance of the semiconductor structure to improve the access speed of the semiconductor structure. In addition, the second protrusion 152 is embedded in the groove a, which is beneficial to improve the stability of the connection between the bit line contact layer 112 and the conductive layer 122.

[0089] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized by, The application relates to a memory device, comprising: a substrate, the substrate having a plurality of spaced-apart word lines, and a trench between adjacent word lines; a bit line contact layer, the bottom surface of the bit line contact layer being in contact with the bottom surface of the trench, and the bit line contact layer having a non-planar contact portion in a direction away from the bottom surface of the trench; a conductive layer, the conductive layer being in contact with the non-planar contact portion of the bit line contact layer.

2. The semiconductor structure of claim 1, wherein, The non-planar contact portion has a first protrusion and at least one groove formed by the first protrusion, the conductive layer has a second protrusion at a position corresponding to the groove, the second protrusion is embedded in the groove, and the bottom surface of the conductive layer is higher than the top surface of the word line, and the same conductive layer is in contact with at least two non-planar contact portions.

3. The semiconductor structure of claim 2, wherein, The number of the first protrusions is at least two, and the combined structure formed by the at least two first protrusions is an axisymmetric pattern in the projection of the substrate.

4. The semiconductor structure of claim 2, wherein, The number of the first protrusions is one, and the first protrusion is an axisymmetric pattern in the projection of the substrate.

5. The semiconductor structure of claim 4, wherein, The first protrusion is a ring or a cross in the projection of the substrate.

6. The semiconductor structure of claim 2, wherein, In a direction perpendicular to the surface of the substrate, the bottom surface of the single groove has at least two regions with different depths.

7. The semiconductor structure of claim 6, wherein, The bottom surface of the groove is a concave surface recessed towards the substrate.

8. The semiconductor structure of claim 1, wherein, The non-planar contact portion has at least two spaced-apart grooves, and in a direction perpendicular to the surface of the substrate, the depths of the grooves are different.

9. The semiconductor structure of claim 2 or 8, wherein, The projection of the groove on the substrate is an axisymmetric pattern.

10. The semiconductor structure of claim 2 or 8, wherein, The projection of the groove on the substrate is a ring or a cross.

11. The semiconductor structure of claim 1, wherein, In a direction perpendicular to the surface of the substrate, the bottom surface of the trench has at least two regions with different depths.

12. The semiconductor structure of claim 1, wherein, The non-planar contact portion is located in the trench, and the non-planar contact portion is a convex surface protruding away from the bottom surface of the trench.

13. A method of manufacturing a semiconductor structure, characterized by, The application relates to a manufacturing method of a memory device, comprising: providing a substrate, the substrate having a plurality of spaced-apart word lines; forming a trench in the substrate between adjacent word lines; forming a bit line contact layer, the bottom surface of the bit line contact layer being in contact with the bottom surface of the trench, and the bit line contact layer having a non-planar contact portion in a direction away from the bottom surface of the trench; forming a conductive layer, the conductive layer being in contact with the non-planar contact portion of the bit line contact layer.

14. The production method according to claim 13, wherein The step of forming the bit line contact layer comprises: forming an initial bit line contact layer filling the trench; forming a mask layer on the surface formed by the substrate and the initial bit line contact layer, the mask layer having an opening exposing at least part of the surface of the initial bit line contact layer; etching the initial bit line contact layer to form the bit line contact layer having the non-planar contact portion, and the non-planar contact portion has a first protrusion and at least one groove formed by the first protrusion; the conductive layer has a second protrusion at a position corresponding to the groove, and the second protrusion is embedded in the groove.

15. The production method according to claim 14, wherein The material of the initial bit line contact layer is polysilicon, the method of etching the initial bit line contact layer comprises a dry etching process, and the etching gas comprises carbon tetrafluoride and argon.

16. The production method according to claim 15, wherein The ratio of the gas flow rate of carbon tetrafluoride to the gas flow rate of argon is 3-6.

17. The production method according to claim 14, wherein The depth of the groove is 3-7 nm in the direction perpendicular to the surface of the substrate.

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