Semiconductor structure and method of manufacturing the same
By forming cross trenches in the semiconductor structure and creating air gaps between adjacent word lines, the parasitic capacitance problem caused by the large dielectric constant of the dielectric layer is solved, thereby improving the operating speed of the semiconductor structure.
Patent Information
- Application Number
- CN202110980473.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-08-25
- Publication Date
- 2026-01-16
- Estimated Expiration
- 2041-08-25
AI Technical Summary
In existing semiconductor devices, the dielectric constant of the dielectric layer between adjacent word lines is relatively large, resulting in large parasitic capacitance and affecting the operating speed.
A cross-groove structure is formed within the substrate. By creating an air gap between adjacent word lines, the dielectric constant is reduced. A wet etching process is used to form a hole structure and deposit word lines therein. The sacrificial layer is then removed to form the air gap.
This reduces the parasitic capacitance between adjacent word lines in the semiconductor structure, thereby improving the performance of the semiconductor structure.
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Figure CN116133379B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND
[0002] A semiconductor device, such as a memory, includes a plurality of word lines arranged adjacent to each other, and adjacent word lines are separated by a dielectric layer.
[0003] However, the dielectric constant of the dielectric layer is large, so that there is a large parasitic capacitance between adjacent word lines, which affects the operating speed of the semiconductor device. SUMMARY
[0004] In view of the above, the embodiments of the present application provide a semiconductor structure and a manufacturing method thereof to solve at least one problem in the background art.
[0005] To achieve the above object, the technical scheme of the present application is as follows:
[0006] The embodiments of the present application provide a manufacturing method of a semiconductor structure, comprising:
[0007] forming a plurality of first grooves filled with a first dielectric layer and extending along a first direction in a substrate;
[0008] forming a plurality of second grooves extending along a second direction in the substrate and the first dielectric layer, the second grooves and the first grooves intersecting each other and defining a plurality of discrete active pillars in the substrate;
[0009] depositing a second dielectric layer on the sidewalls of the second grooves;
[0010] depositing a sacrificial layer in the second grooves, the sacrificial layer being sandwiched between the second dielectric layers;
[0011] removing part of the first dielectric layer and part of the second dielectric layer to form a plurality of hole structures extending along the second direction, the hole structures surrounding the active pillars, and adjacent hole structures being separated by the sacrificial layer;
[0012] forming word lines in the hole structures;
[0013] removing the sacrificial layer to form an air gap between adjacent word lines.
[0014] In the above scheme, the first grooves define the substrate as a plurality of structures extending along the first direction; before forming the second grooves, the method further comprises:
[0015] performing ion implantation on the substrate to form first and second source / drain doped regions on the top and bottom of the structures, respectively.
[0016] In the above solution, after the second dielectric layer is deposited on the sidewall of the second trench, the method further comprises:
[0017] The substrate is doped from the bottom of the second trench to form a plurality of bit lines extending in a first direction, and the adjacent bit lines are separated by the first dielectric layer.
[0018] In the above solution, after the sacrificial layer is deposited in the second trench, the method further comprises:
[0019] A separation layer is deposited in the second trench, the separation layer is located above the sacrificial layer, and both sides of the separation layer are adjacent to the second dielectric layer.
[0020] In the above solution, before the part of the first dielectric layer and the part of the second dielectric layer are removed to form a plurality of hole structures extending in a second direction, the method further comprises:
[0021] The first dielectric layer and the second dielectric layer with a preset thickness are removed to expose the side surface of the separation layer and part of the side surface of the active pillar; wherein the preset thickness is greater than or equal to the thickness of the separation layer;
[0022] A third dielectric layer is deposited on the side surface of the separation layer and the part of the side surface of the active pillar.
[0023] In the above solution, the third dielectric layer has a plurality of first openings exposing the first dielectric layer; forming a plurality of hole structures extending in a second direction comprises: removing part of the first dielectric layer and part of the second dielectric layer from the first openings by a wet etching process to form the hole structures.
[0024] In the above solution, before the word line is formed in the hole structure, the method comprises:
[0025] A gate dielectric layer is formed on the surface of the active pillar surrounded by the hole structure.
[0026] In the above solution, before the sacrificial layer is removed, the method further comprises:
[0027] A fourth dielectric layer is deposited on the substrate, the fourth dielectric layer covers at least the upper surface of the substrate and the word line.
[0028] In the above solution, the substrate comprises a storage area and a peripheral area; removing the sacrificial layer comprises:
[0029] From the upper surface of the fourth dielectric layer, etching down to the sacrificial layer to form at least one second opening, the second opening is located in the peripheral area.
[0030] The sacrificial layer is removed by a wet etching process.
[0031] The application also provides a semiconductor structure, comprising:
[0032] a substrate, the substrate comprising a plurality of first trenches extending in a first direction and a plurality of second trenches extending in a second direction, the first trenches and the second trenches intersecting each other in the substrate to define a plurality of discrete active pillars;
[0033] a first dielectric layer at the bottom of the first trenches;
[0034] a second dielectric layer covering the sidewalls of the bottom of the second trenches;
[0035] an air gap in the second trenches;
[0036] a plurality of word lines extending in the second direction in the first trenches and the second trenches, the word lines surrounding the active pillars and covering the upper surfaces of the first dielectric layer and the second dielectric layer;
[0037] wherein adjacent word lines are separated by the air gap.
[0038] In the above scheme, the air gap extends in the second direction, the upper surface of the air gap is flush with or higher than the upper surface of the word line, and the air gap has a uniform width and height in the extending direction.
[0039] In the above scheme, the air gap extends to the bottom of the second trenches in a direction perpendicular to the substrate, and the second dielectric layer is located on both sides of the air gap.
[0040] In the above scheme, the semiconductor structure further comprises an isolation layer, the isolation layer being located in the second trenches and above the air gap.
[0041] In the above scheme, the semiconductor structure further comprises a third dielectric layer, the third dielectric layer being located above the word lines and covering the side surfaces of the isolation layer and part of the side surfaces of the active pillars.
[0042] In the above scheme, the semiconductor structure further comprises a fourth dielectric layer, the fourth dielectric layer covering at least the upper surfaces of the substrate and the word lines.
[0043] In the above scheme, the semiconductor structure further comprises a gate dielectric layer, the gate dielectric layer being located between the word lines and the active pillars.
[0044] In the scheme, the semiconductor structure further comprises a plurality of bit lines extending along the first direction, the bit lines are formed by doping the bottom of the second trenches, and the adjacent bit lines are separated by the first dielectric layer.
[0045] In the scheme, the semiconductor structure further comprises a first source / drain doped region and a second source / drain doped region, the first source / drain doped region is located at the top of the active pillar, and the second source / drain doped region is located at the bottom of the active pillar.
[0046] The semiconductor structure and the manufacturing method thereof provided by the embodiments of the present application, wherein the manufacturing method comprises: forming a plurality of first trenches filled with a first dielectric layer and extending along a first direction in a substrate; forming a plurality of second trenches extending along a second direction in the substrate and the first dielectric layer, the second trenches and the first trenches intersect with each other and define a plurality of discrete active pillars in the substrate; depositing a second dielectric layer on the sidewalls of the second trenches; depositing a sacrificial layer in the second trenches, the sacrificial layer is sandwiched between the second dielectric layers; removing part of the first dielectric layer and part of the second dielectric layer to form a plurality of hole structures extending along the second direction, the hole structures surround the active pillars, and the adjacent hole structures are separated by the sacrificial layer; forming word lines in the hole structures; and removing the sacrificial layer to form air gaps between the adjacent word lines. The air gaps have a lower dielectric constant, which can reduce the parasitic capacitance between the adjacent word lines in the semiconductor structure, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS
[0047] Figure 1 The flow chart of the manufacturing method of the semiconductor structure provided by the embodiments of the present application is shown in the figure;
[0048] Figure 2 The top view schematic diagram of the semiconductor structure provided by the embodiments of the present application is shown in the figure;
[0049] Figures 3a to 15d The process flow chart of the semiconductor structure provided by the embodiments of the present application is shown in the figure. DETAILED DESCRIPTION
[0050] The exemplary embodiments of the present application will be described in detail with reference to the drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms, and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application can be accurately conveyed to those skilled in the art.
[0051] In the following description, numerous specific details are given to provide a thorough understanding of the application. However, it will be apparent that the application can be practiced without one or more of the specific details. In other instances, well-known
[0052] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numerals can represent like elements throughout the several figures.
[0053] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms since such terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section.
[0054] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0056] The dynamic random memory (DRAM) with vertical transistors provided in the related art includes a plurality of word lines extending in the same direction, and a dielectric layer is arranged between adjacent word lines. However, the dielectric layer has a large dielectric constant, so that a large parasitic capacitance exists between adjacent word lines, which reduces the access speed of data and affects the performance of the dynamic random memory.
[0057] Based on this, the embodiment of the present application provides a manufacturing method of a semiconductor structure, please refer to Figure 1 As shown in the figure, the method comprises the following steps:
[0058] Step 101, forming a plurality of first grooves filled with a first dielectric layer and extending in a first direction in a substrate;
[0059] Step 102, forming a plurality of second grooves extending in a second direction in the substrate and the first dielectric layer, the second grooves and the first grooves intersect with each other, and a plurality of discrete active pillars are defined in the substrate;
[0060] Step 103, depositing a second dielectric layer on the sidewall of the second groove;
[0061] Step 104, depositing a sacrificial layer in the second groove, the sacrificial layer is sandwiched between the second dielectric layer;
[0062] Step 105, removing part of the first dielectric layer and part of the second dielectric layer to form a plurality of hole structures extending in the second direction, the hole structures surround the active pillars, and adjacent hole structures are separated by the sacrificial layer;
[0063] Step 106, forming a word line in the hole structure;
[0064] Step 107, removing the sacrificial layer to form an air gap between adjacent word lines.
[0065] The semiconductor structure manufacturing method provided in this application forms an air gap with a low dielectric constant between adjacent word lines, which can reduce the parasitic capacitance between adjacent word lines of the semiconductor structure, thereby improving the performance of the semiconductor structure.
[0066] The semiconductor structure manufacturing method provided in this application embodiment can be used to form dynamic random access memory (DRAM). However, it is not limited to this; any semiconductor structure with a vertical full-ring gate (VGAA) can be manufactured using the method provided in this application embodiment.
[0067] Figure 2 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of this application; Figures 3a to 15d This is a process flow diagram of the semiconductor structure provided in the embodiments of this application; wherein, Figures 3a-3d For each process step along Figure 2 A schematic diagram of the cross-sectional structure taken by line AA'. Figures 3b-3d For each process step along Figure 2 A schematic diagram of the cross-sectional structure taken from line BB'. Figures 3c-3d For each process step along Figure 2 A schematic diagram of the cross-sectional structure taken by line CC'. Figures 3d-3d For each process step along Figure 2 A cross-sectional structural diagram taken from line DD'. The manufacturing method of the semiconductor structure provided in the embodiments of this application will be further described in detail below with reference to the accompanying drawings. In the detailed description of the embodiments of this application, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this application.
[0068] First, step 101 is performed to form a plurality of first trenches T1, which are filled with a first dielectric layer 21 and extend along a first direction, within the substrate 20, such as... Figures 3a-3d As shown.
[0069] The substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.
[0070] Specifically, forming a plurality of first trenches T1 filled with a first dielectric layer 21 and extending along a first direction in the substrate 20 includes: performing an etching process on the substrate 20 to form a plurality of first trenches T1 extending along the first direction; and filling the first trenches T1 with the first dielectric layer 21.
[0071] The etching process includes, but is not limited to, a self-aligned double patterning process (SADP) and a self-aligned quadruple patterning process (SAQP). In some embodiments, the first trenches T1 are equally spaced in the substrate 20.
[0072] In one embodiment, the first dielectric layer 21 is made of an oxide, such as silicon oxide. The first dielectric layer 21 can be formed in the first trenches T1 by atomic layer deposition (ALD), chemical vapor deposition (CVD), or the like. Optionally, after the first dielectric layer 21 is formed in the first trenches T1, a planarization process, such as chemical mechanical polishing (CMP) and / or an etching process, can be performed to make the upper surface of the first dielectric layer 21 coplanar with the upper surface of the substrate 20.
[0073] Referring to Figure 3c and Figure 3d , the first trenches T1 divide the substrate 20 into a plurality of structures AC extending in a first direction, with the first dielectric layer 21 separating adjacent structures AC.
[0074] In one embodiment, the method further includes performing ion implantation on the substrate 20 to form a first source / drain doped region (not shown) and a second source / drain doped region (not shown) on the top and bottom of the structures AC, respectively.
[0075] Specifically, the ion implantation on the substrate includes implanting first dopant ions from the upper surface of the substrate to form the first source / drain doped region on the top of the structures, and implanting second dopant ions from the lower surface of the substrate to form the second source / drain doped region on the bottom of the structures. More specifically, the first dopant ions and the second dopant ions are the same.
[0076] Next, step 102 is performed to form a plurality of second trenches T2 extending in a second direction in the substrate 20 and the first dielectric layer 21, with the second trenches T2 and the first trenches T1 crossing each other and dividing the substrate 20 into a plurality of discrete active pillars AP, as shown in Figures 4a-4d .
[0077] The formation process of the second trenches T2 includes, but is not limited to, a self-aligned double patterning process (SADP) and a self-aligned quadruple patterning process (SAQP). In some embodiments, the second trenches T2 are equally spaced in the substrate 20.
[0078] In one embodiment, the first direction is perpendicular to the second direction. However, the first direction and the second direction can have an acute angle therebetween in other embodiments.
[0079] In an embodiment, the second trench T2 has a smaller depth than the first trench T1, i.e. the bottom surface of the second trench T2 is higher than the bottom surface of the first trench T1, so that the first dielectric layer 21 located in the first trench T1 has different heights in the extending direction. Specifically, the upper surface of the first dielectric layer 21 located between two adjacent active pillars AP is flush with the upper surface of the substrate 20, as shown in Figure 4c ; and the upper surface of the first dielectric layer 21 located at the intersection of the first trench T1 and the second trench T2 is flush with the bottom surface of the second trench T2, as shown in Figure 4d .
[0080] In an embodiment, the method further comprises forming a barrier layer 22 on the substrate 20, the barrier layer 22 covering at least the upper surface of the active pillar AP, for protecting the top of the active pillar AP from being oxidized, nitrided, damaged or contaminated, etc. in subsequent processes. In a specific embodiment, the barrier layer 22 is formed before etching the substrate 20 and the first dielectric layer 21 to form the second trench T2. In an embodiment, the material of the barrier layer 22 can be an oxide, specifically silicon oxide. The barrier layer 22 can be formed by one or more thin film deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), etc.
[0081] Next, step 103 is performed, in which a second dielectric layer 23 is deposited on the sidewall of the second trench T2, as shown in Figures 5a-5d .
[0082] In an embodiment, the material of the second dielectric layer 23 can be an oxide, specifically silicon oxide. The second dielectric layer 23 can be formed on the exposed surfaces of the plurality of second trenches T2 by atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. Alternatively, after the second dielectric layer 23 is formed in the second trench T2, a back-etching process can be performed to remove the second dielectric layer 23 located on the bottom surface of the second trench T2, so that the bottom of the second trench T2 is exposed to the substrate 20. The second dielectric layer 23 is used to protect the sidewall of the active pillar AP from being oxidized, nitrided, damaged or contaminated, etc. in subsequent processes.
[0083] In an embodiment, after the second dielectric layer 23 is deposited on the sidewall of the second trench T2, the method further comprises doping the substrate 20 from the bottom of the second trench T2, to form a plurality of bit lines BL extending in the first direction, with the first dielectric layer 21 being located between adjacent bit lines BL, as shown in Figures 6a-6d .
[0084] The second source / drain doped region extends from a lower surface of the substrate toward the active pillar, and the second source / drain doped region is at least partially on a bottom surface of the second trench, i.e., the second source / drain doped region is at least partially on the bit line, and the bit line is in contact with the second source / drain doped region.
[0085] In an embodiment, the material of the bit line BL includes, but is not limited to, metal-doped semiconductor material, such as metal-doped silicon, metal-doped germanium, metal-doped silicon germanium. In a specific embodiment, the substrate 20 is a silicon substrate, and the material of the bit line BL includes metal silicide, such as cobalt silicide (CoSi x ), titanium silicide (TiSi x ), nickel silicide (NiSi x ).
[0086] Next, step 104 is performed to deposit a sacrificial layer 24 in the second trench T2, the sacrificial layer 24 being sandwiched between the second dielectric layers 23, as shown in Figures 7a-7d .
[0087] The sacrificial layer 24 extends along a second direction, and the sacrificial layer 24 has a uniform width and height in the direction of extension. In some embodiments, the upper surface of the sacrificial layer 24 is lower than the upper surface of the second dielectric layer 23, and the sacrificial layer 24 extends to the bottom of the second trench T2 in a direction perpendicular to the substrate 20. The material of the sacrificial layer 24 includes, but is not limited to, nitride, such as silicon nitride.
[0088] In an embodiment, after the sacrificial layer 24 is deposited in the second trench T2, the method further includes: depositing an isolation layer 25 in the second trench T2, the isolation layer 25 being located above the sacrificial layer 24, and the two sides of the isolation layer 25 being adjacent to the second dielectric layer 23, as shown in Figures 8a-8b . The isolation layer 25 is an insulating material for isolating adjacent active pillars AP.
[0089] Next, step 105 is performed to remove part of the first dielectric layer 21 and part of the second dielectric layer 23 to form a plurality of hole structures 27 extending along the second direction, the hole structures 27 surrounding the active pillars AP, and adjacent hole structures 27 being separated by the sacrificial layer 24, as shown in Figures 11a-11d .
[0090] In an embodiment, before part of the first dielectric layer 21 and part of the second dielectric layer 23 are removed to form a plurality of hole structures 27 extending along the second direction, the method further includes:
[0091] A first dielectric layer 21 and a second dielectric layer 23 with a preset thickness are removed to expose a side surface of the isolation layer 25 and a partial side surface of the active pillar AP, wherein the preset thickness is greater than or equal to the thickness of the isolation layer 25, as shown in Figures 9a-9d .
[0092] A third dielectric layer 26 is deposited on the side surface of the isolation layer 25 and the partial side surface of the active pillar AP, as shown in Figures 10a-10d . The third dielectric layer 26 plays a role of supporting the isolation layer in the following process steps. The material of the third dielectric layer 26 includes but is not limited to nitride, such as silicon nitride.
[0093] Referring back to Figures 9a-9d , in a specific embodiment, the barrier layer 22 is also removed while the first dielectric layer 21 and the second dielectric layer 23 with a preset thickness are removed.
[0094] Referring back to Figures 10a-10d , in an embodiment, the third dielectric layer 26 has a plurality of first openings R1 exposing the first dielectric layer 21; a plurality of hole structures 27 extending in a second direction are formed by removing part of the first dielectric layer 21 and part of the second dielectric layer 23 from the first openings R1 using a wet etching process, as shown in Figures 11a-11d .
[0095] Next, step 106 is performed to form word lines WL in the hole structures 27, as shown in Figures 12a-12d .
[0096] The material of the word lines WL includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof. The word lines WL can be formed in the hole structures 27 using a chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, or the like. Optionally, after the word lines WL are formed in the hole structures 27, a back etching process is performed to make the upper surface of the word lines WL flush with or lower than the upper surface of the sacrificial layer 24.
[0097] In an embodiment, the word lines WL have a uniform height in the extending direction, and the upper surface of the word lines WL is flush with or lower than the upper surface of the sacrificial layer 24. In a specific embodiment, the ratio of the height of the word lines WL to the height of the active pillar AP ranges from 1 / 3 to 2 / 3.
[0098] In one embodiment, before forming the word line WL within the aperture structure 27, the method further includes forming a gate dielectric layer 28 on the surface of the active pillar AP surrounded by the aperture structure 27. The gate dielectric layer 28 serves to isolate the word line WL and the active pillar AP. The material of the gate dielectric layer 28 includes, but is not limited to, oxides, such as silicon oxide.
[0099] In one specific embodiment, the gate dielectric layer 28 is formed by converting a portion of the active pillar AP into oxide through in-situ thermal oxidation.
[0100] Finally, step 107 is performed to remove the sacrificial layer 24 to form an air gap 31 between adjacent word lines WL, as shown. Figures 14a-14d As shown in 15a-15d.
[0101] In one embodiment, such as Figures 13a-13d As shown, before removing the sacrificial layer 24, the method further includes depositing a fourth dielectric layer 29 on the substrate 20, the fourth dielectric layer 29 at least covering the substrate 20 and the upper surface of the word line WL. The fourth dielectric layer 29 is used to protect the active pillar AP and the word line WL from oxidation, nitriding, damage, or contamination in subsequent processes. The material of the fourth dielectric layer 29 includes, but is not limited to, oxides, such as silicon oxide.
[0102] like Figure 2 As shown, the substrate 20 includes a storage region 20A and a peripheral region 20B, and the second trench T2 extends into the peripheral region 20B.
[0103] In one embodiment, removing the sacrificial layer 24 includes: etching downwards from the upper surface of the fourth dielectric layer 29 to the sacrificial layer 24 to form at least one second opening R2, the second opening R2 being located in the peripheral region 20B of the substrate 20, such as... Figures 14a-14d As shown; the sacrificial layer 24 is removed using a wet etching process, as... Figures 15a-15d As shown.
[0104] See you again Figures 14a-14d In one specific embodiment, the bottom of the second opening R2 extends into the sacrificial layer 24 to increase the contact area between the etching solution and the sacrificial layer 24, thereby removing the sacrificial layer 24 more quickly.
[0105] See you again Figures 15a-15d In one embodiment, the air gap 31 is located within the second groove T2 and extends along the second direction. The upper surface of the air gap 31 is flush with or higher than the upper surface of the character line WL, and the air gap 31 has a uniform width and height in the extending direction.
[0106] In summary, by the design of the embodiments of the present application, the air gap is formed between the adjacent word lines, the air gap has a lower dielectric constant, the parasitic capacitance between the adjacent word lines of the semiconductor structure can be reduced, and finally the performance of the semiconductor structure is improved.
[0107] The embodiments of the present application also provide a semiconductor structure, as shown by comprising: Figures 15a-15d
[0108] a substrate 20, the substrate 20 includes a plurality of first trenches T1 extending along a first direction and a plurality of second trenches T2 extending along a second direction, the first trenches T1 and the second trenches T2 cross each other in the substrate 20 to define a plurality of discrete active pillars AP;
[0109] a first dielectric layer 21 located at the bottom of the first trenches T1;
[0110] a second dielectric layer 23 covering the sidewall of the bottom of the second trenches T2;
[0111] an air gap 31 located in the second trenches T2;
[0112] a plurality of word lines WL extending along the second direction and located in the first trenches T1 and the second trenches T2; the word lines WL surround the active pillars AP and cover the upper surfaces of the first dielectric layer 21 and the second dielectric layer 23;
[0113] wherein the adjacent word lines WL are separated by the air gap 31.
[0114] The substrate can be a semiconductor substrate and can include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon substrate, which can be doped or undoped.
[0115] In an embodiment, the plurality of first trenches T1 are equally spaced in the substrate 20, and the plurality of second trenches T2 are also equally spaced in the substrate 20.
[0116] In an embodiment, the depth of the second trenches T2 is less than the depth of the first trenches T1, i.e., the bottom surface of the second trenches T2 is higher than the bottom surface of the first trenches T1.
[0117] In an embodiment, the first direction is perpendicular to the second direction, but is not limited thereto. In other embodiments, the first direction and the second direction have an acute angle.
[0118] In one embodiment, the first dielectric layer 21 at the bottom of the first trench T1 has different heights in the extending direction, as shown in Figure 15b In some embodiments, the material of the first dielectric layer 21 includes oxide, such as silicon oxide.
[0119] In one embodiment, the semiconductor structure further comprises a plurality of bit lines BL extending in the first direction, the bit lines BL are formed by doping the bottom of the second trench T2, the adjacent bit lines BL are separated by the first dielectric layer 21.
[0120] In particular, the material of the bit lines BL includes but is not limited to metal-doped semiconductor material, such as metal-doped silicon, metal-doped germanium, metal-doped silicon-germanium. In a specific embodiment, the substrate 20 is a silicon substrate, the material of the bit lines BL includes metal silicide, such as cobalt silicide (CoSi x ), titanium silicide (TiSi x ), nickel silicide (NiSi x ).
[0121] In one embodiment, the semiconductor structure further comprises a first source / drain doped region (not shown) at the top of the active pillar AP and a second source / drain doped region (not shown) at the bottom of the active pillar AP. The first source / drain doped region (not shown) and the second source / drain doped region (not shown) can have the same conductivity type. In one embodiment, the second source / drain doped region (not shown) extends from the lower surface of the substrate 20 to the active pillar AP, the second source / drain doped region (not shown) is at least partially above the bottom surface of the second trench T2, i.e. the second source / drain doped region (not shown) is at least partially above the bit line BL, the bit line BL is in contact with the second source / drain doped region (not shown).
[0122] In one embodiment, the word line WL has a uniform height in the extending direction, the ratio of the height of the word line WL to the height of the active pillar AP ranges from 1 / 3 to 2 / 3. The material of the word line WL includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof.
[0123] In an embodiment, the semiconductor structure further comprises a gate dielectric layer 28 between the word line WL and the active pillar AP for isolating the word line WL and the active pillar AP. In a specific embodiment, the gate dielectric layer 28 is formed by converting part of the active pillar AP into oxide through in-situ thermal oxidation, and the material of the gate dielectric layer 28 can be silicon oxide.
[0124] In an embodiment, the air gap 31 extends along a second direction, the upper surface of the air gap 31 is flush with or higher than the upper surface of the word line WL, and the air gap 31 has uniform width and height along the extending direction. In a specific embodiment, the air gap 31 extends to the bottom of the second trench T2 in the direction perpendicular to the substrate 20, and the second dielectric layer 23 is on both sides of the air gap 31 for isolating the air gap 31 and the active pillar AP. In some embodiments, the second dielectric layer 23 can be an oxide material, specifically silicon oxide.
[0125] The air gap is located between adjacent word lines, has a lower dielectric constant, and can reduce the parasitic capacitance between adjacent word lines of the semiconductor structure, ultimately improving the performance of the semiconductor structure.
[0126] In an embodiment, the semiconductor structure further comprises an isolation layer 25 located in the second trench T2 and above the air gap 31. The lower surface of the isolation layer 25 can be flush with or higher than the upper surface of the word line WL. The isolation layer 25 is an insulating material.
[0127] In an embodiment, the semiconductor structure further comprises a third dielectric layer 26 located above the word line WL and covering the side surface of the isolation layer 25 and part of the side surface of the active pillar AP. The lower surface of the third dielectric layer 26 is flush with or lower than the lower surface of the isolation layer 25. The material of the third dielectric layer 26 includes but is not limited to nitride, such as silicon nitride. The isolation layer 25 and the third dielectric layer 26 are used to isolate adjacent active pillars AP.
[0128] In an embodiment, the semiconductor structure further comprises a fourth dielectric layer 29 covering at least the upper surface of the substrate 20 and the word line WL for protecting the active pillar AP and the word line WL from oxidation, damage, or contamination, etc. The fourth dielectric layer 29 includes but is not limited to oxide, such as silicon oxide.
[0129] The above merely provides preferred embodiments of the application, and not for limiting the protection scope of the application. Any modification, equivalent replacement, and improvement made within the principle and technical scope of the application shall fall into the protection scope of the application.
Claims
1. A method of manufacturing a semiconductor structure, characterized by, The method comprises: forming a plurality of first trenches filled with a first dielectric layer and extending along a first direction in a substrate, the first trenches defining a plurality of structures extending along the first direction in the substrate; performing ion implantation on the substrate to form first and second source / drain doped regions on top and bottom of the structures, respectively; forming a plurality of second trenches extending along a second direction in the substrate and the first dielectric layer, the second trenches and the first trenches intersecting each other and defining a plurality of discrete active pillars in the substrate; depositing a second dielectric layer on sidewalls of the second trenches; depositing a sacrificial layer in the second trenches, the sacrificial layer being sandwiched between the second dielectric layer; removing part of the first dielectric layer and part of the second dielectric layer to form a plurality of hole structures extending along the second direction, the hole structures surrounding the active pillars, and adjacent hole structures being separated by the sacrificial layer; forming word lines in the hole structures; removing the sacrificial layer to form air gaps between adjacent word lines.
2. The production method according to claim 1, characterized by After depositing the second dielectric layer on sidewalls of the second trenches, the method further comprises: doping the substrate from bottom of the second trenches to form a plurality of bit lines extending along the first direction, adjacent bit lines being separated by the first dielectric layer.
3. The production method according to claim 1, characterized by After depositing the sacrificial layer in the second trenches, the method further comprises: depositing an isolation layer in the second trenches, the isolation layer being above the sacrificial layer, and two sides of the isolation layer being adjacent to the second dielectric layer.
4. The production method according to claim 3, characterized by Before removing part of the first dielectric layer and part of the second dielectric layer to form a plurality of hole structures extending along the second direction, the method further comprises: removing the first and second dielectric layers of a preset thickness to expose side surfaces of the isolation layer and part of side surfaces of the active pillars; wherein the preset thickness is greater than or equal to a thickness of the isolation layer; depositing a third dielectric layer on the side surfaces of the isolation layer and the part of side surfaces of the active pillars.
5. The production method according to claim 4, characterized by The third dielectric layer has a plurality of first openings exposing the first dielectric layer; forming a plurality of hole structures extending along the second direction, comprising: removing part of the first dielectric layer and part of the second dielectric layer from the first openings to form the hole structures by using a wet etching process.
6. The production method according to claim 1, characterized by Before forming word lines in the hole structures, the method comprises: forming a gate dielectric layer on a surface of the active pillar surrounded by the hole structures.
7. The production method according to claim 1, characterized by Before removing the sacrificial layer, the method further comprises: depositing a fourth dielectric layer on the substrate, the fourth dielectric layer covering at least an upper surface of the substrate and the word lines.
8. The production method according to claim 7, characterized by The substrate comprises a storage region and a peripheral region; removing the sacrificial layer, comprising: etching from an upper surface of the fourth dielectric layer to the sacrificial layer to form at least one second opening in the peripheral region; removing the sacrificial layer by using a wet etching process.
9. A semiconductor structure, characterized by comprises: a substrate including a plurality of first trenches extending in a first direction and a plurality of second trenches extending in a second direction, the first trenches and the second trenches crossing each other to define a plurality of discrete active pillars in the substrate; a first source / drain doped region on top of the active pillar and a second source / drain doped region on bottom of the active pillar; a first dielectric layer on bottom of the first trenches; a second dielectric layer covering sidewalls of bottom of the second trenches; an air gap in the second trenches; a plurality of word lines extending in the second direction in the first trenches and the second trenches, the word lines surrounding the active pillars and covering top surfaces of the first dielectric layer and the second dielectric layer; wherein adjacent word lines are separated by the air gap.
10. The semiconductor structure of claim 9, wherein, The air gap extends in the second direction, a top surface of the air gap is level with or higher than a top surface of the word lines, and the air gap has a uniform width and height in the direction of extension.
11. The semiconductor structure of claim 9, wherein, The air gap extends to a bottom of the second trenches in a direction perpendicular to the substrate, and the second dielectric layer is on both sides of the air gap.
12. The semiconductor structure of claim 9, wherein, The semiconductor structure further includes an isolation layer in the second trenches and above the air gap.
13. The semiconductor structure of claim 12, wherein, The semiconductor structure further includes a third dielectric layer above the word lines and covering side surfaces of the isolation layer and part of side surfaces of the active pillars.
14. The semiconductor structure of claim 9, wherein, The semiconductor structure further includes a fourth dielectric layer covering at least top surfaces of the substrate and the word lines.
15. The semiconductor structure of claim 9, wherein, The semiconductor structure further includes a gate dielectric layer between the word lines and the active pillars.
16. The semiconductor structure of claim 9, wherein, The semiconductor structure further includes a plurality of bit lines extending in the first direction, the bit lines being formed by doping bottoms of the second trenches, and adjacent bit lines being separated by the first dielectric layer.
Citation Information
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