Semiconductor structure and method of fabricating the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to solve the technical problem of poor performance of a semiconductor structure. The manufacturing method comprises the following steps: providing a substrate, wherein the substrate comprises a first semiconductor material layer, a silicon germanium compound layer and a second semiconductor material layer which are sequentially stacked; forming a first groove extending along a first direction and a second groove extending along a second direction in the substrate, and the first groove and the second groove separate the substrate into a plurality of spaced columnar structures; doping the columnar structures, and the silicon germanium compound layer forms a channel region; forming a dielectric layer on the outer circumferential surface of each columnar structure, and forming a gate electrode on the outer circumferential surface of the dielectric layer, wherein the gate electrode is opposite to at least part of the channel region. The silicon germanium compound layer is used to form the channel region, so that the electron mobility in the channel region can be improved, the short channel effect can be improved, and the performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] With the development of semiconductor technology, the requirements for the integration of semiconductor structures are constantly increasing. On the one hand, the integration of semiconductor structures can be improved by improving the semiconductor structure. For example, a dynamic random access memory (DRAM) usually includes multiple storage cells, each of which includes a transistor and a capacitor. The capacitor stores data information, and the transistor controls the reading and writing of the data information in the capacitor. By improving the topological structure of the storage cell, for example, using a 4F2 storage cell, the area occupied by the storage cell can be reduced and the storage density of the memory can be increased. On the other hand, the integration of the semiconductor structure can also be improved by reducing the characteristic size of the semiconductor structure. However, as the characteristic size of the conductor structure decreases, the transistor is prone to produce a short channel effect, resulting in poor performance of the semiconductor structure. Summary of the Invention

[0003] In view of the above problems, an embodiment of the present application provides a semiconductor structure and a manufacturing method thereof, which are used to improve the performance of the semiconductor structure.

[0004] A first aspect of an embodiment of the present application provides a method for manufacturing a semiconductor structure, which includes: providing a substrate, the substrate including a first semiconductor material layer, a silicon-germanium compound layer, and a second semiconductor material layer stacked in sequence; forming a first trench extending along a first direction and a second trench extending along a second direction in the substrate, the first trench and the second trench dividing the substrate into a plurality of spaced-apart columnar structures, the columnar structures including the second semiconductor material layer, the silicon-germanium compound layer, and a portion of the first semiconductor material layer; doping the columnar structures so that one of the first semiconductor material layer and the second semiconductor material layer forms a source region, the other forms a drain region, and the silicon-germanium compound layer forms a channel region; forming a dielectric layer on the outer peripheral surface of each of the columnar structures, and forming a gate located on the outer peripheral surface of the dielectric layer, the gate being opposite to at least a portion of the channel region.

[0005] The method for manufacturing a semiconductor structure provided by the embodiments of the present application has at least the following advantages:

[0006] In the method for manufacturing a semiconductor structure provided in an embodiment of the present application, a columnar structure includes a second semiconductor material layer, a silicon-germanium compound layer, and a portion of a first semiconductor material layer. One of the first semiconductor material layer and the second semiconductor material layer forms a source region, the other forms a drain region, and the silicon-germanium compound layer forms a channel region. A dielectric layer is formed on the outer peripheral surface of the columnar structure, and a gate is formed on the outer peripheral surface of the dielectric layer. The gate is opposite to at least a portion of the channel region. That is, the source region, drain region, channel region, dielectric layer, and gate form a vertical full-all-around gate transistor. When occupying the same substrate area, increasing the height of the columnar structure can increase the length of the channel region, thereby improving the short channel effect of the transistor. At the same time, the full-all-around gate can control the channel region from all sides, improving the channel control capability, further improving the short channel effect of the transistor, reducing the operating voltage, and improving the performance of the semiconductor structure. In addition, using the silicon-germanium compound layer to form the channel region can increase the electron mobility in the channel region, reduce the saturation voltage of the vertical full-all-around gate transistor, and further improve the performance of the semiconductor structure.

[0007] A second aspect of an embodiment of the present application provides a method for manufacturing a semiconductor structure, which includes: providing a substrate, the substrate including a first semiconductor material layer, a silicon germanium compound layer, and a second semiconductor material layer stacked in sequence; forming a first trench extending along a first direction in the substrate, the first trench penetrating the second semiconductor material layer and the silicon germanium compound layer, and extending to the first semiconductor material layer; through doping, one of the first semiconductor material layer and the second semiconductor material layer located between two adjacent first trenches forms a source region, the other forms a drain region, and the silicon germanium compound layer forms a channel region; forming a second trench extending along a second direction in the substrate, the second trench penetrating the second semiconductor material layer and the silicon germanium compound layer, and extending to the first semiconductor material layer, the first trench and the second trench dividing the substrate into a plurality of spaced-apart columnar structures; forming a dielectric layer on the outer peripheral surface of each of the columnar structures, and forming a gate located on the outer peripheral surface of the dielectric layer, the gate being opposite to at least part of the channel region.

[0008] The method for manufacturing a semiconductor structure provided by the embodiments of the present application has at least the following advantages:

[0009] In a method for fabricating a semiconductor structure provided in an embodiment of the present application, after forming a first trench extending in a first direction in a substrate, a doping process is performed to cause one of the first and second semiconductor material layers located between two adjacent first trenches to form a source region, the other to form a drain region, and the silicon-germanium compound layer to form a channel region. A second trench extending in a second direction is then formed in the substrate. The first and second trenches separate the substrate into a plurality of spaced-apart columnar structures. A dielectric layer is formed on the outer periphery of each columnar structure, and a gate is formed on the outer periphery of the dielectric layer, with the gate opposing at least a portion of the channel region. Thus, the source region, drain region, channel region, dielectric layer, and gate form a vertical full-all-around gate transistor. While occupying the same substrate area, increasing the height of the columnar structure can increase the length of the channel region, thereby improving the short-channel effect of the transistor. Furthermore, the full-all-around gate can control the channel region from all sides, thereby improving the channel control capability, further improving the short-channel effect of the transistor, reducing the operating voltage, and improving the performance of the semiconductor structure. In addition, forming a channel region using a silicon-germanium compound layer can improve electron mobility in the channel region, reduce the saturation voltage of the vertical full-all-around gate transistor, and further improve the performance of the semiconductor structure.

[0010] A third aspect of an embodiment of the present application provides a semiconductor structure, which includes a substrate, in which a plurality of spaced-apart columnar structures are formed, the columnar structure including a source region, a channel region, and a drain region stacked in sequence, the material of the channel region including a silicon-germanium compound, a dielectric layer arranged on the outer peripheral surface of the columnar structure, a gate arranged on the outer peripheral surface of the dielectric layer, and the gate opposite to at least a portion of the channel region.

[0011] The semiconductor structure provided by the embodiments of the present application has at least the following advantages:

[0012] In the semiconductor structure provided by the embodiments of the present application, the source region, the channel region, and the drain region are stacked in sequence, with a dielectric layer disposed on the outer periphery of the three regions. A gate is disposed on the outer periphery of the dielectric layer, and the gate is opposed to at least a portion of the channel region to form a vertical full-all-around gate transistor. The length of the channel region is easily adjustable, which facilitates improving the short channel effect of the transistor. At the same time, the full-all-around gate can control the channel region from all four sides, thereby improving the channel control capability, further improving the short channel effect of the transistor, reducing the operating voltage, and improving the performance of the semiconductor structure. In addition, the material of the channel region includes a silicon-germanium compound, which can increase the electron mobility in the channel region, reduce the saturation voltage of the vertical full-all-around gate transistor, and further improve the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0014] Figure 1 A schematic top view of a semiconductor structure in an embodiment of the present application;

[0015] Figure 2 A flow chart of a method for manufacturing a semiconductor structure in an embodiment of the present application;

[0016] Figures 3 to 6 Schematic diagrams of the cross sections of the substrate at AA, BB, CC, and DD in the embodiments of the present application;

[0017] Figures 7 to 10 They are schematic structural diagrams of cross sections at AA, BB, CC, and DD after forming the first trench in an embodiment of the present application;

[0018] Figures 11 to 14 They are schematic structural diagrams of cross sections at AA, BB, CC, and DD after forming a sacrificial layer in an embodiment of the present application;

[0019] Figures 15 to 18 They are schematic structural diagrams of cross sections at AA, BB, CC, and DD after the second trench is formed in an embodiment of the present application;

[0020] Figures 19 to 22 They are schematic structural diagrams of cross sections at AA, BB, CC, and DD after forming a dielectric layer in an embodiment of the present application;

[0021] Figures 23 to 26 They are schematic structural diagrams of cross sections at AA, BB, CC, and DD after forming the third insulating layer in an embodiment of the present application;

[0022] Figures 27 to 30 They are schematic structural diagrams of cross sections at AA, BB, CC, and DD after the third trench is formed in an embodiment of the present application;

[0023] Figures 31 to 34 They are schematic structural diagrams of cross sections at AA, BB, CC, and DD after forming the fourth insulating layer in an embodiment of the present application;

[0024] Figures 35 to 38They are schematic structural diagrams of cross sections at AA, BB, CC, and DD after forming the first protective layer in an embodiment of the present application;

[0025] Figures 39 to 42 They are schematic structural diagrams of cross sections at AA, BB, CC, and DD after a portion of the first protective layer is removed in an embodiment of the present application;

[0026] Figures 43 to 46 They are schematic structural diagrams of cross sections at AA, BB, CC, and DD after forming the second protective layer in an embodiment of the present application;

[0027] Figures 47 to 50 They are schematic structural diagrams of cross sections at AA, BB, CC, and DD after the bit lines are formed in the embodiment of the present application;

[0028] Figures 51 to 54 They are schematic structural diagrams of cross sections at AA, BB, CC, and DD after the sacrificial layer is removed in an embodiment of the present application;

[0029] Figure 55 and Figure 56 They are schematic structural diagrams of cross sections at points AA and CC after capacitors are formed in an embodiment of the present application;

[0030] Figure 57 A structural schematic diagram of a cross section at AA after forming an intermediate layer in an embodiment of the present application;

[0031] Figure 58 A structural schematic diagram of a cross section at AA after etching the silicon-germanium compound layer in an embodiment of the present application;

[0032] Figure 59 This is a structural schematic diagram of a cross section at AA after removing the intermediate layer in an embodiment of the present application;

[0033] Figure 60 Schematic diagram of another structure of the cross section at AA after forming the intermediate layer in an embodiment of the present application;

[0034] Figure 61 Schematic diagram of another structure of the cross section at AA after etching the silicon-germanium compound layer in an embodiment of the present application;

[0035] Figure 62 Schematic diagram of another structure of the cross section at AA after removing the intermediate layer in an embodiment of the present application;

[0036] Figure 63 This is another structural schematic diagram of the cross section at AA after the intermediate layer is formed in an embodiment of the present application;

[0037] Figure 64 Schematic diagram of another structure of the cross section at AA after etching the silicon-germanium compound layer in an embodiment of the present application;

[0038] Figure 65 This is another structural schematic diagram of the cross section at AA after removing the intermediate layer in an embodiment of the present application;

[0039] Figure 66 This is another flow chart of the method for manufacturing a semiconductor structure in an embodiment of the present application.

[0040] Description of reference numerals:

[0041] 10-substrate; 11-first semiconductor material layer;

[0042] 12-silicon-germanium compound layer; 13-second semiconductor material layer;

[0043] 14-first groove; 15-second groove;

[0044] 16-bit line; 17-column structure;

[0045] 20-first insulating layer; 30-sacrificial layer;

[0046] 41-first protective layer; 42-second protective layer;

[0047] 50-dielectric layer; 61-second insulating layer;

[0048] 62-conductive layer; 63-third insulating layer;

[0049] 64-third trench; 65-fourth insulating layer;

[0050] 66-word line; 70-middle layer;

[0051] 81-contact pad; 82-capacitor. DETAILED DESCRIPTION

[0052] In order to improve the performance of the semiconductor structure, in the manufacturing method of the semiconductor structure provided in the embodiment of the present application, by forming a vertical full-ring gate transistor and using a silicon-germanium compound layer to form a channel region, on the one hand, the short channel effect of the transistor can be improved, and on the other hand, the electron mobility in the channel region can be increased, the saturation voltage of the vertical full-ring gate transistor can be reduced, and the performance of the semiconductor structure can be improved.

[0053] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0054] refer to Figure 1 , Figure 1 This is a top view of a semiconductor structure in an embodiment of the present application, in which a word line 66 (WL) and a bit line 16 (BL) are formed. The bit line 16 extends along a first direction, and the word line 66 extends along a second direction. The first direction and the second direction have an angle, for example, the first direction and the second direction may be perpendicular. Specifically, as shown in FIG. Figure 1 As shown, the bit line 16 extends in the vertical direction (Y direction), and the word line 66 extends in the horizontal direction (X direction). The word line 66 or the bit line 16 can be a straight line or a zigzag line.

[0055] Figure 1 There are four different positions: A, B, C, and D. Specifically, the cross section at AA is parallel to the extending direction of the bit line 16 and located on the bit line 16. The cross section at BB is parallel to the extending direction of the bit line 16 and located between adjacent bit lines 16. The cross section at CC is parallel to the extending direction of the word line 66 and located on the word line 66. The cross section at DD is parallel to the extending direction of the word line 66 and located between adjacent word lines 66.

[0056] refer to Figure 2 , an embodiment of the present application provides a method for manufacturing a semiconductor structure, the manufacturing method comprising the following steps:

[0057] Step S101: providing a substrate, wherein the substrate comprises a first semiconductor material layer, a silicon-germanium compound layer, and a second semiconductor material layer stacked in sequence.

[0058] refer to Figures 3 to 6 The substrate 10 includes a first semiconductor material layer 11, a silicon germanium compound layer 12, and a second semiconductor material layer 13, and these three layers are in a vertical direction ( Figure 3 They are arranged in sequence in the Z direction as shown. Figures 3 to 6 As shown, a silicon-germanium compound layer 12 is disposed on the first semiconductor material layer 11 , and a second semiconductor material layer 13 is disposed on the silicon-germanium compound layer 12 .

[0059] The material of the first semiconductor material layer 11 and the material of the second semiconductor material layer 13 may be the same, and the semiconductor material may be silicon, germanium, silicon on insulator (SOI) or germanium on insulator (GOI).

[0060] The material of the silicon-germanium compound layer 12 may be different from the material of the first semiconductor material layer 11 and the material of the second semiconductor material layer 13. The silicon-germanium compound may be silicon germanium, or a mixture containing silicon germanium. In the example, the material of the first semiconductor material layer 11 and the material of the second semiconductor material layer 13 are both silicon, and the material of the silicon-germanium compound layer 12 is silicon germanium. With such an arrangement, the silicon-germanium compound layer 12 can be formed on the first semiconductor material layer 11 by epitaxial growth, and silicon germanium and silicon are combined in a coherent manner, so that the carriers in the quantum well (QW) formed by silicon germanium and silicon have a higher mobility. Among them, carriers, as current carriers, refer to substances with electric charge that can move freely, such as electrons and holes. In addition, the process cost of silicon germanium is comparable to the process cost of silicon, which can effectively control the production cost of semiconductor structures.

[0061] Step S102: forming a first trench extending along a first direction and a second trench extending along a second direction in the substrate, wherein the first trench and the second trench separate the substrate into a plurality of spaced-apart columnar structures, the columnar structures including a second semiconductor material layer, a silicon-germanium compound layer and a portion of the first semiconductor material layer.

[0062] refer to Figures 7 to 18 The number of the first trenches 14 is multiple, the number of the second trenches 15 is multiple, the multiple first trenches 14 are spaced apart and extend along the first direction, the multiple second trenches 15 are spaced apart and extend along the second direction, and the first trenches 14 and the second trenches 15 are connected. The first trenches 14 and the second trenches 15 separate the substrate 10 into multiple columnar structures 17. The columnar structures 17 are as shown in FIG. Figure 15 The area indicated by the dotted line includes the second semiconductor material layer, the silicon-germanium compound layer, and a portion of the first semiconductor material layer adjacent to the silicon-germanium compound layer. There are gaps between the columnar structures 17. For example, a plurality of columnar structures 17 are arranged in an array.

[0063] It should be noted that the depth of the first trench 14 and the depth of the second trench 15 can be different. For example, the depth of the first trench 14 is greater than the depth of the second trench 15, and the width of the first trench 14 and the width of the second trench 15 can be the same. Here, the depth refers to the distance between the bottom of the trench and the top surface of the substrate 10, and the width refers to the distance between the two opposing sidewalls. With this configuration, the first trench 14 separates the portion of the substrate 10 below the columnar structure 17 into a strip-like structure, facilitating the formation of other structures, such as bit lines, within this portion of the substrate 10.

[0064] Step S103 : doping the columnar structure so that one of the first semiconductor material layer and the second semiconductor material layer forms a source region, the other forms a drain region, and the silicon-germanium compound layer forms a channel region.

[0065] refer to Figures 15 to 18 By doping, a source region and a drain region are formed on both sides of the silicon-germanium compound layer 12 in the columnar structure 17. In other words, by doping, one of the first semiconductor material layer 11 and the second semiconductor material layer 13 forms a source region, and the other forms a drain region. For example, the first semiconductor material layer 11 forms a drain region, and the second semiconductor material layer 13 forms a source region.

[0066] Among them, doping can be achieved through processes such as ion implantation (Ion Plantation) or thermal diffusion (Thermal diffusion), the type of doping material in the source region and the drain region can be the same, the silicon-germanium compound layer 12 forms a channel region, the conductivity type (N-type or P-type) of the silicon-germanium compound layer 12 is different from the conductivity type of the first semiconductor material layer 11, and the conductivity type of the first semiconductor material layer 11 is the same as the conductivity type of the second semiconductor material layer 13.

[0067] Step S104 : forming a dielectric layer on the outer peripheral surface of each columnar structure, and forming a gate on the outer peripheral surface of the dielectric layer, wherein the gate is opposite to at least a portion of the channel region.

[0068] refer to Figures 19 to 26 A dielectric layer 50 is formed on the outer peripheral surface of each columnar structure 17. That is, on each columnar structure 17, the dielectric layer 50 surrounds and covers the first semiconductor material layer 11, the silicon-germanium compound layer 12, and the second semiconductor material layer 13. The dielectric layer 50 may be an oxide layer, such as silicon oxide, silicon oxynitride, tantalum oxide, aluminum oxide, hafnium oxide, or silicon hafnium oxide. The thickness of the dielectric layer 50 may be determined according to actual needs.

[0069] A gate is formed on the outer peripheral surface of the dielectric layer 50 outside each columnar structure 17. The gate surrounds and covers the dielectric layer 50. The gate is opposite to at least part of the channel region. There is a gate between two adjacent channel regions. The top surface of the gate is higher than the bottom surface of the channel region, and the top surface of the channel region is higher than the bottom surface of the gate. That is, the gate and the channel region are connected along the same direction. Figure 19 There is at least partial overlap in the Z direction. The gate material can be a metal, such as tantalum, tungsten, tantalum nitride, or titanium nitride. The gate material can also be other conductive materials such as polysilicon.

[0070] In the embodiment of the present application, the source region, the drain region, the channel region, the dielectric layer 50 and the gate form a vertical gate all around transistor (Vertical Gate All Around, abbreviated as VGAA). When occupying the same substrate area, the length of the channel region can be increased by increasing the height of the columnar structure 17, which is convenient for improving the short channel effect of the transistor and improving the performance of the semiconductor structure.

[0071] In a possible embodiment of the present application, forming a dielectric layer on the outer peripheral surface of each columnar structure, and forming a gate on the outer peripheral surface of the dielectric layer, where the gate is opposite to at least a portion of the channel region, may include the following steps:

[0072] Step S1041 : forming a dielectric layer on the outer peripheral surface of the columnar structure.

[0073] Specifically, a dielectric layer 50 is deposited on the outer circumference and top surface of the columnar structure 17, and on the first semiconductor material layer 11 and the first insulating layer 20 located between the columnar structures 17; and then the dielectric layer 50 is etched to retain the dielectric layer 50 located on the outer circumference of the columnar structure 17. Figures 19 to 22 As shown, the remaining dielectric layer 50 surrounds and covers the outer circumference of the columnar structure 17 .

[0074] Step S1042 : forming a second insulating layer, a conductive layer, and a third insulating layer in a stacked arrangement on the first insulating layer and the first semiconductor material layer, wherein the second insulating layer, the conductive layer, and the third insulating layer are filled between the columnar structures after the dielectric layer is formed.

[0075] refer to Figures 23 to 26 A second insulating layer 61 is deposited on the first insulating layer 20 and the first semiconductor material layer 11, a conductive layer 62 is deposited on the second insulating layer 61, and a third insulating layer 63 is deposited on the conductive layer 62. The second insulating layer 61, the conductive layer 62, and the second insulating layer 61 are stacked in sequence. The second insulating layer 61, the conductive layer 62, and the second insulating layer 61 are filled between the columnar structures 17 after the dielectric layer 50 is formed.

[0076] Among them, the second insulating layer 61 can be opposite to the first semiconductor material layer 11 in the columnar structure 17, and the conductive layer 62 can be opposite to the silicon-germanium compound layer 12 in the columnar structure 17. The conductive layer 62 is subsequently used to form a gate, and the second insulating layer 61 can be opposite to the second semiconductor material layer 13 in the columnar structure 17. The second insulating layer 61 and the first insulating layer 20 electrically isolate the conductive layer 62.

[0077] For example, the top surface of the third insulating layer 63 can be flush with the top surface of the second semiconductor material layer 13, for example, by depositing the third insulating layer 63 and etching back to form a relatively flat surface. The material of the second insulating layer 61 can be the same as that of the first insulating layer 20. The second insulating layer 61 contacts the first insulating layer 20 so that the second insulating layer 61 and the first insulating layer 20 form a whole. The material of the third insulating layer 63 can be the same as that of the second insulating layer 61 to facilitate the manufacture of the semiconductor structure.

[0078] Step S1043 , etching the third insulating layer and the conductive layer to form a third trench extending along the second direction. The third trench is located between two adjacent rows of columnar structures and exposes the second insulating layer. The columnar structures in each row are arranged along the second direction.

[0079] refer to Figures 27 to 30 The third insulating layer 63 and the conductive layer 62 are etched in a direction perpendicular to the third insulating layer 63 to form a third trench 64. The third trench 64 extends along the second direction and is located between two adjacent rows of columnar structures 17. The columnar structures 17 in each row are arranged along the second direction, and there is a gap between the third trench 64 and the columnar structure 17. It can be understood that the columnar structure 17 forms a plurality of columnar structure rows along the second direction, and the third trench 64 is located between two adjacent columnar structure rows, and the third trench 64 is spaced apart from the columnar structure 17.

[0080] The third trench 64 penetrates the third insulating layer 63 and the conductive layer 62 to separate the conductive layer 62 into a plurality of spaced apart portions. Each of the separated conductive layers 62 extends along the second direction. The second insulating layer 61 is exposed in the third trench 64. In some possible examples, the third trench 64 extends into the second insulating layer 61, such as Figure 27 and Figure 28 As shown, the bottom of the third trench 64 is located in the second insulating layer 61 . In some other possible examples, the third trench 64 is located on the second insulating layer 61 , that is, the third trench 64 does not extend into the second insulating layer 61 .

[0081] Step S1044: forming a fourth insulating layer in the third trench, wherein the fourth insulating layer isolates the conductive layer into a plurality of word lines, and a portion of the word lines surrounding the dielectric layer forms a gate.

[0082] refer to Figures 31 to 34 A fourth insulating layer 65 is deposited within the third trench 64, completely filling the third trench 64 to isolate the conductive layer 62 into a plurality of word lines 66. The bottom surface of the fourth insulating layer 65 contacts the second insulating layer 61, the side surface of the fourth insulating layer 65 near the bottom surface contacts the second insulating layer 61, and the side surface of the fourth insulating layer 65 near the top surface contacts the third insulating layer 63. The fourth insulating layer 65, the second insulating layer 61, and the third insulating layer 63 can be made of the same material, such as silicon nitride, so that the three layers form a single unit and collectively electrically isolate the word lines 66.

[0083] like Figure 31 and Figure 34 As shown, the conductive layer 62 forms a plurality of word lines 66, each of which includes at least one gate. The portion of the word line 66 surrounding the dielectric layer 50 forms a gate, that is, the gate is a portion of the word line 66.

[0084] In summary, in the method for manufacturing a semiconductor structure provided by an embodiment of the present application, the columnar structure 17 includes a second semiconductor material layer 13, a silicon-germanium compound layer 12, and a portion of the first semiconductor material layer 11. One of the first semiconductor material layer 11 and the second semiconductor material layer 13 forms a source region, the other forms a drain region, and the silicon-germanium compound layer 12 forms a channel region. A dielectric layer 50 is formed on the outer peripheral surface of the columnar structure 17, and a gate is formed on the outer peripheral surface of the dielectric layer 50. The gate is opposite to at least a portion of the channel region, that is, the source region, the drain region, the channel region, the dielectric layer 50, and the gate form a vertical full-all-around gate transistor. When occupying the same substrate area, by increasing the height of the columnar structure 17, the length of the channel region can be increased, which facilitates improving the short channel effect of the transistor. At the same time, the full-all-around gate can control the channel region from all sides, thereby improving the channel control capability, further improving the short channel effect of the transistor, reducing the operating voltage, and improving the performance of the semiconductor structure. In addition, using the silicon-germanium compound layer 12 to form the channel region can increase the electron mobility in the channel region, reduce the saturation voltage of the vertical full-all-around gate transistor, and further improve the performance of the semiconductor structure.

[0085] It should be noted that the reference Figures 7 to 18 In one possible embodiment of the present application, a first trench 14 extending along a first direction and a second trench 15 extending along a second direction are formed in a substrate 10. The first trench 14 and the second trench 15 separate the substrate 10 into a plurality of spaced-apart columnar structures 17. The columnar structures 17 include the second semiconductor material layer 13, the silicon-germanium compound layer 12, and a portion of the first semiconductor material layer 11. The steps include:

[0086] Step S1021 : forming a first trench extending along a first direction in the substrate, wherein the first trench penetrates the second semiconductor material layer and the silicon-germanium compound layer and extends into the first semiconductor material layer.

[0087] refer to Figures 7 to 10 The substrate 10 is wet-etched or dry-etched to form a first trench 14 in the substrate 10. The first trench 14 penetrates the second semiconductor material layer 13 and the silicon-germanium compound layer 12 and extends into the first semiconductor material layer 11. That is, the bottom of the first trench 14 is located in the first semiconductor material layer 11.

[0088] Exemplarily, the plurality of first trenches 14 are formed by a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process to increase the density of the first trenches 14 and ensure the aspect ratio of the first trenches 14 .

[0089] Step S1022 : forming a first insulating layer and a sacrificial layer stacked in the first trench.

[0090] refer to Figures 11 to 14 A first insulating layer 20 is formed in the first trench 14 by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), and a sacrificial layer 30 is formed on the first insulating layer 20.

[0091] The first insulating layer 20 fills the lower portion of the first trench 14, and the sacrificial layer 30 fills the upper portion of the first trench 14. In one possible example, when depositing the sacrificial layer 30, the sacrificial layer 30 fills the first trench 14 and covers the second semiconductor material layer 13. The sacrificial layer 30 located on the second semiconductor material layer 13 is then removed by a process such as chemical mechanical polishing (CMP) so that the sacrificial layer 30 fills the first trench 14.

[0092] The material of the first insulating layer 20 can be different from that of the sacrificial layer 30, so that the sacrificial layer 30 has a greater selectivity with respect to the first insulating layer 20, thereby reducing damage to the first insulating layer 20 during subsequent etching of the sacrificial layer 30. In addition, the first insulating layer 20 can also serve as an etch stop layer for the sacrificial layer 30. For example, the material of the sacrificial layer 30 can be silicon oxide, and the material of the first insulating layer 20 can be silicon nitride or silicon oxynitride. The selectivity of the sacrificial layer 30 with respect to the first insulating layer 20 is greater than or equal to 5.

[0093] like Figures 11 to 14 As shown, the top surface of the first insulating layer 20 is lower than the top surface of the first semiconductor material layer 11, wherein the top surface refers to the surface away from the bottom of the first trench 14, that is, Figures 11 to 14 The source region, drain region and channel region are subsequently formed in the substrate 10 above the first insulating layer 20 . The first insulating layer 20 is also used to isolate the portion of the substrate 10 located between the first trenches 14 .

[0094] Step S1023 , etching a portion of the substrate and a portion of the sacrificial layer to form a second trench extending along the second direction, wherein the second trench exposes the first insulating layer.

[0095] refer to Figures 15 to 18 The substrate 10 and the sacrificial layer 30 are etched to remove portions of the substrate 10 and the sacrificial layer 30, thereby forming second trenches 15 in the substrate 10 and the sacrificial layer 30. During this process, the first insulating layer 20 can serve as an etch stop layer. For example, the plurality of second trenches 15 can be formed by a self-aligned double patterning process or a self-aligned quadruple patterning process.

[0096] like Figures 15 to 18 As shown, the second trench 15 penetrates the second semiconductor material layer 13 and the silicon-germanium compound layer 12 and extends into the first semiconductor material layer 11. The second trench 15 penetrates the sacrificial layer 30 so that the second trench 15 exposes the first insulating layer 20. The bottom of the second trench 15 is located above the bottom of the first trench 14. The second trench 15 also exposes the first semiconductor material layer 11 in the substrate 10.

[0097] It should be noted that the reference Figures 35 to 38 In some possible embodiments, before the step of etching a portion of the substrate 10 and a portion of the sacrificial layer 30 to form a second trench 15 extending along the second direction, and the second trench 15 exposing the first insulating layer 20, the step further includes: forming a first protective layer 41 on the second semiconductor material layer 13 and the sacrificial layer 30, and the first protective layer 41 covers the second semiconductor material layer 13 and the sacrificial layer 30.

[0098] like Figures 35 to 38As shown, a first protective layer 41 is deposited on the second semiconductor material layer 13 and the sacrificial layer 30. The first protective layer 41 covers the second semiconductor material layer 13 and the sacrificial layer 30. The material of the first protective layer 41 can be the same as that of the sacrificial layer 30. In this way, the first protective layer 41 and the sacrificial layer 30 can be formed through a single deposition process, thereby simplifying the manufacturing steps of the semiconductor structure.

[0099] Specifically, a sacrificial material is deposited in the first trench 14, filling the first trench 14 with the sacrificial material. The sacrificial material in the first trench 14 forms a sacrificial layer 30. After the sacrificial material fills the first trench 14, further sacrificial material is deposited, covering the second semiconductor material layer 13 and the sacrificial layer 30. The sacrificial material on the second semiconductor material layer 13 and the sacrificial layer 30 forms a first protective layer 41. The first protective layer 41 may also be planarized to make the top surface of the first protective layer 41 flush.

[0100] It is understandable that when the material of the first protection layer 41 is different from that of the sacrificial layer 30 , the sacrificial layer 30 may be formed in the first trench 14 first, and then the first protection layer 41 may be formed on the sacrificial layer 30 and the second semiconductor material layer 13 .

[0101] Accordingly, reference Figures 39 to 42 , etching part of the substrate 10 and part of the sacrificial layer 30 to form a second trench 15 extending along the second direction, the step of exposing the first insulating layer 20 by the second trench 15 includes: etching the first protective layer 41, part of the substrate 10 and part of the sacrificial layer 30 to form the second trench 15, and retaining the first protective layer 41 located between the second trenches 15.

[0102] like Figures 15 to 18 As shown, the first protection layer 41, the substrate 10, and the sacrificial layer 30 are etched in a direction perpendicular to the substrate 10 to form the desired second trenches 15. The second trenches 15 penetrate the first protection layer 41, and the first protection layer 41 between adjacent second trenches 15 is retained, that is, the first protection layer 41 covers the second semiconductor material layer 13 and the sacrificial layer 30 between adjacent second trenches 15.

[0103] It should be noted that the reference Figures 43 to 54 In a possible embodiment of the present application, after the step of doping the columnar structure 17 so that one of the first semiconductor material layer 11 and the second semiconductor material layer 13 forms a source region, the other forms a drain region, and the silicon-germanium compound layer 12 forms a channel region, the method further includes:

[0104] The first semiconductor material layer 11 exposed in the second trenches 15 is subjected to a silicidation reaction to form a bit line 16 in the first semiconductor material layer 11 between adjacent first trenches 14 . The bit line 16 extends along the first direction and is electrically connected to the source region or the drain region.

[0105] like Figures 47 to 50 As shown, a portion of the bottom of the second trench 15 exposes the first semiconductor material layer 11. By performing a silicidation reaction on the first semiconductor material layer 11 exposed in the second trench 15, a metal silicide is formed in the first semiconductor material layer 11. The metal silicides in adjacent second trenches 15 are connected to form a bit line 16 extending along the first direction. The metal silicide can be titanium silicide, tantalum silicide, cobalt silicide, nickel silicide, or tungsten silicide.

[0106] Specifically, a metal layer is deposited in the second trench 15 and then annealed to allow the metal in the metal layer to react with the semiconductor material (e.g., silicon) in the first semiconductor material layer 11 to form a metal silicide. The excess metal layer is then removed. The metal silicide formed by the silicidation reaction forms an ohmic contact between the bit line 16 and the first semiconductor material layer 11, thereby reducing the contact resistance between the two.

[0107] Before the step of performing a silicidation reaction on the first semiconductor material layer 11 exposed in the second trenches 15 to form a bit line 16 in the first semiconductor material layer 11 between adjacent first trenches 14 and extending the bit line 16 along the first direction, the method further includes:

[0108] A second protective layer 42 is formed on the bottom and sidewalls of the second trench 15, the second semiconductor material layer 13, and the sacrificial layer 30. Figures 43 to 46 As shown, a second protection layer 42 is formed by a deposition process, and the second protection layer 42 covers the bottom and sidewalls of the second trench 15 , the second semiconductor material layer 13 and the sacrificial layer 30 .

[0109] After forming the second protective layer 42, the second protective layer 42 at the bottom of the second trench 15 is removed to expose the first semiconductor material layer 11. Anisotropic etching is then used to remove a portion of the second protective layer 42 at the bottom of the second trench 15 to expose the first semiconductor material layer 11 at the bottom of the second trench 15. The second protective layer 42 on the sidewalls of the second trench 15 is retained to isolate and protect the sidewalls of the second trench 15 and prevent silicidation.

[0110] In some other possible embodiments of the present application, Figures 39 to 46As shown, a first protective layer 41 is formed on the second semiconductor material layer 13 and the sacrificial layer 30, and accordingly, a second protective layer 42 is formed on the bottom and sidewalls of the second trench 15 and on the first protective layer 41, and then the second protective layer 42 located at the bottom of the second trench 15 is removed to expose the first semiconductor material layer 11.

[0111] With this arrangement, when the portion of second protective layer 42 at the bottom of second trench 15 is removed using anisotropic etching, the second protective layer 42 located on top of first protective layer 41 is also removed. At this point, first protective layer 41 can still cover second semiconductor material layer 13 and sacrificial layer 30, preventing the top surface of second semiconductor material layer 13 from being exposed. This ensures that the entire sidewall of second trench 15 is covered. When the metal layer is subsequently formed, it only contacts first semiconductor material layer 11 at the bottom of second trench 15, simplifying the process of forming bit line 16.

[0112] The first semiconductor material layer 11 exposed in the second trench 15 is subjected to a silicidation reaction to form a bit line 16 in the first semiconductor material layer 11 between adjacent first trenches 14. After the step of extending the bit line 16 along the first direction, the second protective layer 42 and the remaining sacrificial layer 30 are removed.

[0113] like Figures 47 to 54 As shown, after forming the bit lines 16, the second protective layer 42 and the remaining sacrificial layer 30 are etched away. If the first protective layer 41 is present, it is also etched away to expose the columnar structures 17, facilitating the formation of the dielectric layer 50 and the like on the columnar structures 17. The second protective layer 42 and the sacrificial layer 30 are made of the same material, and both can be removed in a single etching step, simplifying the semiconductor structure fabrication process.

[0114] refer to Figure 55 and Figure 56 After forming the gate 66, contact pads 71 ​​and capacitors 72 electrically connected to each contact pad 71 are formed on the substrate, wherein the contact pads 71 ​​are spaced apart and correspond one-to-one to and are electrically connected to the columnar structures 17.

[0115] In the embodiment of the present application, the shape of the channel region is not limited, and a portion of the surface of the channel region may be formed with a depression, for example, a circumferential depression is formed on the outer peripheral surface of the channel region to facilitate manufacturing. Figures 57 to 65, etching part of the substrate 10 and part of the sacrificial layer 30 to form a second groove 15 extending along the second direction, after the step (step S1023) of the second groove 15 exposing the first insulating layer 20, it also includes: depositing an intermediate layer 80 between the columnar structures 17, the intermediate layer 80 covering the surface of the first semiconductor material layer 11 of the columnar structure 17, and exposing at least part of the surface of the silicon-germanium compound layer 12 between the columnar structures 17 after the intermediate layer 80 is formed.

[0116] In one possible example, Figure 57 As shown, an intermediate layer 80 is filled between the columnar structures 17, and the top surface of the intermediate layer 80 is flush with the top surface of the first semiconductor material layer 11, or slightly higher than the top surface of the first semiconductor material layer 11, and the top surface of the intermediate layer 80 is lower than the top surface of the silicon-germanium compound layer 12. The outer peripheral surface of the silicon-germanium compound layer 12 of the columnar structure 17 is almost or completely exposed.

[0117] After forming the intermediate layer 80, the surface of the silicon-germanium compound layer 12 exposed between the columnar structures 17 is etched to form a recessed area in the silicon-germanium compound layer 12. Figure 58 As shown, the exposed silicon-germanium compound layer 12 is etched, and a recess is formed in the silicon-germanium compound layer 12 not covered by the intermediate layer 80 . The recess formed on the outer peripheral surface of the silicon-germanium compound layer 12 circumferentially surrounds the silicon-germanium compound layer 12 .

[0118] After the recessed area is formed, the intermediate layer 80 is removed. Figure 59 As shown, after the intermediate layer 80 is removed, the first semiconductor material layer 11 is exposed to facilitate subsequent processes.

[0119] In another possible example, Figure 60 As shown, an intermediate layer 80 is filled between the columnar structures 17. The top surface of the intermediate layer 80 is higher than the top surface of the first semiconductor material layer 11 and lower than the top surface of the silicon-germanium compound layer 12. The intermediate layer 80 is filled between the first semiconductor material layers 11 and between the silicon-germanium compound layers 12. The intermediate layer 80 covers the lower portion of the silicon-germanium compound layer 12, and the upper portion of the silicon-germanium compound layer 12 is exposed. Figure 61 and Figure 62 As shown, a depression is formed on the outer peripheral surface of the upper portion of the silicon-germanium compound layer 12 , and the depression circumferentially surrounds the silicon-germanium compound layer 12 , while the lower portion of the silicon-germanium compound layer 12 is not etched.

[0120] In another possible example, Figure 63 As shown, the columnar structures 17 are filled with an intermediate layer 80, which is filled between the first semiconductor material layer 11 and covers part of the outer peripheral surface of the columnar structure 17, that is, covers the side wall of one side of the silicon germanium compound layer 12 and the second semiconductor material layer 13. Figure 64As shown, the intermediate layer 80 covers the surface of the first semiconductor material layer 11 and the surface on the left side of the columnar structure 17, and the surface on the right side of the columnar structure 17 is exposed. Figure 65 As shown, a depression is formed on a portion of the outer peripheral surface of the silicon-germanium compound layer 12 , but the depression does not surround the silicon-germanium compound layer 12 .

[0121] In an embodiment of the present application, the intermediate layer 80 can also be formed after other steps. For example, after forming a stacked first insulating layer 20 and a sacrificial layer 30 in the first trench 14 (step S1022), the above-mentioned intermediate layer 80 is formed in the first trench 14 to form a depression on the surface of one side of the channel region.

[0122] The present application also provides a method for manufacturing a semiconductor structure, referring to Figure 66 , the production method comprises the following steps:

[0123] Step S201: providing a substrate, wherein the substrate comprises a first semiconductor material layer, a silicon-germanium compound layer, and a second semiconductor material layer stacked in sequence.

[0124] refer to Figures 3 to 6 The substrate 10 includes a first semiconductor material layer 11, a silicon germanium compound layer 12, and a second semiconductor material layer 13, and these three layers are in a vertical direction ( Figure 3 The material of the first semiconductor material layer 11 and the material of the second semiconductor material layer 13 can be the same.

[0125] The silicon-germanium compound layer 12 can be made of silicon germanium or a mixture containing silicon germanium. In this example, the first semiconductor material layer 11 and the second semiconductor material layer 13 are both made of silicon, while the silicon-germanium compound layer 12 is made of silicon germanium. This arrangement allows the silicon-germanium compound layer 12 to be formed on the first semiconductor material layer 11 via epitaxial growth, resulting in higher carrier mobility in the substrate 10 and a lower saturation voltage of the silicon germanium. Furthermore, the process cost of silicon germanium is comparable to that of silicon, effectively controlling the manufacturing cost of the semiconductor structure.

[0126] Step S202 : forming a first trench extending along a first direction in the substrate, wherein the first trench penetrates the second semiconductor material layer and the silicon germanium layer and extends to the first semiconductor material layer.

[0127] refer to Figures 7 to 10The substrate 10 is wet-etched or dry-etched, for example, by a self-aligned double patterning process or a self-aligned quadruple patterning process, to form a first trench 14 in the substrate 10. The first trench 14 extends along a first direction, penetrates the second semiconductor material layer 13 and the silicon-germanium compound layer 12, and extends into the first semiconductor material layer 11. That is, the bottom of the first trench 14 is located in the first semiconductor material layer 11.

[0128] Step S203 : doping is performed so that one of the first semiconductor material layer and the second semiconductor material layer located between two adjacent first trenches forms a source region, the other forms a drain region, and the silicon-germanium compound layer forms a channel region.

[0129] The structure between two adjacent first trenches 14 is doped through processes such as ion implantation or thermal diffusion, so that one of the first semiconductor material layer 11 and the second semiconductor material layer 13 forms a source region, the other forms a drain region, and the silicon-germanium compound layer 12 forms a channel region. The source region, the channel region, and the drain region are stacked in sequence and extend along a first direction. The doping depth of the first semiconductor material layer 11 is lower than the depth of the first trench 14, so that the upper portion of the first semiconductor material layer 11 is doped and the lower portion of the first semiconductor material layer 11 is not doped. The lower portion of the first semiconductor material layer 11 refers to the portion of the first semiconductor material layer 11 near the bottom of the first trench 14.

[0130] Step S204: forming a second trench extending along the second direction in the substrate, the second trench penetrating the second semiconductor material layer and the silicon germanium layer and extending to the first semiconductor material layer, the first trench and the second trench dividing the substrate into a plurality of spaced-apart columnar structures.

[0131] like Figures 15 to 18 As shown, the second trench 15 extends along the second direction, penetrates the second semiconductor material layer 13 and the silicon-germanium compound layer 12, and extends into the first semiconductor material layer 11. The bottom of the second trench 15 is higher than the bottom of the first trench 14. The second trench 15 and the first trench 14 separate the doped substrate 10 into a plurality of spaced-apart columnar structures 17. It will be understood that the second trench 15 separates the source region, channel region, and drain region extending along the first direction, thereby forming the columnar structures 17 in the substrate 10.

[0132] In a possible embodiment, after the step of forming a source region and a drain region in one of the first semiconductor material layer 11 and the second semiconductor material layer 13 located between two adjacent first trenches 14 by doping, and the silicon-germanium compound layer 12 forming a channel region, the step further includes: forming a stacked first insulating layer 20 and a sacrificial layer 30 in the first trench 14, wherein the top surface of the first insulating layer 20 is lower than the top surface of the first semiconductor material layer 11.

[0133] like Figures 11 to 14 As shown, a first insulating layer 20 is formed in the first trench 14 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, and a sacrificial layer 30 is formed on the first insulating layer 20. The first insulating layer 20 fills the lower part of the first trench 14, and the sacrificial layer 30 fills the upper part of the first trench 14. The top surface of the first insulating layer 20 is lower than the top surface of the first semiconductor material layer 11, wherein the top surface is Figures 11 to 14 The upper surface shown.

[0134] The material of the first insulating layer 20 can be different from that of the sacrificial layer 30, so that the sacrificial layer 30 has a greater selectivity with respect to the first insulating layer 20, thereby allowing the first insulating layer 20 to serve as an etch stop layer when the second trench 15 is subsequently formed. For example, the sacrificial layer 30 can be made of silicon oxide, and the first insulating layer 20 can be made of silicon nitride or silicon oxynitride.

[0135] Accordingly, the substrate 10 and the sacrificial layer 30 are etched to form the second trenches 15. For example, the plurality of second trenches 15 are formed by a self-aligned double patterning process or a self-aligned quadruple patterning process.

[0136] Step S205 : forming a dielectric layer on the outer peripheral surface of each columnar structure, and forming a gate on the outer peripheral surface of the dielectric layer, wherein the gate is opposite to at least a portion of the channel region.

[0137] refer to Figures 19 to 22 A dielectric layer 50 is formed on the outer peripheral surface of each columnar structure 17. That is, on each columnar structure 17, the dielectric layer 50 surrounds and covers the first semiconductor material layer 11, the silicon-germanium compound layer 12, and the second semiconductor material layer 13. The dielectric layer 50 may be an oxide layer, such as silicon oxide, silicon oxynitride, tantalum oxide, aluminum oxide, hafnium oxide, or silicon hafnium oxide. The thickness of the dielectric layer 50 may be determined according to actual needs.

[0138] A gate is formed on the outer peripheral surface of the dielectric layer 50 outside each columnar structure 17. The gate surrounds and covers the dielectric layer 50, and the gate is opposite to at least a portion of the channel region. Figures 22 to 25 As shown, a gate is located between two adjacent channel regions. The top surface of the gate is higher than the bottom surface of the channel region, and the top surface of the channel region is higher than the bottom surface of the gate. That is, the gate and channel region at least partially overlap along the Z direction shown in the figure. The gate can be made of a metal such as tantalum, tungsten, tantalum nitride, or titanium nitride. The gate can also be made of other conductive materials such as polysilicon.

[0139] For other processes in this embodiment, reference may be made to other processes in the embodiments described above, and no further details will be given here.

[0140] In the method for manufacturing a semiconductor structure provided in an embodiment of the present application, after forming a first trench 14 extending along a first direction in a substrate 10, a doping process is performed so that one of the first semiconductor material layer 11 and the second semiconductor material layer 13 located between two adjacent first trenches 14 forms a source region, the other forms a drain region, and the silicon-germanium compound layer 12 forms a channel region. Then, a second trench 15 extending along a second direction is formed in the substrate 10. The first trench 14 and the second trench 15 separate the substrate 10 into a plurality of spaced-apart columnar structures 17, and a dielectric layer 50 is formed on the outer peripheral surface of each columnar structure 17, as well as a gate formed on the outer peripheral surface of the dielectric layer 50, with the gate opposite to at least a portion of the channel region. That is, the source region, drain region, channel region, dielectric layer 50, and gate form a vertical full-all-around gate transistor. While occupying the same substrate area, increasing the height of columnar structure 17 can increase the length of the channel region, thereby improving the transistor's short channel effect. At the same time, the full-all-around gate can control the channel region from all four sides, improving the channel control capability, further improving the transistor's short channel effect, reducing the operating voltage, and improving the performance of the semiconductor structure. Furthermore, using silicon-germanium compound layer 12 to form the channel region can increase electron mobility in the channel region, reduce the saturation voltage of the vertical full-all-around gate transistor, and further improve the performance of the semiconductor structure.

[0141] The present application also provides a method for manufacturing a semiconductor structure, referring to Figure 34 to Figure 34 The semiconductor structure includes a substrate 10 (refer to Figure 3 ), a plurality of spaced-apart bit lines 16 are formed in the substrate 10, and the bit lines 16 extend along a first direction. A first insulating layer 20 is disposed between adjacent bit lines 16, electrically isolating adjacent bit lines 16 through the first insulating layer 20. Exemplarily, the first insulating layer 20 fills between adjacent bit lines 16, and a top surface of the first insulating layer 20 is flush with the top surface of the bit lines 16.

[0142] A plurality of spaced-apart columnar structures 17 are also formed within substrate 10, with at least one columnar structure 17 disposed on each bit line 16. Columnar structure 17 includes a source region, a channel region, and a drain region stacked in sequence. The source region or the drain region in columnar structure 17 is electrically connected to bit line 16; for example, the source region or the drain region in columnar structure 17 is in contact with bit line 16. The source and drain regions can be made of the same material, but different from the channel region. The channel region is made of a silicon-germanium compound, such as silicon germanium, to improve carrier mobility and reduce saturation voltage.

[0143] A dielectric layer 50 is disposed on the outer periphery of the columnar structure 17. The dielectric layer 50 surrounds and covers the source region, the channel region, and the drain region. The dielectric layer 50 may be an oxide layer, such as silicon oxide, silicon oxynitride, tantalum oxide, aluminum oxide, hafnium oxide, or hafnium silicon oxide.

[0144] A gate is formed on the outer peripheral surface of the dielectric layer 50, surrounding and covering the dielectric layer 50. The gate is opposite at least a portion of the channel region. Specifically, the top surface of the gate is higher than the bottom surface of the channel region, and the top surface of the channel region is higher than the bottom surface of the gate. That is, the gate and the channel region at least partially overlap along the Z direction shown in the figure. The gate can be made of a conductive material such as tantalum, tungsten, tantalum nitride, titanium nitride, or polysilicon.

[0145] The source region, drain region, channel region, dielectric layer 50, and gate form a vertical full-all-around gate transistor. While occupying the same substrate area, increasing the height of the columnar structure can increase the length of the channel region, thereby improving the short channel effect of the transistor. At the same time, the full-all-around gate can control the channel region from all four sides, improving the channel control capability, further improving the short channel effect of the transistor, reducing the operating voltage, and improving the performance of the semiconductor structure. In the embodiments of the present application, the shape of the channel region is not limited, and a recess can also be formed on the outer peripheral surface of the channel region. For example, the recess can form an annular groove circumferentially surrounding the channel region.

[0146] A second insulating layer 61, a third insulating layer 63, and a fourth insulating layer 65 are formed between the outer circumferences of adjacent dielectric layers 50. The third insulating layer 63 is positioned above and covers the gates. The fourth insulating layer 65 is positioned between two adjacent rows of gates, facing the gates and the third insulating layer 63. The gates in each row are arranged along the second direction. The second insulating layer 61 is positioned below the fourth insulating layer 65 and the gates.

[0147] The two adjacent rows of gates are electrically isolated by a second insulating layer 61, a third insulating layer 63, and a fourth insulating layer 65. The second insulating layer 61, the third insulating layer 63, and the fourth insulating layer 65 can be made of the same material so that they form a single integrated structure. The gates in each row are electrically connected to form word lines 66 extending along the second direction. Specifically, the portion of the word lines 66 that surrounds the dielectric layer 50 forms a gate.

[0148] In the semiconductor structure provided in the embodiments of the present application, the source region, channel region, and drain region are stacked in sequence, with a dielectric layer 50 disposed around the periphery of the three regions. A gate is disposed around the periphery of the dielectric layer 50, and the gate is opposed to at least a portion of the channel region to form a vertical full-all-around gate transistor. The length of the channel region is easily adjustable, thereby improving the short channel effect of the transistor. At the same time, the full-all-around gate can control the channel region from all four sides, thereby improving the channel control capability, further improving the short channel effect of the transistor, reducing the operating voltage, and improving the performance of the semiconductor structure. In addition, the material of the channel region includes a silicon-germanium compound, which can increase the electron mobility in the channel region, reduce the saturation voltage of the vertical full-all-around gate transistor, and further improve the performance of the semiconductor structure.

[0149] In this specification, each embodiment or implementation method is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0150] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first semiconductor material layer, a silicon-germanium compound layer, and a second semiconductor material layer stacked in sequence; A first trench extending along a first direction and a second trench extending along a second direction are formed in the substrate, wherein the first trench and the second trench divide the substrate into a plurality of spaced-apart columnar structures, wherein the columnar structures include the second semiconductor material layer, the silicon-germanium compound layer, and a portion of the first semiconductor material layer, including the following steps: forming a first trench extending along the first direction in the substrate, wherein the first trench penetrates the second semiconductor material layer and the silicon-germanium compound layer and extends into the first semiconductor material layer; forming a first insulating layer and a sacrificial layer stacked in the first trench, wherein a top surface of the first insulating layer is lower than a top surface of the first semiconductor material layer; Etching a portion of the substrate and a portion of the sacrificial layer to form a second trench extending along the second direction, wherein the second trench exposes the first insulating layer; doping the columnar structure so that one of the first semiconductor material layer and the second semiconductor material layer forms a source region, the other forms a drain region, and the silicon-germanium compound layer forms a channel region; A dielectric layer is formed on the outer peripheral surface of each of the columnar structures, and a gate is formed on the outer peripheral surface of the dielectric layer, wherein the gate is opposite to at least a portion of the channel region.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: Before the step of etching a portion of the substrate and a portion of the sacrificial layer to form the second trench extending along the second direction, wherein the second trench exposes the first insulating layer, the method further comprises: forming a first protective layer on the second semiconductor material layer and the sacrificial layer, wherein the first protective layer covers the second semiconductor material layer and the sacrificial layer; The step of etching part of the substrate and part of the sacrificial layer to form the second groove extending along the second direction, wherein the second groove exposes the first insulating layer includes: etching the first protective layer, part of the substrate and part of the sacrificial layer to form the second groove, and retaining the first protective layer located between the second grooves.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: After the step of doping the columnar structure so that one of the first semiconductor material layer and the second semiconductor material layer forms a source region and the other forms a drain region, and the silicon-germanium compound layer forms a channel region, the method further includes: The first semiconductor material layer exposed in the second trench is subjected to a silicidation reaction to form a bit line in the first semiconductor material layer between adjacent first trenches. The bit line extends along a first direction and is electrically connected to the source region or the drain region.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: Performing a silicidation reaction on the first semiconductor material layer exposed in the second trenches to form bit lines in the first semiconductor material layer between adjacent first trenches, before the step of extending the bit lines along the first direction, the method further includes: forming a second protective layer on the bottom and sidewalls of the second trench, on the second semiconductor material layer, and on the sacrificial layer; The second protection layer at the bottom of the second trench is removed to expose the first semiconductor material layer.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein: After performing a silicidation reaction on the first semiconductor material layer exposed in the second trenches to form bit lines in the first semiconductor material layer between adjacent first trenches, wherein the bit lines extend along the first direction, the method further includes: The second protection layer and the remaining sacrificial layer are removed.

6. The method for manufacturing a semiconductor structure according to any one of claims 1 to 5, wherein: The steps of forming a dielectric layer on the outer peripheral surface of each of the columnar structures, and forming a gate on the outer peripheral surface of the dielectric layer, wherein the gate is opposite to at least a portion of the channel region, include: forming a dielectric layer on the outer peripheral surface of the columnar structure; forming a second insulating layer, a conductive layer, and a third insulating layer stacked on the first insulating layer and the first semiconductor material layer, wherein the second insulating layer, the conductive layer, and the third insulating layer are filled between the columnar structures after the dielectric layer is formed; Etching the third insulating layer and the conductive layer to form a third trench extending along the second direction, wherein the third trench is located between two adjacent rows of the columnar structures and exposes the second insulating layer, and the columnar structures in each row are arranged along the second direction; A fourth insulating layer is formed in the third trench, wherein the fourth insulating layer isolates the conductive layer into a plurality of word lines, and a portion of the word lines surrounding the dielectric layer forms the gate.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: The third trench further extends into the second insulating layer, or the third trench is located on the second insulating layer.

8. The method for manufacturing a semiconductor structure according to claim 6, wherein: The step of forming a dielectric layer on the outer peripheral surface of the columnar structure comprises: Depositing the dielectric layer on the outer peripheral surface and the top surface of the columnar structure, and on the first semiconductor material layer and the first insulating layer located between the columnar structures; The dielectric layer is etched to retain the dielectric layer located on the outer peripheral surface of the columnar structure.

9. The method for manufacturing a semiconductor structure according to any one of claims 1 to 5, wherein: After the step of etching a portion of the substrate and a portion of the sacrificial layer to form the second trench extending along the second direction, wherein the second trench exposes the first insulating layer, the method further includes: Depositing an intermediate layer between the columnar structures, wherein the intermediate layer covers the surface of the first semiconductor material layer of the columnar structures, and at least a portion of the surface of the silicon-germanium compound layer is exposed between the columnar structures after the intermediate layer is formed; Etching the surface of the silicon-germanium compound layer exposed between the columnar structures to form a recessed area in the silicon-germanium compound layer; The intermediate layer is removed.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein: The top surface of the intermediate layer is higher than the top surface of the first semiconductor material layer and lower than the top surface of the silicon-germanium compound layer; Alternatively, the intermediate layer is filled between the first semiconductor material layers and covers the sidewalls of one side of the silicon-germanium compound layer and the second semiconductor material layer.

11. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first semiconductor material layer, a silicon-germanium compound layer, and a second semiconductor material layer stacked in sequence; forming a first trench extending along a first direction in the substrate, wherein the first trench penetrates the second semiconductor material layer and the silicon-germanium compound layer and extends to the first semiconductor material layer; Doping is performed so that one of the first semiconductor material layer and the second semiconductor material layer located between two adjacent first trenches forms a source region, the other forms a drain region, and the silicon-germanium compound layer forms a channel region; forming a first insulating layer and a sacrificial layer stacked in the first trench, wherein a top surface of the first insulating layer is lower than a top surface of the first semiconductor material layer; forming a second trench extending along a second direction in the substrate, the second trench penetrating the second semiconductor material layer and the silicon-germanium compound layer and extending to the first semiconductor material layer, the first trench and the second trench dividing the substrate into a plurality of spaced-apart columnar structures; A dielectric layer is formed on the outer peripheral surface of each of the columnar structures, and a gate is formed on the outer peripheral surface of the dielectric layer, wherein the gate is opposite to at least a portion of the channel region.

12. A semiconductor structure manufactured by the manufacturing method according to any one of claims 1 to 11, characterized in that: The invention comprises a substrate, wherein a plurality of spaced-apart columnar structures are formed in the substrate, wherein the columnar structures comprise a source region, a channel region and a drain region stacked in sequence, wherein the material of the channel region comprises a silicon-germanium compound, and a dielectric layer is arranged on the outer peripheral surface of the columnar structure, and a gate is arranged on the outer peripheral surface of the dielectric layer, and the gate is opposite to at least a portion of the channel region.

13. The semiconductor structure according to claim 12, wherein: A plurality of spaced-apart bit lines are further provided in the substrate, the bit lines extending along a first direction, each of the bit lines being provided with at least one columnar structure, and the bit line being electrically connected to a source region or a drain region of the columnar structure; A second insulating layer, a third insulating layer and a fourth insulating layer are further filled between the outer circumferences of adjacent dielectric layers. The third insulating layer is located above the gate, the fourth insulating layer is located between adjacent gates, and the second insulating layer is located below the fourth insulating layer and the gate.

14. The semiconductor structure according to claim 13, wherein: A plurality of spaced-apart word lines are also provided in the substrate, and the gate includes a portion of the word line surrounding the dielectric layer.

15. The semiconductor structure according to claim 13 or 14, characterized in that: A first insulating layer is further provided in the substrate. The first insulating layer is located between adjacent bit lines to electrically isolate the adjacent bit lines.

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