Semiconductor structure and its formation method

Abstract

This application provides a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure includes: providing a substrate; the substrate includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate; the well region includes a plurality of active pillars spaced apart along a first direction, and each of the active pillars includes a plurality of active pillars spaced apart along a second direction; wherein the first direction is perpendicular to the second direction; etching at least the bottom of the well region and a portion of the semiconductor substrate at the bottom of each active pillar to form a plurality of bit line trenches; and forming buried bit lines in the bit line trenches.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers. DRAM consists of many repeating memory cells. Each memory cell contains a transistor and a capacitor. The gate of the transistor is connected to the word line, the drain to the bit line, and the source to the capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0003] In related technologies, the source or drain of transistors in DRAM memory cells is typically formed on the surface of a semiconductor substrate. Therefore, the bit lines of dynamic random access memory are also formed on the surface of the semiconductor substrate. This cannot meet the current demand for high integration in semiconductor devices, and the bit lines' location on the surface of the semiconductor substrate weakens their control capabilities. Furthermore, the structure and fabrication process of the bit lines in related technologies are complex, thus increasing the production cost of semiconductor devices. Summary of the Invention

[0004] In view of this, embodiments of this application provide a semiconductor structure and a method for forming the same.

[0005] In a first aspect, embodiments of this application provide a method for forming a semiconductor structure, the method comprising:

[0006] A substrate is provided; the substrate includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate; the well region includes a plurality of active pillar rows spaced apart along a first direction, and each of the active pillar rows includes a plurality of active pillars spaced apart along a second direction; wherein the first direction is perpendicular to the second direction;

[0007] At least the well region at the bottom of each active pillar and a portion of the semiconductor substrate are etched to form multiple bit line trenches;

[0008] Embedded bit lines are formed in the bit line trench.

[0009] In some embodiments, the bit line trench includes a first bit line trench or a second bit line trench; the method further includes:

[0010] Each pair of adjacent active column columns is sequentially identified as an active column group;

[0011] Among them, the embedded bit line located in the first bit line trench is connected to the bottom of two adjacent active columns in the active column group along the first direction.

[0012] The embedded bit line located in the second bit line trench has two active pins adjacent to each other along the first direction in the active pin group with independent bottoms.

[0013] In some embodiments, forming an embedded bit line in the bit line trench includes:

[0014] Deposit bit line metal material in the first bit line trench or the second bit line trench to form the embedded bit line.

[0015] In some embodiments, a first insulating material is filled between any two adjacent active posts; the first bit line trench is formed by the following steps:

[0016] Along a third direction, the first insulating material between two adjacent columns of active pillars in each active pillar group is etched to form a plurality of first etched grooves; wherein the third direction, the first direction and the second direction are perpendicular to each other;

[0017] Taking the bottom of the first etched groove as the etching starting point, along the third direction, the well region at the bottom of the first etched groove and the semiconductor substrate of the specified thickness are etched, and along the first direction, the well region at the bottom of the active pillar and the semiconductor substrate of the specified thickness are etched to form the first bit line trench.

[0018] In some embodiments, the method further includes:

[0019] After the embedded bit line is formed in the first bit groove, the second insulating material is filled in the first etched groove.

[0020] In some embodiments, a first insulating material is filled between any two adjacent active posts; the second bit trench is formed by the following steps:

[0021] Along a third direction, at least the first insulating material between two adjacent rows of active pillars in each of the active pillar groups is etched to form a plurality of second etched grooves; wherein the third direction, the first direction, and the second direction are mutually perpendicular;

[0022] Along the first direction, the well region at the bottom of the active pillar and a portion of the semiconductor substrate are etched to form the second bit line trench; wherein the bottom of the second bit line trench is flush with the bottom of the second etched groove.

[0023] In some embodiments, the method further includes:

[0024] After the embedded bit line is formed in the second bit line trench, the second etched groove is filled with a second insulating material.

[0025] In some embodiments, the method further includes:

[0026] Before depositing the bit line metal material in the first bit line trench or the second bit line trench, a barrier layer is formed on the inner wall of the first bit line trench or the second bit line trench.

[0027] In some embodiments, the active post is formed in the following manner:

[0028] A patterned mask layer is formed on the surface of the trap region;

[0029] The patterned mask layer is used to etch a portion of the depth of the well region to form a plurality of active pillars spaced apart along the first direction and the second direction.

[0030] In some embodiments, prior to forming the bit line trench, the method further includes:

[0031] At least one first insulating material between two adjacent active pillar groups is etched to form a plurality of third etched grooves; wherein the bottom of the third etched grooves is located inside the semiconductor substrate;

[0032] The second insulating material is filled into the third etched groove.

[0033] In some embodiments, the method further includes:

[0034] Along the third direction, a portion of the second insulating material between any two adjacent active pillars is etched to expose an active pillar with a first preset height; wherein, the first preset height is less than the initial height of the active pillar;

[0035] Embedded letter lines are formed on the exposed sidewall of the active column with a first preset height.

[0036] In some embodiments, forming embedded letter lines on the exposed sidewall of an active column having a first preset height includes:

[0037] A gate oxide layer is formed on the sidewall of the exposed active pillar with a first preset height;

[0038] A word line metal layer is formed by filling the space between any two adjacent active pillars having the gate oxide layer.

[0039] The gate oxide layer and the word line metal layer are etched back to expose an active pillar with a second preset height; the second preset height is less than the first preset height.

[0040] The word line metal layer is graphically represented to form the embedded word line.

[0041] In some embodiments, the patterning of the word line metal layer to form the embedded word line includes:

[0042] The word line metal layer is etched along the third direction, and the word line metal layer between two adjacent active pillars in the first direction is retained to form the embedded word line and the fourth etched groove extending along the first direction.

[0043] In some embodiments, the method further includes:

[0044] A third insulating material is filled between the fourth etched groove and the exposed active post with a second preset height to form a top insulating layer; wherein the top surface of the top insulating layer is flush with the top surface of the patterned mask layer.

[0045] In some embodiments, the method further includes:

[0046] Remove the patterned mask layer from the surface of each active pillar to expose the top surface of the active pillar;

[0047] A capacitor structure is formed on the top surface of the active pillar.

[0048] Secondly, embodiments of this application provide a semiconductor structure, which is formed by the above-described semiconductor structure formation method; the semiconductor structure includes:

[0049] A substrate; the substrate includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate; the well region includes a plurality of active pillar rows spaced apart along a first direction, and each of the active pillar rows includes a plurality of active pillars spaced apart along a second direction; wherein the first direction is perpendicular to the second direction;

[0050] Buried bit lines; the buried bit lines are located in bit line trenches, and the bit line trenches are located at least in the well region at the bottom of each active pillar and in a portion of the thickness of the semiconductor substrate.

[0051] In some embodiments, the bit line trench includes a first bit line trench or a second bit line trench; each pair of adjacent active column columns constitutes an active column group;

[0052] Among them, the embedded bit line located in the first bit line trench is connected to the bottom of two adjacent active columns in the active column group along the first direction.

[0053] The embedded bit line located in the second bit line trench has two active pins adjacent to each other along the first direction in the active pin group with independent bottoms.

[0054] The semiconductor structure and its formation method provided in this application embodiment include providing a substrate; the substrate includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate; the well region includes a plurality of active pillars spaced apart along a first direction, and each active pillar row includes a plurality of active pillars spaced apart along a second direction; wherein the first direction is perpendicular to the second direction; since a plurality of bit line trenches can be formed by etching at least the well region at the bottom of each active pillar and a portion of the semiconductor substrate; thus, buried bit lines can be formed in the bit line trenches, improving the integration of the formed semiconductor device; in addition, the fabrication process of the buried bit lines in this application embodiment is simple, and the formed buried bit lines can be effectively conductive and have strong controllability. Attached Figure Description

[0055] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0056] Figure 1 A schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this application;

[0057] Figures 2a-2p A schematic diagram of a semiconductor structure formation process provided in an embodiment of this application;

[0058] Figures 3a-3k Another schematic diagram of the semiconductor structure formation process provided in this application embodiment;

[0059] Figure 4a and 4b A cross-sectional view of a semiconductor structure provided in an embodiment of this application;

[0060] Explanation of reference numerals in the attached figures:

[0061] 200 - Semiconductor substrate; 201 - Well region; 202 - Patterned mask layer; 201a - Active pillar; 203 - First insulating material; 204 - Second insulating material; 205 - Barrier layer; 206 - Buried bit line; 207 - Gate oxide layer; 208 - Word line metal layer; 209 - Buried word line; 210 - Top insulating layer; A - Third etched trench; B - First etched trench; C1 - First bit line trench; C2 - Second bit line trench; D - Second etched trench; E - Fourth etched trench. Detailed Implementation

[0062] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0063] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0064] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0065] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0066] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0067] Based on the problems existing in related technologies, this application provides a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure includes: providing a substrate; the substrate includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate; the well region includes a plurality of active pillars spaced apart along a first direction, and each active pillar includes a plurality of active pillars spaced apart along a second direction; wherein the first direction is perpendicular to the second direction; since a plurality of bit line trenches can be formed by etching at least the well region at the bottom of each active pillar and a portion of the semiconductor substrate; thus, buried bit lines can be formed in the bit line trenches, improving the integration of the formed semiconductor device; in addition, the fabrication process of the buried bit lines in this application is simple, and the formed buried bit lines can be effectively conductive and have strong controllability.

[0068] This application provides a method for forming a semiconductor structure, such as... Figure 1 As shown, the method for forming the semiconductor structure includes the following steps:

[0069] Step S101: Provide a substrate; the substrate includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate; the well region includes a plurality of active pillars spaced apart along a first direction, and each of the active pillars includes a plurality of active pillars spaced apart along a second direction; wherein the first direction is perpendicular to the second direction.

[0070] In this embodiment, the substrate can be a structure formed by partially doping the semiconductor substrate. The semiconductor substrate can be a silicon substrate, or it can include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InP), or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium aluminum arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and / or indium gallium arsenide phosphide (GaInAsP) or combinations thereof. The well region can be an N-well or a P-well.

[0071] The semiconductor substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side. Ignoring the flatness of the top and bottom surfaces, a direction perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as a third direction. In the direction of the top and bottom surfaces of the semiconductor substrate (i.e., the plane in which the semiconductor substrate lies), two intersecting (e.g., perpendicular) directions are defined. For example, the arrangement direction of multiple active column arrays can be defined as the first direction. Based on the first and second directions, the planar orientation of the semiconductor substrate can be determined. Here, the first direction, the second direction, and the third direction are mutually perpendicular. In this embodiment, the first direction is defined as the X-axis direction, the second direction as the Y-axis direction, and the third direction as the Z-axis direction.

[0072] Step S102: Etch at least the well region at the bottom of each active pillar and a portion of the semiconductor substrate to form multiple bit line trenches.

[0073] In this embodiment of the application, a portion of the well region is retained at the bottom of each active post, and the bit line trench is located at the bottom of each active post.

[0074] Step S103: An embedded bit line is formed in the bit line trench.

[0075] Figures 2a-2p This is a schematic diagram of a semiconductor structure formation process provided in an embodiment of this application. Please refer to the following: Figures 2a-2p The method for forming a semiconductor structure provided in the embodiments of this application will be further described in detail.

[0076] First, you can refer to Figure 2a and 2bStep S101 is performed to provide a substrate; the substrate includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate; the well region includes a plurality of active pillars spaced apart along a first direction, and each of the active pillars includes a plurality of active pillars spaced apart along a second direction; wherein the first direction is perpendicular to the second direction.

[0077] like Figure 2a As shown, the substrate includes a semiconductor substrate 200 and a well region 201 located on the surface of the semiconductor substrate 200. In this embodiment, the semiconductor substrate may be a P-type substrate, and the well region may be an N-well. In other embodiments, the semiconductor substrate may also be an N-type substrate, and the well region may also be a P-well.

[0078] In some embodiments, the active pillar located in the well region can be formed by the following steps:

[0079] A patterned mask layer is formed on the surface of the trap region.

[0080] The patterned mask layer is used to etch a portion of the depth of the well region to form a plurality of active pillars spaced apart along the first direction and the second direction.

[0081] like Figure 2b As shown, a patterned mask layer 202 is formed on the surface of the well region 201. Along the Z-axis direction, the well region 201 is etched through the patterned mask layer 202 to form active pillars 201a spaced apart along the X-axis and Y-axis directions. Among them, multiple active pillars spaced apart along the Y-axis constitute an active pillar column, and multiple active pillar columns are spaced apart along the X-axis direction.

[0082] In some embodiments, after forming the active pillar, the method for forming the semiconductor structure further includes:

[0083] Step S20: Fill the space between any two adjacent active pillars with the first insulating material.

[0084] The first insulating material can be any kind of insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0085] like Figure 2c As shown, a first insulating material 203 is filled between any two adjacent active pillars 201a, wherein the top surface of the first insulating material 203 is flush with the top surface of the patterned mask layer 202.

[0086] Step S21: Sequentially determine each pair of adjacent active column columns as an active column group.

[0087] Step S22: Etch at least the first insulating material between two adjacent active pillar groups to form a plurality of third etched grooves; wherein the bottom of the third etched grooves is located inside the semiconductor substrate.

[0088] like Figure 2d As shown, along the Z-axis direction, the first insulating material 203 between two adjacent active pillar groups, the well region at the bottom of the first insulating material 203 between two adjacent active pillar groups, and a semiconductor substrate of a certain thickness are etched to form a third etched groove A. The bottom of the third etched groove A is located inside the semiconductor substrate 200.

[0089] In this embodiment, a dry etching process can be used to etch the first insulating material, the well region, and part of the semiconductor substrate to form the third etched groove, such as plasma etching, reactive ion etching, or ion milling.

[0090] Step S23: Fill the third etched groove with a second insulating material.

[0091] The second insulating material can be any type of insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. The second insulating material can be the same as or different from the first insulating material. In this embodiment, the second insulating material is the same as the first insulating material.

[0092] like Figure 2e As shown, the third etched groove A is filled with the second insulating material 204.

[0093] Next, you can refer to Figure 2f and 2g Step S102 is performed to etch at least the well region at the bottom of each active pillar and a portion of the semiconductor substrate to form multiple bit line trenches.

[0094] In this embodiment of the application, the bit line trench includes a first bit line trench; the first bit line trench can be formed by the following steps:

[0095] Along a third direction, the first insulating material between two adjacent active pillar columns in each active pillar group is etched to form a plurality of first etched grooves; wherein the third direction, the first direction and the second direction are perpendicular to each other.

[0096] like Figure 2f As shown, along the Z-axis direction, the first insulating material 203 between two adjacent active pillar columns in each active pillar group is etched to form a plurality of first etched grooves B, and the first etched grooves B expose the well region 201.

[0097] Taking the bottom of the first etched groove as the etching starting point, along the third direction, the well region at the bottom of the first etched groove and the semiconductor substrate of the specified thickness are etched, and along the first direction, the well region at the bottom of the active pillar and the semiconductor substrate of the specified thickness are etched to form the first bit line trench.

[0098] In this embodiment of the application, etching the well region at the bottom of the active pillar and the semiconductor substrate of the corresponding thickness can, for each active pillar row, involve etching the entire well region at the bottom of each active pillar and the corresponding semiconductor substrate of the corresponding thickness, or etching a portion of the well region at the bottom of the active pillar along the X-axis direction and the corresponding semiconductor substrate of the corresponding thickness.

[0099] like Figure 2g As shown, with the bottom of the first etched groove B as the etching starting point, the well region at the bottom of the first etched groove B and the semiconductor substrate of the specified thickness are etched along the Z-axis direction, and the well region at the bottom of the active pillar 201a and the semiconductor substrate of the specified thickness are etched along the X-axis direction, forming the first line trench C1.

[0100] In this embodiment of the application, when forming the first line trench C1, the etching along the X-axis direction can be wet etching or bias dry lateral etching.

[0101] In some embodiments, before etching to form the first line trench, the method for forming the semiconductor structure may further include: forming a protective layer on the sidewalls of two adjacent active pillars along a first direction in each group of active pillars. The protective layer is used to protect the active pillars from damage during the etching process to form the first line trench; and the protective layer needs to be removed after the first line trench is formed.

[0102] Next, you can refer to Figure 2h and 2i Step S103 is executed to form an embedded bit line in the bit line trench.

[0103] In this embodiment of the application, the bit line groove includes a first bit line groove, and the step of forming an embedded bit line in the bit line groove includes:

[0104] The embedded bit line is formed by depositing bit line metallic material in the first bit line trench.

[0105] The bit line metal material includes tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicide, or any combination thereof.

[0106] In some embodiments, before depositing the bit line metal material in the first bit line trench, the method further includes forming a barrier layer on the inner wall of the first bit line trench.

[0107] The barrier layer is located between the bit line metal material and the semiconductor substrate, and between the bit line metal material and the well region. The barrier layer is used to prevent the bit line metal material from diffusing into the semiconductor substrate or the well region.

[0108] In this embodiment, the barrier layer can be formed using any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or coating process. The barrier layer can be a silicon nitride layer.

[0109] like Figure 2h and 2i As shown, a barrier layer 205 is formed in the first line trench C1, and a bit line metal material is deposited in the first line trench with the barrier layer 205 to form an embedded bit line 206.

[0110] In this embodiment of the application, the embedded bit line located in the first bit line trench is interconnected at the bottom of two adjacent active columns in the active column group along the first direction.

[0111] It should be noted that in the embodiments of this application, when depositing bit line metal material in the first bit line trench, the bit line metal material is also deposited in the first etching groove B. Subsequently, the bit line metal material deposited in the first etching groove B needs to be etched back, and only the bit line metal material located in the first bit line trench C1 is retained as the embedded bit line.

[0112] It is worth noting that steps S21 to S23 are not strictly related to the formation process of the embedded bit line, and steps S21 to S23 can also be performed after the embedded bit line is formed.

[0113] In some embodiments, after the embedded bit line is formed in the first bit trench, the method of forming the semiconductor structure further includes filling the first etched groove with a second insulating material.

[0114] like Figure 2j As shown, the first etched groove B is filled with a second insulating material 204.

[0115] In some embodiments, after filling the first etched groove with a second insulating material, the method for forming the semiconductor structure further includes the following steps:

[0116] Along the third direction, a portion of the second insulating material between any two adjacent active pillars is etched to expose an active pillar with a first preset height; wherein, the first preset height is less than the initial height of the active pillar.

[0117] like Figure 2k As shown, along the Z-axis, a portion of the second insulating material 204 between any two adjacent active pillars is etched, exposing an active pillar 201a with a first preset height h1, wherein the first preset height h1 is less than the initial height h0 of the active pillar 201a. In this embodiment, the height difference between the initial height h0 and the first preset height h1 can be 10nm-50nm.

[0118] Embedded letter lines are formed on the exposed sidewall of the active column with a first preset height.

[0119] In some embodiments, forming embedded letter lines on the exposed sidewall of an active column having a first preset height includes the following steps:

[0120] A gate oxide layer is formed on the sidewall of the exposed active pillar with a first preset height.

[0121] A word line metal layer is formed by filling the space between any two adjacent active pillars having the gate oxide layer.

[0122] In this embodiment of the application, the word line metal material may be titanium nitride, tungsten, or a combination thereof.

[0123] The gate oxide layer and the word line metal layer are etched back to expose an active pillar with a second preset height; the second preset height is less than the first preset height.

[0124] like Figure 2l and 2m As shown, a gate oxide layer 207 and a word line metal layer 208 are formed on the sidewall of the exposed active pillar 201a with a first preset height, and an active pillar with a second preset height h2 is exposed. The second preset height h2 is less than the first preset height h1. In this embodiment, the second preset height includes 10nm-50nm.

[0125] It should be noted that, in the embodiments of this application, the process of etching back the gate oxide layer and the word line metal layer can be performed in two steps or simultaneously.

[0126] The word line metal layer is graphically represented to form the embedded word line.

[0127] In some embodiments, the process of patterning the word line metal layer to form the embedded word line includes: etching the word line metal layer along the third direction and retaining the word line metal layer between two adjacent active pillars in the first direction to form the embedded word line and a fourth etched groove extending along the first direction.

[0128] like Figure 2n As shown, word line metal layer 208 is etched along the Z-axis direction, while word line metal layer between two adjacent active pillars 201a is retained in the X-axis direction, forming embedded word line 209 and fourth etched groove E extending along the X-axis direction.

[0129] In some embodiments, the method of forming the semiconductor structure further includes: filling a third insulating material between the fourth etched groove and the exposed active pillar having a second predetermined height to form a top insulating layer; wherein the top surface of the top insulating layer is flush with the top surface of the patterned mask layer.

[0130] The third insulating material can be any type of insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. The third insulating material can be the same as or different from the second insulating material. In this embodiment, the third insulating material, the second insulating material, and the first insulating material are all the same.

[0131] like Figure 2o As shown, a third insulating material is filled between the fourth etched groove E and the exposed active post with a second preset height to form a top insulating layer 210, the top surface of which is flush with the top surface of the patterned mask layer 202.

[0132] In some embodiments, the method of forming the semiconductor structure further includes: removing a patterned mask layer from the surface of each active pillar to expose the top surface of the active pillar.

[0133] like Figure 2p As shown, the patterned mask layer 202 on the surface of the active pillar is removed, exposing the top surface of the active pillar 201a, and the top insulating layer 210 is subjected to chemical mechanical polishing (CMP) so that the top surface of the top insulating layer 210 is flush with the top surface of the active pillar 201a.

[0134] In some embodiments, the method for forming the semiconductor structure further includes forming a capacitor structure on the top surface of the active pillar. The capacitor structure may be a pillar-shaped capacitor or a cup-shaped capacitor.

[0135] The semiconductor structure formed by the semiconductor structure formation method provided in this application embodiment has bit lines buried inside the semiconductor substrate, and the source and drain of the transistor are located at the vertical ends of the active pillar, respectively. The source is connected to the buried bit line of the semiconductor structure, and the drain is connected to the formed capacitor structure. In this application embodiment, the buried word line is a ring gate structure. The voltage signal on the word line can control the transistor to turn on or off, thereby reading the data information stored in the capacitor structure through the bit line, or writing the data information into the capacitor structure for storage through the bit line.

[0136] The semiconductor structure formed by the semiconductor structure formation method provided in this application embodiment has adjacent transistors sharing a single embedded bit line. The structure and fabrication process of the bit line are simple and can effectively conduct electricity. Thus, not only is the integration and electrical performance of the formed semiconductor structure improved, but the production cost of the semiconductor structure is also reduced.

[0137] Figures 3a-3k This is another schematic diagram of the semiconductor structure formation process provided in the embodiments of this application. Please refer to the following. Figures 3a-3k The method for forming a semiconductor structure provided in the embodiments of this application will be further described in detail.

[0138] First, step S101 is performed to provide a substrate; the substrate includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate; the well region includes a plurality of active pillars spaced apart along a first direction, and each of the active pillars includes a plurality of active pillars spaced apart along a second direction; wherein the first direction is perpendicular to the second direction.

[0139] The implementation process of step S101 is the same as that of step S101 in the above embodiments, and will not be repeated here.

[0140] In some embodiments, after forming the active pillar, the method for forming the semiconductor structure further includes:

[0141] Fill the space between any two adjacent active posts with a first insulating material.

[0142] Each pair of adjacent active column columns is then identified as an active column group.

[0143] At least two adjacent active pillar groups are etched to form a first insulating material to form a plurality of third etched grooves; wherein the bottom of the third etched grooves is located inside the semiconductor substrate.

[0144] The third etched groove is filled with a second insulating material.

[0145] Next, you can refer to Figure 3a and 3bStep S102 is performed to etch at least the well region at the bottom of each active pillar and a portion of the semiconductor substrate to form multiple bit line trenches.

[0146] In this embodiment of the application, the bit line trench includes a second bit line trench; the second bit line trench can be formed by the following steps:

[0147] Along a third direction, at least the first insulating material between two adjacent active pillar columns in each of the active pillar groups is etched to form a plurality of second etched grooves; wherein the third direction, the first direction and the second direction are perpendicular to each other.

[0148] like Figure 3a As shown, along the Z-axis direction, the first insulating material 203 between two adjacent active pillars in each active pillar group, as well as the well region and a portion of the semiconductor substrate located at the bottom of the first insulating material 203 between two adjacent active pillars, are etched to form a plurality of second etched grooves D, the second etched grooves D exposing the semiconductor substrate 200.

[0149] In this embodiment, a dry etching process can be used to etch the first insulating material, the well region, and part of the semiconductor substrate to form the second etched groove, such as plasma etching, reactive ion etching, or ion milling.

[0150] Along the first direction, the well region at the bottom of the active pillar and a portion of the semiconductor substrate are etched to form the second bit line trench; wherein the bottom of the second bit line trench is flush with the bottom of the second etched groove.

[0151] like Figure 3b As shown, a second bit line trench C2 is formed by etching the well region at the bottom of the source pillar and a portion of the semiconductor substrate along the X-axis direction. The bottom of the second bit line trench C2 is flush with the bottom of the second etched groove D. In this embodiment, the etching along the X-axis direction when forming the second bit line trench C2 can be wet etching or bias dry lateral etching.

[0152] In this embodiment of the application, etching the well region at the bottom of the active pillar and the semiconductor substrate of the corresponding thickness can, for each active pillar row, involve etching the entire well region at the bottom of each active pillar and the corresponding semiconductor substrate of the corresponding thickness, or etching a portion of the well region at the bottom of the active pillar along the X-axis direction and the corresponding semiconductor substrate of the corresponding thickness.

[0153] Next, you can refer to Figure 3c and 3d Step S103 is executed to form an embedded bit line in the bit line trench.

[0154] In this embodiment of the application, the bit line trench includes a second bit line trench, and the step of forming an embedded bit line in the bit line trench includes:

[0155] The embedded bit line is formed by depositing bit line metal material in the second bit line trench.

[0156] In some embodiments, before depositing the bit line metal material in the second bit line trench, the method further includes forming a barrier layer on the inner wall of the second bit line trench.

[0157] The barrier layer is located between the bit line metal material and the semiconductor substrate, and between the bit line metal material and the well region. The barrier layer is used to prevent the bit line metal material from diffusing into the semiconductor substrate or the well region.

[0158] like Figure 3c and 3d As shown, a barrier layer 205 is formed in the second bit line trench C2, and bit line metal material is deposited in the second bit line trench with the barrier layer 205 to form an embedded bit line 206.

[0159] In this embodiment of the application, the embedded bit line located in the second bit line trench has two active pins adjacent to each other along the first direction in the active pin group with independent bottoms.

[0160] It should be noted that in the embodiments of this application, when depositing bit line metal material in the second bit line trench, bit line metal material will also be partially deposited in the second etching groove D. Subsequently, the bit line metal material deposited in the second etching groove D needs to be etched back, and only the bit line metal material located in the second bit line trench C2 is retained as the embedded bit line.

[0161] In some embodiments, after forming the embedded bit line in the second bit line trench, the method of forming the semiconductor structure further includes filling the second etched groove with a second insulating material.

[0162] like Figure 3e As shown, the second etched groove D is filled with a second insulating material 204.

[0163] In some embodiments, after filling the second etched groove with a second insulating material, the method for forming the semiconductor structure further includes the following steps:

[0164] Along the third direction, a portion of the second insulating material between any two adjacent active pillars is etched to expose an active pillar with a first preset height; wherein, the first preset height is less than the initial height of the active pillar.

[0165] like Figure 3fAs shown, along the Z-axis, a portion of the second insulating material 204 between any two adjacent active pillars is etched, exposing an active pillar 201a with a first preset height h1, wherein the first preset height h1 is less than the initial height h0 of the active pillar 201a. In this embodiment, the height difference between the initial height h0 and the first preset height h1 can be 10nm-50nm.

[0166] Embedded letter lines are formed on the exposed sidewall of the active column with a first preset height.

[0167] In this embodiment, the process of forming embedded letter lines on the exposed sidewall of the active column with a first preset height is the same as in the above embodiment, and will not be described in detail here.

[0168] like Figure 3g and 3h As shown, a gate oxide layer 207 and a word line metal layer 208 are formed on the sidewall of the exposed active pillar 201a with a first preset height, and an active pillar with a second preset height h2 is exposed. The second preset height h2 is less than the first preset height h1. In this embodiment, the second preset height includes 10nm-50nm.

[0169] The word line metal layer is graphically represented to form the embedded word line.

[0170] In some embodiments, the process of patterning the word line metal layer to form the embedded word line includes: etching the word line metal layer along the third direction and retaining the word line metal layer between two adjacent active pillars in the first direction to form the embedded word line and a fourth etched groove extending along the first direction.

[0171] like Figure 3i As shown, word line metal layer 208 is etched along the Z-axis direction, while word line metal layer between two adjacent active pillars 201a is retained in the X-axis direction, forming embedded word line 209 and fourth etched groove E extending along the X-axis direction.

[0172] In some embodiments, the method of forming the semiconductor structure further includes: filling a third insulating material between the fourth etched groove and the exposed active pillar having a second predetermined height to form a top insulating layer; wherein the top surface of the top insulating layer is flush with the top surface of the patterned mask layer.

[0173] like Figure 3j As shown, a third insulating material is filled between the fourth etched groove E and the exposed active post with a second preset height to form a top insulating layer 210, the top surface of which is flush with the top surface of the patterned mask layer 202.

[0174] In some embodiments, the method of forming the semiconductor structure further includes: removing a patterned mask layer from the surface of each active pillar to expose the top surface of the active pillar.

[0175] like Figure 3k As shown, the patterned mask layer 202 on the surface of the active pillar is removed to expose the top surface of the active pillar 201a, and the top insulating layer 210 is chemically and mechanically polished so that the top surface of the top insulating layer 210 is flush with the top surface of the active pillar 201a.

[0176] In some embodiments, the method for forming the semiconductor structure further includes forming a capacitor structure on the top surface of the active pillar. The capacitor structure may be a pillar-shaped capacitor or a cup-shaped capacitor.

[0177] The method for forming a semiconductor structure provided in this application is similar to the method for forming a semiconductor structure in the above embodiments. For technical features not disclosed in detail in this application, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0178] The semiconductor structure formed by the semiconductor structure formation method provided in this application has an independent buried bit line for each transistor. The structure and fabrication process of the bit line are simple and can effectively conduct electricity. Thus, not only is the integration and electrical performance of the formed semiconductor structure improved, but the production cost of the semiconductor structure is also reduced.

[0179] In addition, this application also provides a semiconductor structure, which is formed by the semiconductor structure forming method provided in the above embodiments. Figure 4a and 4b A cross-sectional view of the semiconductor structure provided in the embodiments of this application, such as Figure 4a and 4b As shown, the semiconductor structure 40 includes a substrate and a buried bit line 206.

[0180] The substrate includes a semiconductor substrate 200 and a well region 201 located on the surface of the semiconductor substrate 200; the well region 201 includes a plurality of active pillars spaced apart along the X-axis direction, and each of the active pillars includes a plurality of active pillars 201a spaced apart along the Y-axis direction (not shown in the figure).

[0181] The embedded bit line 206 is located in a bit line trench, and the bit line trench is located at least in the well region at the bottom of each active pillar and in a portion of the semiconductor substrate.

[0182] In this embodiment, the bit line trench includes a first bit line trench or a second bit line trench; each pair of adjacent active post columns constitutes an active post group; wherein, the embedded bit lines located in the first bit line trench are interconnected at the bottoms of two adjacent active posts along the X-axis direction in the active post group (e.g., Figure 4a (as shown); the embedded bit line located in the second bit line trench, the bottoms of two adjacent active pins in the active pin group along the X-axis direction are independent of each other (as shown). Figure 4b (As shown).

[0183] In some embodiments, please continue to see Figure 4a and 4b The semiconductor structure 40 further includes a barrier layer 205 located between the semiconductor substrate and the buried bit line, and between the well region and the buried bit line, the barrier layer 205 being used to prevent the bit line metal material of the buried bit line from diffusing into the semiconductor substrate or the well region.

[0184] In some embodiments, please continue to see Figure 4a and 4b The semiconductor structure 40 further includes a gate oxide layer 207 and a buried word line 209 located on the sidewall of the active pillar, the buried word line 209 forming a fully encircling gate structure of the semiconductor structure 40.

[0185] In some embodiments, the semiconductor structure further includes a capacitor structure (not shown) located on the surface of the active pillar.

[0186] The semiconductor structure in this application embodiment is similar to the semiconductor structure formation method in the above embodiments. For technical features not disclosed in detail in this application embodiment, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0187] The semiconductor structure provided in this application embodiment has bit lines embedded inside the semiconductor substrate, which enables the bit lines to conduct effectively and has strong control capabilities, thereby improving the electrical performance of the formed semiconductor device. In addition, the embedded bit lines formed in this application embodiment can also improve the integration of the semiconductor device and increase the application range of the semiconductor device.

[0188] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0189] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0190] The features disclosed in the several method or structural embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0191] The above descriptions are merely some embodiments of this application, but the protection scope of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the protection scope of this application. Therefore, the protection scope of this application should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: A substrate is provided; the substrate includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate; the well region includes a plurality of active pillar rows spaced apart along a first direction, and each of the active pillar rows includes a plurality of active pillars spaced apart along a second direction; wherein the first direction is perpendicular to the second direction; At least the well region at the bottom of each active pillar and a portion of the semiconductor substrate are etched to form multiple bit line trenches; The bit line trench includes a first bit line trench or a second bit line trench; bit line metal material is deposited in the first bit line trench or the second bit line trench to form an embedded bit line; The method further includes: Each pair of adjacent active column columns is sequentially identified as an active column group; The embedded bit line located in the first bit line trench is interconnected at the bottom of two adjacent active columns in the active column group along the first direction. The embedded bit line located in the second bit line trench has two active pins adjacent to each other along the first direction in the active pin group with independent bottoms. A first insulating material is filled between any two adjacent active posts; the first bit line trench is formed by the following steps: Along a third direction, the first insulating material between two adjacent rows of active pillars in each active pillar group is etched to form a plurality of first etched grooves; wherein the third direction, the first direction, and the second direction are mutually perpendicular; Starting from the bottom of the first etched groove, the well region at the bottom of the first etched groove and a portion of the semiconductor substrate are etched along the third direction, and the well region at the bottom of the active pillar and a portion of the semiconductor substrate are etched along the first direction to form the first bit line trench.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The method further includes: After the embedded bit line is formed in the first bit groove, the second insulating material is filled in the first etched groove.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, A first insulating material is filled between any two adjacent active posts; the second bit trench is formed by the following steps: Along a third direction, at least the first insulating material between two adjacent rows of active pillars in each active pillar group is etched to form a plurality of second etched grooves; wherein the third direction, the first direction, and the second direction are mutually perpendicular; Along the first direction, the well region at the bottom of the active pillar and a portion of the semiconductor substrate are etched to form the second bit line trench; wherein the bottom of the second bit line trench is flush with the bottom of the second etched groove.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, The method further includes: After the embedded bit line is formed in the second bit line trench, the second etched groove is filled with a second insulating material.

5. The method for forming a semiconductor structure according to claim 2 or 4, characterized in that, The method further includes: Before depositing the bit line metal material in the first bit line trench or the second bit line trench, a barrier layer is formed on the inner wall of the first bit line trench or the second bit line trench.

6. The method according to claim 5, characterized in that, The active column is formed in the following manner: A patterned mask layer is formed on the surface of the trap region; The patterned mask layer is used to etch a portion of the depth of the well region to form a plurality of active pillars spaced apart along the first direction and the second direction.

7. The method according to claim 6, characterized in that, Before forming the bit line trench, the method further includes: At least the first insulating material between two adjacent active pillar groups is etched to form a plurality of third etched grooves; wherein the bottom of the third etched grooves is located inside the semiconductor substrate; The second insulating material is filled into the third etched groove.

8. The method according to claim 7, characterized in that, The method further includes: Along the third direction, a portion of the second insulating material between any two adjacent active pillars is etched to expose an active pillar with a first preset height; wherein, the first preset height is less than the initial height of the active pillar; Embedded letter lines are formed on the exposed sidewall of the active column with a first preset height.

9. The method according to claim 8, characterized in that, The process of forming embedded letter lines on the exposed sidewall of an active column with a first preset height includes: A gate oxide layer is formed on the sidewall of the exposed active pillar with a first preset height; A word line metal layer is formed by filling the space between any two adjacent active pillars having the gate oxide layer. The gate oxide layer and the word line metal layer are etched back to expose an active pillar with a second preset height; the second preset height is less than the first preset height. The word line metal layer is graphically represented to form the embedded word line.

10. The method according to claim 9, characterized in that, The patterning of the word line metal layer to form the embedded word line includes: The word line metal layer is etched along the third direction, and the word line metal layer between two adjacent active pillars in the first direction is retained to form the embedded word line and the fourth etched groove extending along the first direction.

11. The method according to claim 10, characterized in that, The method further includes: A third insulating material is filled between the fourth etched groove and the exposed active post with a second preset height to form a top insulating layer; wherein the top surface of the top insulating layer is flush with the top surface of the patterned mask layer.

12. The method according to claim 11, characterized in that, The method further includes: Remove the patterned mask layer from the surface of each active pillar to expose the top surface of the active pillar; A capacitor structure is formed on the top surface of the active pillar.

13. A semiconductor structure, characterized in that, The semiconductor structure is formed by the semiconductor structure forming method according to any one of claims 1 to 12; the semiconductor structure comprises: A substrate; the substrate includes a semiconductor substrate and a well region located on the surface of the semiconductor substrate; the well region includes a plurality of active pillar rows spaced apart along a first direction, and each of the active pillar rows includes a plurality of active pillars spaced apart along a second direction; wherein the first direction is perpendicular to the second direction; Buried bit lines; the buried bit lines are located in bit line trenches, and the bit line trenches are located at least in the well region at the bottom of each of the active pillars and in a portion of the thickness of the semiconductor substrate.

14. The semiconductor structure according to claim 13, characterized in that, The bit line trench includes a first bit line trench or a second bit line trench; each pair of adjacent active column columns constitutes an active column group; Among them, the embedded bit line located in the first bit line trench is connected to the bottom of two adjacent active columns in the active column group along the first direction. The embedded bit line located in the second bit line trench has two active pins adjacent to each other along the first direction in the active pin group with independent bottoms.

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