An antifuse device and method of manufacturing the same

Abstract

Embodiments of the present disclosure provide an antifuse device and a manufacturing method thereof. The antifuse device comprises: a first doped region and a second doped region arranged in a substrate; a gate oxide layer on the substrate, the gate oxide layer comprising a first gate oxide layer and a second gate oxide layer arranged next to each other along a first direction, the second gate oxide layer having a length along a second direction greater than a length of the first gate oxide layer along the second direction, wherein the first direction and the second direction are both parallel to a surface of the substrate; the second gate oxide layer comprising a first portion between the first doped region and the second doped region and a second portion between the first doped region and the first gate oxide layer; the first gate oxide layer having a thickness along a third direction less than a thickness of the second gate oxide layer along the third direction, wherein the third direction is a direction perpendicular to the surface of the substrate; and a gate electrode on the gate oxide layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor manufacturing, and particularly relate to a reverse fuse device and a manufacturing method thereof. BACKGROUND

[0002] One-Time-Programmable Read Only Memory (OTPROM) can be programmed by the user once, providing a certain flexibility for the user, but once programmed, the data cannot be erased by electricity, thus simplifying the design complexity and reducing the cost.

[0003] At present, OTP read-only memories include fuse type and reverse fuse type. Among them, the storage unit of the fuse type memory is conductive when no data is written, presenting a low resistance state, which is one state; through certain mechanisms such as high temperature and high voltage, the storage unit is fused, presenting a high resistance state, thereby realizing data writing, which is another state. The storage unit of the reverse fuse type memory is disconnected when no data is written, presenting a high resistance state, which is one state; through a certain mechanism to break down the storage unit, the storage unit is conductive, presenting a low resistance state, thereby realizing the data writing process, which is another state. SUMMARY

[0004] Therefore, embodiments of the present disclosure provide a reverse fuse device and a manufacturing method thereof to solve at least one technical problem in the prior art.

[0005] To achieve the above object, the technical scheme of the present disclosure is as follows:

[0006] In a first aspect, the embodiments of the present disclosure provide a reverse fuse device, which comprises:

[0007] a first doped region and a second doped region arranged in a substrate;

[0008] a gate oxide layer located on the substrate, the gate oxide layer comprising a first gate oxide layer and a second gate oxide layer arranged adjacent along a first direction, the length of the second gate oxide layer along a second direction being greater than the length of the first gate oxide layer along the second direction, wherein the first direction and the second direction are both parallel to the substrate surface; the second gate oxide layer comprises a first part between the first doped region and the second doped region and a second part between the first doped region and the first gate oxide layer; the thickness of the first gate oxide layer along a third direction is less than the thickness of the second gate oxide layer along the third direction, wherein the third direction is a direction perpendicular to the substrate surface;

[0009] a gate located on the gate oxide layer.

[0010] In some embodiments, the first part of the second gate oxide layer and the first gate oxide layer are respectively located on two adjacent sides of the second doped region.

[0011] In some embodiments, a projection of the gate on the substrate is L-shaped.

[0012] In some embodiments, an area of a projection of the second doped region on the substrate is less than an area of a projection of the first doped region on the substrate.

[0013] In some embodiments, a length of a projection of the second doped region on the substrate along the second direction and a length of the first gate oxide layer along the second direction are equal to a length of the second gate oxide layer along the second direction.

[0014] In some embodiments, a sum of areas of projections of the second doped region and the first gate oxide layer on the substrate is equal to an area of a projection of the second gate oxide layer on the substrate.

[0015] In some embodiments, the antifuse device further comprises:

[0016] a word line, the word line being connected with the gate;

[0017] a bit line, the bit line being connected with the first doped region or the second doped region.

[0018] In some embodiments, the first doped region is a source region, and the second doped region is a drain region; or, the first doped region is a drain region, and the second doped region is a source region.

[0019] In a second aspect, the embodiments of the present disclosure provide a manufacturing method of an antifuse device, the manufacturing method comprising:

[0020] providing a substrate;

[0021] forming a gate oxide layer on the substrate; the gate oxide layer comprises a first gate oxide layer and a second gate oxide layer arranged next to each other along a first direction, a length of the second gate oxide layer along a second direction is greater than a length of the first gate oxide layer along the second direction, wherein the first direction and the second direction are both parallel to a substrate surface; the second gate oxide layer comprises a first part and a second part in contact with the first gate oxide layer along the second direction; a thickness of the first gate oxide layer along a third direction is less than a thickness of the second gate oxide layer along the third direction, wherein the third direction is a direction perpendicular to the substrate surface;

[0022] forming a gate on the gate oxide layer;

[0023] a first doped region is formed in the substrate on a side of the second gate oxide layer away from the first gate oxide layer, and a second doped region is formed in the substrate on a side of the first portion of the second gate oxide layer away from the first doped region.

[0024] In some embodiments, the first portion of the second gate oxide layer and the first gate oxide layer are respectively located on two adjacent sides of the second doped region.

[0025] In some embodiments, a projection of the gate on the substrate is L-shaped.

[0026] In some embodiments, an area of a projection of the second doped region on the substrate is less than an area of a projection of the first doped region on the substrate.

[0027] In some embodiments, a length of a projection of the second doped region on the substrate along the second direction and a length of the first gate oxide layer along the second direction are equal to a length of the second gate oxide layer along the second direction.

[0028] In some embodiments, an area of a projection of the second doped region and the first gate oxide layer on the substrate is equal to an area of a projection of the second gate oxide layer on the substrate.

[0029] In some embodiments, the manufacturing method further comprises:

[0030] forming a word line, the word line being connected with the gate;

[0031] forming a bit line, the bit line being connected with the first doped region or the second doped region.

[0032] In some embodiments, the first doped region is a source region, and the second doped region is a drain region; or, the first doped region is a drain region, and the second doped region is a source region.

[0033] The embodiment of the present disclosure provides a antifuse device and a manufacturing method thereof. The antifuse device comprises: a first doped region and a second doped region arranged in a substrate; a gate oxide layer located on the substrate, the gate oxide layer comprises a first gate oxide layer and a second gate oxide layer arranged in a first direction, the length of the second gate oxide layer along a second direction is greater than the length of the first gate oxide layer along the second direction, wherein the first direction and the second direction are parallel to the surface of the substrate; the second gate oxide layer comprises a first part between the first doped region and the second doped region and a second part between the first doped region and the first gate oxide layer; the thickness of the first gate oxide layer along a third direction is less than the thickness of the second gate oxide layer along the third direction, wherein the third direction is a direction perpendicular to the surface of the substrate; a gate electrode located on the gate oxide layer. In the embodiment of the present disclosure, the length of the first gate oxide layer is reduced, so that the length of the first gate oxide layer is less than the length of the second gate oxide layer; the first doped region is arranged in the substrate away from the first part of the second gate oxide layer, and the second doped region is arranged in the substrate away from the second part of the second gate oxide layer; the positional relationship among the first doped region, the second doped region, the first gate oxide layer, the second gate oxide layer and the gate electrode is reasonably adjusted, the structure of the antifuse device is improved, so that the area of the antifuse device is reduced, and the storage density of the antifuse device is further improved. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A planar layout diagram of two antifuse units provided by an embodiment of the present disclosure is provided.

[0035] Figure 2 A planar layout diagram of an antifuse unit provided by an embodiment of the present disclosure is provided.

[0036] Figure 3 A planar layout diagram of two antifuse units provided by another embodiment of the present disclosure is provided. Figure 2 A cross-sectional structure schematic diagram of the antifuse unit along the AA line in the embodiment is provided.

[0037] Figure 4 A planar layout diagram of two antifuse units provided by another embodiment of the present disclosure is provided.

[0038] Figure 5 A planar layout diagram of an antifuse unit provided by another embodiment of the present disclosure is provided.

[0039] Figure 6 A planar layout diagram of two antifuse units provided by another embodiment of the present disclosure is provided. Figure 5 A cross-sectional structure schematic diagram of the antifuse unit along the BB line in the embodiment is provided.

[0040] Figure 7 A cross-sectional structure schematic diagram of the antifuse unit along the CC line in the embodiment is provided. Figure 5

[0041] ​Figure 8 A flowchart of a manufacturing method of a fuse device is provided for the embodiments of the present disclosure.

[0042] Figure 9 A process cross-sectional structure diagram of forming a first gate oxide layer and a second gate oxide layer is provided for the embodiments of the present disclosure.

[0043] The figures include: 101, 201, substrate; 102, 202, active region; 103, source; 203, second doped region; 104, drain; 204, first doped region; 105, 205, P-well region; 106, 206, gate oxide layer; 106a, thin gate oxide layer; 106b, thick gate oxide layer; 206a, first gate oxide layer; 206b, second gate oxide layer; 107, 207, gate; 208, isolation layer; 209, silicide layer; 210, bit line contact pad; 301, channel region; 302, first gate oxide region; 303, second gate oxide region; 304, first oxide layer; 305, second oxide layer. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0045] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid obscuring the present disclosure, some technical features known in the art are not described; that is, not all features of the actual embodiments are described here, and well-known functions and structures are not described in detail.

[0046] In the drawings, the sizes of layers, regions, elements and their relative sizes can be exaggerated for clarity. The same reference signs represent the same elements throughout.

[0047] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0048] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0049] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0050] For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description in order to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail as follows, however, in addition to these detailed descriptions, the present disclosure can also have other implementation manners.

[0051] Read Only Memory (ROM) stores fixed data, which can generally only be read out. Once the information is stored in the read only memory, it cannot be easily changed, and it will not be lost when power is off. ROM is a memory that only provides readout in a computer system. According to different data writing methods, ROM can be divided into fixed ROM and programmable ROM. The latter can be further divided into programmable read only memory (PROM), OTP read only memory, programmable erasable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash memory (Flash ROM) and the like.

[0052] OTP read only memory can be programmed by the user once, which provides a certain flexibility for the user, but once programmed, the data cannot be erased by electricity, thus simplifying the design complexity and reducing the cost.

[0053] At present, OTP read only memory includes fuse type and anti-fuse type. Among them, the anti-fuse memory, before programming, the anti-fuse is a high resistance insulating medium equivalent to a capacitor, almost no current flows through, the data read out by the storage unit is "0"; after programming, a programming voltage is applied, the anti-fuse is broken down, equivalent to a low resistance conductor, the circuit is turned on, a certain current can pass through, the data read out by the storage unit is "1". The anti-fuse storage unit after being broken down forms a permanent conduction circuit, and no matter how many times the subsequent reading process is read, it will not affect the state of the anti-fuse.

[0054] The anti-fuse memory mainly includes upper and lower electrodes and an anti-fuse dielectric layer located between the upper and lower electrodes. According to the different materials of the anti-fuse dielectric layer, the anti-fuse can be classified into oxide-nitride-oxide (ONO) anti-fuse, amorphous silicon (A-Si) anti-fuse and gate oxide layer anti-fuse.

[0055] Further, there are three structures of the gate oxide based antifuse device, which are 3-transistor (3T) structure, 1.5-transistor (1.5T) structure and 1-transistor (1T) structure. The principle of storing data of the three structures is to realize data storage by gate oxide breakdown of MOS tubes. The main difference is the number of MOS tubes of the storage unit. The 3T antifuse storage unit structure stores one bit of data by using three MOS tubes, which are a storage tube, a high-voltage blocking tube and a word line selection tube. The 1.5T antifuse storage unit structure stores one bit of data by using two MOS tubes, but the thicknesses of the gate oxides of the two MOS tubes are different, and the source of the MOS tube with the thick gate oxide and the drain of the MOS tube with the thin gate oxide are coincident. The MOS tube with the thick gate oxide is used for word line control and high-voltage protection, which is equivalent to the high-voltage blocking tube and the word line selection tube in the 3T antifuse storage unit structure. The MOS tube with the thin gate oxide is used for storing data. The 1T antifuse storage unit structure is to make a single transistor by using the MOS tubes with different thicknesses of gate oxides.

[0056] The structure of the antifuse unit provided by an embodiment of the present disclosure will be described in detail below with reference to Figure 1 , Figure 2 and Figure 3 . Here, the antifuse unit provided by an embodiment of the present disclosure is a 1T antifuse unit structure.

[0057] It should be noted that the direction perpendicular to the surface of the substrate is the Z direction. The X direction and the Y direction, which intersect with each other, are defined in the top surface or the bottom surface of the substrate perpendicular to the Z direction, and the top surface or the bottom surface of the substrate perpendicular to the Z direction can be determined based on the X direction and the Y direction. For example, the X direction and the Y direction have a certain included angle. For another example, the X direction and the Y direction are perpendicular to each other, so that the X direction, the Y direction and the Z direction are perpendicular to each other in pairs.

[0058] As shown in Figure 1 , Figure 2 and Figure 3 , the antifuse device comprises a P-well region 105 arranged in a substrate 101, an active region 102 arranged in the P-well region 105, the active region 102 comprising a source 103 and a drain 104; a gate oxide layer 106 arranged on the substrate 101, the gate oxide layer 106 comprising a thin gate oxide layer 106a and a thick gate oxide layer 106b arranged side by side; and a gate 107 arranged on the gate oxide layer 106. Figure 1 and Figure 2 , the dashed box schematically shows the active region 102, Figure 1 and Figure 2 , the solid box schematically shows the antifuse unit.

[0059] It should be noted that, in order to show the positional relationship between the thin gate oxide layer 106a and the thick gate oxide layer 106b, Figure 1 and Figure 2 The filling patterns of the thin gate oxide layer 106a and the thick gate oxide layer 106b are different, which does not mean that the materials of the thin gate oxide layer 106a and the thick gate oxide layer 106b are different. The thin gate oxide layer 106a and the thick gate oxide layer 106b can still be made of the same material. Figure 3 The materials of the thin gate oxide layer 106a and the thick gate oxide layer 106b are the same.

[0060] In addition, in order to show the positional relationship between the thin gate oxide layer 106a and the thick gate oxide layer 106b, and to avoid the gate 107 from blocking the thin gate oxide layer 106a and the thick gate oxide layer 106b, Figure 1 and Figure 2 It can be regarded as a perspective view of the thin gate oxide layer 106a and the thick gate oxide layer 106b through the gate 107, that is, the thin gate oxide layer 106a and the thick gate oxide layer 106b block the gate 107, which does not mean that the thin gate oxide layer 106a and the thick gate oxide layer 106b are actually located above the gate 107.

[0061] Here, the formation of the active region (i.e., the source and the drain) in the substrate can use an ion implantation process. The particles to be doped are incident on the substrate by means of an ion beam, and through a series of physical and chemical interactions, the doped particles gradually lose energy and stay in the substrate to form the source or the drain. The present disclosure does not make special limitations on the doping type of the source and the drain, for example, the source and the drain can be N-type doped.

[0062] Here, the source and the drain can have the same area of the orthographic projection on the substrate.

[0063] Still referring to Figure 1 and Figure 2 The gate oxide layer 106 is located between the source 103 and the drain 104, and the gate oxide layer 106 includes the thin gate oxide layer 106a and the thick gate oxide layer 106b. The thin gate oxide layer 106a and the thick gate oxide layer 106b are arranged side by side along the X direction, and the sidewalls of the thin gate oxide layer 106a and the thick gate oxide layer 106b directly contact each other. The materials of the thin gate oxide layer 106a and the thick gate oxide layer 106b can be the same.

[0064] Here, the thin gate oxide layer is located between the thick gate oxide layer and the source, and the thick gate oxide layer is located between the drain and the thin gate oxide layer.

[0065] Here, the thin gate oxide layer and the thick gate oxide layer can have the same width along the X direction, and / or the thin gate oxide layer and the thick gate oxide layer can have the same length along the Y direction.

[0066] Here, the orthographic projection area of the thin gate oxide layer and the thick gate oxide layer on the substrate can be equal.

[0067] Here, the thickness of the thin gate oxide layer along the Z direction is less than the thickness of the thick gate oxide layer along the Z direction. Figure 3 The illustrated thin gate oxide layer and thick gate oxide layer can be made of the same material, and there is no contact interface between the thin gate oxide layer and the thick gate oxide layer.

[0068] Here, the gate oxide layer includes a thin gate oxide layer and a thick gate oxide layer, the thin gate oxide layer breaks down at a high voltage to generate a conductive channel connecting the gate and the channel region (i.e., between the source and the drain); and the thick gate oxide layer can withstand high voltage and will not be damaged at a programming voltage.

[0069] The above Figures 1 to 3 The illustrated antifuse cell structure has equal orthographic projection areas of the source and the drain on the substrate, the gate oxide layer is located on the substrate and between the source and the drain, and the orthographic projection areas of the thin gate oxide layer and the thick gate oxide layer on the substrate are equal. In this way, the active area of the antifuse cell structure is large, and the area of the antifuse cell structure is large, and the antifuse cell structure needs to be further improved.

[0070] Therefore, the present disclosure provides an antifuse device and a manufacturing method thereof.

[0071] The structure of the antifuse cell provided by another embodiment of the present disclosure will be described in detail below with reference to Figure 4 , Figure 5 , Figure 6 and Figure 7 The antifuse cell provided by another embodiment of the present disclosure is a 1T antifuse cell structure.

[0072] It should be noted that the first direction is the X direction, the second direction is the Y direction, and the first direction and the second direction are both parallel to the substrate surface; the third direction is the Z direction, and the third direction is perpendicular to the substrate surface. Among them, the first direction and the second direction can be perpendicular to each other, so that the first direction, the second direction and the third direction are perpendicular to each other.

[0073] As Figure 4 , Figure 5 , Figure 6 and Figure 7As shown, the antifuse device comprises: an active region 202 (i.e., a second doped region 203 and a first doped region 204) disposed in a substrate 201; a gate oxide layer 206 located on the substrate 201, the gate oxide layer 206 comprising a first gate oxide layer 206a and a second gate oxide layer 206b disposed next to each other along a first direction (i.e., an X direction), the second gate oxide layer 206b having a length along a second direction (i.e., a Y direction) greater than a length of the first gate oxide layer 206a along the second direction (i.e., the Y direction); the second gate oxide layer 206b comprising a first portion between the first doped region 204 and the second doped region 203 and a second portion between the first doped region 204 and the first gate oxide layer 206a; the first gate oxide layer 206a having a thickness along a third direction (i.e., a Z direction) less than a thickness of the second gate oxide layer 206b along the third direction (i.e., the Z direction); and a gate electrode 207 located on the gate oxide layer 206. Figure 4 and Figure 5 The dashed box in FIG. 1A schematically shows the active region 202, Figure 4 and Figure 5 The solid box in FIG. 1A schematically shows the antifuse cell.

[0074] It should be noted that, in order to schematically show the positional relationship between the first gate oxide layer 206a and the second gate oxide layer 206b, Figure 4 and Figure 5 The different filling patterns of the first gate oxide layer 206a and the second gate oxide layer 206b do not mean that the first gate oxide layer 206a and the second gate oxide layer 206b are made of different materials, and the first gate oxide layer 206a and the second gate oxide layer 206b can still be made of the same material. Figure 6 The first gate oxide layer 206a and the second gate oxide layer 206b are made of the same material.

[0075] In addition, in order to schematically show the positional relationship between the first gate oxide layer 206a and the second gate oxide layer 206b, and to avoid the gate electrode 207 from blocking the first gate oxide layer 206a and the second gate oxide layer 206b, Figure 4 and Figure 5 The perspective view of the first gate oxide layer 206a and the second gate oxide layer 206b through the gate electrode 207 can be regarded as a perspective view of the first gate oxide layer 206a and the second gate oxide layer 206b, i.e., the first gate oxide layer 206a and the second gate oxide layer 206b block the gate electrode 207, which does not mean that the first gate oxide layer 206a and the second gate oxide layer 206b are actually located above the gate electrode 207.

[0076] Here, the P-well region 205, the second doped region 203 and the first doped region 204 formed in the substrate 201 can all use an ion implantation process. The present disclosure does not make special limitations on the doping type of the first doped region and the second doped region, for example, the first doped region and the second doped region can be N-type doped.

[0077] In some embodiments, the first doped region is the source region and the second doped region is the drain region; or, the first doped region is the drain region and the second doped region is the source region.

[0078] Here, the first doped region can be the drain region, and the second doped region can be the source region. Thus, the first portion of the second gate oxide layer is located between the source and drain regions, and the second portion of the second gate oxide layer is located between the first gate oxide layer and the drain region. Alternatively, the first doped region can be the source region, and the second doped region can be the drain region. Thus, the first portion of the second gate oxide layer is located between the source and drain regions, and the second portion of the second gate oxide layer is located between the source and the first gate oxide layer.

[0079] In this embodiment of the disclosure, the substrate may be a semiconductor substrate; specifically, it may include at least one elemental semiconductor material (e.g., silicon (Si) substrate, germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., gallium nitride (GaN) substrate, gallium arsenide (GaAs) substrate, indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. It may also include other substrates containing semiconductor materials, such as silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, polycrystalline semiconductor layers on insulating layers, silicon-germanium substrates, etc.

[0080] In some embodiments, the projected area of ​​the second doped region on the substrate is smaller than the projected area of ​​the first doped region on the substrate.

[0081] Here, as Figure 5 As shown, the length of the orthographic projection of the second doped region 203 on the substrate along the Y direction is the difference between the length L2 of the second gate oxide layer and the length L1 of the first gate oxide layer along the Y direction, i.e., (L2-L1); the width of the orthographic projection of the second doped region 203 on the substrate along the X direction is the width of the first gate oxide layer along the X direction, i.e., W1; the area of ​​the orthographic projection of the second doped region 203 on the substrate is (L2-L1)*W1. The length of the orthographic projection of the first doped region 204 on the substrate along the Y direction is the length of the second gate oxide layer along the Y direction, i.e., L2; the width of the orthographic projection of the first doped region 204 on the substrate along the X direction is W3; the area of ​​the orthographic projection of the first doped region 204 on the substrate is L2*W3. By reducing the orthographic projection area of ​​the second doped region on the substrate, the orthographic projection area of ​​the active region on the substrate can be reduced, which is beneficial to reducing the area of ​​the antifuse cell, thereby achieving a higher storage density.

[0082] In this embodiment of the disclosure, the gate oxide layer is located on the substrate, and the gate oxide layer includes a first gate oxide layer and a second gate oxide layer disposed adjacent to each other along the X direction; the length L2 of the second gate oxide layer along the Y direction is greater than the length L1 of the first gate oxide layer along the Y direction.

[0083] In this embodiment of the present disclosure, the width W2 of the second gate oxide layer along the X direction can be the same as the width W1 of the first gate oxide layer along the X direction, that is, W1 = W2.

[0084] Here, the area of ​​the first gate oxide layer is L1*W1, and the area of ​​the second gate oxide layer is L2*W2. The area of ​​the first gate oxide layer is smaller than that of the second gate oxide layer. Reducing the length of the first gate oxide layer can reduce its area, which is beneficial for reducing the area of ​​the antifuse cell and thus enabling higher storage density.

[0085] In this embodiment of the disclosure, the material of the gate oxide layer may be, for example, silicon dioxide.

[0086] Here, the bottom surface of the gate oxide layer (i.e., the first gate oxide layer and the second gate oxide layer) is in direct contact with the substrate; being adjacent along the X direction means that the first gate oxide layer and the second gate oxide layer are arranged side by side along the X direction, and the sidewalls of the first gate oxide layer and the second gate oxide layer are in direct contact. Figure 6 The first gate oxide layer and the second gate oxide layer shown can be made of the same material, and there is no contact interface between the first gate oxide layer and the second gate oxide layer.

[0087] Here, the thickness of the first gate oxide layer along the Z direction is less than the thickness of the second gate oxide layer along the Z direction. The first gate oxide layer is a thin gate oxide layer, and the second gate oxide layer is a thick gate oxide layer. This embodiment does not specifically limit the exact thickness range of the first and second gate oxide layers; the thickness of the first gate oxide layer simply needs to be less than the thickness of the second gate oxide layer.

[0088] like Figure 5As shown, the first gate oxide layer 206a includes two sidewalls arranged oppositely and parallel to the X direction, and two sidewalls arranged oppositely and parallel to the Y direction; the second gate oxide layer 206b also includes two sidewalls arranged oppositely and parallel to the X direction, and two sidewalls arranged oppositely and parallel to the Y direction. The length L1 of the first gate oxide layer 206a along the Y direction refers to the length of the sidewall parallel to the Y direction, and the length L2 of the second gate oxide layer 206b along the Y direction refers to the length of the sidewall parallel to the Y direction. The sidewall parallel to the Y direction of the first gate oxide layer 206a and the sidewall parallel to the Y direction of the second gate oxide layer 206b directly contact, and since the lengths of the first gate oxide layer 206a and the second gate oxide layer 206b along the Y direction are different, part of the sidewall of the second gate oxide layer 206b is still exposed, and the length of the exposed part of the sidewall is (L2-L1).

[0089] In the embodiments of the present disclosure, the second gate oxide layer can include a first part and a second part along the Y direction, the first part of the second gate oxide layer is located between the first doped region and the second doped region, and the second part of the second gate oxide layer is located between the first doped region and the first gate oxide layer.

[0090] Here, the first doped region is arranged in the substrate away from one side of the second gate oxide layer, the second doped region is arranged in the substrate close to one side of the second gate oxide layer, or the second doped region is arranged in the substrate away from one side of the first part of the second gate oxide layer. The length of the orthographic projection of the second doped region on the substrate along the Y direction (i.e., (L2-L1)) is less than the length of the orthographic projection of the first doped region on the substrate along the Y direction (i.e., L2), and the area of the orthographic projection of the second doped region on the substrate is less than the area of the orthographic projection of the first doped region on the substrate.

[0091] Figure 6 For Figure 5 A cross-sectional structure schematic diagram of the antifuse cell along the BB line, Figure 7 For Figure 5 A cross-sectional structure schematic diagram of the antifuse cell along the CC line. Figure 7 A cross-sectional structure of the first part of the second gate oxide layer 206b is shown, and the first part of the second gate oxide layer 206b is located between the second doped region 203 and the first doped region 204. Figure 6 A cross-sectional structure of the second part of the second gate oxide layer 206b is shown, and the second part of the second gate oxide layer 206b is located between the first doped region 204 and the first gate oxide layer 206a.

[0092] Here, the area of the first gate oxide layer is reduced, the area of the second doped region is reduced, and the positional relationship among the first doped region, the second doped region, the first gate oxide layer, and the second gate oxide layer is reasonably adjusted, the structure of the antifuse device is improved, so that in the plan layout, the first gate oxide layer and the second doped region are arranged side by side along the Y direction, thereby reducing the area of the antifuse device and further improving the storage density of the antifuse device.

[0093] In some embodiments, the gate covers the gate oxide layer (i.e., the first gate oxide layer and the second gate oxide layer), and the orthogonal projection of the gate on the substrate is L-shaped. Here, considering that the thicknesses of the part of the gate located on the first gate oxide layer and the part of the gate located on the second gate oxide layer along the Z direction are different, the thicknesses of the part of the gate located on the first gate oxide layer and the part of the gate located on the second gate oxide layer along the Z direction can be the same, and therefore, the surface of the gate away from the substrate is not flat. More specifically, the surface of the gate located on the first gate oxide layer is lower than the surface of the gate located on the second gate oxide layer.

[0094] In the embodiments of the present disclosure, the material of the gate can include but is not limited to a metal material and polysilicon. In the embodiments, since the forming processes of the active region, the gate oxide layer, and the gate are the same as those of the active region, the gate oxide layer, and the gate of the MOS transistor in the prior art, the embodiments are compatible with the prior art and do not increase additional process costs.

[0095] In some embodiments, the first part of the second gate oxide layer and the first gate oxide layer are located on two adjacent sides of the second doped region, respectively.

[0096] In some embodiments, the sum of the length of the orthogonal projection of the second doped region 203 on the substrate along the Y direction and the length of the first gate oxide layer 206a along the Y direction is equal to the length of the second gate oxide layer 206b along the Y direction.

[0097] Here, the length of the first gate oxide layer along the Y direction is reduced, the length of the orthogonal projection of the second doped region on the substrate along the Y direction is reduced, and the positional relationship among the first doped region, the second doped region, the first gate oxide layer, and the second gate oxide layer is reasonably adjusted, so that the sum of the length of the orthogonal projection of the second doped region on the substrate along the Y direction and the length of the first gate oxide layer along the Y direction is equal to the length of the second gate oxide layer along the Y direction, the structure of the antifuse device is improved, thereby reducing the area of the antifuse device and further improving the storage density of the antifuse device.

[0098] In some embodiments, the sum of the areas of the orthogonal projections of the second doped region and the first gate oxide layer on the substrate is equal to the area of the orthogonal projection of the second gate oxide layer on the substrate.

[0099] Here, the area of the first gate oxide layer is reduced, and the area of the second doped region in the substrate is reduced, the sum of the length of the first gate oxide layer along the Y direction and the length of the second doped region in the substrate along the Y direction is equal to the length of the second gate oxide layer along the Y direction, the width of the first gate oxide layer along the X direction is the same as the width of the second gate oxide layer along the X direction, and thus the sum of the area of the second doped region and the area of the first gate oxide layer in the substrate is equal to the area of the second gate oxide layer in the substrate, effectively reducing the area of the antifuse device, so that a higher storage density can be achieved.

[0100] As shown in Figure 6 and Figure 7 , the antifuse device further comprises an isolation layer 208 covering the sidewall of the second gate oxide layer 206b close to the first doped region 204 and close to the second doped region 203, the sidewall of the first gate oxide layer 206a away from the first doped region 204, and the sidewall of the gate 207 close to the first doped region 204 and away from the first doped region 204.

[0101] In the embodiments of the present disclosure, the material of the isolation layer includes but is not limited to silicon dioxide.

[0102] As shown in Figure 5 , the antifuse device further comprises a bit line contact pad 210 electrically connected with the first doped region 204. Here, two adjacent antifuse units share the same bit line contact pad.

[0103] As shown in Figure 5 , the antifuse device further comprises a word line (not shown in the figure) connected with the gate 207, and a bit line (not shown in the figure) connected with the first doped region 204, specifically, the bit line is electrically connected with the first doped region 204 through the bit line contact pad 210. Here, the word line extends along the Y direction, and the Y direction is the direction of the word line; the bit line extends along the X direction, and the X direction is the direction of the bit line.

[0104] Here, the bit line can be connected with the first doped region or the second doped region. In a specific example, the first doped region is a drain region, and the bit line is electrically connected with the drain region through the bit line contact pad.

[0105] Here, the word line read current applied to the gate can be sensed through the channel of the antifuse storage unit via the bit line connected to the drain.

[0106] As shown in Figure 6 , the antifuse device further comprises a silicide layer 209, which can be located between the first doped region 204 and the bit line contact pad 210, for reducing the contact resistance. Here, the silicide layer can be located between any metal and semiconductor, for reducing the contact resistance between the metal and the semiconductor.

[0107] In the embodiments of the present disclosure, the antifuse device can be a single antifuse storage unit, that is, the antifuse device is a single antifuse transistor; or the antifuse device can be an antifuse array, that is, the antifuse device includes a plurality of antifuse transistors arranged in an array.

[0108] In the embodiments of the present disclosure, the antifuse device includes a first gate oxide layer (that is, a thin gate oxide layer) and a second gate oxide layer (that is, a thick gate oxide layer), and the gate oxide layers with different thicknesses are made into one transistor; wherein the first gate oxide layer is broken down under a high voltage to generate a conductive path connecting the gate and the channel region, and can serve as a storage part; and the second gate oxide layer can withstand a high voltage and will not be broken down under a programming voltage, and can serve as an input / output (I / O) control part.

[0109] If a voltage less than the breakdown voltage is applied to the gate, the first gate oxide layer is not broken down, and no current can be detected on the bit line, and the device is equivalent to a capacitor, and the data read on the bit line is "0"; if a programming voltage is applied to the gate, the first gate oxide layer is broken down, and the circuit is turned on to realize data storage. The reading process of the antifuse device is as follows: if the first gate oxide layer in the antifuse device is not broken down, the leakage current of the unbroken antifuse storage unit is small (that is, in the order of nanoamperes), and the output end of the current comparator is in a low state; if the first gate oxide layer in the antifuse device is broken down, when a reading voltage is applied to the gate, a current is generated between the word line and the bit line, and the output end of the current comparator is in a high state.

[0110] In the embodiments of the present disclosure, the area of the first gate oxide layer is reduced, the area of the second doped region (that is, the source region or the drain region) is reduced, and the positional relationship between the second doped region and the first gate oxide layer is recombined, thereby improving the structure of the antifuse storage unit, reducing the area of the antifuse storage unit to 0.8 times of the original area, and achieving higher storage density.

[0111] In the embodiments of the present disclosure, the orthogonal projection of the gate on the substrate is adjusted to be L-shaped, the area of the source is moved and reduced to reduce the area of the active region, so that the area of the chip is reduced to about 2 / 3 of the original area, the chip density is improved, the storage capacity is further increased, and higher storage density is achieved.

[0112] The embodiments of the present disclosure also provide a manufacturing method of an antifuse device, and the manufacturing method includes:

[0113] Step S801: providing a substrate;

[0114] Step S802: forming a gate oxide layer on the substrate; the gate oxide layer comprises a first gate oxide layer and a second gate oxide layer which are arranged next to each other along a first direction, the length of the second gate oxide layer along a second direction is greater than the length of the first gate oxide layer along the second direction, wherein the first direction and the second direction are both parallel to the surface of the substrate; the second gate oxide layer comprises a first part and a second part which is in contact with the first gate oxide layer along the second direction; the thickness of the first gate oxide layer along a third direction is less than the thickness of the second gate oxide layer along the third direction, wherein the third direction is a direction perpendicular to the surface of the substrate;

[0115] Step S803: forming a gate electrode on the gate oxide layer;

[0116] Step S804: forming a first doped region in the substrate on the side of the second gate oxide layer away from the first gate oxide layer, and forming a second doped region in the substrate on the side of the first part of the second gate oxide layer away from the first doped region.

[0117] The steps of forming the first gate oxide layer and the second gate oxide layer will be described in detail below. Figure 9

[0118] As shown in (a), a first oxide layer 304 is formed on the substrate, more specifically, on the channel region 301. As shown in (b), the channel region above includes a first gate oxide region 302 and a second gate oxide region 303, the first oxide layer 304 is removed from the first gate oxide region 302, and only the first oxide layer 304 located in the second gate oxide region 303 remains. As shown in (c), a second oxide layer is formed again on the channel region. That is, the second oxide layer 305 located in the first gate oxide region 302 forms the first gate oxide layer, and the remaining first oxide layer 304 and the second oxide layer 305 located in the second gate oxide region 303 jointly form the second gate oxide layer. Figure 9 Figure 9 Figure 9

[0119] The embodiments of the present disclosure can use a thermal oxide growth process to form the first gate oxide layer and the second gate oxide layer, but the present disclosure is not limited thereto.

[0120] In some embodiments, the first part of the second gate oxide layer and the first gate oxide layer are respectively located on two adjacent sides of the second doped region.

[0121] In some embodiments, the orthographic projection of the gate electrode on the substrate is L-shaped.

[0122] In some embodiments, the orthographic projection area of the second doped region on the substrate is less than the orthographic projection area of the first doped region on the substrate. ​​​​

[0123] In some embodiments, a sum of a length of a positive projection of the second doped region on the substrate along the second direction and a length of the first gate oxide layer along the second direction is equal to a length of the second gate oxide layer along the second direction.

[0124] In some embodiments, a sum of an area of a positive projection of the second doped region and the first gate oxide layer on the substrate is equal to an area of a positive projection of the second gate oxide layer on the substrate.

[0125] In some embodiments, the above manufacturing method further comprises: forming an isolation layer, the isolation layer covering a sidewall of the second gate oxide layer close to the first doped region and close to the second doped region, a sidewall of the first gate oxide layer away from the first doped region, and a sidewall of the gate electrode close to the first doped region and away from the first doped region.

[0126] In some embodiments, the above manufacturing method further comprises: forming a bit line contact pad, the bit line contact pad being electrically connected to the first doped region or the second doped region.

[0127] In some embodiments, the above manufacturing method further comprises: forming a word line, the word line being connected to the gate electrode; and forming a bit line, the bit line being connected to the first doped region or the second doped region.

[0128] In some embodiments, the above first doped region is a source region, and the second doped region is a drain region; or, the first doped region is a drain region, and the second doped region is a source region.

[0129] The embodiment of the present disclosure provides a antifuse device and a manufacturing method thereof. The antifuse device comprises: a first doped region and a second doped region arranged in a substrate; a gate oxide layer on the substrate, the gate oxide layer comprises a first gate oxide layer and a second gate oxide layer arranged next to each other along a first direction, the length of the second gate oxide layer along a second direction is greater than the length of the first gate oxide layer along the second direction, wherein the first direction and the second direction are both parallel to the surface of the substrate; the second gate oxide layer comprises a first part between the first doped region and the second doped region and a second part between the first doped region and the first gate oxide layer; the thickness of the first gate oxide layer along a third direction is less than the thickness of the second gate oxide layer along the third direction, wherein the third direction is a direction perpendicular to the surface of the substrate; a gate electrode on the gate oxide layer. In the embodiment of the present disclosure, by reducing the length of the first gate oxide layer, the length of the first gate oxide layer is less than the length of the second gate oxide layer; the first doped region is arranged in the substrate away from the first part of the second gate oxide layer, and the second doped region is arranged in the substrate away from the second part of the second gate oxide layer; the positional relationship between the first doped region, the second doped region, the first gate oxide layer, the second gate oxide layer and the gate electrode is reasonably adjusted, the structure of the antifuse device is improved, thereby reducing the area of the antifuse device and further improving the storage density of the antifuse device.

[0130] It should be understood that every feature, structure, or characteristic described in relation to an embodiment is included in at least one embodiment of the present disclosure. Therefore, the occurrence of "in one embodiment" or "in an embodiment" at various places in the specification does not necessarily refer to the same embodiment. In addition, these particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the magnitude of the sequence of the processes described above does not mean the execution order, and the execution order of the processes should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence number of the above-mentioned embodiments of the present disclosure is only for description, and does not represent the advantages and disadvantages of the embodiments.

[0131] The above description is only the preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. Any equivalent structural transformation made according to the disclosure content of the present disclosure and the contents of the description and drawings, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. An antifuse device, characterized in that, The antifuse device includes at least one antifuse memory cell, the antifuse memory cell including a single antifuse transistor; the antifuse transistor includes: A first doped region and a second doped region are disposed within the substrate; A gate oxide layer is located on the substrate, the gate oxide layer comprising a first gate oxide layer and a second gate oxide layer disposed adjacent to each other along a first direction, the length of the second gate oxide layer along a second direction being greater than the length of the first gate oxide layer along the second direction, wherein both the first direction and the second direction are parallel to the substrate surface; the second gate oxide layer comprises a first portion located between the first doped region and the second doped region and a second portion located between the first doped region and the first gate oxide layer, the second doped region being located on one side of the first gate oxide layer along the second direction; the thickness of the first gate oxide layer along a third direction is less than the thickness of the second gate oxide layer along the third direction, wherein the third direction is a direction perpendicular to the substrate surface; The gate located on the gate oxide layer.

2. The antifuse device according to claim 1, characterized in that, The first portion of the second gate oxide layer and the first gate oxide layer are located on adjacent sides of the second doped region, respectively.

3. The antifuse device according to claim 1, characterized in that, The gate's orthogonal projection onto the substrate is L-shaped.

4. The antifuse device according to claim 1, characterized in that, The projected area of ​​the second doped region on the substrate is smaller than the projected area of ​​the first doped region on the substrate.

5. The antifuse device according to claim 1, characterized in that, The sum of the length of the orthogonal projection of the second doped region onto the substrate along the second direction and the length of the first gate oxide layer along the second direction is equal to the length of the second gate oxide layer along the second direction.

6. The antifuse device according to claim 1, characterized in that, The sum of the projected areas of the second doped region and the first gate oxide layer on the substrate is equal to the projected area of ​​the second gate oxide layer on the substrate.

7. The antifuse device according to claim 1, characterized in that, The antifuse device also includes: Word lines, which are connected to the gate; Bit lines are connected to the first doped region or the second doped region.

8. The antifuse device according to claim 1, characterized in that, The first doped region is the source region, and the second doped region is the drain region; or, The first doped region is the drain region, and the second doped region is the source region.

9. A method for manufacturing an antifuse device, characterized in that, The antifuse device includes at least one antifuse memory cell, and the antifuse memory cell includes a single antifuse transistor; The manufacturing method includes: Provide substrate; A gate oxide layer is formed on the substrate; the gate oxide layer includes a first gate oxide layer and a second gate oxide layer disposed adjacent to each other along a first direction, the length of the second gate oxide layer along a second direction is greater than the length of the first gate oxide layer along the second direction, wherein both the first direction and the second direction are parallel to the substrate surface; the second gate oxide layer along the second direction includes a first portion and a second portion in contact with the first gate oxide layer, and a second doped region is located on one side of the first gate oxide layer along the second direction; the thickness of the first gate oxide layer along a third direction is less than the thickness of the second gate oxide layer along the third direction, wherein the third direction is a direction perpendicular to the substrate surface; A gate electrode is formed on the gate oxide layer; A first doped region is formed in the substrate on the side of the second gate oxide layer away from the first gate oxide layer, and a second doped region is formed in the substrate on the side of the first portion of the second gate oxide layer away from the first doped region.

10. The method for manufacturing the antifuse device according to claim 9, characterized in that, The first portion of the second gate oxide layer and the first gate oxide layer are located on adjacent sides of the second doped region, respectively.

11. The method for manufacturing the antifuse device according to claim 9, characterized in that, The gate's orthogonal projection onto the substrate is L-shaped.

12. The method for manufacturing the antifuse device according to claim 9, characterized in that, The projected area of ​​the second doped region on the substrate is smaller than the projected area of ​​the first doped region on the substrate.

13. The method for manufacturing the antifuse device according to claim 9, characterized in that, The sum of the length of the orthogonal projection of the second doped region onto the substrate along the second direction and the length of the first gate oxide layer along the second direction is equal to the length of the second gate oxide layer along the second direction.

14. The method for manufacturing the antifuse device according to claim 9, characterized in that, The sum of the projected areas of the second doped region and the first gate oxide layer on the substrate is equal to the projected area of ​​the second gate oxide layer on the substrate.

15. The method for manufacturing the antifuse device according to claim 9, characterized in that, The manufacturing method further includes: A word line is formed, and the word line is connected to the gate. A bit line is formed, which is connected to the first doped region or the second doped region.

16. The method for manufacturing the antifuse device according to claim 9, characterized in that, The first doped region is the source region, and the second doped region is the drain region; or, The first doped region is the drain region, and the second doped region is the source region.

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