Discrete device and manufacturing method
Discrete devices with multi-directional cell layout design have solved the bottleneck of unidirectional pitch miniaturization, achieving increased channel density and reduced on-resistance in a two-dimensional plane, while maintaining low switching losses and high-speed switching characteristics, making them suitable for miniaturized designs with high power density.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-15
- Publication Date
- 2026-04-14
AI Technical Summary
In the existing technology, the unidirectional pitch reduction method has a bottleneck in reducing the on-resistance of power MOSFETs, making it difficult to significantly improve the channel density without sacrificing other performance, and the advanced photolithography process is expensive and complex.
By adopting a multi-directional cell layout design, especially a hexagonal structure, and combining it with the traditional Split Gate process, a multi-directional channel structure is formed through improved layout design and key process steps. This avoids the limitations of unidirectional pitch miniaturization and increases channel density.
Significantly improve channel density, reduce on-resistance, maintain low switching losses and high-speed switching characteristics without relying on more advanced lithography processes, enhance device market competitiveness and reliability, and achieve miniaturized designs with high power density.
Smart Images
Figure CN121865651A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor power device technology, and more specifically to a discrete device and its manufacturing method. Background Technology
[0002] Power MOSFETs, especially those used in low-voltage applications (such as 30V-100V), are core components in modern power management systems, and their performance directly determines the efficiency and power density of the power supply. In order to continuously reduce on-resistance (Rds(on)) and improve current handling capability, the industry has developed trench gate technology, which has further evolved into the split gate structure.
[0003] In traditional split-gate MOSFETs, the device typically employs a deep trench structure. The trench is divided into a top control gate and a bottom shield gate, separated by an isolation oxide layer. Thin gate oxide layers on both sides of the control gate form the channel, while thick field oxide layers on both sides of the shield gate reduce gate-drain capacitance (Cgd) and optimize the electric field distribution. This structure effectively balances low on-resistance and low switching losses, and has become the mainstream technology for medium- and low-voltage high-performance MOSFETs.
[0004] As applications such as servers, communication power supplies, and new energy vehicles place increasingly stringent demands on power density, designers seek to achieve greater output current within a smaller chip area. This necessitates a significant reduction in the specific on-resistance (Rds(on)*Area). It is well known to those skilled in the art that for low- to medium-voltage devices, channel resistance (Rch) constitutes a significant proportion of the total on-resistance (e.g., 35% or higher for 30V devices). Therefore, one of the most effective ways to reduce Rds(on) is to increase the channel density per unit area.
[0005] Currently, the industry commonly uses unidirectional pitch miniaturization, which involves reducing the size of cells in a specific direction (usually the width of the trench) as much as possible through photolithography and process advancements, in order to arrange more channels vertically. However, this method has significant limitations:
[0006] 1. Pitch miniaturization is severely limited by the lithography precision and etching capability of semiconductor manufacturing platforms. When the cost of cutting-edge technology nodes is high, achieving extremely small pitches on mature process platforms faces huge challenges, and may even be impossible.
[0007] 2. Unidirectional size reduction has a linear effect on improving channel density, and the marginal benefit gradually decreases. When the pitch is already small, the percentage increase in density brought by further reduction is limited, making it difficult to achieve a leapfrog increase in channel density.
[0008] 3. Excessive miniaturization can lead to a series of process and reliability issues, such as insufficient photolithography alignment tolerance, difficulty in trench filling, and electric field concentration leading to decreased withstand voltage or long-term reliability risks.
[0009] Therefore, under the existing mature manufacturing process conditions, how to break through the technical bottleneck of unidirectional pitch miniaturization, substantially improve the channel density of cells, and thus significantly reduce the on-resistance of devices without sacrificing other performance has become a key technical problem that urgently needs to be solved in this field. Summary of the Invention
[0010] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a discrete device and its manufacturing method. Through the unique masking layer pattern design in step seven, a multi-directional (e.g., hexagonal) cell layout is innovatively adopted on the layout surface, replacing the traditional unidirectional linear layout. This design breaks through the traditional approach of increasing channel density solely by unidirectional pitch reduction, achieving simultaneous optimization in a two-dimensional plane. This significantly improves channel density and effectively reduces on-resistance without relying on more advanced photolithography processes. The core improvement of the manufacturing method of this invention lies in the layout design and the matching key process steps, which can achieve a performance leap without breaking the photolithography limits of existing manufacturing platforms. This makes it possible to manufacture high-performance discrete devices using mature and cost-controllable process technologies, effectively avoiding the high costs and complex process challenges brought by advanced processes, and greatly enhancing the market competitiveness of the product. This invention addresses the technical bottleneck problem of increasing channels using unidirectional pitch reduction in the prior art.
[0011] To achieve the above and other related objectives, the present invention provides a method for manufacturing discrete devices, comprising the following steps:
[0012] Step 1: Provide an N+ substrate and grow an N epitaxial layer on the N+ substrate;
[0013] Step 2: Deposit a first masking layer on the N epitaxial layer, and photolithographically etch and etch the first masking layer to form a deep trench pattern;
[0014] Step 3: Using the first masking layer as a barrier, etch the N epitaxial layer to form a deep trench;
[0015] Step 4: A thin oxide layer is thermally grown on the upper surface of the N epitaxial layer and the side and bottom surfaces of the deep trench, and then a thick oxide layer is deposited on the thin oxide layer.
[0016] Step Five: Deposit polysilicon on the thick oxide layer, and then etch the polysilicon to form a shield gate polysilicon at the bottom of the deep trench;
[0017] Step Six: Remove the oxide layer above the shield gate polysilicon, deposit an oxide layer on the upper surface of the N epitaxial layer and in the deep trench by HDP, and use chemical mechanical polishing to remove the oxide layer on the upper surface of the N epitaxial layer to planarize the upper surface of the N epitaxial layer;
[0018] Step Seven: Deposit an oxide layer on the first mask layer as the second mask layer, and perform photolithography and etching on the second mask layer to form a shallow trench pattern;
[0019] Step Eight: Remove the second mask layer;
[0020] Step Nine: Use wet etching to form an isolation oxide layer in the deep trench;
[0021] Step Ten: Thermally grow a gate oxide layer, deposit polysilicon again and perform polysilicon etching to form a gate polysilicon;
[0022] Step Eleven: Inject P-type impurity B+ and drive it to form a P-well region;
[0023] Step Twelve: Deposit N-type doping and anneal to form an N+ source region;
[0024] Step Thirteen: Deposit a dielectric above the gate polysilicon;
[0025] Step Fourteen: Perform photolithography and etching above the dielectric to form contact holes;
[0026] Step Fifteen: First deposit metal on the upper surface of the dielectric and in the contact holes to form an emitter metal and contact posts, and then perform photolithography and etching to separately lead out the gate and the source; finally, perform back thinning, back silicon etching and back metallization on the N+ substrate to form a drain metal.
[0027] In an embodiment of the present invention, in Step Seven, the formed shallow trench pattern is a multi-directional structure for increasing the channel density in multiple directions.
[0028] In an embodiment of the present invention, the multi-directional structure is a hexagonal cell structure.
[0029] In an embodiment of the present invention, in Steps Two and Seven, the photolithography and etching include first copying the trench pattern on the mask plate to the photoresist layer of the mask layer through optical exposure technology to form a patterned photoresist; then using physical or chemical methods to remove the material not protected by the photoresist to form a micro-nano structure corresponding to the photoresist pattern.
[0030] In an embodiment of the present invention, in Step Four, the thickness of the thermally grown thin oxide layer is 10 - 50 nm.
[0031] In one embodiment of the present invention, in step nine, the thickness of the isolation oxide layer after wet etching is 300 nm, and the isolation oxide is used to isolate the gate polysilicon and the source polysilicon.
[0032] In one embodiment of the present invention, in step ten, the thickness of the thermally grown gate oxide layer is 20-100 nm.
[0033] In one embodiment of the present invention, in step twelf, the annealing temperature is 900-1100°C.
[0034] The present invention provides a discrete device, which is prepared by the discrete device manufacturing method described above, and includes a substrate, wherein the front side of the substrate is provided with a deep groove and a shallow groove recessed toward the back side of the substrate.
[0035] As described above, the discrete device and manufacturing method of the present invention have the following beneficial effects:
[0036] 1. Through the unique masking layer pattern design in step seven, this invention innovatively adopts a multi-directional cell layout on the printing plate surface, replacing the traditional unidirectional linear layout. This design breaks through the traditional approach of increasing channel density by relying solely on unidirectional pitch reduction, and achieves simultaneous optimization in a two-dimensional plane. Thus, without relying on more advanced photolithography processes, it significantly improves channel density and effectively reduces on-resistance.
[0037] 2. The core improvement of the manufacturing method of the present invention lies in the layout design and the matching key process steps, which can achieve a performance leap without breaking through the lithography limit of the existing manufacturing platform. This makes it possible to manufacture high-performance discrete devices using mature and cost-controllable process technology, effectively avoiding the high costs and complex process challenges brought by advanced process technology, and greatly enhancing the market competitiveness of the product.
[0038] 3. This invention improves channel density while inheriting the inherent advantages of the Split Gate structure. The bottom shielded gate effectively reduces the gate-drain capacitance (Cgd), and the multi-directional compact cell design does not compromise this characteristic; therefore, this invention achieves low on-resistance while maintaining excellent low switching losses and high-speed switching characteristics, realizing a good balance between on-resistance and switching losses.
[0039] 4. The manufacturing method provided by this invention is an improvement on the traditional Split Gate process. The main new steps are highly compatible with existing semiconductor process flows, and there is no need to introduce special or difficult-to-control process modules, which enhances process compatibility and reliability. In addition, the multi-directional design disperses the electric field and avoids the electric field concentration problem that may be caused by excessive miniaturization of unidirectional size, which helps to ensure and improve the long-term reliability of the device.
[0040] 5. This invention can provide a larger output current capability within the same chip area; and can achieve a smaller chip size within the same current specification, which helps to realize high power density and miniaturized design of power supply systems and significantly improves the overall performance of discrete devices. Attached Figure Description
[0041] Figure 1 The diagram shown is a schematic diagram of the planar structure of the discrete device disclosed in this invention.
[0042] Figure 2 Displayed as Figure 1 A sectional view along line A.
[0043] Figure 3 Displayed as Figure 1 Sectional view along line B.
[0044] Figure 4 Displayed as Figure 1 A sectional view along the C-axis.
[0045] Figure 5 The diagram shown is a schematic representation of a superior planar structure of the discrete device disclosed in this invention. Detailed Implementation
[0046] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.
[0047] Please see Figures 1 to 5 It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art and to facilitate understanding. They are not intended to limit the scope of the invention and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, provided they do not affect the effectiveness or purpose of the invention, should fall within the scope of the disclosed technical content. Furthermore, the terms "upper," "lower," "left," "right," "middle," and "one" used in this specification are merely for clarity and not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.
[0048] Example 1, please refer to Figures 1-4 This embodiment provides a method for manufacturing discrete devices, including the following steps:
[0049] Step 1: Provide an N+ substrate and grow an N epitaxial layer on the N+ substrate.
[0050] Step 2: Deposit a first masking layer on the N epitaxial layer, and photolithographically etch and etch the first masking layer to form a deep trench pattern. In this step, the photolithography and etching includes first copying the deep trench pattern on the mask onto the photoresist layer that masks the first masking layer using optical exposure technology to form a patterned photoresist. Then, physical or chemical methods are used to remove the material not protected by the photoresist to form a micro / nano structure corresponding to the photoresist pattern.
[0051] Step 3: Using the first masking layer as a barrier, etch the N epitaxial layer to form a deep trench.
[0052] Step 4: A thin oxide layer is thermally grown on the upper surface of the N epitaxial layer and on the side and bottom surfaces of the deep trench. The thickness of the thermally grown thin oxide layer is 10-50 nm. Then, a thick oxide layer is deposited on the thin oxide layer.
[0053] Step 5: Deposit polysilicon on the thick oxide layer, then etch the polysilicon to form a shielding gate polysilicon at the bottom of the deep trench.
[0054] Step 6: Remove the oxide layer above the shielding gate polysilicon. Deposit oxide layers on the upper surface of the N epitaxial layer and in the deep trench using HDP. Use chemical mechanical polishing to remove the oxide layer on the upper surface of the N epitaxial layer to planarize the upper surface of the N epitaxial layer.
[0055] Step 7: Deposit an oxide layer on the first masking layer as a second masking layer, and photolithographically etch and etch the second masking layer to form a shallow trench pattern. After planarization, the first masking layer on the silicon surface has become as thin as about 1000 Å, so it is necessary to deposit another thin oxide layer on the planarized wafer surface to form a thicker second mask. In this step, the photolithography and etching includes first copying the trench pattern on the mask onto the photoresist layer of the second masking layer using optical exposure technology to form a patterned photoresist. Then, physical or chemical methods are used to remove the material not protected by the photoresist to form a micro / nano structure corresponding to the photoresist pattern. The shallow trench pattern formed in this step is a multi-directional structure, used to increase the channel density from multiple directions. For a more preferred embodiment, please refer to [link to more preferred embodiment]. Figure 5 The multidirectional structure is a flattened hexagonal cell structure, labeled 3, and its top-bottom spacing is easy to adjust; label 2 is the control length of the multidirectional structure. The shorter this length, the smaller the overall area of the source region aperture 4 will be. Therefore, some trade-offs will be made in actual design; label 1 is the cell pitch, which will vary depending on the device voltage.
[0056] This invention, through a unique masking layer pattern design in step seven, innovatively employs a multi-directional cell layout on the printout surface, such as a flattened hexagonal cell structure, replacing the traditional unidirectional linear layout. This design breaks through the traditional approach of increasing channel density solely through unidirectional pitch miniaturization, achieving simultaneous optimization within a two-dimensional plane. This significantly improves channel density and effectively reduces on-resistance without relying on more advanced lithography processes. In actual manufacturing, it can increase the channel density per unit area by approximately 40%. Since channel resistance is a major component of the total on-resistance in low- and medium-voltage devices, the significant increase in channel density directly leads to a significant reduction in the specific on-resistance (Rds(on)*Area) of the device by approximately 14%.
[0057] Step 8: Remove the second masking layer.
[0058] Step nine: Use wet etching to form an isolation oxide layer in the deep trench. The isolation oxide layer has a thickness of 300 nm and is used to isolate the gate polysilicon and the source polysilicon.
[0059] Step 10: Thermally grow a gate oxide layer with a thickness of 20-100 nm; deposit polysilicon again and perform polysilicon etching to form gate polysilicon.
[0060] Step 11: Inject P-type impurity B+ and promote the formation of P-well region.
[0061] Step 12: Deposit N-type doping and anneal to form N+ source region, wherein the annealing temperature is 900-1100℃;
[0062] Step 13: Deposit dielectric material over the gate polysilicon.
[0063] Step 14: Photolithography and etching are performed over the medium to form contact holes.
[0064] Step 15: First, deposit metal on the upper surface of the dielectric and inside the contact hole to form the emitter metal and contact pillars. Then, perform photolithography and etching to bring out the gate and source respectively. Finally, perform back-side thinning, back-side silicon etching and back-side metallization on the N+ substrate to form the drain metal.
[0065] The core improvement of the manufacturing method of this invention lies in the layout design and the matching key process steps, which can achieve a performance leap without breaking the lithography limits of existing manufacturing platforms. This makes it possible to manufacture high-performance discrete devices using mature and cost-controllable process technologies, effectively avoiding the high costs and complex process challenges brought by advanced processes, and greatly enhancing the market competitiveness of the products. This invention increases channel density while inheriting the inherent advantages of the Split Gate structure. The bottom shielded gate effectively reduces the gate-drain capacitance (Cgd), and the multi-directional compact cell design does not compromise this characteristic. Therefore, this invention achieves low on-resistance while maintaining excellent low switching losses and high-speed switching characteristics, achieving a good balance between on-resistance and switching losses. The manufacturing method provided by this invention is an improvement on the traditional SplitGate process. The main new steps include photolithography and etching to form shallow trench patterns, which is highly compatible with existing semiconductor process flows, eliminating the need to introduce special or difficult-to-control process modules, thus enhancing process compatibility and reliability. In addition, the multi-directional design disperses the electric field, avoiding the electric field concentration problem that may be caused by excessive miniaturization of unidirectional dimensions, which helps to ensure and improve the long-term reliability of the device.
[0066] Example 2: This example provides a discrete device, which is prepared by the discrete device manufacturing method described in Example 1. It includes a substrate, and the front side of the substrate is provided with a deep groove 5 and a shallow groove 6 that are recessed toward the back side of the substrate.
[0067] In summary, this invention provides greater output current capability within the same chip area; and achieves a smaller chip size while maintaining the same current specification, facilitating high power density and miniaturized design of power supply systems, and significantly improving the overall performance of discrete devices. Therefore, this invention effectively overcomes the aforementioned shortcomings of the prior art and has high industrial applicability.
[0068] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for manufacturing discrete devices, characterized in that, Includes the following steps: Step 1: Provide an N+ substrate and grow an N epitaxial layer on the N+ substrate; Step 2: Deposit a first masking layer on the N epitaxial layer, and photolithographically etch and etch the first masking layer to form a deep trench pattern; Step 3: Using the first masking layer as a barrier, etch the N epitaxial layer to form a deep trench; Step 4: A thin oxide layer is thermally grown on the upper surface of the N epitaxial layer and the side and bottom surfaces of the deep trench, and then a thick oxide layer is deposited on the thin oxide layer. Step 5: Deposit polysilicon on the thick oxide layer, then etch the polysilicon to form a shielding gate polysilicon at the bottom of the deep trench; Step 6: Remove the oxide layer above the shielding gate polysilicon. Deposit oxide layers on the upper surface of the N epitaxial layer and in the deep trench using HDP. Use chemical mechanical polishing to remove the oxide layer on the upper surface of the N epitaxial layer to planarize the upper surface of the N epitaxial layer. Step 7: Deposit an oxide layer on the first masking layer as a second masking layer, and photolithographically etch and etch the second masking layer to form a shallow trench pattern; Step 8: Remove the second masking layer; Step nine: Use wet etching to form an isolation oxide layer in the deep tank; Step 10: Thermally grow the gate oxide layer, deposit polysilicon again and perform polysilicon etching to form the gate polysilicon; Step 11: Inject P-type impurity B+ and advance to form a P-well region; Step 12: Deposit N-type doping and anneal to form N+ source region; Step 13: Deposit dielectric material over the gate polysilicon; Step 14: Photolithography and etching are performed over the dielectric to form contact holes; Step 15: First, deposit metal on the upper surface of the dielectric and inside the contact hole to form the emitter metal and contact pillars. Then, perform photolithography and etching to bring out the gate and source respectively. Finally, perform back-side thinning, back-side silicon etching and back-side metallization on the N+ substrate to form the drain metal.
2. The discrete device manufacturing method according to claim 1, characterized in that, In step seven, the shallow groove pattern formed is a multi-directional structure, which is used to increase the channel density from multiple directions.
3. The discrete device manufacturing method according to claim 2, characterized in that, The multidirectional structure is a hexagonal cell structure.
4. The discrete device manufacturing method according to claim 1, characterized in that, In steps two and seven, the photolithography and etching process includes first copying the trench pattern on the mask onto the photoresist layer of the mask layer using optical exposure technology to form patterned photoresist. Then, physical or chemical methods are used to remove the material not protected by the photoresist, forming a micro / nano structure corresponding to the photoresist pattern.
5. The discrete device manufacturing method according to claim 1, characterized in that, In step four, the thickness of the thermally grown thin oxide layer is 10-50 nm.
6. The discrete device manufacturing method according to claim 1, characterized in that, In step nine, the thickness of the isolation oxide layer after wet etching is 300 nm, and the isolation oxide is used to isolate the gate polysilicon and the source polysilicon.
7. The discrete device manufacturing method according to claim 1, characterized in that, In step ten, the thickness of the thermally grown gate oxide layer is 20-100 nm.
8. The discrete device manufacturing method according to claim 1, characterized in that, In step twelf, the annealing temperature is 900-1100℃.
9. A discrete device, characterized in that, Prepared by the discrete device manufacturing method according to any one of claims 1-8, comprising a substrate, wherein the front side of the substrate is provided with the deep groove and the shallow groove recessed toward the back side of the substrate.