Semiconductor structure and method of making the same, three-dimensional memory, storage system

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof, a three-dimensional memory and a storage system, and relates to the technical field of semiconductor chips, so as to improve the storage density of the semiconductor structure. The semiconductor structure comprises a first stack structure, a storage structure and a phase change layer. The first stack structure comprises a plurality of first dielectric layers and a plurality of word line layers. The storage structure comprises a ferromagnetic free layer, a tunneling layer, a ferromagnetic pinned layer and a conductive layer; the ferromagnetic free layer is located between the tunneling layer and the first stack structure, the tunneling layer is located between the ferromagnetic free layer and the ferromagnetic pinned layer, the ferromagnetic pinned layer is located between the tunneling layer and the conductive layer, the conductive layer is located on the side of the ferromagnetic pinned layer away from the tunneling layer, and the conductive layer is coupled with a bit line. The phase change layer is at least partially located between the word line layer and the ferromagnetic free layer. The semiconductor structure is applied to a three-dimensional memory to realize data reading and writing operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its fabrication method, a three-dimensional memory, and a storage system. Background Technology

[0002] Magnetic Random Access Memory (MRAM) is a non-volatile magnetic random access memory that combines the high-speed read / write capabilities of static random access memory (SRAM) with the high integration density of dynamic random access memory (DRAM), and can be rewritten virtually an unlimited number of times. One key challenge is improving the storage density of MRAM. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor structure and its fabrication method, a three-dimensional memory, and a storage system to improve the storage density of the semiconductor structure.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0005] On one hand, a semiconductor structure is provided. The semiconductor structure includes a first stacked structure, a memory structure, and a phase change layer. The first stacked structure includes a plurality of alternately stacked first dielectric layers and a plurality of word line layers. The memory structure extends through the first stacked structure; the memory structure includes a ferromagnetic free layer, a tunneling layer, a ferromagnetic pinning layer, and a conductive layer; the ferromagnetic free layer is located between the tunneling layer and the first stacked structure, the tunneling layer is located between the ferromagnetic free layer and the ferromagnetic pinning layer, the ferromagnetic pinning layer is located between the tunneling layer and the conductive layer, the conductive layer is located on the side of the ferromagnetic pinning layer away from the tunneling layer, and the conductive layer is coupled to a bit line. The phase change layer is at least partially located between the word line layers and the ferromagnetic free layer.

[0006] In some embodiments, the adjacent surfaces of any two adjacent layers in the ferromagnetic free layer, the tunneling layer, and the ferromagnetic pinning layer are planar.

[0007] In some embodiments, the orthographic projection of the storage structure onto a reference plane is a polygon, and the reference plane is the plane containing the lower surface of the first stacked structure.

[0008] In some embodiments, the semiconductor structure includes a memory group and a channel isolation structure. The memory group includes two rows of memory structures arranged along a first direction, each row including a plurality of memory structures arranged along a second direction, the first direction intersecting the second direction. Along the first direction, conductive layers of the two rows of memory structures are located between ferromagnetic pinning layers of the two rows of memory structures. The channel isolation structure is at least partially located between any two adjacent memory structures in the memory group.

[0009] In some embodiments, the shape of the orthographic projection of the storage structure onto the reference plane is a circle or an ellipse, and the reference plane is the plane containing the lower surface of the first stacked structure.

[0010] In some embodiments, the word line layer is recessed inward toward the memory structure from its boundary relative to the boundary of the first dielectric layer near the memory structure, to form a recess. The semiconductor structure includes a plurality of phase change layers, each of which is located within one of the recesses.

[0011] In some embodiments, each of the memory structures includes a plurality of ferromagnetic free layers, each of the ferromagnetic free layers being located within one of the recesses, and the phase change layer being located between the ferromagnetic free layers and the word line layer.

[0012] In some embodiments, the phase change layer is located between the word line layer and two first dielectric layers adjacent to the word line layer, and between the word line layer and the memory structure.

[0013] In some embodiments, the phase change layer is located near the boundary of the memory structure and flush with the boundary of the first dielectric layer near the memory structure. The ferromagnetic free layer is a continuous film layer along a third direction and is located between the phase change layer and the memory structure, as well as between the first dielectric layer and the memory structure; the third direction is perpendicular to the reference plane.

[0014] In some embodiments, the semiconductor structure further includes a word line isolation structure that extends through the first stacked structure; the word line isolation structure extends along a fourth direction to divide the word line layer into multiple word lines; the fourth direction is parallel to a reference plane, which is the plane containing the lower surface of the first stacked structure.

[0015] In some embodiments, the storage structure further includes an antiferromagnetic layer located between the conductive layer and the ferromagnetic pinning layer.

[0016] In some embodiments, the semiconductor structure further includes a second stacked structure and a channel structure. The second stacked structure is located on the first stacked structure; the second stacked structure includes at least one select gate layer and at least one second dielectric layer. The channel structure extends through the second stacked structure; the channel structure includes a channel layer electrically connected to the conductive layer, and the channel layer is configured to connect bit lines.

[0017] The semiconductor structure disclosed herein is based on spin-torque magnetic random access memory, which offers advantages such as high speed, low power consumption, and unlimited erasure / write capability. Furthermore, the memory structures can be arrayed along the reference plane, and each memory structure includes multiple memory cells spaced apart in a direction perpendicular to the reference plane. In other words, multiple memory cells are arrayed along the reference plane and spaced apart in a direction perpendicular to the reference plane, thereby achieving three-dimensional storage and increasing the storage density of the semiconductor structure. In addition, word lines can individually control whether a corresponding memory cell can be written to or read from by controlling the on / off state of the phase change layer, thus enabling random read / write operations on any memory cell.

[0018] On the other hand, a method for fabricating a semiconductor structure is provided. The method includes: forming a first stacked structure; the first stacked structure includes a plurality of alternately stacked first dielectric layers and a plurality of word line layers; forming a phase change layer and a memory structure penetrating the first stacked structure; the memory structure includes a ferromagnetic free layer, a tunneling layer, a ferromagnetic pinning layer, and a conductive layer, wherein the ferromagnetic free layer is located between the tunneling layer and the first stacked structure, the tunneling layer is located between the ferromagnetic free layer and the ferromagnetic pinning layer, the ferromagnetic pinning layer is located between the tunneling layer and the conductive layer, and the conductive layer is located on the side of the ferromagnetic pinning layer away from the tunneling layer; the phase change layer is at least partially located between the word line layers and the ferromagnetic free layer.

[0019] In some embodiments, forming the phase change layer and the memory structure penetrating the first stacked structure includes: forming an initial channel via penetrating the first stacked structure; the orthographic projection of the initial channel via onto a reference plane is rectangular, and the reference plane is the plane containing the lower surface of the first stacked structure. A phase change layer is formed within the initial channel via; the phase change layer covers the surface of the word line layer exposed by the initial channel via.

[0020] An initial storage structure is formed within the initial channel hole; the initial storage structure includes an initial ferromagnetic free layer, an initial tunneling layer, an initial ferromagnetic pinning layer, and an initial conductive layer, and the initial storage structure forms a first void within the initial channel hole; the orthographic projection of the initial storage structure onto the reference plane is rectangular, and includes two opposing first sides and two opposing second sides. A first filling layer is formed within the first void.

[0021] Multiple isolation slots are formed throughout the first stacked structure. These isolation slots are arranged sequentially at intervals along the extension direction of the first side. In a projection onto the reference plane, the two outermost isolation slots at both ends respectively cover the two second sides of the initial storage structure. The multiple isolation slots divide the initial storage structure into multiple storage structures. A second filling layer is formed within the multiple isolation slots. The first filling layer and the second filling layer are connected to form a channel isolation structure.

[0022] In some embodiments, forming a phase change layer within the initial channel aperture includes: removing an edge portion of the word line layer near the initial channel aperture via the initial channel aperture, such that the word line layer is recessed inward toward the boundary of the initial channel aperture relative to the boundary of the first dielectric layer near the initial channel aperture, forming a groove. A phase change layer is then formed within the groove.

[0023] In some embodiments, forming the first filler layer includes: forming a first filler film; the first filler film covering the inner wall of the first void and the upper side of the first stacked structure; and removing the portion of the first filler film covering the upper side of the first stacked structure.

[0024] In some embodiments, forming an initial storage structure within the initial channel aperture includes: forming an initial ferromagnetic free layer within the groove, wherein the phase transition layer is located between the ferromagnetic free layer and the word line layer. A tunneling film, a ferromagnetic pinning film, and a conductive film are sequentially formed; the tunneling film, the ferromagnetic pinning film, and the conductive film cover the inner wall of the initial channel aperture and the upper side of the first stacked structure. During the removal of the portion of the first filler film covering the upper side of the first stacked structure, portions of the tunneling film, the ferromagnetic pinning film, and the conductive film covering the upper side of the first stacked structure are also removed.

[0025] In some embodiments, forming the initial ferromagnetic free layer includes: forming a ferromagnetic free film; the ferromagnetic free film filling the groove and covering the inner wall of the initial channel hole and the first stacked structure; and removing the portion of the ferromagnetic free film covering the inner wall of the initial channel hole and the first stacked structure to form the initial ferromagnetic free layer.

[0026] In some embodiments, the storage structure further includes an antiferromagnetic layer. The formation of the initial storage structure within the initial channel aperture, between the formation of the ferromagnetic pinning film and the conductive film, further includes: forming an antiferromagnetic film; the antiferromagnetic film covering the inner wall of the initial channel aperture and the upper side of the first stacked structure. During the removal of portions of the tunneling film, the ferromagnetic pinning film, and the conductive film covering the first stacked structure, the portion of the antiferromagnetic film covering the upper side of the first stacked structure is also removed.

[0027] In some embodiments, forming a plurality of isolation trenches penetrating the first stacked structure includes forming a mask layer. The mask layer includes a plurality of cutout areas arranged sequentially at intervals along the extension direction of the first side, and in a projection onto the reference surface, the two outermost cutout areas at both ends respectively expose two second sides of the initial memory structure. The initial memory structure is etched based on the mask layer to form a plurality of isolation trenches.

[0028] In another aspect, a method for fabricating a semiconductor structure is provided. The method includes: forming an initial stacked structure; the initial stacked structure comprising a plurality of alternately stacked first dielectric layers and a plurality of sacrificial layers; forming a memory structure penetrating the initial stacked structure; the memory structure comprising a ferromagnetic free layer, a tunneling layer, a ferromagnetic pinning layer, and a conductive layer; forming word line gaps penetrating the initial stacked structure; removing the sacrificial layers through the word line gaps to form word line cavities; and sequentially forming a phase change layer and a word line layer within the word line cavity; the phase change layer is located between the word line layer and two adjacent first dielectric layers, and between the word line layer and the memory structure.

[0029] In some embodiments, forming a storage structure penetrating the initial stacked structure includes: forming a first channel hole penetrating the initial stacked structure; sequentially forming a ferromagnetic free film, a tunneling film, a ferromagnetic pinning film, and a conductive film; the ferromagnetic free film, the tunneling film, the ferromagnetic pinning film, and the conductive film covering the inner wall of the first channel hole and the upper side of the initial stacked structure; and removing the portions of the ferromagnetic free film, the tunneling film, the ferromagnetic pinning film, and the conductive film that cover the upper side of the initial stacked structure.

[0030] In some embodiments, the storage structure further includes an antiferromagnetic layer, forming a storage structure that penetrates the initial stacked structure between the formation of the ferromagnetic pinning film and the conductive film. The fabrication method further includes forming an antiferromagnetic film. During the process of removing portions of the ferromagnetic free film, the tunneling film, the ferromagnetic pinning film, and the conductive film that cover the upper side of the initial stacked structure, the portion of the antiferromagnetic film that covers the upper side of the initial stacked structure is also removed.

[0031] In another aspect, a three-dimensional memory is provided. The three-dimensional memory includes the semiconductor structure and peripheral devices as described above, wherein the peripheral devices are electrically connected to the semiconductor structure.

[0032] In another aspect, a storage system is provided. The storage system includes a three-dimensional memory and a controller as described above, the controller being coupled to the three-dimensional memory to control the storage of data in the three-dimensional memory.

[0033] In another aspect, an electronic device is provided. The electronic device includes the storage system described above.

[0034] It is understood that the beneficial effects that the semiconductor structure fabrication method, three-dimensional memory, storage system and electronic device provided in the above embodiments of this disclosure can achieve can be referred to the beneficial effects of the semiconductor structure above, and will not be repeated here. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0036] Figure 1 A cross-sectional view of a three-dimensional memory according to some embodiments;

[0037] Figure 2 A cross-sectional view of another three-dimensional memory according to some embodiments;

[0038] Figure 3A for Figure 2 A cross-sectional view of a string of storage cells in a three-dimensional memory.

[0039] Figure 3B for Figure 1 A cross-sectional view of a string of storage cells in a three-dimensional memory.

[0040] Figure 4 for Figure 3A or Figure 3B Equivalent circuit diagram of the memory cell string;

[0041] Figure 5 This is a structural diagram of a semiconductor structure according to some embodiments;

[0042] Figure 6 For along Figure 5 Cross-sectional view at point AA';

[0043] Figure 7 for Figure 5 A partially enlarged view of the semiconductor structure shown;

[0044] Figure 8 This is a structural diagram of another semiconductor structure according to some embodiments;

[0045] Figure 9 For along Figure 8 Cross-sectional view at point BB';

[0046] Figure 10 for Figure 8 A partially enlarged view of the semiconductor structure shown;

[0047] Figures 11-24 This is a diagram illustrating the fabrication steps of a semiconductor structure fabrication method according to some embodiments;

[0048] Figures 25-37 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0049] Figures 38-41 This is a diagram illustrating the fabrication steps of another semiconductor structure fabrication method according to some embodiments;

[0050] Figure 42 This is a block diagram of a storage system according to some embodiments;

[0051] Figure 43 This is a block diagram of a storage system according to some other embodiments. Detailed Implementation

[0052] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0053] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0054] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0055] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0056] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0057] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0058] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0059] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0060] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0061] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0062] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0063] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0064] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0065] As used herein, the term “vertical / perpendicular” means nominally perpendicular to the main surface (i.e., the lateral surface) of the substrate or source layer.

[0066] See Figure 1Some embodiments of this disclosure provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor structure 100.

[0067] For example, the semiconductor structure 100 may include a substrate 11 that provides a carrying function and a memory array structure 20 located on the substrate 11.

[0068] The substrate 11 mentioned above includes various types, which can be selected and set according to actual needs.

[0069] For example, the material of the substrate 11 includes glass and / or polymethyl methacrylate (PMMA).

[0070] For example, the material of substrate 11 includes at least one of single-crystal silicon (Si), polycrystalline silicon, single-crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0071] For example, the material of substrate 11 may also include at least one of polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyimide (PI).

[0072] See Figure 1 and Figure 2 The storage array structure 20 can be a spin-transfer torque magnetic random storage.

[0073] For example, as shown in the figure, the storage array structure 20 includes a first stack structure 210 and a storage structure 220 extending through the first stack structure 210.

[0074] See Figure 2 and Figure 3A The first stacked structure 210 may include a plurality of first dielectric layers 211 and a plurality of word line layers 212. For example, the plurality of first dielectric layers 211 and the plurality of word line layers 212 are stacked alternately.

[0075] It should be noted that the word line layer 212 includes at least one word line WL, and the word line WL can be electrically connected to the corresponding word line connection line WL-CL via the connecting post 12. Here, the word line layer 212 can be isolated by the word line isolation structure 240 (see...). Figure 5 It is divided into multiple word lines WL.

[0076] The material of the first dielectric layer 211 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and its silicates, and at least one of organic insulating materials.

[0077] The material of the word line layer 212 may include a conductive material, such as at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and silicide.

[0078] See Figure 3A and Figure 3B The storage structure 220 includes a ferromagnetic free layer 221, a tunneling layer 222, a ferromagnetic pinning layer 223, and a conductive layer 224.

[0079] Among them, such as Figure 6 and Figure 7 The ferromagnetic free layer 221 is located between the tunneling layer 222 and the first stacked structure 210. The tunneling layer 222 is located between the ferromagnetic free layer 221 and the ferromagnetic pinning layer 223. The ferromagnetic pinning layer 223 is located between the tunneling layer 222 and the conductive layer 224. The conductive layer 224 is located on the side of the ferromagnetic pinning layer 223 away from the tunneling layer 222.

[0080] It should be noted that the ferromagnetic free layer 221, the tunneling layer 222, and the ferromagnetic nailing layer 223 are sequentially contacted to form a magnetic tunnel junction.

[0081] Here, the ferromagnetic free layer 221 and the conductive layer 224 are configured to connect electrical signals. For example, the ferromagnetic free layer 221 is configured to connect the word line WL, and the conductive layer 224 is configured to connect the bit line BL (see [link]). Figure 1 ), that is, coupled to the bit line BL.

[0082] The material of the aforementioned ferromagnetic free layer 221 includes ferromagnetic materials, such as at least one of cobalt-iron alloy, cobalt-iron-boron alloy, boron-iron alloy, and cobalt-nickel alloy.

[0083] The material of the tunneling layer 222 mentioned above includes an insulating material, which may be non-magnetic or weakly magnetic. The insulating material may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxides (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0084] The material of the aforementioned ferromagnetic nailing layer 223 includes ferromagnetic materials, such as at least one of cobalt-iron alloy, cobalt-iron-boron alloy, boron-iron alloy, and cobalt-nickel alloy.

[0085] The material of the conductive layer 224 mentioned above includes conductive materials, such as at least one of tungsten, cobalt, copper, aluminum, doped polycrystalline silicon, and silicides.

[0086] Furthermore, the magnetization direction of the ferromagnetic free layer 221 can be switched under specific external influences, while the magnetization direction of the ferromagnetic pinning layer 223 is fixed. For example, under the influence of a current flowing along the word line layer 212, the magnetization direction of the ferromagnetic free layer 221 can be switched between a third direction and a fourth direction, with the third and fourth directions being opposite. The magnetization direction of the ferromagnetic pinning layer 223 is along either the third or fourth direction.

[0087] Understandably, when the magnetization directions of the ferromagnetic free layer 221 and the ferromagnetic pinned layer 223 are the same, the resistance of the magnetic tunnel junction is relatively low. When the magnetization directions of the ferromagnetic free layer 221 and the ferromagnetic pinned layer 223 are opposite, the resistance of the magnetic tunnel junction is relatively high.

[0088] Based on this, the resistance of the magnetic tunnel junction can be changed by altering the magnetization direction of the ferromagnetic free layer 221. In other words, the resistance of the magnetic tunnel junction can be used to read the stored information. For example, a relatively high resistance in the magnetic tunnel junction represents the data "0," while a relatively low resistance represents the data "1."

[0089] The following example illustrates the embodiments of this disclosure by showing that a magnetic tunnel junction with relatively high resistance represents data "0" and a magnetic tunnel junction with relatively low resistance represents data "1".

[0090] At this time, see Figure 3A , Figure 3B and Figure 4 A magnetic tunnel junction can form a memory cell C. Multiple magnetic tunnel junctions included in a memory structure 220 can form a memory cell string 400.

[0091] Assume that the voltage that causes the magnetization direction of the ferromagnetic free layer 221 in the magnetic tunnel junction to reverse is V1, and the read voltage is V2.

[0092] It should be noted that V2 is much smaller than V1 to avoid the magnetization direction of the ferromagnetic free layer 221 changing due to a larger V2 during the reading process, which would cause deviations or errors in the read data.

[0093] In some embodiments, during a write operation, a switching voltage V1 is provided to the ferromagnetic free layer 221 via the word line WL, and the bit line BL (conductive layer 224) is grounded, i.e., the voltage of the bit line BL (conductive layer 224) is 0, so that the magnetization direction of the ferromagnetic free layer 221 is opposite to the magnetization direction of the ferromagnetic pinning layer 223, to write the data "0". Alternatively, a switching voltage V1 is provided to the ferromagnetic pinning layer 223 via the bit line BL (conductive layer 224), and the word line WL is grounded, i.e., the voltage of the word line WL is 0, so that the magnetization direction of the ferromagnetic free layer 221 is the same as the magnetization direction of the ferromagnetic pinning layer 223, to write the data "1".

[0094] In other embodiments, during a write operation, a flip voltage V1 is provided to the ferromagnetic free layer 221 via the word line WL, and the bit line BL (conductive layer 224) is grounded, i.e., the voltage of the bit line BL (conductive layer 224) is 0, so that the magnetization direction of the ferromagnetic free layer 221 is the same as the magnetization direction of the ferromagnetic pinned layer 223, to write the data "1". Alternatively, a flip voltage V1 is provided to the ferromagnetic pinned layer 223 via the bit line BL (conductive layer 224), and the word line WL is grounded, i.e., the voltage of the word line WL is 0, so that the magnetization direction of the ferromagnetic free layer 221 is opposite to the magnetization direction of the ferromagnetic pinned layer 223, to write the data "0".

[0095] During the read operation, the read voltage V2 is provided to the ferromagnetic nailing layer 223 through the bit line BL (conductive layer 224), and the word line WL is grounded, that is, the voltage of the word line WL is 0, so as to read the resistance of the magnetic tunnel junction and thus read the written data.

[0096] As described above, the semiconductor structure 100 is a random access memory based on spin-torque magnetism, which has the advantages of high speed, low power consumption, and unlimited erasure and write capability. Furthermore, the memory structures 220 can be arrayed in the direction of the reference plane, and each memory structure 220 includes a plurality of memory cells C spaced apart in a direction perpendicular to the reference plane. That is, the plurality of memory cells C are arrayed in the direction of the reference plane, and in the direction perpendicular to the reference plane (e.g., ... Figure 1 The three-dimensional space is arranged in a Z-direction, thereby realizing storage in three-dimensional space and improving the storage density of the semiconductor structure 100.

[0097] It should be noted that the aforementioned reference surface can be, for example, the lower surface of the first stacked structure 210. Figure 1 The plane containing the surface on the lower middle side.

[0098] In some embodiments, see Figure 9 and Figure 10The aforementioned storage structure 220 also includes an antiferromagnetic layer 225, which is located between the conductive layer 224 and the ferromagnetic pinning layer 223 to improve the magnetic coercivity of the ferromagnetic pinning layer 223 and reduce the risk of other magnetic tunnel junctions on the same bit line BL (or word line WL) being miswritten.

[0099] To prevent interference between multiple memory cells C corresponding to the same memory structure 220 or the same word line WL during write or read operations, the semiconductor structure 100 also includes a phase change layer 230.

[0100] The phase change layer 230 is at least partially located between the word line layer 212 and the ferromagnetic free layer 221. The phase change layer 230 is configured to be turned on or off under the control of the voltage of the word line layer 212. For example, the phase change layer 230 is in the on state when the voltage of the word line layer 212 is greater than or equal to a threshold voltage; and the phase change layer 230 is in the off state when the voltage of the word line layer 212 is less than the threshold voltage.

[0101] The material of the aforementioned phase change layer 230 includes a phase change material, which may include, for example, chalcogenides (such as alloys Ge2Sb2Te, Ge2Sb2Te5, Ge1Sb2Te4, etc.).

[0102] At this time, the word line WL can also control whether a corresponding memory cell C can be written or read by controlling the phase change layer 230 to turn it on or off, thereby realizing random read and write of any memory cell C.

[0103] Assume the threshold voltage of phase change layer 230 is V3. A turn-on voltage V4 is provided to phase change layer 230 through word line WL, where V4 ≥ V3, thus turning on phase change layer 230.

[0104] It should be noted that after the turn-on voltage V4 is removed, the phase change layer 230 will remain in the conducting state for a predetermined time. The aforementioned write and read operations will be performed within this predetermined time.

[0105] For example, during a write operation, an enable voltage V4 is first provided to the phase change layer 230 via the word line WL, causing the phase change layer 230 to conduct.

[0106] Then, a switching voltage V1 is provided to the ferromagnetic free layer 221 through the word line WL, and the bit line BL is grounded, i.e., the voltage of the bit line BL is 0, so that the magnetization direction of the ferromagnetic free layer 221 is opposite to the magnetization direction of the ferromagnetic nailing layer 223, in order to write the data "0". Alternatively, a switching voltage V1 is provided to the ferromagnetic nailing layer 223 through the bit line BL, and the word line WL is grounded, i.e., the voltage of the word line WL is 0, so that the magnetization direction of the ferromagnetic free layer 221 is the same as the magnetization direction of the ferromagnetic nailing layer 223, in order to write the data "1".

[0107] For example, in a read operation, an enable voltage V4 is first provided to the phase change layer 230 through the word line WL, so that the phase change layer 230 is turned on.

[0108] Then, the read voltage V2 is supplied to the ferromagnetic nail layer 223 through the bit line BL, and the word line WL is grounded, that is, the voltage of the word line WL is 0, so as to read the resistance of the magnetic tunnel junction and thus read the written data.

[0109] In some embodiments, such as Figure 9 and Figure 10 As shown, the word line layer 212 is located near the boundary of the memory structure 220, and is recessed inward in a direction away from the memory structure 220 compared to the boundary of the first dielectric layer 211 near the memory structure 220, to form a groove. At this time, the semiconductor structure 100 includes a plurality of phase change layers 230, and each phase change layer 230 may be located in a groove.

[0110] Here, the phase change layer 230 is close to the boundary of the memory structure 220. It can be recessed inward relative to the boundary of the first dielectric layer 211 near the memory structure 220, or it can be flush with the boundary of the first dielectric layer 211 near the memory structure 220.

[0111] For example, such as Figure 9 and Figure 10 As shown, the phase change layer 230 is close to the boundary of the memory structure 220, and is recessed inward in a direction away from the memory structure 220 compared to the boundary of the first dielectric layer 211. At this time, the semiconductor structure 100 includes a plurality of ferromagnetic free layers 221, and each ferromagnetic free layer 221 may also be located in a groove.

[0112] In other embodiments, such as Figure 6 and Figure 7 As shown, the phase change layer 230 is located between the word line layer 212 and the two first dielectric layers 211 adjacent to the word line layer 212, and between the word line layer 212 and the memory structure 220. That is, the phase change layer 230 covers the end of the word line layer 212 near the memory structure 220 and the two surfaces of the word line layer 212 adjacent to the first dielectric layers 211.

[0113] Here, the phase change layer 230 is close to the boundary of the memory structure 220. It can be recessed inward relative to the boundary of the first dielectric layer 211 near the memory structure 220, or it can be flush with the boundary of the first dielectric layer 211 near the memory structure 220.

[0114] For example, such as Figure 6 and Figure 7As shown, the phase change layer 230 is near the boundary of the memory structure 220 and flush with the boundary of the first dielectric layer 211 near the boundary of the memory structure 220. At this time, the ferromagnetic free layer 221 can be a continuous film layer along the third direction Z, and is located between the phase change layer 230 and the memory structure 220, as well as between the first dielectric layer 211 and the memory structure 220. The third direction Z is perpendicular to the reference plane.

[0115] In some embodiments, see Figure 5 The shape of the orthographic projection of the storage structure 220 onto the reference plane is circular or elliptical, and the reference plane is the lower surface of the first stacked structure 210. Figure 5 The plane containing the surface on the lower middle side.

[0116] Here, as Figure 6 and Figure 7 As shown, the phase change layer 230 can be located between the word line layer 212 and the two first dielectric layers 211 adjacent to the word line layer 212, and between the word line layer 212 and the memory structure 220. That is, the phase change layer 230 covers the end of the word line layer 212 near the memory structure 220 and the two surfaces of the word line layer 212 adjacent to the first dielectric layers 211.

[0117] Furthermore, the phase change layer 230 is close to the boundary of the memory structure 220 and is flush with the boundary of the first dielectric layer 211 close to the boundary of the memory structure 220. At this time, the ferromagnetic free layer 221 is a film layer that is continuous along the third direction Z and is located between the phase change layer 230, the first dielectric layer 211 and the memory structure 220.

[0118] In this case, word line layer 212 and phase change layer 230 can be formed by replacing the sacrificial layer after forming memory structure 220, which simplifies the process. Furthermore, word line layer 212 does not need to be etched during the formation of memory structure 220, and the material of word line layer 212 does not affect the process of forming memory structure 220. This makes it easier to select materials with lower resistance for word line layer 212 and reduce the power consumption of semiconductor structure 100.

[0119] In other embodiments, see Figure 8 In the aforementioned ferromagnetic free layer 221, tunneling layer 222, and ferromagnetic pinning layer 223, the adjacent surfaces of any two adjacent layers are planar. In this case, the magnetic tunnel junction can have more stable magnetism, thereby improving the stability of data writing and reading.

[0120] For example, such as Figure 8 , Figure 9 and Figure 10 As shown, the orthographic projection of the storage structure 220 onto the reference plane is a polygon; for example, the orthographic projection of the storage structure 220 onto the reference plane is a triangle, a rectangle, or a trapezoid, etc.

[0121] The orthographic projection of the storage structure 220 onto the reference plane can be, for example, a rectangle, or the storage structure 220 can be, for example, a cuboid, which reduces manufacturing costs.

[0122] Based on this, refer to Figure 8 The aforementioned semiconductor structure 100 may include a memory group 260 and a channel isolation structure 270.

[0123] The storage group 260 includes two rows of storage structures 220 arranged along a first direction X, and each row of storage structures 220 includes multiple storage structures 220 arranged along a second direction Y. The first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y. Furthermore, along the first direction X, the conductive layer 224 of the two rows of storage structures 220 is located between the ferromagnetic pinning layers 223 of the two rows of storage structures 220.

[0124] Furthermore, the semiconductor structure 100 may include multiple memory groups 260, which may be arranged in an array. For example, see... Figure 8 Multiple memory groups 260 are arranged in multiple rows and columns along the first direction X and the second direction Y to increase the number of memory structures 220 and improve the storage density of the semiconductor structure 100.

[0125] Based on this, such as Figure 8 As shown, the channel isolation structure 270 is at least partially located between any two adjacent storage structures 220 in the storage group 260.

[0126] For example, the channel isolation structure 270 covers the surface of the conductive layer 224 away from the ferromagnetic free layer 221, as well as the two opposite sides of the ferromagnetic free layer 221, the tunneling layer 222, the ferromagnetic pinning layer 223, and the conductive layer 224 in the first direction X. That is, the channel isolation structure 270 has a plurality of mounting slots, and each storage structure 220 is located in one mounting slot.

[0127] In this configuration, an initial channel structure can be divided into multiple storage structures 220 in a storage group 260 by the channel isolation structure 270. The process is simple, and the specific process flow can be referred to below. The embodiments disclosed herein will not be described in detail here.

[0128] In some embodiments, see Figure 5 and Figure 6 The aforementioned semiconductor structure 100 further includes a word line isolation structure 240, which penetrates the first stacked structure 210. Here, the word line isolation structure 240 extends along a fourth direction to divide the word line layer 212 into multiple word lines WL.

[0129] It should be noted that the fourth direction is parallel to the reference plane; for example, the fourth direction can be the same as the first direction X.

[0130] Furthermore, before forming the word line isolation structure 240, the sacrificial layer can be replaced by the gate isolation gap to form the aforementioned word line layer 212 and phase change layer 230, which is a low-difficulty process.

[0131] In some embodiments, such as Figure 6 As shown, the word line isolation structure 240 includes an insulating isolation portion 241, which is in contact with the side of the first dielectric layer 211, the phase change layer 230 and the word line layer 212.

[0132] It should be noted that the material of the insulating isolation part 241 includes insulating materials, which may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0133] In some embodiments, the word line isolation structure 240 may further include a gate line filling layer. A cavity is provided inside the insulating isolation portion, and the gate line filling layer fills the cavity to provide mechanical support.

[0134] It should be noted that the material of the gate line filling layer can be a conductive material or an insulating material, and the embodiments disclosed herein do not specifically limit it.

[0135] In some embodiments, see Figure 2 and Figure 3A The aforementioned storage array structure 20 also includes a second stack structure 280 and a channel structure 290.

[0136] like Figure 2 and Figure 3A As shown, the second stacked structure 280 is located on the first stacked structure 210. For example, the second stacked structure 280 is located on the side of the first stacked structure 210 away from the substrate 11.

[0137] The second stacked structure 280 includes at least one select gate layer 281 and at least one second dielectric layer 282. For example, the second stacked structure 280 includes one select gate layer 281 and one second dielectric layer 282.

[0138] The material of the selected gate layer 281 may include a conductive material, such as at least one selected from tungsten, cobalt, copper, aluminum, doped polysilicon, and silicide. Here, the material of the selected gate layer 281 may be the same as or different from the material of the word line layer 212; this disclosure does not specifically limit the material used in the embodiments.

[0139] The material of the second dielectric layer 282 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxides (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and at least one of organic insulating materials. Here, the material of the second dielectric layer 282 may be the same as or different from the material of the first dielectric layer 211; this disclosure does not specifically limit the material used in the embodiments.

[0140] like Figure 1 and Figure 3B As shown, the channel structure 290 extends through the second stack structure 280. The channel structure 290 includes a channel layer 291, which is electrically connected to the conductive layer 224, and is configured to connect bit lines BL.

[0141] Here, the channel layer 291 and the select gate layer 281 can be constructed as simple metal-oxide-semiconductor (MOS) transistors to serve as switching transistors, thereby simplifying the process and reducing manufacturing costs.

[0142] For example, the channel structure 290 further includes a third dielectric layer 292 located between the channel layer 291 and the select gate layer 281. In this case, the channel layer 291, the third dielectric layer 292, and the select gate layer 281 form a select transistor T.

[0143] At this time, the memory cell string 400 also includes a selection transistor T. Thus, the read and write operations of memory cells C can be controlled by the selection transistor T. In other words, the conduction state of one source channel (bit line BL) in the memory cell string 400 can be controlled by the selection transistor T, and data writing and reading of each memory cell C in the memory cell string 400 can be completed by the voltage written on the word line WL of the word line layer 212.

[0144] In some embodiments, such as Figure 3A and Figure 3B As shown, the channel structure 290 also includes a channel filling layer 293. The channel layer 291 has an inner cavity, which is filled by the channel filling layer 293 to provide mechanical support.

[0145] It should be noted that the material of the channel filling layer 293 includes an insulating material, which may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials, and this disclosure is not limited thereto.

[0146] See also Figure 1 and Figure 2 In some embodiments, the semiconductor structure 100 may further include an array interconnect layer 300. The array interconnect layer 300 may be coupled to the memory cell string 400. The array interconnect layer 300 may include the drain (i.e., bit line BL) of the memory cell string 400, and the drain may be coupled to the conductive layer 224 (see...). Figure 3A ) Coupling.

[0147] The array interconnect layer 300 may include one or more first interlayer insulating layers 310, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 310. The contacts may include, for example, bit line contacts BL-CNT coupled to bit line BL; and select gate layer contacts, coupled to select gate layer 281 (see [link to [link]). Figure 3A Coupling. The array interconnect layer 300 may also include one or more first interconnect conductor layers 320. The first interconnect conductor layer 320 may include multiple interconnect lines, such as bit lines BL, and word line interconnect lines WL-CL coupled to word lines WL.

[0148] The materials of the first interconnect conductor layer 320 and the contacts can be conductive materials, such as one or more combinations of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials.

[0149] The material of the first interlayer insulation layer 310 is an insulating material, such as one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0150] In some embodiments, see Figure 1 and Figure 2 The three-dimensional memory 10 may also include peripheral devices 200 coupled to the semiconductor structure 100.

[0151] Here, the peripheral device 200 can be located on the side of the memory array structure 20 away from the substrate 11.

[0152] The peripheral device 200 may include peripheral circuitry. This peripheral circuitry is configured to control and sense the array device. The peripheral circuitry can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to support the operation (or function) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0153] In some embodiments, such as Figure 1 and Figure 2 As shown, the peripheral device 200 may include a substrate 201, a transistor 202 disposed on the substrate 201, and a peripheral interconnect layer 203 disposed on the substrate 201. The peripheral circuit may include the transistor 202.

[0154] The substrate 201 can be made of single-crystal silicon or other suitable materials, such as silicon-germanium, germanium or silicon-on-insulator thin film.

[0155] The peripheral interconnect layer 203 is coupled to the transistor 202 to enable the transmission of electrical signals between the transistor 202 and the peripheral interconnect layer 203. The peripheral interconnect layer 203 may include one or more second interlayer insulating layers 204, and may also include one or more second interconnect conductor layers 205. Different second interconnect conductor layers 205 may be coupled to each other via contacts.

[0156] The materials of the second interconnect conductor layer 205 and the contacts can be conductive materials, such as one or more combinations of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials.

[0157] The material of the second interlayer insulation layer 204 is an insulating material, such as one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0158] In some embodiments, such as Figure 1 and Figure 2 As shown, the peripheral interconnect layer 203 can be coupled to the array interconnect layer 300, so that the semiconductor structure 100 and the peripheral device 200 can be coupled.

[0159] Here, since the peripheral interconnect layer 203 is coupled to the array interconnect layer 300, the peripheral circuit in the peripheral device 200 can be coupled to the memory cell string 400 in the semiconductor structure 100 to realize the transmission of electrical signals between the peripheral circuit and the memory cell string 400.

[0160] See also some possible implementations. Figure 1 and Figure 2 An adhesive interface 500 can be provided between the peripheral interconnect layer 203 and the array interconnect layer 300. Through the adhesive interface 500, the peripheral interconnect layer 203 and the array interconnect layer 300 can be bonded and coupled to each other.

[0161] Some embodiments of this disclosure also provide a method for fabricating a semiconductor structure; see [link to relevant documentation]. Figure 25 The preparation method includes steps S100 to S200.

[0162] S100: See Figure 11 This forms the first stacked structure 210.

[0163] In the above steps, the first stacked structure 210 includes a plurality of first dielectric layers 211 and a plurality of word line layers 212. Exemplarily, the plurality of first dielectric layers 211 and the plurality of word line layers 212 are stacked alternately.

[0164] The first stacked structure 210 can be formed on the substrate 11 using any of the following thin film deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0165] It should be noted that the materials of the substrate 11, the first dielectric layer 211 and the word line layer 212 can all be referred to above, and will not be repeated here.

[0166] S200: See also Figure 9 and Figure 16 This forms a phase change layer 230 and a storage structure 220 that penetrates the first stacked structure 210.

[0167] In the above steps, such as Figure 10As shown, the memory structure 220 includes a ferromagnetic free layer 221, a tunneling layer 222, a ferromagnetic pinning layer 223, and a conductive layer 224. The ferromagnetic free layer 221 is located between the tunneling layer 222 and the first stacked structure 210. The tunneling layer 222 is located between the ferromagnetic free layer 221 and the ferromagnetic pinning layer 223. The ferromagnetic pinning layer 223 is located between the tunneling layer 222 and the conductive layer 224. The conductive layer 224 is located on the side of the ferromagnetic pinning layer 223 away from the tunneling layer 222. The phase change layer 230 is at least partially located between the word line layer 212 and the ferromagnetic free layer 221.

[0168] In some embodiments, see Figure 8 and Figure 9 In the ferromagnetic free layer 221, tunneling layer 222, and ferromagnetic pinning layer 223, the adjacent surfaces of any two adjacent layers are planes. For example, the orthographic projection of the storage structure 220 onto the reference plane can be a polygon; for instance, the orthographic projection of the storage structure 220 onto the reference plane can be a rectangle.

[0169] In other embodiments, see Figure 5 and Figure 6 The orthographic projection of the storage structure 220 onto the reference plane can be circular or elliptical.

[0170] The following uses the example of a rectangle as the orthographic projection of the storage structure 220 onto the reference plane to illustrate the embodiments of this disclosure.

[0171] At this time, as Figure 26 As shown, the above S200 may include, for example, S210 to S260.

[0172] S210: See also Figure 13 and Figure 14 This forms an initial channel hole CH' that penetrates the first stacked structure 210.

[0173] In the above steps, the orthographic projection of the initial channel hole CH' onto the reference plane is a rectangle, and the reference plane is the plane containing the lower surface of the first stacked structure 210.

[0174] The initial channel hole CH' penetrating the first stacked structure 210 can be formed by a dry / wet etching process. For example, the initial channel hole CH' is formed by an anisotropic etching process (any one of dry etching processes such as ion milling, plasma etching, reactive ion etching, and laser ablation).

[0175] S220: See also Figure 16 A phase change layer 230 is formed within the initial channel hole CH'.

[0176] In the above steps, the phase change layer 230 covers the surface of the word line layer 212 exposed by the initial channel via CH'. The phase change layer 230 is at least partially located between the word line layer 212 and the ferromagnetic free layer 221.

[0177] In some embodiments, such as Figure 27 As shown, S220 includes S221 to S222.

[0178] S221: See also Figure 14 The edge portion of word line layer 212 near the initial channel hole CH' is removed via the initial channel hole CH'.

[0179] In the above steps, the edge portion of the word line layer 212 near the initial channel hole CH' is removed through the initial channel hole CH', so that the word line layer 212 is close to the boundary of the initial channel hole CN, and is recessed inward in a direction away from the initial channel hole CN compared to the boundary of the first dielectric layer 211 near the initial channel hole CN, forming a groove.

[0180] The initial channel hole CH' can be used as an etchant channel to etch the end of the word line layer 212 exposed at the initial channel hole CH', and the etchant is used to etch the word line layer 212.

[0181] S222: See also Figure 15 A phase change layer 230 is formed in the groove.

[0182] In some embodiments, such as Figure 28 As shown, S222 may include S2221 to S2222.

[0183] S2221: See also Figure 15 A phase change thin film is formed at 230°.

[0184] In the above steps, the phase change film 230' covers the inner wall of the groove, and also covers the inner wall of the initial channel hole CH' and the upper side of the first stacked structure 210. The phase change film 230' can be formed using any of the following thin film deposition processes: CVD, PVD, or ALD.

[0185] S2222: See also Figure 16 The phase change film 230' covering the inner wall of the initial channel hole CH' and the upper part of the first stacked structure 210 is removed to form the phase change layer 230.

[0186] In the above steps, the inner wall of the phase change film 230' covering the initial channel hole CH' and the upper part of the first stacked structure 210 can be removed by dry / wet etching process.

[0187] S230: See also Figure 20 An initial storage structure 220' is formed within the initial channel hole CH'.

[0188] In the above steps, the initial memory structure 220' includes an initial ferromagnetic free layer 221", an initial tunneling layer 222", an initial ferromagnetic pinning layer 223", and an initial conductive layer 224", and the initial memory structure 220' forms a first void within the initial channel hole CH' (see 19). The orthographic projection of the initial memory structure 220' onto the reference plane is rectangular, and includes two opposing first sides L1 and two opposing second sides L2.

[0189] Among them, such as Figure 29 As shown, S230 may include S231 to S233.

[0190] S231: See also Figure 14 and Figure 16 An initial ferromagnetic free layer 221" is formed in the groove.

[0191] In some embodiments, such as Figure 30 As shown, S231 may include S2311 to S2312.

[0192] S2311: See also Figure 17 , forming a ferromagnetic free thin film 221'.

[0193] In the above steps, the ferromagnetic free thin film 221' fills the groove and covers the inner wall of the initial channel hole CH' and the upper side of the first stacked structure 210. The ferromagnetic free thin film 221' can be formed using any of the following thin film deposition processes: CVD, PVD, and ALD.

[0194] S2312: See also Figure 17 and Figure 18 Remove the ferromagnetic free thin film 221' covering the inner wall of the initial channel hole CH' and the first Figure 1 The upper part of the stacked structure 210 forms an initial ferromagnetic free layer 221".

[0195] In the above steps, a dry / wet etching process can be used to remove the ferromagnetic free film covering the inner wall of the initial channel hole CH' and the upper part of the first stacked structure 210.

[0196] S232: See also Figure 19 The tunneling film 222', the ferromagnetic pinning film 223', and the conductive film 224' are formed sequentially.

[0197] In the above steps, the tunneling film 222', the ferromagnetic pinning film 223', and the conductive film 224' cover the inner wall of the initial channel hole CH' and the upper side of the first stacked structure 210. The tunneling film 222', the ferromagnetic pinning film 223', and the conductive film 224' can be formed sequentially using any of the following thin film deposition processes: CVD, PVD, and ALD.

[0198] S233: Remove the portion of the tunneling film 222', the ferromagnetic pinning film 223', and the conductive film 224' that covers the upper side of the first stacked structure 210.

[0199] In the above steps, by removing the portion of the tunneling film 222', the ferromagnetic pinning film 223', and the conductive film 224' that covers the upper side of the first stacked structure 210, the initial tunneling layer 222" and the initial ferromagnetic pinning layer 223" and the initial conductive layer 224" can be formed.

[0200] It should be noted that the method of removing the portions of the tunneling film 222', the ferromagnetic anchor film 223', and the conductive film 224' covering the upper side of the first stacked structure 210 is not unique. For example, the removal of the portions of the tunneling film 222', the ferromagnetic anchor film 223', and the conductive film 224' covering the upper side of the first stacked structure 210 can be performed simultaneously with the removal of the portion of the first filler film covering the upper side of the first stacked structure 210 mentioned below. That is, during the process of removing the portion of the first filler film covering the upper side of the first stacked structure 210, the portions of the tunneling film 222', the ferromagnetic anchor film 223', and the conductive film 224' covering the upper side of the first stacked structure 210 are also removed to simplify the process and reduce costs.

[0201] Furthermore, in some embodiments, the storage structure 220 further includes an antiferromagnetic layer 225. In this case, between the formation of the ferromagnetic pinning film 223' and the conductive film 224', S223 further includes the formation of an antiferromagnetic film 225', which covers the inner wall of the initial channel hole CH' and the upper side of the first stacked structure 210. Moreover, during the removal of portions of the tunneling film 222', the ferromagnetic pinning film 223', and the conductive film 224' covering the first stacked structure 210, the portion of the antiferromagnetic film 225' covering the upper side of the first stacked structure 210 is also removed.

[0202] S240: See also Figure 20 A first filling layer 271 is formed within the first gap.

[0203] In some embodiments, such as Figure 31 As shown, S240 includes S241 to S242.

[0204] S241: Form the first filling film.

[0205] In the above steps, the first filling film covers the inner wall of the first void and the upper side of the first stacked structure. The first filling film can be formed using any of the following thin film deposition processes: CVD, PVD, and ALD.

[0206] S242: Remove the portion of the first filler film covering the upper side of the first stacked structure 210.

[0207] In the above steps, either chemical mechanical planarization (CMP) or dry / wet etching processes are used to remove the portion of the first filling film covering the upper side of the first stacked structure 210.

[0208] For example, CMP is used to remove the portion of the first filler film covering the upper side of the first stacked structure 210. At this time, during the process of removing the portion of the first filler film covering the upper side of the first stacked structure 210 using CMP, the portions of the tunneling film 222', the ferromagnetic anchoring film 223', and the conductive film 224' covering the upper side of the first stacked structure 210 can also be removed simultaneously to simplify the process and reduce costs.

[0209] S250: See also Figure 22 This forms multiple isolation slots S that penetrate the first stacked structure 210.

[0210] In the above steps, multiple isolation slots S are arranged sequentially at intervals along the extension direction of the first side, and in the orthographic projection onto the reference plane, the two outermost isolation slots S at both ends respectively cover the two second sides of the initial storage structure 220'. The multiple isolation slots divide the initial storage structure 220' into multiple storage structures 220 (see...). Figure 8 ).

[0211] The isolation trench S penetrating the first stacked structure 210 can be formed by a dry / wet etching process. For example, the isolation trench S is formed by anisotropic etching (any one of dry etching processes such as ion milling, plasma etching, reactive ion etching, and laser ablation).

[0212] It should be noted that when the orthographic projection of the initial storage structure 220' onto the reference plane is a rectangle, the first side can be the long side of the rectangle, and the second side can be the short side of the rectangle.

[0213] In some embodiments, such as Figure 32 As shown, S250 includes S251 to S252.

[0214] S251: See also Figure 21 , forming a mask layer 13.

[0215] In the above steps, the mask layer 13 includes multiple cutout areas M, which are arranged sequentially at intervals along the extension direction of the first side. In the orthographic projection onto the reference plane, the two outermost cutout areas M at both ends expose the two second sides of the initial storage structure 220'.

[0216] S252: See also Figure 21 and Figure 22 Based on the mask layer 13, the initial storage structure 220' is etched to form multiple isolation trenches S.

[0217] In the above steps, the etchant can etch the initial storage structure 220' through the cutout area M of the mask layer 13 to form the isolation trench S.

[0218] S260: See also Figure 8 , Figure 9 and Figure 22 A second filling layer 272 is formed within multiple isolation grooves S.

[0219] In the above steps, the first filling layer 271 and the second filling layer 272 are connected to form a channel isolation structure 270.

[0220] It should be noted that the materials of the first filling layer 271 and the second filling layer 272 can refer to the materials of the channel isolation structure 270 described above, and will not be repeated here in this embodiment.

[0221] In some embodiments, such as Figure 33 As shown, S260 includes S261 to S262.

[0222] S261: Form a second filling film.

[0223] In the above steps, the second filling film covers the inner wall of the isolation trench S and the upper side of the first stacked structure 210. The second filling film can be formed using any of the following thin film deposition processes: CVD, PVD, and ALD.

[0224] S262: Remove the portion of the second filler film covering the upper side of the first stacked structure 210.

[0225] In the above steps, chemical mechanical planarization (CMP) and dry / wet etching processes are used to remove the portion of the first filling film covering the upper side of the first stacked structure 210.

[0226] In some embodiments, between S100 and S200, such as Figure 34 As shown, the method for fabricating the above-mentioned semiconductor structure also includes S150.

[0227] S150: See also Figure 12 , forming a protective layer 14.

[0228] In the above steps, the protective layer 14 covers the upper surface of the first stacked structure 210. Furthermore, in S200, the storage structure 220 extends through the protective layer 14.

[0229] In some embodiments, see Figure 37 The methods for preparing the aforementioned semiconductor structure also include S900 and S910.

[0230] S900: See also Figure 23 This forms a second stacked structure 280.

[0231] In the above steps, such as Figure 3A and Figure 23 The second stacked structure 280 is located on the first stacked structure 210, and the second stacked structure 280 includes a plurality of second dielectric layers 282 and a plurality of select gate line layers 281. Exemplarily, the plurality of second dielectric layers 282 and the plurality of select gate line layers 281 are stacked alternately. The second stacked structure 280 can be formed on the first stacked structure 210 using any of the thin film deposition processes of CVD, PVD, and ALD.

[0232] S910: See also Figure 3A , Figure 23 and Figure 24 This forms a channel structure 290 that penetrates the second stacked structure 280.

[0233] In the above steps, a second channel hole CH2 penetrating the second stacked structure 280 can be formed by a dry / wet etching process. Then, a channel structure 290 is formed in the second channel hole CH2, and the channel structure 290 is electrically connected to the memory structure 220.

[0234] The channel structure 290 includes a channel layer 291, which is electrically connected to the conductive layer 224, and the channel layer 291 is configured to connect bit lines BL.

[0235] It should be noted that the structure and materials of the channel structure 290 can be referred to above, and will not be repeated here in the embodiments disclosed herein.

[0236] Some embodiments of this disclosure also provide a method for fabricating a semiconductor structure, see below. Figure 35 This includes S300 to S700.

[0237] S300: See also Figure 38 This forms the initial stacked structure 210'.

[0238] In the above steps, the initial stacked structure 210' includes a plurality of alternating first dielectric layers 211 and a plurality of sacrificial layers 212'.

[0239] It should be noted that the material of the first dielectric layer 211 is different from the material of the gate sacrificial layer 212', so that the first dielectric layer 211 and the gate sacrificial layer 212' have different etching selectivity ratios for the same etchant. For example, the material of the first dielectric layer 211 is silicon dioxide, and the material of the gate sacrificial layer 212' is silicon nitride.

[0240] The initial stacked layer 210' can be formed on the substrate using any of the thin film deposition processes of CVD, PVD, or ALD.

[0241] S400: See also Figure 40 This forms a storage structure 220 that runs through the initial stacked structure 210'.

[0242] In the above steps, such as Figure 10 As shown, the storage structure 220 includes a ferromagnetic free layer 221, a tunneling layer 222, a ferromagnetic pinning layer 223, and a conductive layer 224.

[0243] In some embodiments, see Figure 8 and Figure 9 In the ferromagnetic free layer 221, tunneling layer 222, and ferromagnetic pinning layer 223, the adjacent surfaces of any two adjacent layers are planes. For example, the orthographic projection of the storage structure 220 onto the reference plane can be a rectangle.

[0244] In other embodiments, see Figure 5 and Figure 6 The orthographic projection of the storage structure 220 onto the reference plane can be circular or elliptical.

[0245] The following example illustrates the embodiments of this disclosure by taking the orthographic projection of the storage structure 220 onto the reference plane as a circle or an ellipse.

[0246] At this time, as Figure 36 As shown, the above S400 may include S410 to S430.

[0247] S410: See also Figure 39 This forms the first channel hole CH1 that penetrates the initial stacked structure 210'.

[0248] In the above steps, the orthographic projection of the first channel hole CH1 on the reference plane is a circle or an ellipse, and the reference plane is the plane where the lower surface of the first stacked structure 210 is located.

[0249] The initial stacked layer 210' can be etched using a dry / wet etching process to form the first channel hole CH1. For example, the first channel hole CH1 is formed using anisotropic etching (any one of dry etching methods such as ion milling, plasma etching, reactive ion etching, or laser ablation).

[0250] S420: See also Figure 17 and Figure 19 A ferromagnetic free thin film 221', a tunneling thin film 222', a ferromagnetic pinned thin film 223', and a conductive thin film 224' are formed sequentially.

[0251] In the above steps, the ferromagnetic free film 221', the tunneling film 222', the ferromagnetic pinning film 223', and the conductive film 224' cover the inner wall of the first channel hole CH1 and the upper side of the initial stacked structure 210'.

[0252] S430: See also Figure 18 , Figure 20 and Figure 40 Remove the portion of the ferromagnetic free film 221', tunneling film 222', ferromagnetic pinning film 223', and conductive film 224' that covers the upper side of the initial stacked structure 210'.

[0253] In the above steps, either CMP or dry / wet etching processes can be used to remove the portion of the ferromagnetic free film 221', tunneling film 222', ferromagnetic pinning film 223', and conductive film 224' that covers the upper side of the initial stacked structure 210'.

[0254] In some embodiments, between forming the ferromagnetic pinning film 223' and the conductive film 224', S400 further includes forming an antiferromagnetic film 225'. Furthermore, during S430, the portion of the antiferromagnetic film 225' covering the upper side of the initial stacked structure 210' is removed.

[0255] S500: See Figure 40 This forms the word line gap GLS that runs through the initial stacked structure 210'.

[0256] In the above steps, word line gaps (GLS) penetrating the initial stacked layer 210' can be formed using dry / wet etching processes. For example, anisotropic etching (any one of dry etching methods such as ion milling, plasma etching, reactive ion etching, and laser ablation) is used to form the word line gaps (GLS).

[0257] S600: See also Figure 41 By removing the sacrificial layer 212' through the word line gap GLS, a word line cavity is formed.

[0258] In the above steps, the word line gap (GLS) can be used as an etchant channel, and isotropic etching can be used to remove the sacrificial layer 212' to form a word line cavity.

[0259] S700: See also Figure 6 and Figure 41 A phase change layer 230 and a word line layer 212 are formed sequentially within the word line cavity.

[0260] In the above steps, the phase change layer 230 is located between the word line layer 212 and the two first dielectric layers 211 adjacent to the word line layer 212, and between the word line layer 212 and the memory structure 220.

[0261] In some embodiments, such as Figure 35 As shown, the method for fabricating the semiconductor structure also includes S800.

[0262] S800: See also Figure 6 and Figure 41 A word line isolation structure 240 is formed within the word line gap GLS.

[0263] In the above steps, any one of the thin film deposition processes, such as CVD, PVD, or ALD, can be used to form the word line isolation structure 240 within the word line gap (GLS). The structure and materials of the word line isolation structure 240 can be referred to above, and will not be repeated here.

[0264] In some embodiments, see Figure 37 The methods for preparing the aforementioned semiconductor structure also include S900 and S910.

[0265] S900: See reference Figure 23 This forms a second stacked structure 280.

[0266] In the above steps, the second stacked structure 280 is located on the first stacked structure 210, and the second stacked structure 280 includes a plurality of second dielectric layers 282 and a plurality of select gate line layers 281. Exemplarily, the plurality of second dielectric layers 282 and the plurality of select gate line layers 281 are alternately stacked. The second stacked structure 280 can be formed on the first stacked structure 210 using any of the thin film deposition processes selected by CVD, PVD, or ALD.

[0267] S910: See also Figure 3A , Figure 23 and Figure 24 This forms a channel structure 290 that penetrates the second stacked structure 280.

[0268] In the above steps, a second channel hole CH2 penetrating the second stacked structure 280 can be formed by a dry / wet etching process. Then, a channel structure 290 is formed in the second channel hole CH2, and the channel structure 290 is electrically connected to the memory structure 220.

[0269] The channel structure 290 includes a channel layer 291, which is electrically connected to the conductive layer 224, and the channel layer 291 is configured to connect bit lines BL.

[0270] It should be noted that the structure and materials of the channel structure 290 can be referred to above, and will not be repeated here in the embodiments disclosed herein.

[0271] Figure 42 This is a block diagram of a storage system according to some embodiments. Figure 43 This is a block diagram of a storage system according to some other embodiments.

[0272] Please see Figure 42 and Figure 43 Some embodiments of this disclosure also provide a storage system 1000. The storage system 1000 includes a controller 30 and a three-dimensional memory 10 as described in some of the embodiments above, the controller 30 being coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

[0273] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0274] In some embodiments, see Figure 42 The storage system 1000 includes a controller 30 and a three-dimensional memory 10, and the storage system 1000 can be integrated into a three-dimensional memory card.

[0275] Among them, 3D memory cards include any one of the following: PC card (PCMCIA, the International Association for Personal Computer 3D Memory Cards), Compact Flash (CF) card, Smart Media (SM) card, 3D memory, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0276] In other embodiments, see Figure 43The storage system 1000 includes a controller 30 and multiple three-dimensional storage devices 10, and the storage system 1000 is integrated into a solid state drive (SSD).

[0277] In some embodiments of the storage system 1000, the controller 30 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0278] In other embodiments, controller 30 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0279] In some embodiments, the controller 30 may be configured to manage data stored in the semiconductor structure 100 and to communicate with external devices (e.g., a host). In some embodiments, the controller 30 may also be configured to control operations of the semiconductor structure 100, such as read, erase, and program operations. In some embodiments, the controller 30 may also be configured to manage various functions relating to data stored or to be stored in the semiconductor structure 100, including at least one of bad block management, garbage collection, logic-to-physical address translation, and wear leveling. In some embodiments, the controller 30 is also configured to process error correction codes relating to data read from or written to the semiconductor structure 100.

[0280] Of course, controller 30 can also perform any other suitable function, such as formatting semiconductor structure 100; for example, controller 30 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0281] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0282] Some embodiments of this disclosure also provide an electronic device. The electronic device can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0283] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0284] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: The first stacked structure includes multiple alternating first dielectric layers and multiple word line layers; The storage structure extends through the first stacked structure; The storage structure includes a ferromagnetic free layer, a tunneling layer, a ferromagnetic pinning layer, and a conductive layer; the ferromagnetic free layer is located between the tunneling layer and the first stacked structure, the tunneling layer is located between the ferromagnetic free layer and the ferromagnetic pinning layer, the ferromagnetic pinning layer is located between the tunneling layer and the conductive layer, the conductive layer is located on the side of the ferromagnetic pinning layer away from the tunneling layer, and the conductive layer is coupled to a bit line; the storage structure further includes an antiferromagnetic layer, which is located between the conductive layer and the ferromagnetic pinning layer; A phase change layer, at least partially located between the word line layer and the ferromagnetic free layer, is coupled to both the word line layer and the ferromagnetic free layer.

2. The semiconductor structure according to claim 1, characterized in that, In the ferromagnetic free layer, the tunneling layer, and the ferromagnetic pinning layer, the adjacent surfaces of any two adjacent layers are planes.

3. The semiconductor structure according to claim 2, characterized in that, The orthographic projection of the storage structure onto the reference plane is a polygon, and the reference plane is the plane containing the lower surface of the first stacked structure.

4. The semiconductor structure according to claim 2, characterized in that, include: A storage group includes two rows of storage structures arranged along a first direction, each row of storage structures including multiple storage structures arranged along a second direction, the first direction intersecting the second direction; Along the first direction, the conductive layer of the two rows of memory structures is located between the ferromagnetic nailing layers of the two rows of memory structures; The channel isolation structure is located, at least partially, between any two adjacent memory structures in the memory group.

5. The semiconductor structure according to claim 1, characterized in that, The shape of the orthographic projection of the storage structure onto the reference plane is circular or elliptical, and the reference plane is the plane containing the lower surface of the first stacked structure.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that, The word line layer is close to the boundary of the storage structure, and is recessed inward in a direction away from the storage structure compared to the first medium layer which is close to the boundary of the storage structure, to form a groove; The semiconductor structure includes a plurality of phase change layers, each of which is located within a recess.

7. The semiconductor structure according to claim 6, characterized in that, Each of the memory structures includes a plurality of ferromagnetic free layers, each of the ferromagnetic free layers being located within one of the recesses, and the phase change layer being located between the ferromagnetic free layers and the word line layer.

8. The semiconductor structure according to any one of claims 1 to 5, characterized in that, The phase change layer is located between the word line layer and the two first dielectric layers adjacent to the word line layer, and between the word line layer and the memory structure.

9. The semiconductor structure according to claim 8, characterized in that, The phase change layer is close to the boundary of the storage structure and is flush with the boundary of the first dielectric layer near the storage structure; The ferromagnetic free layer is a continuous film layer along a third direction and is located between the phase change layer and the memory structure, as well as between the first dielectric layer and the memory structure; the third direction is perpendicular to the reference plane.

10. The semiconductor structure according to claim 1, characterized in that, Also includes: A word line isolation structure extends through the first stacked structure; The word line isolation structure extends along the fourth direction to divide the word line layer into multiple word lines; The fourth direction is parallel to the reference plane, which is the plane containing the lower surface of the first stacked structure.

11. The semiconductor structure according to claim 1, characterized in that, Also includes: The second stacking structure is located on top of the first stacking structure; The second stacked structure includes at least one select gate layer and at least one second dielectric layer; A channel structure extends through the second stacked structure; the channel structure includes a channel layer electrically connected to the conductive layer, and the channel layer is configured as a connection bit line.

12. A method for fabricating a semiconductor structure, characterized in that, include: Forming the first stacked structure; The first stacked structure includes multiple alternating first dielectric layers and multiple word line layers; A phase change layer and a memory structure extending through the first stacked structure are formed; the memory structure includes a ferromagnetic free layer, a tunneling layer, a ferromagnetic pinning layer, and a conductive layer, wherein the ferromagnetic free layer is located between the tunneling layer and the first stacked structure, the tunneling layer is located between the ferromagnetic free layer and the ferromagnetic pinning layer, the ferromagnetic pinning layer is located between the tunneling layer and the conductive layer, and the conductive layer is located on the side of the ferromagnetic pinning layer away from the tunneling layer; the phase change layer is at least partially located between the word line layer and the ferromagnetic free layer, and the phase change layer is coupled to the word line layer and the ferromagnetic free layer; the memory structure further includes an antiferromagnetic layer located between the conductive layer and the ferromagnetic pinning layer.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, The memory structure forming the phase change layer and penetrating the first stacked structure includes: An initial channel hole is formed that penetrates the first stacked structure; the orthographic projection of the initial channel hole onto a reference plane is a rectangle, and the reference plane is the plane containing the lower surface of the first stacked structure; A phase change layer is formed within the initial channel aperture; the phase change layer covers the surface of the word line layer exposed by the initial channel aperture; An initial storage structure is formed within the initial channel hole; the initial storage structure includes an initial ferromagnetic free layer, an initial tunneling layer, an initial ferromagnetic pinning layer, and an initial conductive layer, and the initial storage structure forms a first void within the initial channel hole; the orthographic projection of the initial storage structure onto the reference plane is rectangular, and includes two opposing first sides and two opposing second sides; A first filling layer is formed within the first gap; Multiple isolation slots are formed that penetrate the first stacked structure. The multiple isolation slots are arranged sequentially at intervals along the extension direction of the first side. In the orthographic projection onto the reference plane, the two outermost isolation slots at both ends of the multiple isolation slots respectively cover the two second sides of the initial storage structure. The multiple isolation slots divide the initial storage structure into multiple storage structures. A second filling layer is formed within the plurality of isolation grooves; the first filling layer and the second filling layer are connected to form a channel isolation structure.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, The formation of a phase change layer within the initial channel aperture includes: The edge portion of the word line layer near the initial channel hole is removed through the initial channel hole, so that the boundary of the word line layer near the initial channel hole is recessed inward in a direction away from the initial channel hole compared to the boundary of the first dielectric layer near the initial channel hole, forming a groove; A phase change layer is formed within the groove.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, The formation of the first filling layer includes: A first filling film is formed; the first filling film covers the inner wall of the first void and the upper side of the first stacked structure; Remove the portion of the first filler film covering the upper side of the first stacked structure.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that, The process of forming an initial storage structure within the initial channel aperture includes: An initial ferromagnetic free layer is formed within the groove; the phase transition layer is located between the ferromagnetic free layer and the word line layer; A tunneling film, a ferromagnetic anchoring film, and a conductive film are formed sequentially; the tunneling film, the ferromagnetic anchoring film, and the conductive film cover the inner wall of the initial channel hole and the upper side of the first stacked structure. During the process of removing the portion of the first filling film covering the upper side of the first stacked structure, the portions of the tunneling film, the ferromagnetic pinning film, and the conductive film covering the upper side of the first stacked structure are also removed.

17. The method for preparing a semiconductor structure according to claim 16, characterized in that, The formation of the initial ferromagnetic free layer includes: A ferromagnetic free film is formed; the ferromagnetic free film fills the groove and covers the inner wall of the initial channel hole and the upper side of the first stacked structure; Remove the portion of the ferromagnetic free film covering the inner wall of the initial channel hole and the upper side of the first stacked structure to form an initial ferromagnetic free layer.

18. The method for preparing a semiconductor structure according to claim 16, characterized in that, The storage structure further includes an antiferromagnetic layer. Between the formation of the ferromagnetic pinning film and the conductive film, the sequential formation of the tunneling film, the ferromagnetic pinning film, and the conductive film further includes: An antiferromagnetic thin film is formed; the antiferromagnetic thin film covers the inner wall of the initial channel hole and the upper side of the first stacked structure; During the process of removing the portions of the tunneling film, the ferromagnetic pinning film, and the conductive film that cover the first stacked structure, the portion of the antiferromagnetic film that covers the upper side of the first stacked structure is also removed.

19. The method for preparing a semiconductor structure according to claim 13, characterized in that, The plurality of isolation trenches forming the first stacked structure include: A mask layer is formed; the mask layer includes multiple cutout areas, which are arranged sequentially at intervals along the extension direction of the first side, and in the orthographic projection onto the reference surface, the two outermost cutout areas at both ends of the multiple cutout areas expose the two second sides of the initial storage structure respectively. The initial storage structure is etched based on the mask layer to form multiple isolation trenches.

20. A method for fabricating a semiconductor structure, characterized in that, include: Forming the initial stacking structure; The initial stacked structure includes multiple alternating first dielectric layers and multiple sacrificial layers; A storage structure is formed that extends through the initial stacked structure; the storage structure includes a ferromagnetic free layer, a tunneling layer, a ferromagnetic pinning layer, and a conductive layer; Forming word line gaps that penetrate the initial stacked structure; By removing the sacrificial layer through the word line gap, a word line cavity is formed; A phase change layer and a word line layer are sequentially formed within the word line cavity; The phase change layer is located between the word line layer and the two first dielectric layers adjacent to the word line layer, and between the word line layer and the memory structure. The phase change layer is coupled to the word line layer and the ferromagnetic free layer.

21. The method for preparing a semiconductor structure according to claim 20, characterized in that, The storage structure forming the initial stacked structure includes: A first channel hole is formed through the initial stacked structure; A ferromagnetic free film, a tunneling film, a ferromagnetic pinning film, and a conductive film are formed sequentially; the ferromagnetic free film, the tunneling film, the ferromagnetic pinning film, and the conductive film cover the inner wall of the first channel hole and the upper part of the initial stacked structure. Remove the portions of the ferromagnetic free film, the tunneling film, the ferromagnetic pinning film, and the conductive film that cover the upper side of the initial stacked structure.

22. The method for preparing a semiconductor structure according to claim 21, characterized in that, The storage structure further includes an antiferromagnetic layer, between the formation of the ferromagnetic pinning film and the conductive film, the storage structure forming through the initial stacked structure further includes: Formation of an antiferromagnetic thin film; During the process of removing the portions of the ferromagnetic free film, the tunneling film, the ferromagnetic pinning film, and the conductive film that cover the upper side of the initial stacked structure, the portion of the antiferromagnetic film that covers the upper side of the initial stacked structure is also removed.

23. A three-dimensional memory, characterized in that, include: A semiconductor structure, wherein the semiconductor structure is the semiconductor structure as described in any one of claims 1 to 11; Peripheral devices are electrically connected to the semiconductor structure.

24. A storage system, characterized in that, It includes a controller and a three-dimensional memory as described in claim 23, wherein the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

25. An electronic device, characterized in that, Including the storage system as described in claim 24.

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