A method of manufacturing a semiconductor device

Abstract

A method for fabricating a semiconductor device is disclosed. The method includes forming a magnetic tunneling junction (MTJ) on a substrate, forming a first intermetal dielectric layer on the MTJ, removing portions of the first intermetal dielectric layer to form a damaged layer directly above the MTJ and a recess exposing the damaged layer, performing an ultraviolet light curing process on the damaged layer, and performing a planarization process to remove the damaged layer and portions of the first intermetal dielectric layer.

Description

TECHNICAL FIELD

[0001] The present application relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a magnetoresistive random access memory (MRAM) device. BACKGROUND

[0002] It is known that the magnetoresistance (MR) effect is an effect in which the resistance of a material changes with the application of a magnetic field. The physical quantity is defined as the difference in resistance with and without a magnetic field divided by the original resistance, and is used to represent the rate of change in resistance. At present, the magnetoresistance effect has been successfully applied in the production of hard disks, and has important commercial application value. In addition, using the characteristic that the giant magnetoresistance material has different resistance values in different magnetization states, a magnetic random access memory (MRAM) can also be made, which has the advantage of being able to continue to retain stored data without power.

[0003] The magnetoresistance effect described above is also applied in the field of magnetic field sensors, for example, an electronic compass component for mobile phones that is matched with a global positioning system (GPS) to provide the user with information about the direction of movement. At present, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned prior art usually include: occupying a large chip area, expensive manufacturing process, high power consumption, insufficient sensitivity, and being easily affected by temperature changes, etc., and it is necessary to further improve. SUMMARY

[0004] One embodiment of the present application discloses a method for fabricating a semiconductor device, which mainly forms a magnetic tunneling junction (MTJ) on a substrate, then forms a first intermetallic dielectric layer on the MTJ, removes part of the first intermetallic dielectric layer to form a damaged layer directly above the MTJ and a recess to expose the damaged layer, performs an ultraviolet light curing fabrication process on the damaged layer, and then performs a planarization fabrication process to remove the damaged layer and part of the first intermetallic dielectric layer. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figures 1 to 10 A schematic diagram of a method for fabricating an MRAM device according to one embodiment of the present application.

[0006] Explanation of main element symbols

[0007] 12: substrate

[0008] 14: MRAM region

[0009] 16: logic region

[0010] 18: interlayer dielectric layer

[0011] 20: metal interconnect structure

[0012] 22: metal interconnect structure

[0013] 24: intermetal dielectric layer

[0014] 26: metal interconnect

[0015] 28: stop layer

[0016] 30: intermetal dielectric layer

[0017] 32: metal interconnect

[0018] 34: barrier layer

[0019] 36: metal layer

[0020] 38: MTJ stack structure

[0021] 42: lower electrode

[0022] 44: fixed layer

[0023] 46: barrier layer

[0024] 48: free layer

[0025] 50: upper electrode

[0026] 52: MTJ

[0027] 56: capping layer

[0028] 58: protective layer

[0029] 62: intermetal dielectric layer

[0030] 70: metal interconnect

[0031] 72: stop layer

[0032] 74: intermetal dielectric layer

[0033] 76: metal interconnect

[0034] 78: stop layer

[0035] 82: reflective layer

[0036] 84: patterned mask

[0037] 86: recess

[0038] 88: damaged layer

[0039] 90: ultraviolet light curing fabrication process DETAILED DESCRIPTION

[0040] Reference will now be made to Figures 1 to 10 , Figures 1 to 10 FIG. 1 is a schematic diagram of a method for fabricating an MRAM element according to an embodiment of the present application. As shown in FIG. 1, a substrate 12, such as a substrate 12 formed of a semiconductor material selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., is first provided, wherein the substrate 12 preferably defines an MRAM region 14 and a logic region 16 thereon. Figure 1

[0041] The substrate 12 can include active (active) elements such as metal-oxide semiconductor (MOS) transistors, passive (passive) elements, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 18 thereon. More specifically, the substrate 12 can include planar or non-planar (e.g., fin-type transistors) MOS transistor elements, wherein the MOS transistors can include gate structures (e.g., metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, etc., and the interlayer dielectric 18 can be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric 18 can have a plurality of contact plugs electrically connected to the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes related to planar or non-planar transistors and interlayer dielectric are well known in the art, they will not be described here.

[0042] Then, metal interconnect structures 20, 22 are formed on the interlayer dielectric 18 to electrically connect the aforementioned contact plugs in sequence, wherein the metal interconnect structure 20 includes an intermetal dielectric layer 24 and a metal interconnect 26 embedded in the intermetal dielectric layer 24, and the metal interconnect structure 22 includes a stop layer 28, an intermetal dielectric layer 30, and a metal interconnect 32 embedded in the stop layer 28 and the intermetal dielectric layer 30.

[0043] ​In this embodiment, each metal interconnect 26 in metal interconnect structure 20 preferably comprises a trench conductor, and each metal interconnect 32 in metal interconnect structure 22 disposed in MRAM region 14 comprises a via conductor. In addition, each metal interconnect 26, 32 in each metal interconnect structure 20, 22 can be embedded in intermetal dielectric layer 24, 30 and / or stop layer 28 and electrically connected to each other according to a single damascene process or a dual damascene process. For example, each metal interconnect 26, 32 can further comprise a barrier layer 34 and a metal layer 36, wherein barrier layer 34 can be selected from a group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and metal layer 36 can be selected from a group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), and the like, but not limited thereto. Since the single damascene or dual damascene process is well known in the art, no further elaboration is provided herein. In addition, metal layer 36 in metal interconnect 26 preferably comprises copper, metal layer 36 in metal interconnect 32 preferably comprises tungsten, intermetal dielectric layer 24, 30 preferably comprises silicon oxide such as tetraethyl orthosilicate (TEOS), and stop layer 28 comprises a nitrogen doped carbide (NDC) layer, silicon nitride, or silicon carbon nitride (SiCN), but not limited thereto.

[0044] Next, a lower electrode 42, an MTJ stack structure 38, an upper electrode 50, and a patterned mask (not shown) are formed on the metal interconnect structure 22. In this embodiment, the MTJ stack structure 38 can be formed by first sequentially forming a pinned layer 44, a barrier layer 46, and a free layer 48 on the lower electrode 42. In this embodiment, the lower electrode 42 and the upper electrode 50 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer 44 may contain ferromagnetic materials such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), and cobalt (Co). Furthermore, the fixing layer 44 can also be made of an antiferromagnetic (AFM) material, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer 46 can be made of an insulating material containing oxides, such as aluminum oxide (AlO). x The free layer 48 can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer 48 can be "freely" changed by an external magnetic field.

[0045] Subsequently, as Figure 2 As shown, a patterned mask is used as the mask to perform one or more etching processes to remove a portion of the upper electrode 50, a portion of the MTJ stack structure 38, a portion of the lower electrode 42, and a portion of the intermetallic dielectric layer 30 to form multiple MTJs 52 in the MRAM region 14. It is worth noting that the etching process performed on the patterned upper electrode 50, MTJ stack structure 38, lower electrode 42, and intermetallic dielectric layer 30 in this embodiment may include reactive ion etching (RIE) and / or ion beam etching (IBE). Due to the characteristics of the ion beam etching process, the remaining upper surface of the intermetallic dielectric layer 30 is preferably slightly lower than the upper surface of the metal interconnect 32, and the upper surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface. It should also be noted that when removing part of the intermetallic dielectric layer 30 using the ion beam etching process in this embodiment, it is preferable to remove part of the metal interconnects 32 at the same time, so that the metal interconnects 32 form an inclined sidewall near the junction of MTJ 52.

[0046] A masking layer 56 is then formed on the MTJ 52 and covers the surface of the inter-metal dielectric layer 30 of the MRAM region 14 and the logic region 16. In this embodiment, the masking layer 56 preferably comprises silicon nitride, but other dielectric materials such as, but not limited to, silicon oxide, silicon oxynitride, or silicon carbide may be selected according to the fabrication process requirements.

[0047] Then as Figure 3 As shown, an atomic layer deposition (ALD) process is first performed to form a protective layer 58 covering each MTJ 52 and the intermetallic dielectric layer 30 of the logic region 16. An etch-back process is then performed to remove a portion of the protective layer 58 between the MRAM region 14 and the logic region 16, creating a V-shape on the top surface of the protective layer 58 between the two upper electrodes 50. Finally, another photolithography and etching process is used to remove the protective layer 58, the masking layer 62, and a portion of the intermetallic dielectric layer 30 of the logic region 16. In this embodiment, the protective layer 58 preferably comprises silicon oxide, but is not limited to this.

[0048] In this embodiment, after removing part of the protective layer 58 using the aforementioned etching process, the top surface of the remaining protective layer 58 is preferably higher than the top surfaces of the two upper electrodes 50 by a distance, for example, about 300-500 angstroms, and simultaneously forms a V-shape on the top surface of the protective layer 58 in the MRAM region 14. The V-shape is preferably located between the two MTJs 52 and the two upper electrodes 50, the valley point of the V-shape is higher than the top surface of the upper electrodes 50, and the angle of the V-shape is preferably greater than 110 degrees or more preferably greater than 120 degrees.

[0049] Subsequently, as Figure 4 As shown, an intermetallic dielectric layer 62 is first formed on the protective layer 58 using a process such as flowable chemical vapor deposition (FCVD). In this embodiment, the intermetallic dielectric layer 62 preferably comprises an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, for example, but not limited to silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH). It should be noted that after the formation of the intermetallic dielectric layer 62 in this stage, the top of the intermetallic dielectric layer 62 of the logic region 16 is preferably lower than the top of the intermetallic dielectric layer 62 of the MRAM region 14, creating a significant height difference between the two.

[0050] like Figure 5 As shown, a reflective layer 82 is first formed on the surface of the intermetallic dielectric layer 62 between the MRAM region 14 and the logic region 16. Then, a patterned mask 84, such as a patterned photoresist, is formed on the reflective layer 82, wherein the patterned mask 84 has an opening exposing the surface of the reflective layer 82. In this embodiment, the reflective layer 82 preferably comprises a metal or a metal nitride, such as tantalum or tantalum nitride, but is not limited thereto.

[0051] like Figure 6 As shown, an etching process is then performed using a patterned mask 84 as a mask to remove part of the reflective layer 82 and part of the intermetallic dielectric layer 62 to form a groove 86, and then the patterned mask 84 is removed. It is worth noting that when removing part of the reflective layer 82 and part of the intermetallic dielectric layer 62 by etching in this stage, it is preferable to change the texture of the intermetallic dielectric layer 62 to form a damaged layer 88 and expose the surface of the damaged layer 88 in the groove 86.

[0052] Subsequently, as Figure 7 As shown, a UV curing process 90 is performed to remove the methyl (CH3) bonds in the damaged layer 88 and simultaneously harden the damaged layer 88 slightly. This prevents the area of ​​the damaged layer 88 from collapsing during the subsequent grinding process and allows for the even removal of the dielectric layer 62 between the damaged layer 88 and the surrounding metal.

[0053] Then as Figure 8 As shown, a planarization process is performed, for example, by using chemical mechanical polishing (CMP) to remove all reflective layers 82, all damaged layers 88, and part of the intermetallic dielectric layer 62 of MRAM region 14 and logic region 16, so that the top of the intermetallic dielectric layer 62 of MRAM region 14 and logic region 16 is approximately flush.

[0054] Then as Figure 9 As shown, a pattern transfer fabrication process is performed, for example, by using a patterned mask (not shown) to remove part of the intermetallic dielectric layer 62, part of the intermetallic dielectric layer 30, and part of the stop layer 28 of the logic region 16 to form contact holes (not shown) and expose the underlying metal interconnects 26. Then, the contact holes are filled with the desired conductive material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or combinations thereof. Next, a planarization fabrication process is performed, for example, by chemical mechanical polishing to remove part of the metal material to form contact plugs or metal interconnects 70 that electrically connect the metal interconnects 26 within the contact holes.

[0055] Subsequently, as Figure 10As shown, a stop layer 72 is first formed on the MRAM region 14 and the logic region 16 and covers the inter-metal dielectric layer 62 and the metal interconnect 70, an inter-metal dielectric layer 74 is formed on the stop layer 72, and one or more photolithography and etching fabrication processes are performed to remove portions of the inter-metal dielectric layer 74, portions of the stop layer 72, portions of the inter-metal dielectric layer 62, portions of the protective layer 58, and portions of the masking layer 56 in the MRAM region 14 and the logic region 16 to form contact holes (not shown). Then, conductive material is filled into the contact holes and a planarization fabrication process such as CMP is performed to form metal interconnects 76 in the MRAM region 14 and the logic region 16, respectively, to connect the underlying MTJ 52 and the metal interconnect 70, wherein the metal interconnects 76 in the MRAM region 14 preferably directly contact the underlying upper electrode 50, and the metal interconnects 76 in the logic region 16 contact the underlying metal interconnect 70. Then, another stop layer 78 is formed on the inter-metal dielectric layer 70 and covers the metal interconnects 76.

[0056] In this embodiment, the stop layer 72 and the stop layer 78 can comprise the same or different materials, which can be selected from the group consisting of a nitrogen doped carbide (NDC) layer, a silicon nitride layer, and a silicon carbon nitride (SiCN) layer. Like the metal interconnects formed as described above, the metal interconnects 76 formed in the inter-metal dielectric layer 74 can be embedded in the inter-metal dielectric layer 74 according to a single damascene fabrication process or a dual damascene fabrication process. For example, the metal interconnects 76 can further comprise a barrier layer and a metal layer, wherein the barrier layer can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), etc., but not limited thereto. Since the single damascene or dual damascene fabrication process is well known in the art, no further description is provided herein. Thus, the fabrication of the semiconductor device according to this embodiment is completed.

[0057] In summary, according to the present application, at least one MTJ is first formed on a substrate, then an inter-metal dielectric layer is formed to cover the MTJ, and an etching process is performed to remove portions of the inter-metal dielectric layer and form a damaged layer on the top of the MTJ and a recess to expose the surface of the damaged layer. Then, an ultraviolet curing fabrication process is performed to slightly harden the damaged layer. Thus, when a planarization fabrication process is performed to remove the damaged layer and the surrounding inter-metal dielectric layer, the area of the damaged layer will not collapse, and the top surface of the inter-metal dielectric layer in the MRAM region and the logic region will not have a large height difference.

[0058] The above merely describes the preferred embodiments of the present application, and any equivalent changes and modifications made according to the application scope of claims should be within the scope of the present application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, Comprising: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first intermetal dielectric layer on the magnetic tunneling junction; removing portions of the first intermetal dielectric layer to form a damaged layer and a recess on the magnetic tunneling junction, the recess exposing the damaged layer; and performing an ultraviolet light cure fabrication process on the damaged layer.

2. The method of claim 1, wherein the substrate comprises a magnetoresistive random access memory (MRAM) region and a logic region, the method comprising: forming a second intermetal dielectric layer on the substrate; forming a first metal interconnect on the magnetoresistive random access memory region and a second metal interconnect on the logic region; forming the magnetic tunneling junction on the first metal interconnect; forming a capping layer on the magnetic tunneling junction; and forming the first intermetal dielectric layer on the capping layer.

3. The method of claim 2, further comprising: forming a reflective layer on the first intermetal dielectric layer; and removing the reflective layer and the first intermetal dielectric layer to form the recess.

4. The method of claim 2, wherein a top surface of the first intermetal dielectric layer of the logic region is lower than a top surface of the first intermetal dielectric layer of the magnetoresistive random access memory region.

5. The method of claim 1, further comprising planarizing the first intermetal dielectric layer after performing the ultraviolet light cure fabrication process.

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