Inserting a proxy read instruction in an instruction pipeline in a processor

Abstract

It is disclosed to insert a proxy read instruction in an instruction pipeline of a processor. A scheduler circuit is configured to identify when a produced value generated by execution of a producer instruction in the instruction pipeline will not be available through a data forwarding path for processing a subsequent consumer instruction. In that case, the scheduling circuit is configured to insert a proxy read instruction in the instruction pipeline to cause execution of an operation to generate the same produced value as generated by a previous execution of the producer instruction in the instruction pipeline. Thus, the produced value will remain available in the instruction pipeline to be made available again through the data forwarding path to an earlier stage of the instruction pipeline for consumption by the consumer instruction, which can avoid a pipeline stall.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Patent Application Serial No. 16 / 983445, filed August 3, 2020, entitled “INSERTING APROXY READINSTRUCTION IN AN INSTRUCTION PIPELINE IN A PROCESSOR”, which is incorporated herein by reference in its entirety. Technical Field

[0003] The techniques disclosed herein generally relate to processing instructions in an instruction pipeline within a central processing unit (CPU), and more specifically to forwarding producer data generated by the execution of producer instructions to an earlier stage in the instruction pipeline for consumption by its consumer instructions. Background Technology

[0004] Microprocessors perform computational tasks in a wide variety of applications. A typical microprocessor includes one or more Central Processing Units (CPUs). A CPU includes one or more processor cores, each executing software instructions that instruct the processor to fetch data from a location in memory, perform one or more processor operations using the fetched data, and generate stored results in memory. A processor may include one or more instruction pipelines, also known as "instruction paths," for processing instructions. Instruction pipelining is a processing technique that increases the throughput of computer instructions executed by a processor. In this respect, the processing of each instruction is broken down into a series of steps, rather than each instruction being processed sequentially and fully executed before processing the next instruction. These steps are executed in an instruction pipeline consisting of multiple stages. As an instruction flows through the various pipeline stages, there are multiple cycles between the time it takes to fetch an instruction from memory and the time it takes to actually execute that instruction. A processor may also have multiple instruction pipelines to parallelize instruction processing.

[0005] Optimal processor performance can be achieved if all stages in the instruction pipeline can process instructions simultaneously and sequentially as they are inserted into the pipeline. However, dangers can arise in the instruction pipeline that prevent the execution of the next instruction without leading to erroneous computation results. One type of danger is the read-after-write (RAW) danger. The RAW danger occurs when an instruction needs (i.e., consumes) the result of a previously issued but incomplete instruction. For example, if a series of multiply-accumulate (MAC) instructions with the same destination (i.e., target) are processed in the instruction stream of the instruction pipeline, the produced value from a previous MAC instruction (as a producer instruction) is used as the source value for a subsequent MAC instruction (as a consumer). If the previous MAC instruction has not completed execution, the source value for the subsequent MAC instruction will not be updated, and the subsequent MAC instruction will use a previously stored, potentially incorrect, source value as its source. To mitigate the RAW danger, the scheduler circuitry in the instruction pipeline can stall consumer instructions until their producer instructions are fully executed, thus avoiding the RAW danger, but at the cost of reduced instruction throughput.

[0006] To avoid or reduce instruction pipeline stalls, instruction pipelines can be configured with circuitry to enable data forwarding. Data forwarding is a mechanism in the instruction pipeline where a produced value from a producer instruction, committed but not yet written to the register file, is forwarded to an earlier stage of the instruction pipeline for consumption by subsequent consumer instructions. The register file in a processor is a hardware circuitry element comprising an array of registers, each configured to store a value. Registers in the register file can be physical or logical registers and can be dynamically renamed when invoked in a processing instruction. In this way, a produced value can be readily available for consumption by a consumer instruction even if it has not yet been written to the register file and is already available there, without stalling the consumer instruction in the instruction pipeline. For example, the instruction set architecture (ISA) supported by the processor may include MAC instructions, which support naming two vector sources to be multiplied together and the target to be accumulated according to the format Vx+=op(Vu,Vv). In this example, Vu and Vv identify the source vector registers used for two source vectors to be multiplied together and accumulated with the third vector register in the third source vector register Vx. The third source vector register Vx is also the destination register used to store the accumulated vector result. Therefore, the execution stage of an instruction pipeline with data forwarding capability can support the execution of multiple MAC instructions with the same destination in the instruction data stream processed in the instruction pipeline with only two register read input ports. The two read input ports can be used to access the vectors in the source vector registers Vu and Vv. Data forwarding can be used to forward the accumulated destination vector from the vector destination of a previous MAC instruction executed in the instruction pipeline as the input vector to a subsequent MAC instruction executed in the instruction pipeline.

[0007] However, in this example, if the previous MAC instruction has already written the accumulated target vector to the register file before a subsequent MAC instruction with the same destination as the previous MAC instruction is ready to consume the target vector, data forwarding cannot be used to forward the target vector generated by the previous MAC instruction as input to the subsequent MAC instruction. In this case, the target vector must be read from the register file when executing the subsequent MAC instruction. However, if the execution stage of the instruction pipeline only has two input read ports, it is not possible to read two named multiplication source inputs and accumulation source inputs simultaneously because there are not three (3) input ports available. To avoid expanding the number of read input ports (which could increase the circuitry area in the instruction pipeline), MAC instructions can be processed in two separate instruction pipelines so that a total of four (4) read input ports are available. However, this technique consumes throughput in an additional instruction pipeline that could otherwise be used to process other instructions. Summary of the Invention

[0008] The aspects disclosed herein include inserting proxy fetch instructions into the instruction pipeline of a processor. The insertion of proxy fetch instructions can maintain produced values ​​in the instruction pipeline for consumption. A processor is provided that includes instruction processing circuitry comprising one or more instruction pipelines, each including multiple instruction processing stages configured to pipeline and execute fetched instructions. Scheduler circuitry is included in the instruction processing circuitry of the scheduling stage to schedule the issuance of instructions to be executed in its instruction pipeline. The executed instructions include producer instructions that cause execution circuitry in the execution stage of the instruction pipeline to generate produced values. The executed instructions also include consumer instructions that consume these produced values ​​upon execution. The produced values ​​can be written back to memory (such as a register file) via write-back circuitry in a write-back stage of the instruction pipeline for access by subsequent processing instructions. The instruction pipeline(s) may include a data forwarding mechanism that forwards produced values ​​from producer instructions that have been committed but not yet written to a register file to an earlier stage of the instruction pipeline for consumption by subsequent consumer instructions. However, if the generated value is generated too early in the instruction pipeline before it is ready to be consumed by the processing of the consumer instruction, it may cause the pipeline to stall in order to retrieve the generated value from the register file later when the consumer instruction is being processed.

[0009] In an exemplary aspect disclosed herein, to avoid pipeline stalls, the scheduler circuitry in the instruction pipeline is configured to identify when a produced value generated by the execution of a producer instruction in the instruction pipeline will no longer be available for consumption by subsequent consumer instructions via the data forwarding path. In this case, the scheduler circuitry is configured to insert a proxy fetch instruction into the instruction pipeline. The proxy fetch instruction causes the processor to perform an operation to generate the same produced value as that generated by a previous execution of a producer instruction in the instruction pipeline. Therefore, the produced value remains available in the instruction pipeline to be available again via the data forwarding path to earlier stages of the instruction pipeline for consumption by consumer instructions. In this way, the produced value is again available for consumption by consumer instructions without having to retrieve it from the register file when processing the consumer instruction. If the produced value generated by the execution of the producer instruction must be retrieved from the register file for consumption by the consumer instruction, it may cause a stall in the instruction pipeline, which is not necessary if the produced value is available via the data forwarding path.

[0010] The scheduler circuit can be configured to insert proxy fetch instructions as a forwarding mechanism into the instruction pipeline only for certain types of instructions known to have consumer instructions, which, depending on the desired design, may be fetched and inserted into the instruction pipeline within a given number of clock cycles. For example, the scheduler circuit can be configured to insert proxy fetch instructions as a forwarding mechanism into the instruction pipeline for multiply-accumulate (MAC) instructions. MAC instructions include a destination or target for storing a generated accumulated value, which can be the generated value and source for another MAC instruction with the same target. Some applications may have so many of these MAC instructions (closely following each other in the computer software program of the instructions to be executed) that inserting proxy fetch instructions for the accumulated value into the instruction pipeline can be advantageous if the accumulated value cannot yet be consumed by a subsequent MAC instruction. As another example, by providing the ability to insert proxy fetch instructions as a forwarding mechanism for generating values, the read input port in the execution phase of the instruction pipeline can be preserved. For example, if the execution phase has two (2) register read ports and the processing instruction, such as the MAC instruction, has three (3) source registers, one of which is also the destination / target register used to generate the value, the ability to insert a proxy read instruction to forward the accumulated value generation can avoid adding a third register read port to the execution phase, so that the instruction can be executed without causing pipeline stalls.

[0011] In this regard, in one exemplary aspect, a processor is provided. The processor includes a register file comprising a plurality of register entries, each register entry being associated with a physical register and configured to store a data value. The processor also includes instruction processing circuitry. The instruction processing circuitry includes fetch circuitry configured to fetch a plurality of instructions into an instruction pipeline within one or more instruction pipelines, the plurality of instructions including producer instructions and consumer instructions. Each of the one or more instruction pipelines includes execution circuitry configured to execute a producer instruction comprising at least one source register and a destination register to generate a produced value to be written to the destination register in the register file. The instruction processing circuitry also includes scheduler circuitry. The scheduler circuitry is configured to: receive a fetched consumer instruction comprising at least one source register (corresponding to the destination register of the producer instruction), and determine whether the produced value generated by the execution of the producer instruction will be forwarded in at least one data forwarding path in the instruction pipeline so that the source register in at least one source register available in the execution circuitry as a consumer instruction is consumed. In response to the determination that the source register whose generated value cannot be consumed as a consumer instruction in the instruction pipeline, the scheduler circuitry is configured to insert a proxy read instruction into the instruction pipeline, the proxy read instruction including the destination register storing the generated value.

[0012] In another exemplary aspect, a method is provided to provide produced data generated by the execution of producer instructions to consumer instructions in a processor. The method includes fetching a plurality of instructions into an instruction pipeline within one or more instruction pipelines, the plurality of instructions including producer instructions and consumer instructions. The method further includes executing a producer instruction including at least one source register and a destination register to generate a produced value to be written to a destination register in a register file, the register file including a plurality of register entries, each register entry associated with a physical register and configured to store a data value. The method further includes receiving a fetched consumer instruction, the fetched consumer instruction including at least one source register corresponding to the destination register of the producer instruction. The method further includes determining whether the produced value generated by the execution of the producer instruction will be forwarded in at least one data forwarding path in the instruction pipeline to be consumed by a source register in at least one source register available in the execution circuitry as a consumer instruction. The method further includes, in response to determining that the produced value cannot be consumed by a source register in the instruction pipeline as a consumer instruction, inserting a proxy read instruction into the instruction pipeline, the proxy read instruction including the destination register storing the produced value. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of an exemplary processor-based system including a central processing unit (CPU), which includes a scalar processor and a vector processor.

[0014] Figure 2 This is a schematic diagram of an exemplary instruction processing circuit, which may be included in... Figure 1 The CPU, in the processor, extracts and processes instructions for execution;

[0015] Figure 3 yes Figure 2 A schematic diagram showing additional details of an exemplary instruction pipeline in the instruction processing circuitry;

[0016] Figure 4 This is a schematic diagram of an exemplary instruction pipeline, which can be provided in... Figure 2 In the instruction processing circuit, the instruction processing circuit is configured to insert a proxy read instruction into the instruction pipeline for a generated value produced by the execution of a production instruction, which cannot be consumed by its consumer instruction through the data forwarding path;

[0017] Figure 5 Is Figure 4A diagram of an exemplary sequence of computer instructions extracted and processed in the instruction pipeline of the instruction processing circuitry, wherein the scheduler circuitry is configured to insert a proxy read instruction for a generated value produced by the execution of a production instruction that cannot be consumed by its consumer instruction via the data forwarding path;

[0018] Figure 6 This is a flowchart illustrating an exemplary process of a scheduler circuit configured to... Figure 4 Insert proxy read instructions into the instruction pipeline for the generated values ​​produced by the execution of production instructions, which cannot be consumed by their consumer instructions through the data forwarding path;

[0019] Figure 7 This is a schematic diagram of another exemplary instruction processing circuit, which includes multiple instruction pipelines and can be provided in... Figure 2 In the instruction processing circuitry, the instruction processing circuitry is configured to: insert, in one or more instruction pipelines within the instruction pipeline, a proxy read instruction for a generated value produced by the execution of a production instruction, which cannot be consumed by its consumer instruction via a data forwarding path; and

[0020] Figure 8 This is an exemplary block diagram of a processor-based system, which includes one or more CPUs, each of which includes a processor, the processor including instruction processing circuitry, and the instruction processing circuitry including one or more instruction pipelines (such as...). Figure 4 and Figure 7 (Instruction pipeline in the instruction pipeline), wherein each instruction processing circuit is configured to insert, in one or more instruction pipelines in the instruction pipeline, a proxy read instruction for a generated value produced by the execution of a production instruction, which cannot be consumed by its consumer instruction through the data forwarding path. Detailed Implementation

[0021] Several exemplary aspects of this disclosure are now described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0022] The aspects disclosed herein include inserting proxy fetch instructions into the instruction pipeline of a processor. The insertion of proxy fetch instructions can maintain produced values ​​in the instruction pipeline for consumption. A processor is provided that includes instruction processing circuitry comprising one or more instruction pipelines, each including multiple instruction processing stages configured to pipeline and execute fetched instructions. Scheduler circuitry is included in the instruction processing circuitry of the scheduling stage to schedule the issuance of instructions to be executed in its instruction pipeline. The executed instructions include producer instructions that cause execution circuitry in the execution stage of the instruction pipeline to generate produced values. The executed instructions also include consumer instructions that consume these produced values ​​when executed. The produced values ​​can be written back to memory (such as a register file) by write-back circuitry in the write-back stage of the instruction pipeline for access by subsequent processing instructions. Multiple instruction pipelines may include a data forwarding mechanism that forwards produced values ​​from producer instructions, which have been committed but not yet written to the register file, to an earlier stage of the instruction pipeline so that they are available for consumption by subsequent consumer instructions. However, if a produced value is generated too early in the instruction pipeline before it is ready to be consumed by the processing of a consumer instruction, it may cause the pipeline to stall in order to retrieve the produced value from the register file later when processing the consumer instruction.

[0023] In an exemplary aspect disclosed herein, to avoid pipeline stalls, the scheduler circuitry in the instruction pipeline is configured to identify when a produced value generated by the execution of a producer instruction in the instruction pipeline will no longer be consumed via the data forwarding path for processing subsequent consumer instructions. In this case, the scheduler circuitry is configured to insert a proxy fetch instruction into the instruction pipeline. The proxy fetch instruction causes the processor to perform an operation to generate the same produced value as that generated by the previous execution of the producer instruction in the instruction pipeline. Therefore, the produced value remains available in the instruction pipeline to be available again via the data forwarding path to earlier stages of the instruction pipeline for consumption by consumer instructions. In this way, the produced value is again available for processing as a consumer instruction, without having to retrieve it from the register file when processing the consumer instruction. If the produced value generated by the execution of the producer instruction must be retrieved from the register file for processing the consumer instruction, it may cause a stall in the instruction pipeline, which is not necessary if the produced value is available via the data forwarding path.

[0024] in this regard, Figure 1This is a schematic diagram of a central processing unit (CPU) 100, which includes an exemplary vector processor 102 and a scalar processor 104 (also referred to as a "scalar engine") 104. The CPU 100 may be provided in a semiconductor die 106. The vector processor 102 includes execution circuitry 108 and other specific exemplary circuitry and functions to provide vector processing operations, including exemplary vector processing operations. The vector processor 102 includes a programmable data path 110 between a vector register file 112 and the execution circuitry 108. The programmable data path 110 can be programmed to provide different programmable data path configurations. In this way, the programmable data path 110 between the execution circuitry 108 and the vector register file 112 in the vector processor 102 can be programmed and reprogrammed to provide different, specific types of vector processing operations in different operating modes without requiring a separate vector processor 102 within the CPU 100.

[0025] Continue to refer to Figure 1 Vector processor 102 includes a vector register file 112 configured to receive and store vector data 114 associated with vector registers from vector unit data memory 116. For example, vector data 114 is X bits wide, where 'X' is defined according to design choice (e.g., 512 bits). Vector data 114 can be divided into vector data sample sets 117. As a non-limiting example, vector data 114 can be 256 bits wide and can include smaller vector data sample sets 117(Y)-117(0). Vector processor 102 is capable of providing vector processing to certain selected vector data sample sets 117(Y)-117(0) that are provided in parallel to achieve a high degree of parallelism. Vector register file 112 includes registers configured to store results generated when vector processor 102 processes vector data 114. The vector processor 102 also includes a condition register 118, which is configured to provide conditions to the vector processor 102 for conditional execution of vector instructions and is configured to store updated conditions as a result of the execution of vector instructions.

[0026] Continue to refer to Figure 1The CPU 100 also includes a scalar processor 104 to provide scalar processing in addition to the vector processing provided by the vector processor 102. In this embodiment, as a non-limiting example, the scalar processor 104 is a 32-bit Reduced Instruction Set Computing (RISC) scalar processor. In this example, the scalar processor 104 includes an arithmetic logic unit (ALU) 128 for supporting scalar instruction processing. The scalar processor 104 also includes a general-purpose register (GPR) file 130 that stores data in registers for use by the scalar processor 104 when executing scalar instructions. An integer unit data memory 132 is included in the CPU 100 to provide data from the autonomous memory 133 to the GPR file 130 for access by the scalar processor 104 for scalar instruction execution. As a non-limiting example, the integer unit data memory 132 may be a cache memory.

[0027] Continue to refer to Figure 1 The CPU 100 includes an instruction dispatch circuit 134 configured to fetch an instruction 136 from an instruction memory 138, decode the fetched instruction 136, and, based on the instruction type, direct the decoded fetched instruction 136 to either the scalar processor 104 or the vector processor 102. The CPU 100 also includes a memory controller 140, which includes a memory controller register 142 configured to receive a memory address from the GPR heap 130 when the scalar processor 104 is executing a vector instruction that requires access to main memory via the memory controller data path 144.

[0028] Figure 2 This is a schematic diagram of an exemplary instruction processing circuit 200, which may be included in... Figure 1 In the CPU 100, the vector processor 102 and / or scalar processor 104 extract and process the extracted instructions 136 for execution. In this regard, the instruction extraction circuit 202 extracts the instructions from the vector processor 102 and / or scalar processor 104. Figure 1 Instruction memory 138, a portion of instruction dispatch circuitry 134, fetches instruction 136 as fetch instruction 136F. As an example, instruction memory 138 may be provided in main memory 133 of CPU 100 or may be provided as a portion of main memory 133. Figure 2As shown, an instruction cache 204 can also be provided in the CPU 100 to cache the fetched instruction 136F from the instruction memory 138, thereby reducing the latency of the instruction fetch circuit 202 fetching instruction 136F. The instruction processing circuit 200 also includes an instruction decoding circuit 206 configured to decode the fetched instruction 136F fetched by the instruction fetch circuit 202 into a decoded instruction 136D. The decoded instruction 136D can be analyzed to determine its instruction type and required action, which can then be used to determine which instruction pipeline I0-I should place the decoded instruction 136D in. N Furthermore, a control flow prediction circuit 208 is provided in the instruction processing circuit 200 to infer or predict the target address of the control flow instruction 136D (such as a conditional branch instruction).

[0029] Instruction fetch circuit 202 is configured to dispatch decoded instruction 136D to one or more instruction pipelines I0-I in instruction processing circuit 200. N The instruction is executed. The instruction processing circuit 200 processes the decoded instruction 136D before it reaches the execution circuit 212. Instruction pipeline I0-I is provided across different processing circuits or stages of the instruction processing circuit 200. N The decoded instruction 136D is preprocessed and processed in a series of steps before being executed in the execution circuit 212. These steps are performed concurrently to increase throughput.

[0030] Continue to refer to Figure 2 In this example, the decoded instruction 136D is placed in instruction pipeline I0-I of instruction processing circuit 200. N In one or more instruction pipelines. After identifying and arbitrating the readiness of instruction 136D with all its source operations ready, when decoded instruction 136D is ready (i.e., when its source operands are available), issuing circuit 224 dispatches the decoded instruction 136D to instruction pipeline I0-I in execution circuit 212. N In the instruction processing circuit 200, a write-back circuit 226 is also provided as a final stage. The write-back circuit 226 is configured to update the processor's architecture and memory state for the executed instruction 136D and to handle exceptions caused by the executed instruction 136D. The write-back circuit 226 can be configured to forward the generated data from the execution circuit 212 to the instruction pipeline I0-I in the instruction processing circuit 200. N An earlier stage in the process.

[0031] Figure 3 Is as Figure 2 The instruction pipeline I0-I in the instruction processing circuit 200 NAn example of a single instruction pipeline I in an instruction pipeline X Additional details are illustrated in the diagram to show instruction pipeline I. X An example of data forwarding in [the context]. Figure 3 Instruction Pipeline I X The instruction is not configured to insert a proxy read instruction for a produced value generated by the execution of a production instruction in one or more instruction pipelines within the instruction pipeline. This produced value cannot be consumed by its consumer instruction via the data forwarding path. Instruction Pipeline I X It can be Figure 2 The instruction pipeline I0-I in the instruction processing circuit 200 N Any instruction pipeline in the pipeline, and can be included in Figure 2 In the instruction dispatch circuit 134. Figure 2 The instruction pipeline I0-I in the instruction processing circuit 200 N Components and Figure 3 Instruction Pipeline I X Common elements among the components are shown using common element numbers and are not described further.

[0032] refer to Figure 3 Instruction Pipeline I XThe system includes an execution circuit 212, which includes an arithmetic logic unit (ALU) 302 configured to perform logical operations on three (3) input data 304(1)-304(3) and receive each input data 304(1)-304(3) from the corresponding output ports 306(1)-306(3) of the corresponding multiplexer circuits 308(1)-308(3). Each multiplexer circuit 308(1)-308(3) includes a corresponding input port 310(1)-310(3) configured to receive data stored in register Rx in register files 112 and 130. Register files 112 and 130 have three (3) register read ports 312(1)-312(3) for reading data stored in register Rx into execution circuit 212 as operands for the execution of instruction 136D. In this way, instruction 136D with three (3) source register operands can be executed based on the source data for all three (3) named source register operands retrieved from register files 112 and 130 in execution circuit 212 in one (1) beat operation. A beat is the amount of data that can be transferred from memory at one time based on the physical data bit width of the memory (i.e., the number of data pins). A memory burst data transfer is a continuous transfer of multi-beat data from memory based on a single addressing operation. Scheduler circuit 313 controls the dispatch of instruction 136D to execution circuit 212 for execution when instruction 136D is known to be ready for execution. For example, instruction 136D, including the source register operand, is not dispatched for execution until the data in the named source register operand is ready to be consumed. ALU 302 is configured to generate a produced value 314 on output port 316 based on the executed instruction 136D. Write-back circuitry 226 can write the produced value 314 back to the destination register Rx in register files 112, 130. In this way, the produced value 314 generated by the execution of producer instruction 136D can be retrieved for consumption by its consumer instruction 136D, which runs on instruction pipeline I. X Follow the producer instruction 136D.

[0033] Figure 3 Instruction Pipeline I X It also includes data forwarding capabilities. Instruction Pipeline I XThe route includes a path that allows execution circuit 212 and write-back circuit 226 to forward the generated value 314 produced according to the execution of producer instruction 136D to the input ports 320(1)-320(3) of the corresponding multiplexer circuits 308(1)-308(3) in execution circuit 212 via corresponding data forwarding paths 222(1), 222(2). Data forwarding paths 222(1), 222(2) are paths from which data can be forwarded from one stage of instruction processing circuit 300 to a previous stage. In this example, multiplexer circuits 308(1)-308(3) each include two (2) input ports 320(1)-320(3), each input port coupled to the corresponding data forwarding path 222(1), 222(2). In this way, the generated value 314 can be consumed by the subsequent consumer instruction 136D, which names the source register in which the generated value 314 is stored. Therefore, the generated value 314, which can be successfully forwarded in time to be consumed by the subsequent consumer instruction 136D during execution, does not need to be fetched from register files 112, 130 and / or instruction memory 138 to enable the consumer instruction 136 to be executed; otherwise, it would lead to instruction pipeline I... X The pause in the instruction pipeline and thus reduce the instruction pipeline I X The throughput. In the case of data forwarding, ALU 302 can behave as if any number of output ports 306(1)-306(3) were used as input ports. ALU 302 can treat three (3) output ports 306(1)-306(3) from the corresponding multiplexer circuits 308(1)-308(3) as three (3) input ports to read up to three (3) register data Rx from register files 112, 130. ALU 302 can also be configured to receive register data Rx only from fewer than all output ports 306(1)-306(3) and receive the generated value 314 as input data from another (some other) output port 306(1)-306(3) for transmission via instruction pipeline I. X The data forwarding capability is used to receive the generated value 314.

[0034] therefore, Figure 3 Instruction Pipeline I XIt is configured to execute instruction 136D with three (3) source register operands in one (1) cycle by register files 112 and 130 without pipeline stalling due to the three (3) register read ports 312(1)-312(3). An example of instruction 136D with three (3) source operands is the multiply-accumulate (MAC) instruction, with the instruction format Rw+=op(Ru, Rv). The data in registers Ru and Rv are two named source registers multiplied together and accumulated with a third source register operand Rw, which is also the destination register of instruction 136D. For this MAC instruction, the data stored in registers Ru, Rv, and Rw can be read and provided to ALU 302 through the three (3) register read ports 312(1)-312(3) and the associated multiplexer circuits 308(1)-308(3). The value 314 generated from the execution of the MAC instruction can be written back to register files 112, 130 by write-back circuit 226 via data forwarding path 222(2), and / or forwarded back to one of the multiplexer circuits 308(1)-308(3) as input data via data forwarding path 222(1).

[0035] Furthermore, as another example, instruction pipeline I X It can handle back-to-back MAC instructions, where the first MAC instruction is the producer of subsequent MAC instructions. For example, the named destination register of the first MAC instruction, which is the producer instruction, can be the source / destination register of the next MAC instruction, which is the consumer instruction. Figure 3 Instruction Pipeline I X Producer / consumer back-to-back MAC instructions can be executed without pipeline stalling. This is because the final accumulated value of the first executed producer MAC instruction can be forwarded to multiplexer circuits 308(1)-308(3) via data forwarding paths 222(1) and 222(2) to serve as the source for subsequent consumer MAC instructions. Therefore, for the second consumer MAC instruction, it is not necessary to obtain the final accumulated value of the first executed producer MAC instruction from register files 112 and 130. In other words, the final generated value of the first executed MAC instruction can be made available in time via data forwarding paths 222(1) and 222(2) for consumption by subsequent MAC instructions that name the target register of the first MAC instruction as the source register. For example, both the first MAC instruction and the subsequent MAC instruction can name the same target operand Rw as the source register and target register according to the instruction format discussed above.

[0036] Possible expectation reduction Figure 3Instruction Pipeline I X The number of register read ports 312(1)-312(3) in register files 112 and 130 is reduced to decrease the number of instruction pipeline I. X The complexity. For example, it may be desirable to reduce the number of register read ports 312(1)-312(3) to only two (2) read ports. For example, register read port 312(3) can be eliminated, and the multiplexer circuit 308(3) includes only two (2) input ports 320(3) from data forwarding paths 222(1) and 222(2). Figure 3 Instruction Pipeline I X An example of this modification is in Figure 4 Instruction Pipeline I Y It is shown in the diagram. Instruction Pipeline I Y It can be Figure 2 Instruction Pipeline I0-I N One of the instruction pipelines. As discussed in more detail below, to avoid the instruction pipeline I caused by the reduction in the number of available register read ports. Y Pipeline pauses can insert proxy read instructions into instruction pipeline I. Y In the instruction pipeline I, Y The mechanism for generating values ​​during forwarding. In this way, the generated value can be consumed by consumer instruction 136D via data forwarding paths 222(1), 222(2), instead of having to retrieve the generated value 314 written back by write-back circuit 226 from register files 112, 130.

[0037] Figure 4 The instruction processing circuit 400 in the middle includes similar to Figure 3 Instruction Pipeline I X Instruction Pipeline I Y Common components are indicated by common component numbers. However, Figure 4 Instruction Pipeline I Y It only includes two (2) register read ports 312(1) and 312(2), and does not include the third register read port 312(3). Therefore, in Figure 4 Instruction Pipeline I YIn this context, if one (1) of the three (3) source operands is obtained from data forwarding paths 222 (1) and 222 (2) when it is generated from the previously executed producer instruction 136D, then the input of the source data of the three (3) source operand instruction 136D can be processed in only one (1) clock cycle. Therefore, in the above example of back-to-back producer and consumer MAC instructions 136D, if the final generated value 314 from the execution of the first producer MAC instruction 136D can be forwarded through data forwarding paths 222 (1) and 222 (2) for consumption by the subsequent consumer MAC instruction 136D, then instruction pipeline I can be avoided. Y The pause in the middle.

[0038] However, if the source input of the subsequent consumer MAC instruction 136D is prematurely generated from the instruction pipeline I before it is ready to be fetched from register files 112 and 120... Y If the first producer MAC instruction 136D in the instruction pipeline ultimately produces the value 314, then subsequent consumer MAC instructions 136D will need to be executed in instruction pipeline I. Y A pause occurs. This is because the final produced value 314 from the execution of the first producer MAC instruction 136D will not be available through data forwarding paths 222(1), 222(2). The final produced value 314 will be written to register files 112, 130 by write-back circuitry 226 before it is ready to be consumed by subsequent consumer MAC instructions 136D. This is due to the elimination of instruction pipeline I. Y The third register read port 312(3) in the pipeline means that all three (3) source inputs from the three (3) named source registers of the subsequent consumer MAC instruction 136D cannot be retrieved in one (1) cycle. Therefore, the pipeline pause allows the subsequent consumer MAC instruction 136D to first retrieve two (2) source data from register read ports 312(1), 312(2) to multiply them together in one cycle as an intermediate generated value 314. Then, the intermediate generated value 314 can be forwarded through data forwarding paths 222(1), 222(2) to be consumed and accumulated in subsequent cycles along with the third source data received from register read ports 312(1), 312(2) to generate the final generated value 314 for the subsequent consumer MAC instruction 136D.

[0039] As described below, Figure 4 Instruction Pipeline I Y Configured to: when the generated value 314 cannot be forwarded to instruction pipeline I via data forwarding paths 222(1) and 222(2) Y In earlier stages of consumption, when consumer instructions are given for consumption of 136D, to avoid Figure 4Instruction Pipeline I Y The pause in the instruction pipeline. In this regard, the instruction processing circuit 400 includes a scheduler circuit 413, which is configured to: identify when the produced value 314 generated by the execution of the producer instruction 136D cannot be processed in the instruction pipeline I. Y The output value 314 from the execution of producer instruction 136D is consumed as a source of consumer instruction 136D. For example, as described above, the output value 314 from the execution of producer instruction 136D may be available too early in data forwarding paths 222(1), 222(2) and cannot be consumed by consumer instruction 136D. To avoid pipeline stalls in this case, in the example disclosed herein, scheduler circuit 413 is configured to: in instruction pipeline I Y Insert proxy read instruction 404 as part of instruction pipeline I Y The mechanism that generates value 314 during forwarding. Agent read instruction 404 causes... Figure 4 Instruction pipeline I in instruction processing circuit 400 Y Execute operations to perform operations in an earlier stage of the instruction pipeline I. Y The same generated value 314 is generated in instruction pipeline I to keep the generated value 314 in instruction pipeline I. Y In this way, the generated value 314 can be consumed by the consumer instruction 136D again through the data forwarding paths 222(1) and 222(2), instead of having to retrieve the generated value 314 written back by the write-back circuit 226 from the register files 112 and 130.

[0040] In addition to including the third multiplexer circuit 408(3), Figure 4 The instruction processing circuit 400 includes Figure 3 The two multiplexer circuits 308(1) and 308(2) are in the multiplexer circuit. The multiplexer circuit 408(3) does not include input port 310 from register files 112 and 130. However, the multiplexer circuit 408(3) includes two (2) input ports 320(3) and an output port 406(3) to ALU 302, each input port being coupled to a corresponding data forwarding path 222(1) and 222(2). In this way, the generated value 314 can be successfully forwarded as a third source data value by the multiplexer circuit 408(3) as data 405(3) to ALU 302 to execute consumer instruction 136D that consumes the generated value 134. As mentioned above, the multiplexer circuit 408(3) does not need to have input ports to register files 112 and 130 because the scheduler circuit 413 is configured to: in instruction pipeline I Y Insert proxy read instruction 404 as part of instruction pipeline I Y The mechanism that generates value 314 during forwarding. The execution of the proxy read instruction 404 occurs in instruction pipeline I. YThe generated value 314 is regenerated in the instruction pipeline. This generated value 314 can be forwarded to an earlier stage via data forwarding paths 222(1) and 222(2) and then forwarded to the multiplexer circuit 408(3) to keep the generated value 314 in the instruction pipeline I. Y Medium lasting.

[0041] Figure 5 It is possible Figure 4 Instruction pipeline I of instruction processing circuit 400 Y A diagram of an exemplary sequence of computer instructions 500 extracted and processed, wherein the agent reads the instructions. <pri>Inserted into instruction pipeline I Y In the middle. For example Figure 5 As shown, computer instruction 500 includes instructions I1 and I2. Instructions I1 and I2 are three (3) source operand MAC instructions, which have in the instruction pipeline I Y The same accumulator destination register R2 is assigned in the instruction pipeline, where instruction I1 is a producer MAC instruction for consumer MAC instruction I2. Y When the producer MAC instruction I1 is executed and the execution circuit 212 generates the generated value 314(2) of instruction I1 for the target register R2 in clock cycle 4 (CLK4), the execution circuit 212 forwards the generated value 314(1) in data forwarding paths 222(1) and 222(2). However, as Figure 5 As shown, before the second instruction I2 is ready to consume the source data of register R2, the generated value 314(1) is generated in instruction pipeline I. Y The instruction is forwarded prematurely. In this case, the scheduler circuit 413 in instruction pipeline I... Y A proxy read instruction PRI is inserted, which is executed to generate the same generated value 314(1) as the generated value 314(2) forwarded in data forwarding paths 222(1) and 222(2). When the second instruction I2 is ready to be executed, the generated value 314(2) forwarded in data forwarding paths 222(1) and 222(2) can be consumed. Therefore, instruction pipeline I is avoided. Y The pause in the middle.

[0042] For example, the surrogate read instruction PRI can be an instruction that behaves similarly to copying a value stored in a source register to a register that is the same as the destination register, similar to an instruction with the format Rx = COPY Rx, where 'Rx' is the source register and the destination register. Another example of the surrogate read instruction PRI is an instruction that moves a value stored in a source register to a register that is the same as the destination register, such as an instruction with the format Rx = MOVE Rx, where 'Rx' is the source register and the destination register. Yet another example of the surrogate read instruction PRI is an instruction that stores a value stored in a source register into a register that is the same as the destination register, such as an instruction with the format Rx = Rx, where 'Rx' is the source register and the destination register.

[0043] Figure 4 The scheduler circuit 413 in the instruction processing circuit 400 can be configured to: determine whether the generated value 314 will be executed in instruction pipeline I. Y The value 314 is forwarded to the execution circuit 212 so that it can be consumed in different ways as the source register Rx for the consumer instruction 136D. For example, the scheduler circuit 413 can be configured to determine whether the generated value 314 will be consumed in the instruction pipeline I by determining whether the generated value 314 is written back to the register files 112 and 130 by the write-back circuit 226 before the consumer instruction 136D is received in the scheduler circuit 413. Y The value 314 is forwarded to be consumed in execution circuit 212 as a source register for consumer instruction 136D. As another example, scheduler circuit 413 can be configured to determine whether the generated value 314 will be consumed in instruction pipeline I by determining whether it has been written back to register files 112, 130 before consumer instruction 136D is dispatched to execution circuit 212. Y The input is forwarded to be consumed in the execution circuit 212 as the source register Rx of the consumer instruction 136D.

[0044] Similarly, if instruction pipeline I Y Will generate by Figure 5 The value 314 generated by the execution of MAC instruction I1 (which is not ready (i.e., too late) for data forwarding when MAC instruction I2 arrives at execution circuit 212 for execution) then Figure 4 The scheduler circuit 413 in the instruction processing circuit 400 can also be configured to recognize this situation. For example, the scheduler circuit 413 can be configured to determine whether the produced value 314(1), generated by the execution of instruction I1 (as producer instruction 136D) and intended to be consumed as the source register Rx of instruction I2 (as consumer instruction 136D), is not ready to be forwarded in data forwarding paths 222(1), 222(2) to be consumed as the source register Rx of consumer instruction 136D. In this case, the scheduler circuit 412 can be configured to pause instruction pipeline I. Y The instruction I2 in the middle makes the value 314(1) available on data forwarding paths 222(1) and 222(2) so that it can be consumed when instruction I2 is executed.

[0045] Figure 6 It is a diagram. Figure 4 A flowchart of an exemplary process 600 of the scheduler circuit 413 in the instruction processing circuit 400, wherein process 600 is in instruction pipeline I Y A proxy read instruction is inserted, which is for the generated value 314 produced by the execution of the production instruction 136D that cannot be consumed by its consumer instruction 136D through data forwarding paths 222(1) and 222(2). Process 600 begins with the instruction processing circuit 400 fetching multiple instructions 136 into the instruction pipeline I. Y In this context, Directive 136 includes Producer Directive 136 and Consumer Directive 136. Figure 6 (See box 602 in the original text). Process 600 also includes executing the decoded producer instruction 136D (the decoded producer instruction 136D includes at least one source register R). X-S and target register R X-T This generates the target register R to be written into register files 112 and 130. X-T The generated value is 314. Register files 112 and 130 include multiple register entries, each associated with a physical register and configured to store a data value. Figure 6 (See box 604 in the original text). Process 600 also includes receiving the extracted consumer instruction 136F, which includes a target register R corresponding to the producer instruction 136D. X At least one source register R X ( Figure 2 (Box 606 in the diagram). Process 600 includes: scheduler circuit 413 determining whether the produced value 314 generated by the execution of producer instruction 136D will be added to instruction pipeline I. Y The data is forwarded in at least one data forwarding path 222(1), 222(2) to be available in execution circuit 212 as at least one source register R for consumer instruction 136F. X Source register R in X Consumed ( Figure 6 (See box 608 in the document). Process 600 further includes: in response to determining that the generated value 314 cannot be in instruction pipeline I... Y The source register R in the consumer instruction 136F is used as the source register. X Consumed, the scheduler circuit in instruction pipeline I Y Insert a PRI, which includes a destination register R that stores the value 314. X ( Figure 6 (Box 610 in the middle).

[0046] Figure 7 This is a schematic diagram of another exemplary instruction processing circuit 700, which includes multiple instruction pipelines I. Z (1) I Z (2) and can be provided in Figure 2 In the instruction processing circuit 200. As described below, the instruction processing circuit 700 includes a scheduler circuit 712, which is also configured to: in the instruction pipeline I Z (1) I Z In one or more instruction pipelines in (2), a proxy read instruction is inserted for the generated value produced by the execution of the production instruction. Without a proxy read instruction, the generated value cannot be used as the output value for its corresponding instruction pipeline I. Z (1) I Z The data forwarding value in (2) is consumed by its consumer instruction 136D.

[0047] like Figure 7 As shown, the instruction processing circuit 700 includes an instruction fetching circuit 704 in the fetch stage F1. The instruction fetching circuit 704 is used to fetch instruction 136 and is supplied by all instruction pipelines I. Z (1) I Z (2) Shared. Instruction fetch circuit 704 is configured to fetch instruction 136 as fetch instruction 136F. Scheduler circuit 712 is configured to: based on whether the decoded instruction 136D is identified as being in instruction pipeline I Z (1) I Z (2) contains an earlier producer instruction 136D, which allocates each extracted instruction 136D to the corresponding instruction pipeline I. Z (1) I Z (2) In, for example, the scheduler circuit 712 can assign the fetch instruction 136F, which is a consumer instruction, to the same instruction pipeline I as the producer instruction 136D it identifies. Z (1) I Z (2) so that the instruction pipeline I of this allocation Z (1) I Z The data forwarding mechanism in (2) can be used to receive generated values ​​to be consumed by consumer instructions. The instruction processing circuit 700 also includes each corresponding instruction pipeline I in the decoding stage D1. Z (1) I Z (2) The instruction decoding circuits 706(1) and 706(2) are configured to decode the extracted instruction 136F into the decoded instruction 136D so as to know the instruction type of each instruction.

[0048] Continue to refer to Figure 7 Each instruction pipeline I Z (1) I Z (2) Includes a common write-first-in-first-out (FIFO) buffer 708 in buffer stage P1 and a read FIFO buffer 710 in second buffer stage P2 to store corresponding read and write decoded instructions 136D awaiting dispatch for execution. For example, the write and read FIFO buffers 708, 710 can be reservation stations configured to hold read and write decoded instructions 136D until their corresponding source operands are ready, as determined by scheduler circuit 712. A wake-up signal 714 is generated and transmitted to scheduler circuit 712 to indicate when producer instruction 136D has been issued for execution. Scheduler circuit 712 can use this information to determine whether the read or write decoded instruction 136D in the write and read FIFO buffers 708, 710 is ready to be dispatched to its corresponding instruction pipeline I. Z (1) I Z (2) is executed. Instruction Pipeline I Z (1) I Z (2) Includes register stage R, which includes corresponding register read circuits 720(1) and 720(2). Each register read circuit is configured to read data from the register file of the two source operands for the instruction. This means that these instruction pipelines I Z (1) I Z (2) It has two (2) input ports from the register file.

[0049] Continue to refer to Figure 7 Specifically, instruction pipeline I Z (1) It is configured to perform MAC operations on MAC instructions. Therefore, in this example, any MAC instruction 136F that is fetched will be assigned to instruction pipeline I. Z (1). In this example, instruction pipeline I Z (1) Includes a first execution stage E1, which includes a multiplication and reduction circuit 726 configured to multiply two (2) source operands to be multiplied together, retrieved from the register file according to a register read operation in register stage R. Instruction Pipeline I Z (1) It also includes a 32-bit (32b) ALU 728 (1) in the second execution stage E2, which is configured to multiply the two (2) source operands retrieved from the register file according to the register read operation in the register stage R, and generate a produced value 732 (1). Instruction Pipeline I Z (1) It also includes a write-back circuit 734(1) in the write-back stage WB, which is configured to write the generated value 732(1) generated by ALU 728(1) back to the register file.

[0050] Continue to refer to Figure 7 Specifically, instruction pipeline I Z (2) It is configured to perform a shift operation. Therefore, in this example, any shift instruction 136F that is fetched will be assigned to instruction pipeline I. Z (2). In this example, instruction pipeline I Z (2) Includes a first execution stage E1, which includes a shift bit counter circuit 736 configured to perform a shift operation on data read from the register file in register stage R. Instruction Pipeline I Z (2) It also includes the 32b ALU 728(2) in the second execution stage E2, which is configured to perform logical operations on the two (2) source operands retrieved from the register file according to the register read operation in the register stage R, and generate the produced value 732(2). Instruction Pipeline I Z (2) It also includes a write-back circuit 734(2) in the write-back stage WB, which is configured to write the generated value 732(2) generated by ALU 728(2) back to the register file.

[0051] Continue to refer to Figure 7 Instruction Pipeline I Z (1) is shown as including data forwarding capabilities via data forwarding paths 740(1) and 740(2). Note that other instruction pipelines I Z (2) It may also include data forwarding paths 740(1) and 740(2). Instruction Pipeline I Z (1) The second execution phase E2 is configured to forward the produced value 732(1) generated by the execution of producer instruction 136D back to instruction pipeline I via either or both of data forwarding paths 740(1) and 740(2). Z (1) The corresponding first execution stage E1 and second execution stage E2. In this way, the generated value 732(1) can be consumed by the subsequent consumer instruction 136D in the first execution stage E1 and the second execution stage E2, which names the source register Rx to which the generated value 732(1) is allocated. Therefore, the generated value 732(1) that can be successfully forwarded in time in the first execution stage E1 and the second execution stage E2 for consumption by the subsequent consumer instruction 136D does not need to be fetched from the register file for the consumer instruction 136D to be executed, which would otherwise have caused the instruction pipeline I Z The pause in (1) and thus reduce the instruction pipeline I Z Throughput in (1).

[0052] However, if in instruction pipeline I Z In the first execution stage E1 and the second execution stage E2 of (1), if the generated value 732(1) cannot be successfully forwarded in time for consumption by the subsequent consumer instruction 136D, then the scheduler circuit 712 is configured to recognize this situation. In this case, the scheduler circuit 712 is configured to: in instruction pipeline I Z (1) Insert the proxy read instruction PRI as a queuing instruction in the instruction pipeline I. Z (1) regenerates the mechanism that produces the value 732(1), for example, as previously in Figure 4 Instruction Pipeline I Y The agent read command PRI is discussed in the document. Figure 7 Instruction pipeline I in instruction processing circuit 700 Z (1) Execute the operation to perform it at an earlier stage in the instruction pipeline I. Z The same generated value 732(1) is generated in (1). In this way, via data forwarding paths 740(1) and 740(2), the generated value 732(1) is made available again to consumer instruction 136D that was not previously ready to receive the generated value 732(1) for consumption, without the need for such generated value 732(1) to be stored and then retrieved from the register file when processing consumer instruction 136D.

[0053] A processor including instruction processing circuitry can be provided in or integrated into any processor-based device, the instruction processing circuitry including one or more instruction pipelines, such as... Figure 4 and Figure 7 The instruction pipeline, wherein each instruction processing circuit is configured to: insert an agent to read instructions in one or more instruction pipelines in the instruction pipeline for a generated value produced by the execution of a production instruction that cannot be consumed by its consumer instruction in the data forwarding path. Examples, but not limited to, include: head-mounted displays, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, wireless equipment, satellite wireless equipment, music players, digital music players, portable music players, digital video players, video players, digital video discs (DVD1 players), portable digital video players, motor vehicles, vehicle components, avionics systems, drones, and multi-rotor aircraft.

[0054] in this regard, Figure 8 The illustration shows an example of a processor-based system 800, which may include a CPU 802. The CPU 802 includes one or more processors 804, each processor 804 including one or more instruction processing circuits 806, each instruction processing circuit 806 including one or more instruction pipelines. As a non-limiting example, such as Figure 4 and Figure 7 Instruction Pipeline I Y I Z Each instruction processing circuit 806 may include a scheduler circuit 808, which is configured to insert a proxy read instruction into one or more instruction pipelines in the instruction pipeline for a generated value produced by the execution of a production instruction that cannot be consumed by its consumer instruction in the data forwarding path.

[0055] In this example, a processor-based system 800 is provided in IC 810. IC 810 may be included in or provided as a system-on-chip (SoC) 812. The processor-based system 800 includes a CPU 802, which includes one or more processors 804. CPU 802 may include a cache memory 814 coupled to the processor(s) 804 for fast access to temporarily stored data. CPU 802 is coupled to a system bus 815 and may couple master and slave devices included in the processor-based system 800 to each other. It is well known that CPU 802 communicates with these other devices by exchanging address information, control information, and data information on the system bus 815. Although... Figure 8 Not shown in the diagram, but multiple system buses 815 may be provided, each forming a different architecture. For example, CPU 802 may transmit bus transaction requests to main memory 816, which is an example of a slave device. Memory system 816 may include memory array 818, and access to memory array 818 is controlled by memory controller 820.

[0056] Other master and slave devices can be connected to system bus 815. For example... Figure 8 As shown, these devices may include a memory system 816 and one or more input devices 822. The input devices 822 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Other devices may also include one or more output devices 824 and one or more network interface devices 826, such as audio, video, other visual indicators, etc. As an example, other devices may also include one or more display controllers 828. The display controllers 828 may include one or more instruction processing circuits 806, each instruction processing circuit 806 including one or more instruction pipelines, such as... Figure 4 and Figure 7 Instruction Pipeline I Y I Z Each instruction processing circuit 806 may include a scheduler circuit 808, which is configured to insert a proxy read instruction into one or more instruction pipelines in the instruction pipeline for a generated value produced by the execution of a production instruction that cannot be consumed by its consumer instruction in the data forwarding path.

[0057] The network interface devices 826 can be any of the devices configured to allow data exchange with the network 830. The network 830 can be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and blueprints. TM Networks and the Internet. Multiple network interface devices 826 can be configured to support any type of desired communication protocol.

[0058] CPU 802 can also be configured to access multiple display controllers 828 via system bus 815 to control information sent to one or more displays 832. The multiple display controllers 828 send information to the multiple displays 832 for display via one or more video processors 834, which process the information to be displayed into a format suitable for the multiple displays 832. The multiple displays 832 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, etc.

[0059] Figure 8 The processor-based system 800 may include a stored instruction set 836 configured to control instruction scheduling and configured to insert proxy read instructions into one or more instruction pipelines in the instruction pipeline for produced values ​​generated by the execution of producer instructions that cannot be consumed by their consumer instructions in the data forwarding path. As an example of a non-transitory computer-readable medium 838, the instructions 836 may be stored in a memory array 818 of a memory system 816, a CPU 802, a video processor 834, and a network 830.

[0060] Although computer-readable medium 838 is shown as a single medium in exemplary embodiments, the term "computer-readable medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more instruction sets. The term "computer-readable medium" may also include any medium capable of storing, encoding, or carrying instruction sets for execution by a processing device and causing the processing device to perform any or more methods of the embodiments disclosed herein. The term "computer-readable medium" includes, but is not limited to, solid-state storage, optical media, and magnetic media.

[0061] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium, and executed by a processor or other processing device, or a combination of both. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally according to their functionality. How such functionality is implemented depends on the specific application, design choices, and / or the design state imposed on the overall system. Those skilled in the art can implement the described functionality in varying ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure.

[0062] The various illustrative logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein can be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0063] The aspects disclosed herein can be embodied in hardware and instructions stored in that hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated into the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0064] It should also be noted that operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The described operations can be performed in many different orders besides the order illustrated. Furthermore, the operations described in a single operational step can actually be performed in many different steps. Additionally, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that the operational steps illustrated in the flowcharts can be modified in many different ways, as will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout this specification may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0065] The prior description of this disclosure is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is consistent with the widest scope of the principles and novel features disclosed herein.< / pri>

Claims

1. A processor comprising: a register file comprising a plurality of register entries, each register entry configured to store a data value; and an instruction processing circuit comprising: fetch circuitry configured to fetch a plurality of instructions into an instruction pipeline, the plurality of instructions comprising a producer instruction and a consumer instruction; the instruction pipeline comprising: execution circuitry configured to execute the producer instruction comprising a source register and a destination register to generate a produced value to be written into the destination register in the register file; and scheduler circuitry configured to: receive the fetched consumer instruction comprising a source register corresponding to the destination register of the producer instruction; and in response to determining that the produced value will not be available in the instruction pipeline to be consumed as the source register of the consumer instruction: insert an agent read instruction in the instruction pipeline, the agent read instruction comprising the destination register storing the produced value.

2. The processor of claim 1, wherein the scheduler circuitry is further configured to determine whether the produced value generated by the execution of the producer instruction will be forwarded in at least one data forwarding path in the instruction pipeline to be available to be consumed in the execution circuitry as the source register of the consumer instruction.

3. The processor of claim 1, wherein the scheduler circuitry is further configured to, in response to determining that the produced value will be available to be consumed as the source register of the consumer instruction in at least one data forwarding path: not insert an agent read instruction in the instruction pipeline, the agent read instruction comprising the destination register storing the produced value.

4. The processor of claim 1, wherein the execution circuitry is further configured to forward the produced value generated by the execution of the producer instruction in at least one data forwarding path to be consumed as the source register of the consumer instruction.

5. The processor of claim 1, wherein the execution circuitry is further configured to: execute the agent read instruction to regenerate the produced value; and forward the regenerated produced value in at least one data forwarding path.

6. The processor of claim 5, wherein: the agent read instruction comprises a copy instruction; and the execution circuitry is configured to execute the agent read instruction to regenerate the produced value by being configured to copy the produced value into the destination register.

7. The processor of claim 5, wherein: the agent read instruction comprises a move instruction; and the execution circuitry is configured to execute the agent read instruction to regenerate the produced value by being configured to move the produced value into the destination register.

8. The processor of claim 5, wherein: the agent read instruction comprises an instruction comprising a source register that is the same register as the destination register, wherein the source register contains the produced value; and the execution circuitry is configured to execute the agent read instruction to regenerate the produced value by being configured to copy the produced value from the source register into the destination register. The execution circuit is configured to execute the agent read instruction to regenerate the produced value.

9. The processor of claim 5, wherein the execution circuit is further configured to consume the regenerated produced value as the source register of the consumer instruction to be executed.

10. The processor of claim 1, wherein the scheduler circuit is configured to determine whether the produced value is to be forwarded in the instruction pipeline to be available in the execution circuit to be consumed as the source register of the consumer instruction by being configured to determine whether the produced value is to be forwarded in at least one data forwarding path earlier than the produced value can be consumed from the at least one data forwarding path as the source register of the consumer instruction.

11. The processor of claim 1, wherein: the instruction pipeline further comprises a writeback circuit configured to write back the produced value generated by the execution circuit by executing a producer instruction to the register file corresponding to the target register of the producer instruction; and the scheduler circuit is configured to determine whether the produced value generated by execution of the producer instruction to be consumed as the source register of the consumer instruction is written back to the register file compared to the produced value being forwarded in at least one data forwarding path earlier than the produced value can be consumed from the at least one data forwarding path as the source register of the consumer instruction by being configured to determine whether the produced value generated by execution of the producer instruction to be consumed as the source register of the consumer instruction is written back to the register file.

12. The processor of claim 11, wherein the scheduler circuit is configured to determine whether the produced value is written back to the register file by being configured to determine whether the produced value generated by execution of the producer instruction to be consumed as the source register of the consumer instruction is written back to the register file before the consumer instruction is scheduled by the scheduler circuit.

13. The processor of claim 11, wherein: the scheduler circuit is further configured to dispatch the consumer instruction to be executed in the execution circuit; and the scheduler circuit is configured to determine whether the produced value generated by execution of the producer instruction to be consumed as the source register of the consumer instruction is written back to the register file before the consumer instruction is dispatched to the execution circuit by being configured to determine whether the produced value generated by execution of the producer instruction to be consumed as the source register of the consumer instruction is written back to the register file before the consumer instruction is dispatched to the execution circuit.

14. The processor of claim 1, wherein the scheduler circuit is further configured to: determine whether the produced value generated by execution of the producer instruction to be consumed as the source register of the consumer instruction is to be forwarded in at least one data forwarding path too late to be consumed from the at least one data forwarding path as the source register of the consumer instruction; and ​ stall the consumer instruction in the instruction pipeline in response to determining that the produced value will be forwarded too late in the at least one data forwarding path to be consumed from the at least one data forwarding path as the source register for the consumer instruction.

15. The processor of claim 1, wherein: the execution circuit includes at least one read input port coupled to the register file, the at least one read input port configured to receive data values from the register file; and the consumer instruction includes a number of source registers that is greater than a number of read input ports among the at least one read input port.

16. The processor of claim 1, wherein the instruction pipeline further includes at least one data forwarding path configured to forward the produced value generated by execution of the producer instruction to be available to be consumed as the source register for the consumer instruction.

17. The processor of claim 1, wherein: the producer instruction includes a producer multiply-accumulate (MAC) instruction, the MAC instruction including two source registers and a third source register, the third source register also being the destination register for the producer instruction; the consumer instruction includes a consumer MAC instruction, the consumer MAC instruction including two source registers and a third source register, the third source register also being the destination register for the consumer instruction; and the destination register for the producer MAC instruction includes the destination register for the consumer MAC instruction.

18. The processor of claim 17, wherein the execution circuit includes only two read input ports coupled to the register file, each of the two read input ports configured to receive data values from the register file.

19. The processor of claim 1, wherein the instruction pipeline further includes a writeback circuit configured to write back the produced value generated by the execution circuit through execution of a producer instruction to the register file corresponding to the destination register for the producer instruction.

20. The processor of claim 1, integrated into an integrated circuit (IC).

21. The processor of claim 1, integrated into a device selected from a group consisting of a head mounted display, a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a transportation component, avionics systems, a drone, and a multi-copter.

22. A method of providing produced data generated by execution of a producer instruction to a consumer instruction in a processor, comprising: fetching a plurality of instructions into an instruction pipeline, the plurality of instructions including a producer instruction and a consumer instruction; executing the producer instruction including a source register and a destination register to generate a produced value to be written to the destination register in a register file, the register file including a plurality of register entries, each register entry associated with a physical register and each configured to store a data value; receiving a fetched consumer instruction, the consumer instruction including a source register corresponding to the destination register of the producer instruction; and in response to determining that the produced value cannot be consumed in the instruction pipeline as the source register of the consumer instruction, inserting a proxy read instruction in the instruction pipeline, the proxy read instruction including the destination register storing the produced value. determining whether the produced value generated by execution of the producer instruction will be forwarded in at least one data forwarding path in the instruction pipeline to be available in execution circuitry to be consumed as the source register of the consumer instruction.

23. The method of claim 22, further comprising: in response to determining that the produced value will be available to be consumed as the source register of the consumer instruction in at least one data forwarding path, without inserting a proxy read instruction in the instruction pipeline, the proxy read instruction including the destination register storing the produced value.

24. The method of claim 22, further comprising:

25. The method of claim 22, further comprising: executing the proxy read instruction to regenerate the produced value; and forwarding the regenerated produced value in at least one data forwarding path. copying the produced value into the destination register to regenerate the produced value. moving the produced value into the destination register to regenerate the produced value.

26. The method of claim 25, wherein executing the proxy read instruction comprises:

28. The method of claim 25, further comprising consuming the regenerated produced value as the source register of the consumer instruction to be executed.

27. The method of claim 25, wherein executing the proxy read instruction comprises: ​ ​ 29. The method of claim 22, wherein determining whether the produced value is to be forwarded in the instruction pipeline to be available in execution circuitry to be consumed as the source register of the consumer instruction comprises: determining whether the produced value is to be forwarded in at least one data forwarding path earlier than the produced value can be consumed as the source register of the consumer instruction from the at least one data forwarding path.

30. The method of claim 22, further comprising: determining whether the produced value generated by execution of the producer instruction to be consumed as the source register of the consumer instruction is to be forwarded in at least one data forwarding path too late to be consumed as the source register of the consumer instruction from the at least one data forwarding path; and responsive to determining that the produced value is to be forwarded in the at least one data forwarding path too late to be consumed as the source register of the consumer instruction from the at least one data forwarding path, stalling the consumer instruction in the instruction pipeline. ​

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