Power-on operation execution method and device, chip and electronic equipment

Abstract

This application discloses a power-on operation execution method, apparatus, chip, and electronic device, belonging to the field of computer technology. The method includes: after the chip is connected to a host, when the frequency of the chip's first clock signal switches to a stable state, starting the chip's processor; receiving a reset signal sent by the host, the reset signal being sent after the frequency of the host's second clock signal switches to a stable state; and performing a power-on operation in response to the reset signal; wherein the time point when the frequency of the first clock signal switches to a stable state is earlier than the time point when the second clock signal switches to a stable state. Since the time point when the frequency of the first clock signal switches to a stable state is earlier than the time point when the second clock signal switches to a stable state, it is equivalent to advancing the processor startup process before receiving the reset signal. Therefore, there is no need to perform the processor startup operation during the power-on process, thereby shortening the time consumed by the chip's power-on process.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a power-on operation execution method, apparatus, chip, and electronic device. Background Technology

[0002] When a PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) chip is connected to a PCIe host, the power-on process of the PCIe chip must meet the timing requirements of the PCIe protocol, and the power-on process cannot take more than 20 milliseconds.

[0003] However, in related technologies, the power-on process of PCIe chips takes a long time, and there are cases where the timing requirements are not met, which can easily cause PCIe chips to malfunction. Therefore, there is an urgent need to provide a method to reduce the time consumed by the power-on process. Summary of the Invention

[0004] This application provides a power-on operation execution method, apparatus, chip, and electronic device, which can reduce the time consumed during the power-on process. The technical solution is as follows:

[0005] On one hand, a power-on operation execution method is provided, the method comprising:

[0006] After the chip is connected to the host, when the frequency of the chip's first clock signal switches to a stable state, the chip's processor is started.

[0007] The system receives a reset signal sent by the host, which is sent after the frequency of the host's second clock signal has reached a stable state.

[0008] In response to the reset signal, a power-on operation is performed;

[0009] The time point at which the frequency of the first clock signal switches to a stable state is earlier than the time point at which the second clock signal switches to a stable state.

[0010] On the other hand, a power-on operation execution method is provided, executed by an electronic device, the electronic device including a chip and a host, the method comprising:

[0011] After the chip is connected to the host, when the frequency of the chip's first clock signal switches to a stable state, the chip's processor is started.

[0012] After the frequency of the host's second clock signal is switched to a stable state, a reset signal is sent from the host to the processor.

[0013] The processor receives the reset signal and, in response to the reset signal, performs a power-on operation.

[0014] The time point at which the frequency of the first clock signal switches to a stable state is earlier than the time point at which the second clock signal switches to a stable state.

[0015] On the other hand, a power-on operation execution device is provided, the device comprising:

[0016] A startup module is used to start the processor of the chip when the frequency of the first clock signal of the chip switches to a stable state after the chip is connected to the host.

[0017] The signal receiving module is used to receive a reset signal sent by the host, which is sent after the frequency of the host's second clock signal is switched to a stable state;

[0018] The power-on module is used to perform a power-on operation in response to the reset signal;

[0019] The time point at which the frequency of the first clock signal switches to a stable state is earlier than the time point at which the second clock signal switches to a stable state.

[0020] Optionally, the device further includes:

[0021] An initialization module is used to perform initialization operations on the chip through the processor.

[0022] Optionally, the chip includes a controller and a physical layer, and the initialization module is used to perform initialization operations on the controller and the physical layer through the processor.

[0023] Optionally, the initialization module is configured to perform initialization operations on the controller and the physical layer based on the first clock signal via the processor.

[0024] Optionally, the initialization module includes:

[0025] The first frequency conversion unit is used to perform frequency conversion operation on the first clock signal to obtain the frequency-converted first clock signal;

[0026] The first initialization unit is used to perform initialization operations on the controller and the physical layer based on the frequency-converted first clock signal through the processor.

[0027] Optionally, during the initialization operation of the controller and the physical layer, the clock signals of the controller and the physical layer are the first clock signal; the apparatus further includes:

[0028] The clock switching module is used to determine the second clock signal as the clock signal replaced by the controller and the physical layer when the controller and the physical layer are initialized.

[0029] Optionally, the controller and the physical layer are connected to a clock phase-locked loop (PLL). The clock switching module is used to control the first clock signal to stop entering the PLL and control the second clock signal to enter the PLL when the controller and the physical layer are initialized.

[0030] Optionally, the clock phase-locked loop is connected to a clock gating system, and the first clock signal enters the clock phase-locked loop through the clock gating system. The clock switching module is used for:

[0031] Close the clock gating to stop the first clock signal from entering the clock phase-locked loop;

[0032] If the duration after the first clock signal stops entering the clock phase-locked loop reaches a first duration, the first clock signal entering the clock gating will be switched to the second clock signal;

[0033] If the duration after switching the first clock signal into the clock gate to the second clock signal reaches a second duration, the clock gate is opened so that the second clock signal enters the clock phase-locked loop.

[0034] Optionally, the controller and the physical layer are connected by a clock phase-locked loop, and the power-on module includes:

[0035] The second frequency conversion unit is used to respond to the reset signal and control the clock phase-locked loop to perform frequency conversion operation on the second clock signal through the processor to obtain the frequency-converted second clock signal;

[0036] The state entry unit is used to control the chip to enter the detection state based on the frequency-converted second clock signal through the controller and the physical layer.

[0037] Optionally, the power-on module includes:

[0038] The second frequency conversion unit is used to respond to the reset signal and, through the processor, perform a frequency conversion operation on the second clock signal to obtain a frequency-converted second clock signal;

[0039] The second initialization unit is used to perform initialization operations on the chip through the processor;

[0040] The state entry unit is used to control the chip to enter the Detect state based on the frequency-converted second clock signal.

[0041] Optionally, the chip envelope controller and the physical layer are connected to a clock phase-locked loop; the second frequency conversion unit is used to control the clock phase-locked loop to perform frequency conversion on the second clock signal through the processor to obtain the frequency-converted second clock signal;

[0042] The second initialization unit is used to perform initialization operations on the controller and the physical layer through the processor;

[0043] The state entry unit is used to control the chip to enter the Detect state based on the frequency-converted second clock signal through the controller and the physical layer.

[0044] Optionally, the power-on operation includes a first operation performed by the processor, the processor being configured to execute the first operation in response to an operation instruction corresponding to the first operation; the device further includes an instruction control module, configured to perform at least one of the following:

[0045] The chip also includes other components besides the processor. When the power-on operation is performed, the other components are controlled to stop sending operation instructions corresponding to other operations besides the first operation to the processor.

[0046] The processor responds to operation instructions according to priority, with the operation instruction corresponding to the first operation having the highest priority.

[0047] On the other hand, a power-on operation execution device is provided, the device comprising:

[0048] A startup module is used to start the processor of the chip when the frequency of the first clock signal of the chip switches to a stable state after the chip is connected to the host.

[0049] The signal transmission module is used to send a reset signal to the processor through the host after the frequency of the second clock signal of the host is switched to a stable state;

[0050] The power-on module is used to receive the reset signal through the processor and, in response to the reset signal, perform a power-on operation.

[0051] The time point at which the frequency of the first clock signal switches to a stable state is earlier than the time point at which the second clock signal switches to a stable state.

[0052] Optionally, the signal sending module is configured to send the reset signal to the processor via the host when the duration of the second clock signal being in a stable state reaches a third duration.

[0053] On the other hand, a chip is provided that includes at least one computer program, which, when the chip is running on an electronic device, performs the operations executed by the power-on operation execution method as described above.

[0054] On the other hand, an electronic device is provided, the electronic device including a chip and a host;

[0055] The chip is used to start the processor of the chip when the frequency of the first clock signal of the chip switches to a stable state after the chip is connected to the host.

[0056] The host is used to send a reset signal to the processor after the frequency of the host's second clock signal is switched to a stable state;

[0057] The chip is also configured to receive the reset signal via the processor and, in response to the reset signal, perform a power-on operation.

[0058] The time point at which the frequency of the first clock signal switches to a stable state is earlier than the time point at which the second clock signal switches to a stable state.

[0059] The method, apparatus, chip, and electronic device provided in this application start the chip's processor when the frequency of the chip's first clock signal switches to a stable state. When the frequency of the host's second clock signal switches to a stable state, the chip receives a reset signal and performs a power-on operation in response to the reset signal. Since the time point when the frequency of the first clock signal switches to a stable state is earlier than the time point when the second clock signal switches to a stable state, it is equivalent to advancing the processor's startup process to before receiving the reset signal. Therefore, there is no need to perform the processor startup operation during the power-on process, thereby shortening the time consumed by the chip's power-on process. Attached Figure Description

[0060] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0061] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0062] Figure 2 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0063] Figure 3This is a flowchart of a power-on operation execution method provided in an embodiment of this application;

[0064] Figure 4 This is a flowchart of another power-on operation execution method provided in an embodiment of this application;

[0065] Figure 5 This is a schematic diagram of another chip structure provided in an embodiment of this application;

[0066] Figure 6 This is a flowchart of a clock signal switching method provided in an embodiment of this application;

[0067] Figure 7 This is a timing diagram of a power-on operation execution method provided in an embodiment of this application;

[0068] Figure 8 This is a flowchart of another power-on operation execution method provided in the embodiments of this application;

[0069] Figure 9 This is a flowchart of another power-on operation execution method provided in the embodiments of this application;

[0070] Figure 10 This is a schematic diagram of the structure of a power-on operation execution device provided in an embodiment of this application;

[0071] Figure 11 This is a schematic diagram of another power-on operation execution device provided in an embodiment of this application;

[0072] Figure 12 This is a schematic diagram of another power-on operation execution device provided in the embodiments of this application. Detailed Implementation

[0073] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0074] It is understood that the terms "first," "second," etc., used in this application may be used to describe various concepts herein, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of this application, a first clock signal may be referred to as a second clock signal, and similarly, a second clock signal may be referred to as a first clock signal.

[0075] "At least one" refers to one or more clock signals. For example, at least one clock signal can be any integer number of clock signals greater than or equal to one, such as one clock signal, two clock signals, three clock signals, etc. "Multiple" refers to two or more clock signals. For example, multiple clock signals can be any integer number of clock signals greater than or equal to two, such as two clock signals, three clock signals, etc. "Each" refers to each of the at least one clock signal. For example, each clock signal refers to each of the multiple clock signals. If the multiple clock signals are three clock signals, then each clock signal refers to each of the three clock signals.

[0076] To facilitate understanding of the embodiments of this application, the chip provided in the embodiments of this application will be explained first. This chip can be applied to various types of electronic devices, such as mobile phones, tablets, laptops, desktop computers, intelligent voice interaction devices, smart speakers, smart home appliances, or in-vehicle terminals. This chip can provide various types of functions, such as image processing, voice recognition, or intelligent navigation.

[0077] Optionally, the chip is an Artificial Intelligence (AI) chip, which uses artificial intelligence technology to achieve the above functions. Artificial intelligence uses digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, encompassing both hardware and software technologies. Fundamental AI technologies include sensors, AI chips, cloud computing, distributed storage, big data processing, operating / interactive systems, and mechatronics. AI software technologies include computer vision, speech processing, natural language processing, machine learning / deep learning, autonomous driving, and intelligent transportation.

[0078] Optionally, this chip can be applied to electronic devices (such as in-vehicle terminals) in Intelligent Traffic Systems (ITS) to achieve functions such as intelligent navigation. Intelligent Traffic Systems integrate advanced technologies (information technology, computer technology, data communication technology, sensor technology, electronic control technology, automatic control theory, operations research, artificial intelligence, etc.) into transportation, service control, and vehicle manufacturing, strengthening the connection between vehicles, roads, and users to form a comprehensive transportation system that ensures safety, improves efficiency, enhances the environment, and conserves energy.

[0079] Figure 1This is a schematic diagram of an electronic device provided in an embodiment of this application. The electronic device includes a chip 101 and a host 102, for example, the host 102 is a PCIe host, and the chip 101 is a PCIe chip. The chip 101 is used to connect to the host 102. After the chip 101 is connected to the host 102, a power-on operation needs to be performed on the chip 101. In this embodiment, the power-on operation refers to the operation performed from the time the chip 101 receives the reset signal (PERST#, PCI Express Reset) to the time the chip enters the Detect state. After the chip 101 is connected to the host 102, when the frequency of the first clock signal of the chip 101 switches to a stable state, the processor of the chip 101 is started. After the frequency of the second clock signal of the host 102 switches to a stable state, a reset signal is sent to the processor. The chip 101 receives the reset signal through the processor and performs the power-on operation in response to the reset signal. The time point when the frequency of the first clock signal switches to a stable state is earlier than the time point when the second clock signal switches to a stable state.

[0080] In one possible implementation, the chip 101 is used to perform chip initialization operations via a processor.

[0081] In one possible implementation, the chip includes a controller and a physical layer, and the chip 101 is used to initialize the controller and the physical layer via a processor.

[0082] In one possible implementation, the chip 101 is used to initialize the controller and physical layer via a processor based on a first clock signal.

[0083] In one possible implementation, the chip 101 is used for:

[0084] The first clock signal is frequency-converted to obtain the frequency-converted first clock signal;

[0085] The processor initializes the controller and physical layer based on the first clock signal after frequency conversion.

[0086] In one possible implementation, when initializing the controller and physical layer, the clock signals of the controller and physical layer are first clock signals; the chip 101 is used to determine the second clock signal as the clock signal after the controller and physical layer initialization is completed.

[0087] In one possible implementation, the controller and the physical layer are connected to a clock phase-locked loop (PLL). Chip 101 is used to control the first clock signal to stop entering the PLL and to control the second clock signal to enter the PLL when the controller and the physical layer are initialized.

[0088] In one possible implementation, the clock phase-locked loop is connected to a clock gating system. A first clock signal enters the clock phase-locked loop through the clock gating system. The chip 101 is used for:

[0089] Turn off the clock gating to stop the first clock signal from entering the clock phase-locked loop;

[0090] If the time elapsed after the first clock signal stops entering the clock phase-locked loop reaches the first time elapsed, the first clock signal entering the clock gate will be switched to the second clock signal.

[0091] If the duration after switching the first clock signal to the second clock signal that enters the clock gating reaches the second duration, the clock gating is opened so that the second clock signal enters the clock phase-locked loop.

[0092] In one possible implementation, the controller and the physical layer are connected via a clock-locked loop, and the chip 101 is used for:

[0093] In response to the reset signal, the processor controls the clock phase-locked loop to perform a frequency conversion operation on the second clock signal to obtain the frequency-converted second clock signal;

[0094] Through the controller and physical layer, the control chip enters the detection state based on the frequency-converted second clock signal.

[0095] In one possible implementation, the chip 101 is used for:

[0096] In response to the reset signal, the processor performs a frequency conversion operation on the second clock signal to obtain the frequency-converted second clock signal;

[0097] The processor performs initialization operations on the chip;

[0098] Based on the second clock signal after frequency conversion, the control chip enters the Detect state.

[0099] In one possible implementation, the chip encloses the controller and the physical layer, and the controller and the physical layer are connected by a clock phase-locked loop; the chip 101 is used for:

[0100] The processor controls the clock phase-locked loop to perform frequency conversion on the second clock signal to obtain the frequency-converted second clock signal.

[0101] The processor performs initialization operations on the controller and physical layer;

[0102] Through the controller and physical layer, the control chip enters the Detect state based on the frequency-converted second clock signal.

[0103] In one possible implementation, the power-on operation includes a first operation performed by a processor, the processor being configured to perform the first operation in response to an operation instruction corresponding to the first operation; the chip 101 is configured to perform at least one of the following:

[0104] The chip also includes other components besides the processor. When the power-on operation is performed, the other components are controlled to stop sending operation instructions corresponding to operations other than the first operation to the processor.

[0105] The processor responds to operation instructions according to priority, with the first operation corresponding to the highest priority instruction.

[0106] In one possible implementation, the host 102 is configured to send a reset signal to the processor when the duration of the second clock signal being in a stable state reaches a third duration.

[0107] Figure 2 This is a schematic diagram of the structure of a chip provided in an embodiment of this application, such as... Figure 2 As shown, chip 101 includes a processor 201, a controller, and a physical layer 202. The processor 201 is used to initialize the controller and physical layer 202 of the chip. The controller and physical layer 202 are also used to control chip 101 to enter a Detect state. The processor 201 is also used to control the chip to generate the clock signals required by the controller and physical layer 202. The chip provided in this embodiment also includes at least one computer program, which, when the chip is running on an electronic device, performs the operations executed by the power-on operation execution method described below.

[0108] In another embodiment, the electronic device further includes a memory, a peripheral device interface, and at least one peripheral device. Optionally, the peripheral device includes at least radio frequency circuitry.

[0109] The memory may include one or more computer-readable storage media, which may be non-transitory. The memory may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices.

[0110] Peripheral device interfaces can be used to connect at least one I / O (Input / Output) related peripheral device to the processor and memory. In some embodiments, the processor, memory, and peripheral device interface are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor, memory, and peripheral device interface can be implemented on separate chips or circuit boards.

[0111] Radio frequency (RF) circuits are used to receive and transmit RF signals, also known as electromagnetic signals. RF circuits communicate with communication networks and other communication devices via electromagnetic signals. RF circuits convert electrical signals into electromagnetic signals for transmission, or convert received electromagnetic signals back into electrical signals. Optionally, RF circuits include: antenna systems, RF transceivers, one or more amplifiers, tuners, oscillators, digital signal processors, codec chipsets, user identity module cards, etc. RF circuits can communicate with other devices through at least one wireless communication protocol. These wireless communication protocols include, but are not limited to: metropolitan area networks (MANs), various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks (WLANs), and / or WiFi (Wireless Fidelity) networks.

[0112] Figure 3 This is a flowchart illustrating a power-on operation execution method provided in an embodiment of this application. The execution subject in this embodiment is a chip; see [link to relevant documentation]. Figure 3 The method includes:

[0113] 301. After the chip is connected to the host, when the frequency of the chip's first clock signal switches to a stable state, the chip's processor is started.

[0114] After the chip is connected to the host, it needs to be powered on. This power-on process must meet certain timing requirements. For example, when the host is a PCIe host and the chip is a PCIe chip, the power-on process of the PCIe chip must meet the timing requirements of the PCIe protocol, which stipulates that the power-on process cannot take more than 20 milliseconds.

[0115] The chip includes a processor, such as an ARM processor (Advanced RISC Machines, a type of RISC microprocessor). The processor within the chip is the core of its computation and control, and is the final execution unit for information processing and program execution. In this embodiment, after the chip is connected to the host, it is powered on and generates a first clock signal. For a short period after the first clock signal is generated, its frequency is unstable, also known as an indeterminate state. During this period, the state of the first clock signal is uncertain. Subsequently, the frequency of the first clock signal gradually stabilizes. When the frequency of the first clock signal reaches a stable state, the chip's processor is activated.

[0116] The clock signal includes high-level and low-level states, which are used to represent the high and low states between signal oscillations. It can play the role of a timer in a synchronization circuit, such as ensuring the synchronous operation of various components in a chip.

[0117] 302. Receive the reset signal sent by the host. The reset signal is sent after the frequency of the host's second clock signal has switched to a stable state.

[0118] After the chip is connected to the host, the host generates a second clock signal. For a short period after the second clock signal is generated, its frequency is unstable, also known as an indeterminate state. During this period, the state of the second clock signal is uncertain. Subsequently, the frequency of the second clock signal gradually stabilizes. Once the frequency of the second clock signal reaches a stable state, the host generates a reset signal and sends this reset signal to the chip. Therefore, the chip receives the reset signal from the host, which is used to notify the chip to initiate the power-on process.

[0119] Since the chip's power-on operation requires a stable second clock signal, and the chip cannot know when the host's second clock signal frequency is stable, the host needs to send a reset signal to the chip after the second clock signal frequency switches to a stable state to notify the chip that the second clock signal is stable and the power-on process can begin.

[0120] The first clock signal reaches a stable frequency earlier than the second clock signal. Therefore, the chip's processor can be started before the chip receives a reset signal. In other words, step 301 is completed before step 302.

[0121] 303. In response to the reset signal, perform a power-on operation.

[0122] Since the reset signal is sent by the host after the frequency of the second clock signal has stabilized, it serves as a marker that the second clock signal is in a stable state. The chip can then utilize the stable second clock signal to perform a power-on operation. Therefore, the chip responds to the reset signal and performs a power-on operation. In this embodiment, the power-on operation refers to the operation performed from the time the chip receives the reset signal (PERST#, PCI Express Reset) until the chip enters the Detect state. The power-on process is also the process from the time the chip receives the reset signal until the chip enters the Detect state.

[0123] The method provided in this application starts the chip's processor when the frequency of the chip's first clock signal switches to a stable state. When the frequency of the host's second clock signal switches to a stable state, the chip receives a reset signal and performs a power-on operation in response to the reset signal. Since the time point when the frequency of the first clock signal switches to a stable state is earlier than the time point when the second clock signal switches to a stable state, it is equivalent to advancing the processor's startup process to before receiving the reset signal. Therefore, there is no need to perform the processor startup operation during the power-on process, thereby shortening the time consumed by the chip's power-on process.

[0124] Figure 4 This is a flowchart of another power-on operation execution method provided in this application embodiment. The execution subject in this application embodiment is a chip; see [link to relevant documentation]. Figure 4 The method includes:

[0125] 401. After the chip is connected to the host, when the frequency of the chip's first clock signal switches to a stable state, the chip's processor is started.

[0126] The processor of the chip needs a stable clock signal to start. In this embodiment, the chip's first clock signal is used to start the processor. Therefore, when the frequency of the chip's first clock signal switches to a stable state, the processor is started using that first clock signal. Thus, it is not necessary to wait for the host's second clock signal to switch to a stable state before starting the processor, thereby advancing the processor startup process to before the frequency of the second clock signal switches to a stable state.

[0127] The stable state of the first clock signal's frequency means that the frequency of the first clock signal remains unchanged. Optionally, the first clock signal is considered stable when its frequency remains constant at the target frequency, for example, the target frequency is 100 MHz (Mega Hertz). Optionally, the frequency of the first clock signal is determined to have stabilized at the target frequency when the duration of the first clock signal's frequency at the target frequency reaches a fourth duration.

[0128] In one possible implementation, after the chip is connected to the host, it is powered on. The chip includes a board-level crystal oscillator, which generates a first clock signal (ref_clk) upon power-on. The frequency of this first clock signal gradually stabilizes. Optionally, the chip includes a board-level power rail. After the chip is connected to the host, this board-level power rail gradually transforms the voltage to a target voltage, for example, 1.8V, to provide ASIC (Application Specific Integrated Circuit) power to the chip. Optionally, when the board-level power rail transforms to the target voltage, the chip generates a power-on-okay signal (power_on_okay). This power-on-okay signal notifies the chip to enter a ready state, meaning the chip is ready to perform a power-on operation.

[0129] In one possible implementation, the chip's processor includes an ARM core bootloader and a bootloader. The ARM core bootloader runs before the ARM core (processor core) and is used to boot the processor. The bootloader is used to start the chip's processor. The chip loads the bootloader via the ARM core bootloader, thereby starting the chip's processor. Optionally, the time consumed to start the chip's processor is approximately 11.53 milliseconds.

[0130] 402. The processor initializes the controller and physical layer based on the first clock signal.

[0131] The chip includes a controller and a physical layer (PHY). After the chip powers on the processor, the processor initializes the controller and physical layer based on a stable first clock signal. The controller controls the integrated circuits in the chip, while the physical layer performs functions such as encoding / decoding, scrambling and descrambling, serial-to-parallel conversion, differential transmission and reception, and link training, providing a transmission medium for data communication.

[0132] Initializing the controller and physical layer requires a stable clock signal. In this embodiment, the first clock signal is used to initialize the controller and physical layer. It is not necessary to wait for the frequency of the host's second clock signal to switch to a stable state before initializing the controller and physical layer. This advances the initialization process of the controller and physical layer to before the frequency of the second clock signal switches to a stable state.

[0133] In one possible implementation, the chip performs a frequency conversion operation on the first clock signal to obtain a frequency-converted first clock signal. The processor then performs initialization operations on the controller and physical layer based on this frequency-converted first clock signal. The first clock signal has a first frequency, for example, 100MHz. Since the initialization of the controller and physical layer requires a second frequency clock signal, for example, 50MHz, the chip first converts the first clock signal from the first frequency to the second frequency. Then, the processor performs the initialization operations on the controller and physical layer based on this second-frequency first clock signal.

[0134] In one possible implementation, the chip includes Serdes (Serializer-Deserializer), and the chip's processor controls the Serdes to load drivers for initializing the controller and physical layer.

[0135] It should be noted that step 402 above only illustrates the process of initializing the chip by taking the initialization operation of the controller and physical layer as an example. In addition, the initialization operation may also include initialization operations of other components in the chip, and this embodiment of the application does not limit this.

[0136] It should be noted that this application embodiment only uses the first clock signal as an example to illustrate the process of initializing the controller and physical layer through the processor. In another embodiment, the processor can also perform initialization operations on the controller and physical layer based on other clock signals, as long as the clock signal is a stable frequency clock signal.

[0137] 403. When the controller and physical layer initialization is completed, the second clock signal is determined to be the clock signal after the controller and physical layer have been replaced.

[0138] When initializing the controller and physical layer, the clock signal of the controller and physical layer is the first clock signal. However, subsequent operations of the controller and physical layer after initialization need to be completed based on the second clock signal of the host. Therefore, when the controller and physical layer are initialized, the chip determines the second clock signal as the clock signal after the controller and physical layer have been replaced. That is, the first clock signal provided to the controller and physical layer is switched to the second clock signal.

[0139] The second clock signal is a clock signal generated on the host machine, which provides it to the chip. After the chip connects to the host machine, the host machine generates the second clock signal. For a short period after its generation, the frequency of this second clock signal is unstable, gradually stabilizing thereafter. The point at which the second clock signal reaches a stable state is later than the point at which the first clock signal reaches a stable state. When the chip identifies this second clock signal as the clock signal after the control layer and physical layer have been replaced, it may be in an unstable state or a stable state.

[0140] In one possible implementation, the controller and physical layer are connected by a clock phase-locked loop (PLL). A clock signal enters the PLL and is provided to both the controller and physical layer. During the initialization of the controller and physical layer, the chip controls a first clock signal to enter the PLL, thereby providing the first clock signal to the controller and physical layer. Once the controller and physical layer initialization is complete, the chip stops the first clock signal from entering the PLL and controls a second clock signal to enter the PLL, thereby providing the second clock signal to the controller and physical layer.

[0141] A phase-locked loop (PLL) is a feedback control circuit used to integrate clock signals. In this embodiment, the PLL's function is to frequency-convert the clock signal.

[0142] Optionally, the clock phase-locked loop (PLL) is connected to a clock gating system, and a first clock signal enters the PLL through the clock gating system. The chip controls the first clock signal to stop entering the PLL and controls a second clock signal to enter the PLL, including: closing the clock gating system to stop the first clock signal from entering the PLL; if a first duration has elapsed after the first clock signal stops entering the PLL, switching the first clock signal entering the clock gating system to the second clock signal; and if a second duration has elapsed after the first clock signal entering the clock gating system is switched to the second clock signal, opening the clock gating system to allow the second clock signal to enter the PLL.

[0143] The clock gating is used to control the transmission of clock signals. When a clock signal enters the clock gating, it continues to transmit to the next component connected to the clock gating when the gating is open. When the clock gating is closed, the clock signal is "intercepted" and cannot enter the next component connected to the clock gating. In this embodiment, considering that directly switching the first clock signal entering the clock phase-locked loop (PLL) to the second clock signal would generate clock glitches during the switching process, which could easily lead to circuit failures in the PLL if transmitted to it, the PLL is connected to a clock gating. By closing the clock gating, the first clock signal is prevented from entering the PLL. Only after a first duration has elapsed since the first clock signal stopped entering the PLL is the first clock signal switched to the second clock signal. And only after a second duration has elapsed since the first clock signal switched to the second clock signal is the clock gating reopened, thus avoiding clock glitches.

[0144] Optionally, the first duration is a first number of clock cycles, for example, the first number can be configured to be 2 to 15, and the default configuration value of the first number is 10. The second duration is a second number of clock cycles, for example, the second number can be configured to be 2 to 15, and the default configuration value of the second number is 10.

[0145] Figure 5 This is a schematic diagram of another chip structure provided in an embodiment of this application. Taking a PCIe host 501 and a PCIe chip 502 as an example, after the PCIe chip 502 is connected to the PCIe host 501, the PCIe host 501 provides a reset signal and a second clock signal to the PCIe chip 502. The PCIe chip 502 includes a clock control module 512, a clock switching module 522, a clock gating module 532, a clock phase-locked loop 542, a controller, and a physical layer 552. The connection relationship between the various components is detailed in [reference needed]. Figure 5 As shown.

[0146] The clock control module 512 is used to control the clock switching module 522 and the clock gating module 532. The clock switching module 522 is used to switch the clock signal transmitted to the clock gating module 532. The clock gating module 532 is used to control the clock signal transmitted to the clock phase-locked loop 542. The clock phase-locked loop 541 is used to perform frequency conversion operation on the clock signal.

[0147] The first clock signal generated on the PCIe chip and the second clock signal provided by the PCIe host are both transmitted to the clock switching module 522. Before the controller and physical layer 552 are initialized, the clock switching module 522 controls the transmission of the first clock signal to the clock gating 532, "intercepting" the second clock signal. When the controller and physical layer 552 are initialized, the clock control module 512 controls the clock gating 532 to close, so that the first clock signal stops entering the clock phase-locked loop 542. When the duration for which the first clock signal stops entering the clock phase-locked loop 542 reaches a first duration, the clock control module 512 controls the clock switching module 522 to switch the clock signal transmitted to the clock gating 532 from the first clock signal to the second clock signal. When the duration for which the clock signal transmitted to the clock gating 532 switches from the first clock signal to the second clock signal reaches a second duration, the clock control module 512 controls the clock gating 532 to open, so that the second clock signal enters the clock phase-locked loop 542, thereby completing the clock switching from the first clock signal to the second clock signal.

[0148] Figure 6 This is a flowchart of a clock signal switching method provided in an embodiment of this application, such as... Figure 6 As shown, the method includes the following steps.

[0149] 601. After the controller and physical layer are initialized, the ARM core (processor core) in the chip configures and starts the clock switching process, controls the clock gating in the chip to close, so that the first clock signal stops entering the clock phase-locked loop.

[0150] 602. The chip monitors in real time whether the duration after the clock gating is closed has reached the first duration. If the duration after the clock gating is closed has reached the first duration, then the following step 603 is executed. If the duration after the clock gating is closed has not reached the first duration, then the clock gating remains closed.

[0151] 603. The chip switches the first clock signal that enters the clock gating to the second clock signal.

[0152] 604. The chip monitors in real time whether the duration after the clock signal switch has reached the second duration. If the duration after the clock signal switch has reached the second duration, then the following step 605 is executed. If the duration after the clock signal switch has not reached the second duration, then the clock gate remains closed.

[0153] 605. When the duration after the clock signal switching reaches the second duration, control the clock gate to open so that the second clock signal enters the clock phase-locked loop.

[0154] Among them, in the above Figure 6During the clock switching process shown, the state of the chip is maintained by a state machine. The state and state description of each stage are shown in Table 1 below.

[0155] Table 1

[0156]

[0157] 404. Receive the reset signal sent by the host. The reset signal is sent after the frequency of the host's second clock signal has switched to a stable state.

[0158] After the chip is connected to the host, the host generates a second clock signal. Initially, the frequency of this second clock signal is unstable. Subsequently, the frequency of the second clock signal gradually stabilizes. After a period of stable operation, the host generates a reset signal and sends it to the chip. The chip receives this reset signal from the host, which is used to notify the chip to initiate the power-on process. Optionally, this reset signal is sent when the duration of the host's second clock signal being in a stable state reaches a third duration, for example, a minimum of 100 microseconds.

[0159] The first clock signal reaches a stable state earlier than the second clock signal. Therefore, the chip's processor and the controller and physical layer can be initialized before the chip receives a reset signal. That is, steps 401-403 are completed before step 404. Optionally, when the frequency of the first clock signal remains unchanged for a fourth duration, it is determined that the frequency of the first clock signal has reached a stable state; similarly, when the frequency of the second clock signal remains unchanged for a fourth duration, it is determined that the frequency of the second clock signal has reached a stable state.

[0160] 405. In response to the reset signal, the processor controls the clock phase-locked loop to perform frequency conversion on the second clock signal to obtain the frequency-converted second clock signal.

[0161] The operation of the controller and physical layer requires the host's second clock signal, which is a third-frequency clock signal, for example, 100MHz. The controller and physical layer, however, require a fourth-frequency second clock signal, such as 500MHz or 250MHz. Therefore, before providing the second clock signal to the controller and physical layer, the processor must control a clock phase-locked loop to perform a frequency conversion operation on the second clock signal, transforming the third-frequency second clock signal to the fourth-frequency second clock signal, thus obtaining the clock signal required for the operation of the controller and physical layer.

[0162] 406. Through the controller and physical layer, based on the frequency-converted second clock signal, the control chip enters the Detect state.

[0163] After receiving the frequency-converted second clock signal, the chip, through the initialized controller and physical layer, and the frequency-converted second clock signal, controls the chip to enter the Detect state. The Detect state, also known as the LTSSM (Link Training and Status State Machine) Detect state, is the initial state of Link Training.

[0164] It should be noted that the chip performs a power-on operation in response to a reset signal by executing steps 405-406. In this embodiment, the power-on operation includes frequency conversion of the second clock signal and controlling the chip to enter the Detect state. In another embodiment, the power-on operation of the chip may also include other operations.

[0165] It should be noted that, in one possible implementation, the power-on operation includes a first operation executed by the processor, which is used to execute the first operation in response to an operation instruction corresponding to the first operation. For example, the first operation refers to the frequency conversion operation of the control clock phase-locked loop on the second clock signal in step 405 above. Therefore, the power-on operation execution method in this embodiment further includes at least one of the following:

[0166] (1) The chip also includes other components besides the processor. When the power-on operation is performed, the chip controls the other components to stop sending operation instructions corresponding to other operations besides the first operation to the processor.

[0167] For example, other components include DMA (Direct Memory Access) or registers. To reduce the time consumed by the power-on operation, during the power-on operation, other components are controlled to stop sending operation instructions corresponding to operations other than the first operation to the processor. This ensures that the processor can only receive operation instructions corresponding to the first operation, thus preventing processor resources from being occupied by other operations and guaranteeing that the processor can execute the first operation in a timely manner. This reduces the time consumed by the processor to execute the first operation, thereby reducing the time consumed by the processor to execute the first operation, and consequently reducing the time consumed by the power-on operation.

[0168] (2) The processor responds to operation instructions according to priority, with the first operation corresponding to the highest priority operation instruction.

[0169] The chip's processor responds to each operation instruction in sequence according to the priority of the received operation instructions. Since the operation instruction corresponding to the first operation has the highest priority, the processor will respond to the operation instruction corresponding to the first operation first, thereby executing the first operation in the power-on operation in a timely manner, reducing the time consumed by the processor to execute the first operation, and thus reducing the time consumed by the power-on operation.

[0170] In related technologies, the chip uses the host's second clock signal to start the chip's processor and perform initialization operations on the controller and physical layer. Therefore, the chip will only start the chip's processor and perform initialization operations on the controller and physical layer after receiving a reset signal. The chip's power-on process includes the processor's startup process, the frequency conversion process of the second clock signal, the initialization process of the controller and physical layer, and the process of entering the Detect state. The chip's power-on process takes a long time, and there are cases where the power-on process does not meet the timing requirements. For example, the PCIe protocol requires that the power-on process take no more than 20 milliseconds. However, in practical applications, the processor startup process takes T0 = 11.53 milliseconds, the second clock signal frequency conversion process takes T1 = 0.84 milliseconds, the controller and physical layer initialization process takes T2 = 7.56 milliseconds, and the process of entering the Detect state takes T3 = 1.32 milliseconds. In addition, the power-on process also includes the time consumed by the processor configuration and response, which is T4 = 1 millisecond. Therefore, the total power-on time is T0 + T1 + T2 + T3 + T4 = 22.25 milliseconds, which exceeds the 20ms requirement of the PCIe protocol. As a result, there is a possibility that the chip may fail to power on properly on the host, causing the chip to malfunction.

[0171] In this embodiment, the chip uses a first clock signal to start the chip's processor and perform initialization operations on the controller and physical layer. Therefore, when the first clock signal is stable, the chip's processor can be started and the controller and physical layer can be initialized without waiting for a reset signal to be received. Thus, the chip's power-on process only includes the frequency conversion process of the second clock signal and the process of entering the Detect state, thereby reducing the time consumed by the chip's power-on process.

[0172] Figure 7 This is a timing diagram of a power-on operation execution method provided in an embodiment of this application, as shown below. Figure 7As shown, time s0 represents the moment the chip connects to the host. Starting from time s0, the chip's board-level power rail begins to transform to 1.8V, providing ASIC power to the chip. After the transformation is complete, the power-ready signal goes high. The time consumed from the chip connecting to the host to the power-ready signal going high is approximately 20 milliseconds. Before the power-ready signal goes high, the frequency of the first clock signal provided to the chip by the board-level crystal oscillator stabilizes at 100MHz.

[0173] like Figure 7 As shown, when the frequency of the first clock signal stabilizes at 100MHz, the ARM Core Bootloader starts the processor by loading the boot program. The time consumed by starting the processor is T0. When the processor has finished starting, the SerDes driver is loaded by the processor to initialize the controller and physical layer. The time consumed by initializing the controller and physical layer is T2. When the controller and physical layer initialization is complete, the clock signal of the controller and physical layer is switched from the first clock signal to the second clock signal ARM Core. At this time, the preparation work before the chip power-on operation is completed.

[0174] like Figure 7 As shown, when the host's second clock signal remains stable for 100 microseconds, the host generates a reset signal and sends it to the chip. Time s1 represents the moment the reset signal is generated. At this time, the ARM Core controls the clock phase-locked loop to perform a frequency conversion operation on the second clock signal, resulting in a frequency-converted second clock signal. The time consumed by this frequency conversion operation is T1. Upon receiving the frequency-converted second clock signal, the controller and physical layer control the chip to enter the Detect state. The time consumed by entering the Detect state is T3. The process from the chip receiving the reset signal to the chip entering the Detect state is the chip's power-on process.

[0175] In practical applications, T1 = 0.84 milliseconds, T3 = 1.32 milliseconds, and the power-on process also includes the time consumed by the processor configuration and response, which is T4 = 1 millisecond. Therefore, in this embodiment, the power-on process takes T1 + T3 + T4 = 3.16 milliseconds, which fully meets the 20ms requirement of the PCIe protocol.

[0176] The method provided in this application starts the chip's processor when the frequency of the chip's first clock signal switches to a stable state, and performs initialization operations on the controller and physical layer after the processor starts. When the frequency of the host's second clock signal switches to a stable state, the chip receives a reset signal and performs a power-on operation in response to the reset signal. Since the time point when the frequency of the first clock signal switches to a stable state is earlier than the time point when the second clock signal switches to a stable state, it is equivalent to advancing the processor startup process and the controller and physical layer initialization process to before receiving the reset signal. Therefore, there is no need to perform the operation of starting the processor and initializing the controller and physical layer during the power-on process, thereby shortening the time consumed by the chip's power-on process.

[0177] Furthermore, by shortening the time consumed by the chip's power-on operation, the timing requirements of the power-on process can be guaranteed, thereby ensuring the normal operation of the chip and improving the chip's adaptability to different hosts.

[0178] Furthermore, when switching clock signals, the first clock signal entering the clock phase-locked loop is switched to the second clock signal only after the first clock signal stops entering the clock phase-locked loop for a certain duration. The clock gating is then reopened only after the second duration has elapsed since the first clock signal entering the clock gating was switched to the second clock signal. This avoids clock glitches during the clock signal switching process.

[0179] Furthermore, during the power-on operation, other components are controlled to stop sending operation instructions corresponding to operations other than the first operation to the processor. This ensures that the processor can only receive operation instructions corresponding to the first operation, thus preventing the processor's resources from being occupied by other operations. This guarantees that the processor can execute the first operation in a timely manner, thereby reducing the time consumed by the processor in executing the first operation and consequently reducing the time consumed by the power-on operation.

[0180] Furthermore, the processor prioritizes responding to the operation instruction corresponding to the first operation, thereby executing the first operation in the power-on operation in a timely manner, reducing the time consumed by the processor in executing the first operation, and thus reducing the time consumed by the power-on operation.

[0181] Figure 4 In one embodiment, the processor startup process and the controller and physical layer initialization process are moved forward to before the reset signal is received, thereby reducing the time consumed by the power-on operation. In another embodiment, only the processor startup process can be moved forward to before the reset signal is received, while the controller and physical layer initialization processes are still performed as part of the power-on process after the reset signal is received. Details are as follows. Figure 8 Examples of implementations.

[0182] Figure 8 This is a flowchart illustrating another power-on operation execution method provided in this application embodiment. The execution subject in this application embodiment is a chip; see [link to relevant documentation]. Figure 8 The method includes:

[0183] 801. After the chip is connected to the host, when the frequency of the chip's first clock signal switches to a stable state, the chip's processor is started.

[0184] The processor startup process in step 801 is the same as the processor startup process in step 401 above, and will not be described again here.

[0185] 802. Receive the reset signal sent by the host. The reset signal is sent after the frequency of the host's second clock signal has switched to a stable state.

[0186] The time point at which the frequency of the first clock signal switches to a stable state is earlier than the time point at which the second clock signal switches to a stable state. The process of receiving the reset signal in step 801 is the same as the process of receiving the reset signal in step 404 above, and will not be described again here.

[0187] 803. In response to the reset signal, the processor controls the clock phase-locked loop to perform frequency conversion on the second clock signal to obtain the frequency-converted second clock signal.

[0188] The controller and the physical layer are connected by a clock phase-locked loop. The process of frequency conversion of the second clock signal in step 803 is the same as the process of frequency conversion of the second clock signal in step 405 above, and will not be described again here.

[0189] 804. The processor performs initialization operations on the controller and physical layer.

[0190] The chip includes a controller and a physical layer. In response to a reset signal sent by the host, the chip initializes the controller and physical layer through the processor based on the frequency-converted second clock signal.

[0191] The initialization process for the controller and physical layer in step 804 differs from that in step 402 in that the timing of the initialization and the clock signal used are different. In step 402, the initialization of the controller and physical layer occurs after the processor has finished booting up. At this point, the chip's first clock signal is stable, but the host's second clock signal is not yet stable. Therefore, the initialization of the controller and physical layer is based on this first clock signal and is not part of the power-on process. However, in step 804, the initialization of the controller and physical layer occurs after the second clock signal has been frequency-converted. Since the frequency-converted second clock signal is already available, the initialization of the controller and physical layer is directly based on this frequency-converted second clock signal, and this initialization is part of the power-on process.

[0192] In addition, the process of initializing the controller and physical layer in step 804 is the same as the process of initializing the controller and physical layer in step 402 above, and will not be repeated here.

[0193] 805. Through the controller and physical layer, based on the second clock signal after frequency conversion, the control chip enters the Detect state.

[0194] The process of the control chip entering the Detect state in step 805 is the same as the process of the control chip entering the Detect state in step 406 above, and will not be repeated here.

[0195] It should be noted that, taking steps 803-805 above as an example, this embodiment illustrates that the chip, in response to a reset signal, performs a frequency conversion operation on the second clock signal through the processor to obtain a frequency-converted second clock signal, initializes the chip through the processor, and controls the chip to enter the Detect state based on the frequency-converted second clock signal. Besides this, the chip can also use other methods to perform frequency conversion on the second clock signal or use other methods to control the chip to enter the Detect state; this embodiment does not limit this approach.

[0196] It should be noted that, in one possible implementation, the power-on operation includes a first operation executed by the processor, which is used to execute the first operation in response to an operation instruction corresponding to the first operation. For example, the first operation refers to the frequency conversion operation of the control clock phase-locked loop on the second clock signal in step 803 above. Therefore, the power-on operation execution method in this embodiment further includes at least one of the following:

[0197] (1) The chip also includes other components besides the processor. When the power-on operation is performed, the chip controls the other components to stop sending operation instructions corresponding to other operations besides the first operation to the processor.

[0198] (2) The processor responds to operation instructions according to priority, with the first operation corresponding to the highest priority operation instruction.

[0199] The method provided in this application starts the chip's processor when the frequency of the chip's first clock signal switches to a stable state. When the frequency of the host's second clock signal switches to a stable state, the chip receives a reset signal and performs a power-on operation in response to the reset signal. Since the time point when the frequency of the first clock signal switches to a stable state is earlier than the time point when the second clock signal switches to a stable state, it is equivalent to advancing the processor's startup process to before receiving the reset signal. Therefore, there is no need to perform the processor startup operation during the power-on process, thereby shortening the time consumed by the chip's power-on process.

[0200] Furthermore, by shortening the time consumed by the chip's power-on operation, the timing requirements of the power-on process can be guaranteed, thereby ensuring the normal operation of the chip and improving the chip's adaptability to different hosts.

[0201] Furthermore, during the power-on operation, other components are controlled to stop sending operation instructions corresponding to operations other than the first operation to the processor. This ensures that the processor can only receive operation instructions corresponding to the first operation, thus preventing the processor's resources from being occupied by other operations. This guarantees that the processor can execute the first operation in a timely manner, thereby reducing the time consumed by the processor in executing the first operation and consequently reducing the time consumed by the power-on operation.

[0202] Furthermore, the processor prioritizes responding to the operation instruction corresponding to the first operation, thereby executing the first operation in the power-on operation in a timely manner, reducing the time consumed by the processor in executing the first operation, and thus reducing the time consumed by the power-on operation.

[0203] Figure 9 This is a flowchart illustrating another power-on operation execution method provided in this application embodiment. The execution subject in this application embodiment is an electronic device, which includes a chip and a processor. See [link to relevant documentation]. Figure 9 The method includes:

[0204] 901. After the chip is connected to the host, when the frequency of the chip's first clock signal switches to a stable state, the chip's processor is started.

[0205] The processor startup process in step 901 is the same as the processor startup process in step 401 above, and will not be described again here.

[0206] 902. After the frequency of the host's second clock signal is switched to a stable state, a reset signal is sent from the host to the processor.

[0207] After the chip is connected to the host, the host generates a second clock signal. Initially, the frequency of this second clock signal is unstable. Subsequently, the frequency of the second clock signal gradually stabilizes. After a period of time in a stable state, the host generates a reset signal and sends this reset signal to the chip.

[0208] In one possible implementation, a reset signal is sent from the host to the processor when the duration of the second clock signal's stable state reaches a third duration. When the duration of the second clock signal's stable state reaches the third duration, a reset signal is generated on the host, and the electronic device sends this reset signal to the chip via the host. Optionally, the chip is a PCIe chip, the host is a PCIe host, and the third duration is specified by the PCIe protocol, for example, the minimum third duration is 100 microseconds.

[0209] The time point at which the frequency of the first clock signal switches to a stable state is earlier than the time point at which the frequency of the second clock signal switches to a stable state.

[0210] 903. The processor receives a reset signal and, in response to the reset signal, performs a power-on operation.

[0211] Electronic devices receive a reset signal sent by the host through the chip's processor. This reset signal is used to notify the chip to start the power-on process. The chip then responds to the reset signal and performs a power-on operation.

[0212] The process of powering on the chip in step 903 is the same as that in steps 803-805, and will not be described again here. Alternatively, after the electronic device starts the chip's processor, it initializes the controller and physical layer through the processor. When the controller and physical layer initialization is complete, the second clock signal is determined to be the clock signal after the controller and physical layer have been replaced. In this case, the process of powering on the chip in step 903 is the same as that in steps 405-406, and will not be described again here.

[0213] The method provided in this application starts the chip's processor when the frequency of the chip's first clock signal switches to a stable state. When the frequency of the host's second clock signal switches to a stable state, the chip receives a reset signal and performs a power-on operation in response to the reset signal. Since the time point when the frequency of the first clock signal switches to a stable state is earlier than the time point when the second clock signal switches to a stable state, it is equivalent to advancing the processor's startup process to before receiving the reset signal. Therefore, there is no need to perform the processor startup operation during the power-on process, thereby shortening the time consumed by the chip's power-on process.

[0214] Figure 10 This is a schematic diagram of the structure of a power-on operation execution device provided in an embodiment of this application. See also... Figure 10 The device includes:

[0215] The startup module 1001 is used to start the chip's processor when the frequency of the chip's first clock signal switches to a stable state after the chip is connected to the host.

[0216] The signal receiving module 1002 is used to receive the reset signal sent by the host. The reset signal is sent after the frequency of the host's second clock signal switches to a stable state.

[0217] Power-on module 1003 is used to perform a power-on operation in response to a reset signal;

[0218] The time point at which the frequency of the first clock signal switches to a stable state is earlier than the time point at which the frequency of the second clock signal switches to a stable state.

[0219] The power-on operation execution device provided in this application starts the chip's processor when the frequency of the chip's first clock signal switches to a stable state. When the frequency of the host's second clock signal switches to a stable state, the chip receives a reset signal and performs a power-on operation in response to the reset signal. Since the time point when the frequency of the first clock signal switches to a stable state is earlier than the time point when the second clock signal switches to a stable state, it is equivalent to advancing the processor's startup process to before receiving the reset signal. Therefore, there is no need to perform the processor startup operation during the power-on process, thereby shortening the time consumed by the chip's power-on process.

[0220] Optionally, see Figure 11 The device also includes:

[0221] Initialization module 1004 is used to perform chip initialization operations through the processor.

[0222] Optionally, see Figure 11 The chip includes a controller and a physical layer. The initialization module 1004 is used to perform initialization operations on the controller and physical layer through the processor.

[0223] Optionally, the initialization module 1004 is used to perform initialization operations on the controller and physical layer via the processor based on a first clock signal.

[0224] Optionally, see Figure 11 The initialization module 1004 includes:

[0225] The first frequency conversion unit 1014 is used to perform frequency conversion operation on the first clock signal to obtain the frequency-converted first clock signal.

[0226] The first initialization unit 1024 is used to perform initialization operations on the controller and physical layer through the processor based on the first clock signal after frequency conversion.

[0227] Optionally, see Figure 11 During the initialization of the controller and physical layer, the clock signals for the controller and physical layer are the first clock signals; the device also includes:

[0228] The clock switching module 1005 is used to determine the second clock signal as the clock signal after the controller and physical layer have been replaced when the controller and physical layer initialization is completed.

[0229] Optionally, see Figure 11 The controller and the physical layer are connected to a clock phase-locked loop. The clock switching module 1005 is used to control the first clock signal to stop entering the clock phase-locked loop and to control the second clock signal to enter the clock phase-locked loop when the controller and the physical layer are initialized.

[0230] Optionally, see Figure 11 The clock phase-locked loop is connected to a clock gating system. The first clock signal enters the clock phase-locked loop through the clock gating system. The clock switching module 1005 is used for:

[0231] Turn off the clock gating to stop the first clock signal from entering the clock phase-locked loop;

[0232] If the time elapsed after the first clock signal stops entering the clock phase-locked loop reaches the first time elapsed, the first clock signal entering the clock gate will be switched to the second clock signal.

[0233] If the duration after switching the first clock signal to the second clock signal that enters the clock gating reaches the second duration, the clock gating is opened so that the second clock signal enters the clock phase-locked loop.

[0234] Optionally, see Figure 11 The controller and physical layer are connected by a clock phase-locked loop. The power-on module 1003 includes:

[0235] The second frequency conversion unit 1013 is used to respond to the reset signal and control the clock phase-locked loop to perform frequency conversion operation on the second clock signal through the processor to obtain the frequency-converted second clock signal.

[0236] The state entry unit 1023 is used to control the chip to enter the detection state based on the frequency-converted second clock signal through the controller and physical layer.

[0237] Optionally, see Figure 11 Power-on module 1003 includes:

[0238] The second frequency conversion unit 1013 is used to respond to the reset signal by performing a frequency conversion operation on the second clock signal through the processor to obtain the frequency-converted second clock signal.

[0239] The second initialization unit 1033 is used to perform initialization operations on the chip through the processor;

[0240] The state entry unit 1023 is used to control the chip to enter the Detect state based on the second clock signal after frequency conversion.

[0241] Optionally, see Figure 11 The chip envelopes the controller and the physical layer, and the controller and the physical layer are connected to a clock phase-locked loop; the second frequency conversion unit 1013 is used to control the clock phase-locked loop to perform frequency conversion on the second clock signal through the processor to obtain the frequency-converted second clock signal.

[0242] The second initialization unit 1033 is used to perform initialization operations on the controller and physical layer through the processor;

[0243] The state entry unit 1023 is used to control the chip to enter the Detect state based on the frequency-converted second clock signal through the controller and physical layer.

[0244] Optionally, see Figure 11 The power-on operation includes a first operation performed by the processor, which is used to execute the first operation in response to an operation instruction corresponding to the first operation; the device also includes an instruction control module 1006, which is used to perform at least one of the following:

[0245] The chip also includes other components besides the processor. When the power-on operation is performed, the other components are controlled to stop sending operation instructions corresponding to operations other than the first operation to the processor.

[0246] The processor responds to operation instructions according to priority, with the first operation corresponding to the highest priority instruction.

[0247] It should be noted that the power-on operation execution device provided in the above embodiments is only illustrated by the division of the above functional modules when performing the power-on operation. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the chip can be divided into different functional modules to complete all or part of the functions described above. In addition, the power-on operation execution device and the power-on operation execution method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0248] Figure 12 This is a schematic diagram of another power-on operation execution device provided in an embodiment of this application. See also... Figure 12 The device includes:

[0249] The startup module 1201 is used to start the chip's processor when the frequency of the chip's first clock signal switches to a stable state after the chip is connected to the host.

[0250] The signal transmission module 1202 is used to send a reset signal to the processor through the host after the frequency of the host's second clock signal has switched to a stable state;

[0251] The power-on module 1203 is used to receive a reset signal through the processor and perform a power-on operation in response to the reset signal;

[0252] The time point at which the frequency of the first clock signal switches to a stable state is earlier than the time point at which the frequency of the second clock signal switches to a stable state.

[0253] The power-on operation execution device provided in this application starts the chip's processor when the frequency of the chip's first clock signal switches to a stable state. When the frequency of the host's second clock signal switches to a stable state, the chip receives a reset signal and performs a power-on operation in response to the reset signal. Since the time point when the frequency of the first clock signal switches to a stable state is earlier than the time point when the second clock signal switches to a stable state, it is equivalent to advancing the processor's startup process to before receiving the reset signal. Therefore, there is no need to perform the processor startup operation during the power-on process, thereby shortening the time consumed by the chip's power-on process.

[0254] Optionally, the signal transmitting module 1202 is used to send a reset signal to the processor through the host when the duration of the second clock signal being in a stable state reaches a third duration.

[0255] It should be noted that the power-on operation execution device provided in the above embodiments is only illustrated by the division of the above functional modules when performing a power-on operation. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the electronic device can be divided into different functional modules to complete all or part of the functions described above. In addition, the power-on operation execution device and the power-on operation execution method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0256] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0257] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present application should be included within the protection scope of the present application.

Claims

1. A power-on operation execution method, characterized in that, The method includes: After the chip is connected to the host, a first clock signal is generated on the chip, and the frequency of the first clock signal is unstable. When the frequency of the first clock signal of the chip switches from an unstable state to a stable state, the processor of the chip is started. The system receives a reset signal sent by the host. The reset signal is sent after the frequency of the host's second clock signal switches from an unstable state to a stable state. The second clock signal is generated on the host after the chip is connected to the host. In response to the reset signal, a power-on operation is performed; The time point at which the frequency of the first clock signal switches to a stable state is earlier than the time point at which the second clock signal switches to a stable state.

2. The method according to claim 1, characterized in that, Before receiving the reset signal sent by the host, the method further includes: The processor performs initialization operations on the chip.

3. The method according to claim 2, characterized in that, The chip includes a controller and a physical layer. The initialization operation of the chip through the processor includes: The processor performs initialization operations on the controller and the physical layer.

4. The method according to claim 3, characterized in that, The initialization operation of the controller and the physical layer through the processor includes: The processor performs initialization operations on the controller and the physical layer based on the first clock signal.

5. The method according to claim 4, characterized in that, The initialization operation of the controller and the physical layer by the processor based on the first clock signal includes: The first clock signal is frequency-converted to obtain the frequency-converted first clock signal; The processor performs initialization operations on the controller and the physical layer based on the frequency-converted first clock signal.

6. The method according to claim 3, characterized in that, When initializing the controller and the physical layer, the clock signals of the controller and the physical layer are the first clock signal; the method further includes: When the controller and the physical layer are initialized, the second clock signal is determined to be the clock signal after the controller and the physical layer have been replaced.

7. The method according to claim 6, characterized in that, The controller and the physical layer are connected by a clock phase-locked loop. The step of determining the second clock signal as the replaced clock signal for the controller and the physical layer upon completion of controller and physical layer initialization includes: When the controller and the physical layer are initialized, the first clock signal is stopped from entering the clock phase-locked loop, and the second clock signal is controlled to enter the clock phase-locked loop.

8. The method according to claim 7, characterized in that, The clock phase-locked loop is connected to a clock gating system. The first clock signal enters the clock phase-locked loop through the clock gating system. Controlling the first clock signal to stop entering the clock phase-locked loop and controlling the second clock signal to enter the clock phase-locked loop includes: Close the clock gating to stop the first clock signal from entering the clock phase-locked loop; If the duration after the first clock signal stops entering the clock phase-locked loop reaches a first duration, the first clock signal entering the clock gating will be switched to the second clock signal; If the time elapsed after the first clock signal entering the clock gate is switched to the second clock signal reaches a second duration, the clock gate is opened so that the second clock signal enters the clock phase-locked loop.

9. The method according to claim 3, characterized in that, The controller and the physical layer are connected by a clock-locked loop. The power-on operation, performed in response to the reset signal, includes: In response to the reset signal, the processor controls the clock phase-locked loop to perform a frequency conversion operation on the second clock signal to obtain a frequency-converted second clock signal; Based on the frequency-converted second clock signal, the controller and the physical layer control the chip to enter the Detect state.

10. The method according to claim 1, characterized in that, The power-on operation in response to the reset signal includes: In response to the reset signal, the processor performs a frequency conversion operation on the second clock signal to obtain a frequency-converted second clock signal; The processor performs initialization operations on the chip. Based on the frequency-converted second clock signal, the chip is controlled to enter the Detect state.

11. The method according to claim 10, characterized in that, The chip envelope controller and physical layer are connected to a clock phase-locked loop; The step of performing a frequency conversion operation on the second clock signal through the processor to obtain a frequency-converted second clock signal includes: The processor controls the clock phase-locked loop to perform a frequency conversion operation on the second clock signal to obtain the frequency-converted second clock signal; The initialization operation of the chip via the processor includes: The processor performs initialization operations on the controller and the physical layer. The second clock signal after frequency conversion controls the chip to enter the Detect state, including: Based on the frequency-converted second clock signal, the controller and the physical layer control the chip to enter the Detect state.

12. The method according to any one of claims 1-11, characterized in that, The power-on operation includes a first operation performed by the processor, the processor being configured to execute the first operation in response to an operation instruction corresponding to the first operation; the method further includes at least one of the following: The chip also includes other components besides the processor. When the power-on operation is performed, the other components are controlled to stop sending operation instructions corresponding to other operations besides the first operation to the processor. The processor responds to operation instructions according to priority, with the operation instruction corresponding to the first operation having the highest priority.

13. A method for performing a power-on operation, characterized in that, Performed by an electronic device, the electronic device including a chip and a host, the method includes: After the chip is connected to the host, a first clock signal is generated on the chip and a second clock signal is generated on the host. The frequencies of the first clock signal and the second clock signal are in an unstable state. When the frequency of the first clock signal of the chip switches from an unstable state to a stable state, the processor of the chip is started. After the frequency of the host's second clock signal switches from an unstable state to a stable state, the host sends a reset signal to the processor. The processor receives the reset signal and, in response to the reset signal, performs a power-on operation. The time point at which the frequency of the first clock signal switches to a stable state is earlier than the time point at which the second clock signal switches to a stable state.

14. The method according to claim 13, characterized in that, After the frequency of the second clock signal of the host switches from an unstable state to a stable state, the step of sending a reset signal to the processor through the host includes: When the duration of the second clock signal being in a stable state reaches a third duration, the host sends the reset signal to the processor.

15. A power-on operation actuator, characterized in that, The device includes: The startup module is used to generate a first clock signal on the chip after the chip is connected to the host. The frequency of the first clock signal is unstable. The startup module is also used to start the processor of the chip when the frequency of the first clock signal of the chip switches from an unstable state to a stable state; The signal receiving module is used to receive a reset signal sent by the host. The reset signal is sent after the frequency of the host's second clock signal switches from an unstable state to a stable state. The second clock signal is generated on the host after the chip is connected to the host. The power-on module is used to perform a power-on operation in response to the reset signal; The time point at which the frequency of the first clock signal switches to a stable state is earlier than the time point at which the second clock signal switches to a stable state.

16. A power-on operation actuator, characterized in that, The device includes: The startup module is used to generate a first clock signal on the chip and a second clock signal on the host after the chip is connected to the host. The frequencies of the first clock signal and the second clock signal are in an unstable state. The startup module is also used to start the processor of the chip when the frequency of the first clock signal of the chip switches from an unstable state to a stable state; The signal transmission module is used to send a reset signal to the processor through the host after the frequency of the host's second clock signal switches from an unstable state to a stable state; The power-on module is used to receive the reset signal through the processor and, in response to the reset signal, perform a power-on operation. The time point at which the frequency of the first clock signal switches to a stable state is earlier than the time point at which the second clock signal switches to a stable state.

17. A chip, characterized in that, The chip includes at least one computer program that, when the chip is running on an electronic device, performs the operations executed by the power-on operation execution method as described in any one of claims 1 to 12.

18. An electronic device, characterized in that, The electronic device includes a chip and a host; The chip is used to generate a first clock signal on the chip after the chip is connected to the host, and the frequency of the first clock signal is in an unstable state. The host is used to generate a second clock signal on the host after the chip is connected to the host, and the frequency of the second clock signal is in an unstable state. The chip is also used to start the chip's processor when the frequency of the chip's first clock signal switches from an unstable state to a stable state; The host is also configured to send a reset signal to the processor after the frequency of the host's second clock signal switches from an unstable state to a stable state; The chip is also configured to receive the reset signal via the processor and, in response to the reset signal, perform a power-on operation. The time point at which the frequency of the first clock signal switches to a stable state is earlier than the time point at which the second clock signal switches to a stable state.

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