Method of forming a power semiconductor device

Abstract

A method of forming a power semiconductor device includes providing a semiconductor substrate having an active region and a termination region surrounding the active region. An epitaxial layer is disposed on the semiconductor substrate. An etching process is performed on the epitaxial layer to form a first trench disposed in the active region and a second trench disposed in the termination region. A second trench width of the second trench is less than a first trench width of the first trench. An oxidation process is performed to form a dielectric structure having a first dielectric layer disposed in the first trench and a dielectric region completely covering a trench region of the second trench.

Description

Technical Field

[0001] This invention relates to a method for forming a power semiconductor device, and more particularly to a method for forming a dielectric structure that completely covers the trench region of the cutoff region of the power semiconductor device. Background Technology

[0002] Power semiconductor devices include insulated-gate bipolar transistors (IGBTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs). These devices are used in power management, such as power controllers, switching circuits, and power supplies. Power semiconductor devices are designed to withstand high voltages; therefore, the active components can be driven by high currents. To prevent voltage breakdown or channeling effects, these devices utilize cutoff structures to avoid these problems.

[0003] In existing power semiconductor devices, the cutoff structure typically consists of localized oxidation of silicon or a shielding electrode surrounding the active component. However, existing cutoff structures have several drawbacks. Localized oxidation of silicon requires the formation of doped regions to mitigate high electric fields, necessitating additional ion implantation processes, which can complicate the manufacturing process. Forming a shielding electrode in a trench as a protective structure offers another solution for the cutoff structure; however, the shielding electrode needs sufficient width, depth, or length to achieve the desired performance, characteristics that are easily affected by process variations during its formation. Therefore, existing manufacturing processes still present significant challenges.

[0004] As electronic devices become increasingly smaller, power transistor devices may also face size limitations. When using shielding electrodes as cutoff structures, there may not be enough space in the surrounding area to accommodate such electrode structures. Size issues can become a significant problem when fabricating power semiconductor devices.

[0005] In summary, there are still many problems with the fabrication methods of power semiconductor devices. Therefore, the present invention provides a method for forming a power semiconductor device, which solves the deficiencies of the prior art and enhances its practical application in industry. Summary of the Invention

[0006] To address the problems of the prior art, the present invention aims to provide a method for forming a power semiconductor device that can maintain a high breakdown voltage of the power semiconductor device in a relatively small device configuration.

[0007] According to one objective of the present invention, a method for forming a power semiconductor device is provided, comprising the following steps: providing a semiconductor substrate having an active region and a cutoff region surrounding the active region; disposing an epitaxial layer on the semiconductor substrate; etching the epitaxial layer to form a first trench and a second trench, the first trench being disposed in the active region and a junction region located between the active region and the cutoff region, the second trench being disposed in the cutoff region, wherein the width of the second trench is smaller than the width of the first trench; performing an oxidation process to form a dielectric structure having a first dielectric layer disposed in the first trench and a dielectric region completely covering the trench region of the second trench.

[0008] Preferably, the method may further include the following steps: setting a shielding electrode in the trench space formed by the first dielectric layer and etching the shielding electrode in the active region; performing oxide deposition to form a second dielectric layer covering the shielding electrode; etching the second dielectric layer in the active region and setting a gate electrode on the first trench in the active region; forming a doped region between the gate electrodes; performing oxide deposition to form a third dielectric layer covering the active region and the cutoff region; forming a metal layer on the third dielectric layer, the metal layer contacting the doped region through contact holes.

[0009] Preferably, the dielectric region may have a patterned shape at the bottom of the dielectric region, the patterned shape corresponding to the bottom shape of the second trench.

[0010] Preferably, the pattern shape may include a continuous wave shape or a continuous wavy shape.

[0011] Preferably, the width of the first trench is approximately 1.2-1.5µm and the width of the second trench is approximately 0.9-1.1µm.

[0012] Preferably, the first trench may have a first trench depth and the second trench may have a second trench depth, wherein the second trench depth is less than the first trench depth.

[0013] Preferably, the depth of the first trench and the depth of the second trench can be approximately 1-50µm.

[0014] Preferably, the cutoff region may have a cutoff length of approximately 1-200µm.

[0015] Preferably, the dielectric region may contain silicon dioxide.

[0016] Preferably, the epitaxial layer can be a lightly doped N-type layer, and the doped region can be a heavily doped N-type region.

[0017] According to one objective of the present invention, a method for forming a power semiconductor device is provided, comprising the following steps: providing a semiconductor substrate having an active region, a cutoff region adjacent to the active region, and a trench ring region surrounding the active region and the cutoff region; disposing an epitaxial layer on the semiconductor substrate; etching the epitaxial layer to form a first trench, a second trench, and a third trench, wherein the first trench is disposed in the active region and a junction region located between the active region and the cutoff region, the second trench is disposed in the cutoff region, and the third trench is disposed in the trench ring region, wherein the second trench width of the second trench is smaller than the first trench width of the first trench; performing an oxidation process to form a dielectric structure, the dielectric structure having a first dielectric layer disposed in the first trench and the third trench and a dielectric region completely covering the trench region of the second trench.

[0018] Preferably, the method may further include the following steps: disposing a shielding electrode in a first trench space and a second trench space, the first trench space being formed by a first dielectric layer in a first trench, and the second trench space being formed by a first dielectric layer in a third trench; etching the shielding electrode in the active region; performing oxide deposition to form a second dielectric layer covering the shielding electrode; etching the second dielectric layer in the active region and disposing a gate electrode on the first trench in the active region; forming a doped region between the gate electrodes; performing oxide deposition to form a third dielectric layer covering the active region, the cutoff region, and the trench ring region; and forming a metal layer on the third dielectric layer, the metal layer contacting the doped region through contact holes.

[0019] Preferably, the dielectric region may have a patterned shape at the bottom of the conductive region, the patterned shape corresponding to the bottom shape of the second trench.

[0020] Preferably, the pattern shape may include a continuous wave shape or a continuous wavy shape.

[0021] Preferably, the width of the first trench is approximately 1.2-1.5 µm and the width of the second trench is approximately 0.9-1.1 µm.

[0022] Preferably, the width of the third groove can be greater than the width of the second groove, and the width of the third groove is approximately 1.2-1.5µm.

[0023] Preferably, the first trench may have a first trench depth, the second trench may have a second trench depth, and the third trench may have a third trench depth, wherein the second trench depth is less than the first trench depth or the third trench depth.

[0024] Preferably, the depth of the first trench and the depth of the third trench can be approximately 1-50 µm.

[0025] Preferably, the cutoff region may have a cutoff length of approximately 1-200 µm.

[0026] Preferably, the dielectric region may contain silicon dioxide.

[0027] As described above, the method for forming a power semiconductor device according to the present invention can have the following beneficial effects:

[0028] 1. The method of forming a power semiconductor device can improve the stability of the maintenance electric field in the cut-off region of the power semiconductor by maintaining the breakdown voltage in the dielectric region that is completely covered by the cut-off region.

[0029] 2. The method of forming a power semiconductor device can reduce the cutoff length of the power semiconductor device, and thus reduce the overall size of the power semiconductor device.

[0030] 3. The method for forming power semiconductor devices can form dielectric regions through the same oxidation process without adding additional processes, reducing the sensitivity to placement variations. Attached Figure Description

[0031] To make the technical features, detailed structure, advantages, and effects of the present invention more apparent, the present invention will be described in conjunction with the embodiments described in the following figures:

[0032] Figure 1 This is a schematic diagram of a power semiconductor device according to an embodiment of the present invention;

[0033] Figures 2A to 2C This is a schematic diagram of a manufacturing process for forming a power semiconductor device according to an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of the three-dimensional structure of a power semiconductor device according to an embodiment of the present invention;

[0035] Figures 4A to 4F This is a schematic diagram of a manufacturing process for forming a power semiconductor device according to an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of the three-dimensional structure of a power semiconductor device according to an embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of a power semiconductor device according to another embodiment of the present invention;

[0038] Figures 7A to 7I This is a schematic diagram illustrating a manufacturing process for forming a power semiconductor device according to another embodiment of the present invention;

[0039] Figure 8A and Figure 8B This is a schematic diagram of the three-dimensional structure of a power semiconductor device according to another embodiment of the present invention.

[0040] 11, 21, 31, 41, 51: Semiconductor substrate

[0041] 12, 22, 32, 42, 52: Epitaxial layers

[0042] 13, 23, 33, 43A, 53A: First trench

[0043] 14, 44: Second trench

[0044] 15, 25, 35, 45, 55: First dielectric layer

[0045] 16, 26, 36, 46, 56: Dielectric regions

[0046] 17, 37, 47, 57: Shielding electrodes

[0047] 18, 38, 48, 58: Gate electrodes

[0048] 19, 39, 49, 59: Doped regions

[0049] 43B, 53B: Third trench

[0050] 100, 200, 300, 400: Power semiconductor devices

[0051] 151, 251, 351, 451, 551: Trench space

[0052] 152, 352, 452, 552: Second dielectric layer

[0053] 153, 453: Third dielectric layer

[0054] 161, 261, 361, 461, 561: Pattern shapes

[0055] 191, 491: Contact holes

[0056] 192, 492: Metallic layer

[0057] AR: Active Zone

[0058] AR1: First Active Zone

[0059] AR2: Second Active Zone

[0060] A-A', B-B': Cross-section

[0061] CL: Connecting lines

[0062] CS: Corner Structure

[0063] DA: Dielectric region

[0064] D1: Depth of the first trench

[0065] D2: Second trench depth

[0066] D3: Third trench depth

[0067] GP: Gate pad

[0068] JR: Interface Area

[0069] L: Cutoff length

[0070] RR: Trench Circumferential Region

[0071] RS: Repeating structure

[0072] T: Active trench

[0073] TR: Termination Zone

[0074] W1: Width of the first groove

[0075] W2: Width of the second groove

[0076] W3: Width of the third groove Detailed Implementation

[0077] To understand the technical features, content, advantages, and effects of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and in the form of embodiments. The drawings used are for illustration and auxiliary purposes only and may not represent the actual proportions and precise configurations after the implementation of the present invention. Therefore, the proportions and configurations of the accompanying drawings should not be used to interpret or limit the scope of the present invention in actual implementation.

[0078] Those skilled in the art will understand that the described embodiments can be adapted in other different ways, and the exemplary embodiments of the present invention are for explanation and understanding only. The drawings and descriptions are illustrative in nature and not limiting. The same or similar reference numerals refer to the same or similar components in the specification.

[0079] Throughout this specification, it should be understood that although the terms “first,” “second,” and “third” may be used herein to describe various components, these components should not be limited by these terms, which are intended to indicate the distinction between one component and another. Therefore, the term “or” includes any and all combinations of all relevant listed items.

[0080] It should be understood that when a component is referred to as "on another component or layer," or "connected to," or "coupled to," it can be directly on, directly connected to, or directly coupled to another component or layer, or there may be intermediate components or layers in between. Conversely, when a component is referred to as "directly on another component or layer," or "directly connected to," or "directly coupled to," there are no intermediate components or layers.

[0081] Please see Figure 1 This is a schematic diagram of a power semiconductor device according to an embodiment of the present invention. Figure 1 A top view of a power semiconductor device 100 is shown. The power semiconductor device 100 includes an active region AR and a cutoff region TR, with the cutoff region TR surrounding the active region AR. Since the power semiconductor device 100 is designed to withstand high voltages, the active region AR can be driven by high current. To prevent voltage breakdown or other channeling effects, the cutoff region TR is positioned around the active region AR to prevent such effects. The cutoff region TR also isolates the device from influences from external components.

[0082] The active region AR includes multiple active trenches T, in which shielding electrodes and gate electrodes are disposed. The cutoff region TR may comprise several trenches fabricated using the same process as the active trenches T. In this invention, a dielectric region DA completely covers the trench regions of the cutoff region TR. The dielectric region DA surrounds the active region AR to maintain the electric field in the cutoff region TR and reduce process variability sensitivity to breakdown voltage. The dielectric region DA completely covers a dielectric material, such as silicon dioxide. Detailed structure and fabrication methods of the power semiconductor device 100 will be further described in subsequent embodiments.

[0083] Please see Figures 2A to 2C This is a schematic diagram of the manufacturing process for forming a power semiconductor device according to an embodiment of the present invention. Figures 2A to 2C Mark along Figure 1 A view of section A-A'.

[0084] exist Figure 2A In the manufacturing process, a semiconductor substrate 11 is provided, which is disposed in the active region AR and the cutoff region TR. The manufacturing process provides an epitaxial growth process to deposit an epitaxial layer 12 on the semiconductor substrate 11, which is also disposed in the active region AR and the cutoff region TR. The epitaxial layer 12 may have a first conductivity type, such as a lightly doped N-type layer.

[0085] exist Figure 2BIn this process, the manufacturing procedure includes an etching process. In this process, a photoresist layer is disposed on the epitaxial layer 12. The photoresist layer can be a patterned layer or a stacked layer containing materials such as oxygen or nitrogen. Using the photoresist layer as a rigid photomask, multiple trenches can be formed by etching the epitaxial layer 12. These trenches include a first trench 13 and a second trench 14. The first trench 13 is disposed between the active region AR and the junction region JR, with the junction region JR located between the active region AR and the cutoff region TR. The second trench 14 is disposed in the cutoff region TR. In this invention, the number of first trenches 13 and second trenches 14 is for illustrative purposes only; the number of trenches may vary depending on the type of power device.

[0086] The first trench 13 includes a first trench width W1 and a first trench depth D1, and the second trench 14 includes a second trench width W2 and a second trench depth D2. The second trench width W2 is smaller than the first trench width W1. The first trench width W1 can be approximately 1.2-1.5µm, while the second trench width W2 can be approximately 0.9-1.1µm. In this invention, the first trench width W1 can be 1.4µm, and the second trench width W2 can be 1.0µm. The difference between the first trench 13 and the second trench 14 can be formed by using photomasks with different patterns. Since the first trench width W1 is larger than the second trench width W2, the etching rate of the first trench 13 is faster than that of the second trench 14. Therefore, the first trench depth D1 is deeper than the second trench depth D2. The first trench depth D1 and the second trench depth D2 can be approximately 1-50µm. In this invention, the first trench depth D1 can be 6.0µm, and the second trench depth D2 can be 4.5µm.

[0087] exist Figure 2C In this invention, the manufacturing process may include an oxidation process to form a dielectric structure. The oxidation process may be a thermal oxidation process. In this process, a dielectric material, such as silicon dioxide, is formed and covers the first trench 13 and the second trench 14. In this invention, the dielectric structure has a first dielectric layer 15 disposed in the first trench 13 and a dielectric region 16 that completely covers the trench region of the second trench 14. As described above, the widths W1 and W2 of the first trench are not the same. In the active region AR, the surface of the first trench 13 is covered by a dielectric material to form the first dielectric layer 15, and trench spaces 151 remain in the first trench 13 and are formed by the first dielectric layer 15. In the cutoff region TR, the second trench 14 has a smaller trench width, and all trench regions are filled with dielectric material to form the dielectric region 16. In this invention, the dielectric region 16 may be a completely oxidized trench region. The dielectric region 16 has a pattern shape 161 at its bottom, which is naturally formed by an oxidation process. Depending on the width W2 of the second trench or the distance between the two second trenches 14, the pattern shape 161 can be a continuous wave shape or a continuous corrugated shape.

[0088] The manufacturing process for forming the dielectric structure is the same oxidation process as that for forming the dielectric layer of the active region AR. No additional process is required for the dielectric region 16 of the cutoff region TR. Therefore, the manufacturing process can be simplified and process variability can be reduced.

[0089] The semiconductor power device includes a completely oxide dielectric region 16 in the cutoff region TR, and the cutoff length L of the cutoff region TR is approximately 1-200 µm. In this invention, the cutoff length L can be 10 µm. Such a cutoff length L is only half the length of the existing structure. According to this structure, the area where the cutoff region TR is set can be reduced, and the size of the power semiconductor device can also be reduced.

[0090] Please see Figure 3 This is a schematic diagram of the three-dimensional structure of a power semiconductor device according to an embodiment of the present invention. As shown, the power semiconductor device 200 includes a semiconductor substrate 21 and an epitaxial layer 22 disposed on the semiconductor substrate 21. The semiconductor substrate 21 may be made of a semiconductor compound. The epitaxial layer 22 may be an n-type lightly doped layer. The power semiconductor device 200 can be divided into two regions, namely an active region AR and a cutoff region TR, with the cutoff region TR surrounding the active region AR to prevent breakdown voltage or other channel effects.

[0091] The active region AR includes multiple first trenches 23 disposed in the active region AR and the junction region JR located between the active region AR and the cutoff region TR. A first dielectric layer 25 is disposed on the surface of the first trenches 23, covering the sidewall surfaces and bottom surfaces of the first trenches 23. The trench space 251 in the first trenches 23 is formed by the first dielectric layer 25. The trench space 251 can be used to house shielding electrodes and gate electrodes; the detailed structure of these electrodes will be described in subsequent embodiments.

[0092] In the cutoff region TR, multiple second trenches can be formed using the same manufacturing process as that used to form the first trench 23. The first trench may have a first trench width, and the second trenches may have a second trench width, which is smaller than the first trench width. Due to the different trench widths, all areas of the second trenches are filled with a dielectric material, such as silicon dioxide, forming dielectric regions 26. Dielectric regions 26 have a patterned shape 261 at their bottom, formed via an oxidation process, and the patterned shape 261 corresponds to the bottom shape of the second trench. The patterned shape 261 can be a continuous wave shape or a continuous corrugated shape. The dielectric regions 26 in the cutoff region TR are formed using the same oxidation process as that used to form the dielectric layer in the active region AR. The dielectric regions 26 do not require additional processes, reducing dimensional variations that occur during the manufacturing process.

[0093] The first trench has a first trench depth D1 and the second trench has a second trench depth D2. The depth of the dielectric region 26 is based on the second trench depth D2, which is less than the first trench depth D1. The first trench depth D1 and the second trench depth D2 can be approximately 1-50 µm. In this invention, the first trench depth D1 can be 6 µm and the second trench depth D2 can be 4.5 µm. The cutoff region TR can have a cutoff length L, which is determined by the dielectric region 26. The cutoff length L is approximately 1-200 µm. In this invention, the cutoff length L can be 10 µm. A narrower cutoff length L reduces the area required for the cutoff region, thus reducing the amount of material used to form the power semiconductor device 200, such as the material used to form the semiconductor substrate 21 and the epitaxial layer 22, thereby reducing manufacturing costs accordingly.

[0094] Please see Figures 4A to 4F This is a schematic diagram of the manufacturing process for forming a power semiconductor device according to an embodiment of the present invention. Figures 4A to 4F The manufacturing process for forming the active area. This manufacturing process also includes, for example: Figures 2A to 2C In the program described above, the same labels refer to the same components, and identical content will not be described again.

[0095] exist Figure 4A In the manufacturing process, the shielding electrode is positioned within the trench space 151. For example... Figure 2C As shown, trench space 151 is formed in the first trench 13 of the active region AR and the junction region JR, and conductive structures are formed in trench space 151. The manufacturing process includes a deposition process to form a shielding electrode 17 in trench space 151, the shielding electrode 17 comprising a polysilicon electrode. Anisotropic etching is performed on shielding electrode 17, and shielding electrode 17 in active region AR is further etched to create space for forming gate electrode.

[0096] exist Figure 4B In the manufacturing process, an oxide deposition process is performed to form a second dielectric layer covering the shielding electrode. The trench space 151 of the active region AR and the junction region JR is covered by an oxide layer to form a second dielectric layer 152. An oxide material, such as silicon dioxide, is filled into the trench space 151 and covers the shielding electrode 17 of the active region AR and the junction region JR.

[0097] exist Figure 4C In the manufacturing process, an etching process is performed on the second dielectric layer 152 of the active region AR to create a space for forming the gate electrode. Therefore, the manufacturing process provides a gate electrode 18 in the space of the first trench 13 of the active region AR. The gate electrode 18 includes a polysilicon electrode, and the gate electrode 18 is etched back to form a gate structure.

[0098] exist Figure 4DIn the manufacturing process, an implantation process is performed to form a doped region 19 between the gate electrodes 18. The doped region 19 is disposed on the top surface of the epitaxial layer 12 between the gate electrodes 18. The doped region 19 is also disposed between the gate electrode 18 and the shielding electrode 17. The doped region 19 may be an N-type heavily doped region, and a P-type well channel region is formed between the doped region 19 and the epitaxial layer 12.

[0099] exist Figure 4E In the manufacturing process, another oxidation process is performed to form a third dielectric layer 153. The third dielectric layer 153 covers the active region AR and the cutoff region TR, and the third dielectric layer 153 may be an interlayer insulating layer.

[0100] exist Figure 4F In the manufacturing process, an etching process is performed on the third dielectric layer 153 to form contact holes 191. Contact holes 191 contact the doped region 19. The manufacturing process forms a metal layer 192 on the third dielectric layer 153 and fills the contact holes 191. The metal layer 192 can serve as the source contact point of the power semiconductor device 100. The metal layer 192 is made of a conductive metal.

[0101] exist Figures 4A to 4F The manufacturing process described is a method for forming active regions (ARs). However, the invention is not limited to this embodiment; in other embodiments, different types of active regions can be fabricated using corresponding processes. These processes can be combined with the process for forming cutoff regions to achieve the benefits of high performance and small size in power semiconductor devices.

[0102] Please see Figure 5 This is a schematic diagram of the three-dimensional structure of a power semiconductor device according to an embodiment of the present invention. As shown in the figure, the power semiconductor device 300 includes a semiconductor substrate 31 and an epitaxial layer 32 disposed on the semiconductor substrate 31. The semiconductor substrate 31 may be made of a semiconductor compound. The epitaxial layer 32 may be an n-type lightly doped layer. The power semiconductor device 300 can be divided into two regions, namely an active region AR and a cutoff region TR. The cutoff region TR surrounds the active region AR to prevent breakdown voltage or other channel effects.

[0103] The active region AR includes multiple first grooves 33, which are disposed in the active region AR and the interface region JR located between the active region AR and the cutoff region TR.

[0104] In the cutoff region TR, a dielectric region 36 is disposed in the cutoff region TR, and the dielectric region 36 completely covers all trench areas of the second trench in the cutoff region TR. The dielectric region 36 has a pattern shape 361 at its bottom, and the pattern shape 361 corresponds to the bottom shape of the second trench. The pattern shape 361 can be a continuous wave shape or a continuous corrugated shape.

[0105] In the active region AR, a first dielectric layer 35 is disposed on the surface of the first trench 33, covering the sidewall and bottom surfaces of the first trench 33. A shielding electrode 37 is disposed on the first dielectric layer 35, and a second dielectric layer 352 covers the shielding electrode 37. A gate electrode 38 is disposed on the shielding electrode 37 in the active region AR, and the shielding electrode 37 and the gate electrode 38 are separated by the second dielectric layer 352. A doped region 39 is disposed between the gate electrodes 38, and the doped region 39 may be an N-type heavily doped region.

[0106] The active region AR includes a plurality of first trenches 33 disposed between the active region AR and the junction region JR located between the active region AR and the cutoff region TR. The cutoff region TR includes a plurality of second trenches formed by the same manufacturing process as forming the first trenches 33. The first trenches may have a first trench width and the second trenches may have a second trench width, the second trench width being smaller than the first trench width. Due to the different trench widths, all regions of the second trenches are filled with a dielectric material, such as silicon dioxide, forming dielectric regions 36.

[0107] The first trench has a first trench depth D1 and the second trench has a second trench depth D2. The depth of the dielectric region 36 is based on the second trench depth D2, which is less than the first trench depth D1. The first trench depth D1 and the second trench depth D2 can be approximately 1-50 µm. In this invention, the first trench depth D1 can be 6.0 µm and the second trench depth D2 can be 4.5 µm. The cutoff region TR can have a cutoff length L, which is determined by the dielectric region 36. The cutoff length L is approximately 1-200 µm. In this invention, the cutoff length L can be 10 µm. A narrower cutoff length L reduces the area required for the cutoff region, thus reducing the material used to form the power semiconductor device 200 and correspondingly lowering the manufacturing cost.

[0108] Please see Figure 6 This is a schematic diagram of a power semiconductor device according to another embodiment of the present invention. Figure 6 A top view of a power semiconductor device 400 is shown. The power semiconductor device 400 includes an active region AR, a cutoff region TR, and a trench ring region RR. The cutoff region TR is adjacent to the active region AR. In this invention, the active region AR includes a first active region AR1 and a second active region AR2. A gate pad GP and a connection line CL are disposed between the first active region AR1 and the second active region AR2. The gate pad GP is connected to a current source, and the connection line CL is connected to a metal contact in the active region AR.

[0109] The cutoff region TR is located on one side of the first active region AR1 and on the other side of the second active region AR2, meaning the cutoff region covers both sides of the active region AR. For the same reason of preventing voltage breakdown or other channel effects, a trench ring region RR is provided. The trench ring region RR surrounds the active region AR and the cutoff region TR to prevent these effects from occurring, and the trench ring region RR also isolates the effects from external components.

[0110] The active region AR includes multiple active trenches T, in which shielding electrodes and gate electrodes are disposed. The cutoff region TR may comprise trenches fabricated using the same process as the active trenches T. In this invention, the dielectric region DA completely covers the trench regions of the cutoff region TR. The trench ring region RR also comprises a trench structure fabricated using the same process as the active trenches T, these trenches surrounding the semiconductor device as a ring structure.

[0111] The dielectric region DA is completely covered by a dielectric material, such as silicon dioxide. Shielding electrodes are disposed in the trench structure of the active trench T and the trench ring region RR. The detailed structure and fabrication method of the power semiconductor device 400 will be further described in subsequent embodiments.

[0112] Please see Figures 7A to 7I This is a schematic diagram of the manufacturing process for forming a power semiconductor device according to another embodiment of the present invention. Figures 7A to 7I Mark along Figure 6 View of section B-B'.

[0113] exist Figure 7A In the manufacturing process, a semiconductor substrate 41 is provided, which is disposed in the active region AR, the cutoff region TR, and the trench ring region RR. The manufacturing process provides an epitaxial growth process to deposit an epitaxial layer 42 on the semiconductor substrate 41, which is also disposed in the active region AR, the cutoff region TR, and the trench ring region RR. The epitaxial layer 42 may have a first conductivity type, such as a lightly doped N-type layer.

[0114] exist Figure 7B In this process, the manufacturing procedure includes an etching process. In this process, a photoresist layer is disposed on the epitaxial layer 42. The photoresist layer can be a patterned layer or a stacked layer containing materials such as oxygen or nitrogen. Using the photoresist layer as a rigid photomask, multiple trenches can be formed by etching the epitaxial layer 42. These trenches include a first trench 43A, a second trench 44, and a third trench 43B. The first trench 43A is disposed between the active region AR and the junction region JR, with the junction region JR located between the active region AR and the cutoff region TR. The second trench 44 is disposed in the cutoff region TR, and the third trench 43B is disposed in the trench ring region RR. In this invention, the number of the first trench 43A and the second trench 44 is for illustrative purposes only; the number of trenches can vary depending on the type of power device. The third trench 43B can be a single trench structure.

[0115] The first trench 43A includes a first trench width W1 and a first trench depth D1; the second trench 44 includes a second trench width W2 and a second trench depth D2; and the third trench 43B includes a third trench width W3 and a third trench depth D3. The second trench width W2 is smaller than either the first trench width W1 or the third trench width W3. The first trench width W1 and the third trench width W3 can be approximately 1.2-1.5 µm, while the second trench width W2 can be approximately 0.9-1.1 µm. The first trench depth D1 or the third trench depth D3 is deeper than the second trench depth D2. The first trench depth D1, the second trench depth D2, and the third trench depth D3 can be approximately 1-50 µm.

[0116] In this invention, the first trench 43A and the third trench 43B have the same trench structure, the width W1 of the first trench and the width W3 of the third trench can be 1.4µm, and the depth D1 of the first trench and the depth D3 of the third trench can be 6.0µm. The second trench 44 is smaller than the first trench 43A or the third trench 43B, the width W2 of the second trench can be 1.0µm, and the depth D2 of the second trench can be 4.5µm.

[0117] exist Figure 7C In this invention, the manufacturing process may include an oxidation process to form a dielectric structure. The oxidation process may be a thermal oxidation process. In this process, a dielectric material, such as silicon dioxide, is formed and covers the first trench 43A, the second trench 44, and the third trench 43B. In this invention, the dielectric structure has a first dielectric layer 45 disposed in the first trench 43A and the third trench 43B, and a dielectric region 46 completely covering the trench region of the second trench 44. The surfaces of the first trench 43A and the third trench 43B are covered by a dielectric material to form the first dielectric layer 45, and trench spaces 451 are still present in both the first trench 43A and the third trench 43B. In the cutoff region TR, the second trench 44 has a smaller trench width, and all trench regions are filled with dielectric material to form the dielectric region 46. In this invention, the dielectric region 46 may be a completely oxidized trench region. The dielectric region 46 has a pattern shape 461 at its bottom, and the pattern shape 461 corresponds to the bottom shape of the second trench 44. The pattern shape 461 is naturally formed by an oxidation process, and the pattern shape 461 can be a continuous wave shape or a continuous wavy shape.

[0118] The fabrication process for forming the dielectric structure is the same oxidation process as that for forming the dielectric layer of the active region AR and the trench ring region RR. No additional process is required for the dielectric region 46 of the cutoff region TR, thus simplifying the fabrication process and reducing process variability. The cutoff length L of the cutoff region TR can be 10µm. This cutoff length L is only half the length of existing structures. Based on this structure, the area where the cutoff region TR is located can be reduced, thereby minimizing the size of the power semiconductor device.

[0119] exist Figure 7D In the manufacturing process, the shielding electrode is positioned within the trench space 451. For example... Figure 7C As shown, trench space 451 is formed in first trench 43A and third trench 43B, and conductive structures are formed in trench space 451. The manufacturing process includes a deposition process to form shielding electrode 47 in trench space 451, shielding electrode 47 comprising a polysilicon electrode. Anisotropic etching is performed on shielding electrode 47, and shielding electrode 47 in active region AR is further etched to create space for forming gate electrode.

[0120] exist Figure 7E In the manufacturing process, an oxide deposition process is performed to form a second dielectric layer covering the shielding electrode. The trench space 451 of the active region AR, the junction region JR, and the trench ring region RR is covered by an oxide layer to form a second dielectric layer 452. The oxide material, such as silicon dioxide, is filled into the trench space 451 and covers the shielding electrode 47 of the active region AR, the junction region JR, and the trench ring region RR.

[0121] exist Figure 7F In the manufacturing process, an etching process is performed on the second dielectric layer 452 of the active region AR to create a space for forming the gate electrode. Therefore, the manufacturing process provides a gate electrode 48 in the space of the first trench 43A of the active region AR. The gate electrode 48 includes a polysilicon electrode, and the gate electrode 48 is etched back to form a gate structure.

[0122] exist Figure 7G In the manufacturing process, an implantation process is performed to form a doped region 49 between the gate electrodes 48. The doped region 49 is disposed on the top surface of the epitaxial layer 42 between the gate electrodes 48. The doped region 49 is also disposed between the gate electrode 48 and the shielding electrode 47. The doped region 49 can be an N-type heavily doped region, and a P-type well channel region is formed between the doped region 49 and the epitaxial layer 12.

[0123] exist Figure 7H In the manufacturing process, another oxidation process is performed to form a third dielectric layer 453. The third dielectric layer 453 covers the active region AR, the cutoff region TR, and the trench ring region RR. The third dielectric layer 453 may be an interlayer insulating layer.

[0124] exist Figure 7I In the manufacturing process, an etching process is performed on the third dielectric layer 453 to form contact holes 491. Contact holes 491 contact the doped region 49. The manufacturing process forms a metal layer 492 on the third dielectric layer 453 and fills the contact holes 491. The metal layer 492 can serve as the source contact point of the power semiconductor device 400. The metal layer 492 is made of conductive metal.

[0125] Please see Figure 8A and Figure 8B This is a schematic diagram of the three-dimensional structure of a power semiconductor device according to another embodiment of the present invention. Figure 8A Mark as Figure 6 The power semiconductor device 400 has a repeating structure RS in a three-dimensional configuration. Figure 8B Mark as Figure 6 The corner structure CS of the power semiconductor device 400.

[0126] exist Figure 8A In the repeating structure RS, a semiconductor substrate 51 and an epitaxial layer 52 disposed on the semiconductor substrate 51 are included. The semiconductor substrate 51 may be made of a semiconductor compound. The epitaxial layer 52 may be an n-type lightly doped layer. The repeating structure RS includes an active region AR, a cutoff region TR, and a trench ring region RR. The cutoff region TR is disposed adjacent to the active region AR, and the trench ring region RR covers the outer side of the cutoff region TR to prevent breakdown voltage or other channel effects.

[0127] The active region AR includes multiple first trenches 53A, which are disposed in the active region AR and the interface region JR located between the active region AR and the cutoff region TR.

[0128] In the cutoff region TR, a dielectric region 56 is disposed in the cutoff region TR, and the dielectric region 56 completely covers all trench areas of the second trench in the cutoff region TR. The dielectric region 56 has a pattern shape 561 at its bottom, and the pattern shape 561 corresponds to the bottom shape of the second trench. The pattern shape 561 can be a continuous wave shape or a continuous corrugated shape.

[0129] The trench ring region RR includes a third trench 53B, similar to the first trench 53A of the active region AR. A first dielectric layer 55 is disposed on the surfaces of the first trench 53A and the third trench 53B, covering the sidewall surfaces and bottom surfaces of the first trench 53A and the third trench 53B. A shielding electrode 57 is disposed on the first dielectric layer 55, and a second dielectric layer 552 covers the shielding electrode 57. A gate electrode 58 is disposed on the shielding electrode 57 of the active region AR, and the shielding electrode 57 is separated from the gate electrode 58 by the second dielectric layer 552. A doped region 59 is disposed between the gate electrodes 58, and the doped region 59 may be an N-type heavily doped region.

[0130] exist Figure 8B In this design, the corner structure CS contains a structure similar to the repeating structure RS. The corner structure CS includes an active region AR, a cutoff region TR, and a trench ring region RR. The cutoff region TR is located adjacent to the active region AR, and the trench ring region RR covers the outer side of the cutoff region TR to prevent breakdown voltage or other channel effects. Because the corner structure CS is located at a corner, the trench ring region RR surrounds the active region AR and the cutoff region TR.

[0131] The structure of the active region AR and the cutoff region TR is similar to that described in the repeating structure RS. The active region AR includes multiple first trenches 53A, and the shielding electrode 57 and the gate electrode 58 are disposed in the first trenches. The cutoff region TR includes a dielectric region 56, which is completely covered by a dielectric material such as silicon dioxide. The dielectric region 56 has a patterned shape 561 at its bottom, which corresponds to the bottom shape of the second trench. The patterned shape 561 can be a continuous wave shape or a continuous corrugated shape. The trench ring region RR includes a third trench 53B, similar to the first trenches 53A of the active region AR, and the shielding electrode 57 is disposed in the third trench 53B to form a protective ring for the device.

[0132] The active region AR includes multiple first trenches 53A, and the trench ring region RR includes a third trench 53B. The cutoff region TR includes multiple second trenches formed by the same manufacturing process as forming the first trenches 53A and the third trench 53B. The first trenches 53A may have a first trench width, the second trenches may have a second trench width, and the third trenches may have a third trench width, wherein the width of the second trenches is smaller than the width of either the first trench or the third trench. Due to the different trench widths, all regions of the second trenches are filled with a dielectric material, such as silicon dioxide, forming a dielectric region 56.

[0133] The first trench has a first trench depth D1, the second trench has a second trench depth D2, and the third trench has a third trench depth D3. The depth of the dielectric region 56 is based on the second trench depth D2, which is less than the first trench depth D1 or the third trench depth D3. The first trench depth D1, the second trench depth D2, and the third trench depth D3 can be approximately 1-50 µm. In this invention, the first trench depth D1 and the third trench depth D3 can be 6.0 µm, and the second trench depth D2 can be 4.5 µm. The cutoff region TR can have a cutoff length L, and the cutoff length L is determined by the dielectric region 56. The cutoff length L is approximately 1-200 µm. In this invention, the cutoff length L can be 10 µm. A narrower cutoff length L reduces the area required for the cutoff region, thus reducing the material used to form the power semiconductor device 200, and consequently reducing manufacturing costs.

[0134] The above description is illustrative only and not restrictive. Any equivalent modifications or alterations made without departing from the spirit and scope of this invention should be included in the appended claims.

Claims

1. A method for forming a power semiconductor device, characterized in that, Include: A semiconductor substrate is provided, the semiconductor substrate having an active region and a cutoff region surrounding the active region; An epitaxial layer is disposed on the semiconductor substrate; The epitaxial layer is etched to form a first trench and a second trench. The first trench is disposed in the active region and the interface region located between the active region and the cutoff region. The second trench is disposed in the cutoff region. The second trench width of the second trench is smaller than the first trench width of the first trench, and the second trench depth of the second trench is smaller than the first trench depth of the first trench. An oxidation process is performed to form a dielectric structure having a first dielectric layer disposed in the first trench and a dielectric region surrounding the active region, wherein the trench region of the second trench is completely covered by a dielectric material to form the dielectric region, and the depth of the dielectric region is less than the depth of the first trench according to the depth of the second trench, wherein the dielectric material comprises silicon dioxide, and the epitaxial layer disposed between the first trench in the junction region and the adjacent second trench is completely oxidized to form the dielectric region, and a patterned shape is provided at the bottom of the dielectric region, the patterned shape corresponding to the bottom shape of the second trench; A deposition process is performed to place a shielding electrode in a trench space, the trench space being formed by the first dielectric layer in the first trench in the active region and the junction region; The shielding electrode in the active region is etched to create a space for forming the gate electrode; Oxidation deposition is performed to form a second dielectric layer covering the shielding electrode and the trench space; The second dielectric layer in the active region is etched to further fabricate the space forming the gate electrode; A deposition process is performed to fill the space for forming the gate electrode on the first trench in the active region to provide the gate electrode; A doped region is formed between the gate electrodes; An oxidation deposition is performed to form a third dielectric layer covering the active region and the cutoff region; as well as A metal layer is formed on the third dielectric layer, and the metal layer contacts the doped region through contact holes.

2. The method for forming a power semiconductor device as claimed in claim 1, characterized in that, The pattern shape includes a continuous wave shape.

3. The method for forming a power semiconductor device as described in claim 1, characterized in that, The width of the first groove is 1.2-1.5 µm and the width of the second groove is 0.9-1.1 µm.

4. The method for forming a power semiconductor device as claimed in claim 1, characterized in that, The depth of the first trench and the depth of the second trench are 1-50 µm.

5. The method for forming a power semiconductor device as claimed in claim 1, characterized in that, The cutoff region has a cutoff length of 1-200 µm.

6. The method for forming a power semiconductor device as claimed in claim 1, characterized in that, The epitaxial layer is an N-type lightly doped layer, and the doped region is an N-type heavily doped region.

7. A method for forming a power semiconductor device, characterized in that, Include: A semiconductor substrate is provided, the semiconductor substrate having an active region, a cutoff region adjacent to the active region, and a trench ring region surrounding the active region and the cutoff region; An epitaxial layer is disposed on the semiconductor substrate; The epitaxial layer is etched to form a first trench, a second trench, and a third trench. The first trench is disposed in the active region and the interface region located between the active region and the cutoff region. The second trench is disposed in the cutoff region. The third trench is disposed in the trench ring region. The second trench width of the second trench is smaller than the first trench width of the first trench, and the second trench depth of the second trench is smaller than the first trench depth of the first trench. An oxidation process is performed to form a dielectric structure having a first dielectric layer disposed in the first trench and the third trench and a dielectric region surrounding the active region, wherein the trench region of the second trench is completely covered by a dielectric material to form the dielectric region, and the depth of the dielectric region is less than the depth of the first trench according to the depth of the second trench, wherein the dielectric material comprises silicon dioxide, and the epitaxial layer disposed between the first trench and the adjacent second trench in the junction region is completely oxidized to form the dielectric region; A deposition process is performed to place shielding electrodes in a first trench space and a second trench space, the first trench space being formed by the first dielectric layer in the first trench in the active region and the junction region, and the second trench space being formed by the first dielectric layer located in the third trench. The shielding electrode in the active region is etched to create a space for forming the gate electrode; Oxidation deposition is performed to form a second dielectric layer covering the shielding electrode and the first trench space; The second dielectric layer in the active region is etched to further fabricate the space forming the gate electrode; A deposition process is performed to fill the space for forming the gate electrode on the first trench in the active region to provide the gate electrode; A doped region is formed between the gate electrodes; Oxidation deposition is performed to form a third dielectric layer covering the active region, the cutoff region, and the trench ring region; as well as A metal layer is formed on the third dielectric layer, and the metal layer contacts the doped region through contact holes.

8. The method for forming a power semiconductor device as described in claim 7, characterized in that, The dielectric region has a patterned shape at its bottom, the patterned shape corresponding to the bottom shape of the second trench.

9. The method for forming a power semiconductor device as claimed in claim 8, characterized in that, The pattern shape includes a continuous wave shape.

10. The method for forming a power semiconductor device as claimed in claim 7, characterized in that, The width of the first groove is 1.2-1.5 µm and the width of the second groove is 0.9-1.1 µm.

11. The method for forming a power semiconductor device as claimed in claim 7, characterized in that, The width of the third groove is greater than the width of the second groove, and the width of the third groove is 1.2-1.5µm.

12. The method for forming a power semiconductor device as claimed in claim 7, characterized in that, The third trench has a third trench depth, and the second trench depth is less than the first trench depth and the third trench depth.

13. The method for forming a power semiconductor device as claimed in claim 12, characterized in that, The depth of the first trench and the depth of the third trench are 1-50 µm.

14. The method for forming a power semiconductor device as claimed in claim 7, characterized in that, The cutoff region has a cutoff length of 1-200 µm.

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