A gate-all-around transistor structure and its manufacturing method

Abstract

The present invention provides a gate-all-around transistor structure and a method for fabricating the same. The structure comprises: a substrate layer, an insulating layer, a top semiconductor layer, a gate, a source, and a drain; a groove is provided between the insulating layer and the top semiconductor layer, and a pre-doped layer is provided on the bottom surfaces of the semiconductor bosses on both sides of the groove; a gate dielectric layer is wrapped around the surface of the suspended channel, and a gate electrode layer is wrapped around the surface of the gate dielectric layer; the gate dielectric layer and the gate electrode layer constitute the gate, and the gate length above and on the sidewalls of the suspended channel is greater than the gate length below the suspended channel. By providing pre-doped layers at the bottom of the semiconductor bosses at both ends of the suspended channel, the present invention enables the π-channel structure in the channel region of the device to control device switching less effectively than a full-surround channel structure. This reduces the parasitic capacitance and bias electric field between the source, drain, and gate while fully utilizing the excellent electrical performance of the full-surround gate transistor.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a ring-gate transistor structure and a preparation method thereof. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, the critical dimensions of semiconductor devices, especially field-effect transistors (MOSFETs), have continued to shrink, even down to 10nm and below nodes. However, the short-channel effect of the devices has become increasingly significant, and traditional planar devices can no longer meet the performance and integration requirements of the devices.

[0003] As semiconductor device sizes continue to shrink, gate-all-around (GAA) silicon nanowire transistors, due to their shorter channel length, further reduce device size and exhibit superior performance. In existing device structures, when fabricating gate-all-around transistor structures, to ensure minimal overlap between the source and drain regions and the gate within the groove beneath the silicon nanowire, thereby reducing parasitic capacitance and mitigating the bias electric field on the gate dielectric, and due to the limited precision of photolithography alignment, the gate length at the top of the silicon nanowire is typically set to be longer than the gate length within the groove to avoid overlap between the gate and the source and drain regions within the groove.

[0004] However, the above solution will result in the appearance of GAA-type channels in which the gate completely wraps the channel and π-type channels in which the gate does not completely wrap the channel in the channel region of the device. Since the π-type channel lacks the wrapping of the back gate in the groove, the opening of the π-type channel is often later than that of the GAA-type channel, resulting in a larger subthreshold slope and a smaller on-state current density of the device as a whole, thereby limiting the GAA silicon nanowire transistor from exhibiting its ideal electrical performance. Therefore, a method is needed that can reduce the parasitic capacitance caused by the overlap of the gate and the source and drain while avoiding the performance limitation of the π-type channel on the GAA silicon nanowire transistor.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of this application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are explained in the background technology part of this application. Summary of the Invention

[0006] In view of the above shortcomings of the prior art, an object of the present invention is to provide a ring-gate transistor structure and a preparation method thereof, so as to solve the problem of limited channel turn-on performance of the ring-gate transistor in the prior art.

[0007] To achieve the above object, the present invention provides a gate-all-around transistor structure, comprising: a substrate layer, an insulating layer, a top semiconductor layer, a gate, a source, and a drain;

[0008] The insulating layer is disposed on the substrate layer, and the top semiconductor layer is disposed on the insulating layer;

[0009] A groove is provided between the insulating layer and the top semiconductor layer, the groove does not penetrate the insulating layer, the top semiconductor layer includes a suspended channel and a semiconductor boss, the semiconductor bosses are provided on both sides of the groove, the semiconductor bosses are connected to the suspended channel, the suspended channel spans the groove, and pre-doped layers are provided on the bottom surfaces of the semiconductor bosses on both sides of the groove to adjust the threshold voltage of the channel corresponding to the pre-doped layer;

[0010] The surface of the suspended channel is wrapped with a gate dielectric layer, the surface of the gate dielectric layer is wrapped with a gate electrode layer, the gate dielectric layer and the gate electrode layer constitute the gate, the gate dielectric layer and the gate electrode layer together fill the groove, and the length of the gate above and on the sidewall of the suspended channel is greater than the length of the gate below the suspended channel;

[0011] The top semiconductor layer at both ends of the suspended channel is respectively provided with a source region and a drain region, the source electrode is provided above the source region, and the drain electrode is provided above the drain region.

[0012] Optionally, a thickness of the suspended channel above the groove is smaller than a thickness of the semiconductor bosses on both sides of the groove.

[0013] Optionally, when the ring-gate transistor structure is an NMOS device, the pre-doped layer is N-type doped; when the ring-gate transistor structure is a PMOS device, the pre-doped layer is P-type doped.

[0014] Optionally, a passivation layer is provided on the sidewall of the gate above the suspended channel, and the projection of the passivation layer on the substrate layer extends to a peripheral area of ​​the projection of the groove on the substrate layer.

[0015] The present invention further provides a method for preparing a gate-all-around transistor structure, the method being used to prepare any of the above-mentioned gate-all-around transistor structures, the method comprising:

[0016] Providing a patterned SOI substrate, the SOI substrate comprising a substrate layer, an insulating layer, and a top semiconductor layer, wherein a groove is provided between the top semiconductor layer and the insulating layer, and the groove does not penetrate the insulating layer;

[0017] Patterning the top semiconductor layer to form a suspended channel that is suspended and spans the groove and a semiconductor boss on both sides of the groove, wherein the semiconductor boss is connected to the suspended channel;

[0018] doping the semiconductor protrusions on both sides of the groove to form a pre-doped layer on the bottom surface of the semiconductor protrusions close to the insulating layer;

[0019] forming a fully surrounding gate dielectric layer on the surface of the suspended channel, forming a gate electrode layer on the surface of the gate dielectric layer, and pattern-etching the gate electrode layer to expose the source region and drain region of the top semiconductor layer, wherein the gate dielectric layer and the gate electrode layer constitute a gate, wherein the length of the gate formed above the suspended channel is greater than the length of the gate formed below the suspended channel, and the gate dielectric layer and the gate electrode layer together fill the groove;

[0020] Using the gate electrode layer as a mask, an ion implantation process is performed on the source and drain regions to form the source and drain regions, and the portion of the gate dielectric layer other than that surrounded by the gate electrode layer is removed; a source electrode is formed on the source region, and a drain electrode is formed on the drain region.

[0021] Optionally, after forming the suspended channel, the suspended channel is rounded and thinned.

[0022] Optionally, after removing the portion of the gate dielectric layer outside the portion surrounded by the gate electrode layer, a passivation layer is formed on the sidewall of the gate electrode layer, and the projection of the passivation layer on the substrate layer extends to the peripheral area of ​​the projection of the groove on the substrate layer.

[0023] Optionally, the pre-doped layer is obtained by performing self-aligned doping on the top semiconductor layer using an ion implantation method with a preset implantation depth.

[0024] Optionally, after ion implantation is performed on the top semiconductor layer, an annealing process is performed.

[0025] Optionally, before ion implantation into the top semiconductor layer, an implantation buffer layer is provided on the top semiconductor layer.

[0026] As described above, the gate-all-around transistor structure and the method for manufacturing the same of the present invention have the following beneficial effects:

[0027] The present invention provides a pre-doped layer at the bottom of the semiconductor bosses at both ends of the suspended channel, so that the π-channel structure in the channel region of the device has a weaker control capability over the device switch than the full-surround channel structure, thereby reducing the parasitic capacitance and bias electric field between the source, drain and gate while giving full play to the excellent electrical performance of the full-surround gate transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Shown is a schematic diagram of a gate-all-around transistor structure in the prior art.

[0029] Figure 2A schematic diagram of a GAA channel of a gate-all-around transistor structure in the prior art is shown.

[0030] Figure 3 A schematic diagram of a π-shaped channel of a gate-all-around transistor structure in the prior art is shown.

[0031] Figure 4 Shown is a schematic diagram of the ring gate transistor structure in the present invention.

[0032] Figure 5 It is a schematic diagram showing the π-type channel of the ring-gate transistor structure in the present invention.

[0033] Figure 6 Schematic diagram showing a GAA channel of a gate-all-around transistor structure in the present invention.

[0034] Figure 7 It is a schematic diagram showing the provision of a pre-doped layer in step 3 of the method for preparing a gate-all-around transistor structure in the present invention.

[0035] Component number description

[0036] 10. substrate layer; 20. insulating layer; 21. groove; 30. top semiconductor layer; 31. suspended channel; 32. semiconductor platform;

[0037] 33, pre-doped layer; 331, implanted ion beam; 41, gate dielectric layer; 42, gate electrode layer; 43, passivation layer; 44, source;

[0038] 45. Drain; A1, GAA type channel; A2, π type channel. DETAILED DESCRIPTION

[0039] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] For example, when describing the embodiments of the present invention, schematic diagrams illustrating device structures may be partially enlarged for ease of explanation. These schematic diagrams are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0041] For convenience of description, spatially relative terms such as "under," "below," "below," "below," "above," and "upper" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0042] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0043] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0044] In the prior art, such as Figure 1 As shown in the figure, when preparing the ring-gate transistor structure, in order to ensure that the source and drain regions do not overlap too much with the gate in the groove 21 below the silicon nanowire, so as to reduce parasitic capacitance and alleviate the bias electric field at the gate dielectric, and because the lithography alignment accuracy is limited, the gate length at the top of the silicon nanowire is usually set to be greater than the gate length in the groove 21 to avoid the gate and source and drain in the groove 21 from overlapping. However, such a structural setting will cause the channel region of the device to have the following Figure 2 The gate shown completely surrounds the GAA channel A1 and Figure 3 The gate shown does not completely wrap around the π-type channel A2. Figure 2 and Figure 3 for Figure 1 As shown in the local enlarged view, since the π-type channel A2 lacks the wrapping of the back gate in the groove 21, the opening of the π-type channel A2 is often later than the opening of the GAA-type channel A1, resulting in a larger subthreshold slope of the entire device and a smaller on-state current density, which limits the GAA silicon nanowire transistor from exhibiting its ideal electrical performance.

[0045] like Figure 4 As shown, the present invention provides a gate-all-around transistor structure, which includes: a substrate layer 10, an insulating layer 20, a top semiconductor layer 30, a gate, a source 44 and a drain 45;

[0046] The insulating layer 20 is disposed on the substrate layer 10 , and the top semiconductor layer 30 is disposed on the insulating layer 20 ;

[0047] A groove 21 is provided between the insulating layer 20 and the top semiconductor layer 30. The groove 21 does not penetrate the insulating layer 20. The top semiconductor layer 30 includes a suspended channel 31 and a semiconductor boss 32. The semiconductor bosses 32 are located on both sides of the groove 21. The semiconductor bosses 32 are connected to the suspended channel 31. The suspended channel 31 spans the groove 21. Pre-doped layers 33 are provided on the bottom surfaces of the semiconductor bosses 32 on both sides of the groove 21 to adjust the threshold voltage of the channel corresponding to the pre-doped layers 33.

[0048] The surface of the suspended channel 31 is wrapped with a gate dielectric layer 41, and the surface of the gate dielectric layer 41 is wrapped with a gate electrode layer 42. The gate dielectric layer 41 and the gate electrode layer 42 constitute the gate. The gate dielectric layer 41 and the gate electrode layer 42 together fill the groove 21. The length of the gate above and on the sidewall of the suspended channel 31 is greater than the length of the gate below the suspended channel 31.

[0049] The top semiconductor layer 30 at both ends of the suspended channel 31 is provided with a source region and a drain region, respectively. The source electrode 44 is provided above the source region, and the drain electrode 45 is provided above the drain region.

[0050] Figure 5 and Figure 6 for Figure 4 In the partial enlarged view, the present invention provides a pre-doped layer 33 on the bottom surface of the semiconductor boss 32 on both sides of the groove 21, so that Figure 5 The π-type channel A2 shown can precede the Figure 6 The GAA channel A1 shown is turned on, so that the turning on of the ring-gate transistor depends on the turning on of the GAA channel A1, so that the ring-gate transistor is mainly controlled by the GAA channel A1, so that the gate length at the top and sidewall of the suspended channel 31 can be kept greater than the gate length in the groove 21, and the overlapping area between the source and drain region and the gate in the groove 21 below the suspended channel 31 projected on the substrate layer 10 is reduced to reduce parasitic capacitance, while allowing the ring-gate transistor to fully reflect the performance of its ideal ring-gate channel structure, reduce the subthreshold slope of the device, and increase the on-state current density.

[0051] In one embodiment, the thickness of the suspended channel 31 above the groove 21 is smaller than the thickness of the semiconductor protrusion 32 on both sides of the groove 21 .

[0052] The present invention sets the thickness of the suspended channel 31 above the groove 21 to be smaller than the thickness of the semiconductor bosses 32 on both sides of the groove 21, so that when the pre-doped layer 33 is subsequently formed, the pre-doped ions will not gather on the suspended channel 31 above the groove 21, but will be deposited at the bottom of the semiconductor boss 32, thereby ensuring the early opening of the π-type channel A2.

[0053] Specifically, the doping position of the pre-doped ions is ensured by coordinating the thickness of the suspended channel 31 with the process conditions when the pre-doped layer 33 is provided.

[0054] Specifically, the exposed surface of the suspended channel 31 is surrounded by the gate, and the length of the gate above and on the sidewalls (not shown in the drawings) of the suspended channel 31 is greater than the length of the gate below the suspended channel 31. The sidewalls refer to the side surfaces of the suspended channel 31 exposed except the upper surface and the lower surface connected to the groove 21, on which the gate is arranged in the three-dimensional structure, so that there is no overlapping area between the source region, the drain region and the gate in the groove 21.

[0055] In one embodiment, the suspended channel 31 can be a variety of semiconductor nanostructures such as semiconductor nanowires and semiconductor nanosheets.

[0056] In one embodiment, the depth of the recess 21 in the top semiconductor layer 30 is greater than 5 nanometers.

[0057] In one embodiment, the thickness of the suspended channel 31 is 1 nm-100 nm.

[0058] In one embodiment, when the gate-all-around transistor structure is an NMOS device, the pre-doped layer 33 is N-type doped; when the gate-all-around transistor structure is a PMOS device, the pre-doped layer 33 is P-type doped.

[0059] In one embodiment, a passivation layer 43 is provided on the sidewall of the gate above the suspended channel 31 , and the projection of the passivation layer 43 on the substrate layer 10 extends to the peripheral area of ​​the projection of the groove 21 on the substrate layer 10 .

[0060] The present invention further provides a method for preparing a gate-all-around transistor structure, the method being used to prepare any of the above-mentioned gate-all-around transistor structures, the method comprising:

[0061] Step 1: providing a patterned SOI substrate, wherein the SOI substrate includes a substrate layer 10, an insulating layer 20, and a top semiconductor layer 30, wherein a groove 21 is provided between the top semiconductor layer 30 and the insulating layer 20, and the groove 21 does not penetrate the insulating layer 20;

[0062] Step 2: Patterning the top semiconductor layer 30 to form a suspended channel 31 suspended and spanning the groove 21 and a semiconductor platform 32 on both sides of the groove 21 , wherein the semiconductor platform 32 is connected to the suspended channel 31 ;

[0063] Step 3: doping the semiconductor protrusions 32 on both sides of the groove 21 to form a pre-doped layer 33 on the bottom surface of the semiconductor protrusions 32 close to the insulating layer 20;

[0064] Step 4: forming a fully surrounding gate dielectric layer 41 on the surface of the suspended channel 31, forming a gate electrode layer 42 on the surface of the gate dielectric layer 41, and patterning and etching the gate electrode layer 42 to expose the source and drain regions of the top semiconductor layer 30. The gate dielectric layer 41 and the gate electrode layer 42 form a gate. The length of the gate formed above the suspended channel 31 is greater than the length of the gate formed below the suspended channel 31. The gate dielectric layer 41 and the gate electrode layer 42 together fill the groove 21.

[0065] Step 5: Using the gate electrode layer 42 as a mask, perform an ion implantation process on the source and drain regions to form the source and drain regions, and remove the portion of the gate dielectric layer 41 outside the area surrounded by the gate electrode layer 42; form a source 44 on the source region, and form a drain 45 on the drain region.

[0066] The preparation method of the ring-gate transistor structure of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the preparation method of the ring-gate transistor structure protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0067] First, step 1 is performed to provide a patterned SOI substrate. The SOI substrate includes a substrate layer 10 , an insulating layer 20 and a top semiconductor layer 30 . A groove 21 is provided between the top semiconductor layer 30 and the insulating layer 20 . The groove 21 does not penetrate the insulating layer 20 .

[0068] Specifically, the SOI substrate having a groove 21 between the top semiconductor layer 30 and the insulating layer 20 is obtained by bonding two patterned substrates. Both patterned substrates have a structure in which the insulating layer 20 is provided on the substrate layer 10. After both insulating layers 20 are patterned, the patterned openings are aligned and bonded to obtain the groove 21. Then, the substrate layer 10 of one of the patterned substrates is debonded to obtain the SOI substrate.

[0069] Then, step 2 is performed to pattern the top semiconductor layer 30 to form a suspended channel 31 suspended above and spanning the groove 21 and a semiconductor platform 32 on both sides of the groove 21 , wherein the semiconductor platform 32 is connected to the suspended channel 31 .

[0070] In one embodiment, after the suspended channel 31 is formed, the suspended channel 31 is rounded and thinned.

[0071] Next, step 3 is performed to dope the semiconductor protrusions 32 on both sides of the groove 21 , so that a pre-doped layer 33 is formed on the bottom surface of the semiconductor protrusions 32 close to the insulating layer 20 .

[0072] The present invention sets the pre-doped layer 33 so that the π-type channel A2 of the ring-gate transistor in which it is located is opened before the GAA-type channel A1 on the surface of the suspended channel 31, so that the ring-gate transistor is mainly controlled by the GAA-type channel A1 and the excellent performance of the ring-gate transistor can be fully exerted.

[0073] In one embodiment, step 3 may be performed first to form the pre-doped layer 33, and then step 2 may be performed to pattern the top semiconductor layer 30.

[0074] In one embodiment, Figure 7 As shown, the pre-doped layer 33 is obtained by self-aligned doping of the top semiconductor layer 30 using an ion implantation method with a preset implantation depth by using an implantation ion beam 331 .

[0075] The present invention sets the pre-doped layer 33 by self-aligned doping, thereby more accurately controlling the doping position to ensure that the π-type channel A2 is opened before the GAA-type channel A1, so as to fully exert the excellent performance of the ring-gate transistor.

[0076] In one embodiment, after ion implantation is performed on the top semiconductor layer 30 , an annealing process is performed.

[0077] The present invention performs an annealing process after ion implantation to activate the implanted ions, thereby further ensuring that the π-type channel A2 is opened in advance.

[0078] In one embodiment, the annealing temperature after ion implantation is 500-1200° C., and the annealing time is less than 2 minutes.

[0079] In one embodiment, before ion implantation into the top semiconductor layer 30 , an implantation buffer layer is disposed on the top semiconductor layer 30 .

[0080] The present invention provides an implantation buffer layer to reduce damage to the top semiconductor layer 30 during ion implantation, thereby ensuring normal working performance of the channel.

[0081] In one embodiment, the material of the injection buffer layer is an insulating dielectric material, including but not limited to any one or any combination of silicon oxide or silicon nitride.

[0082] In one embodiment, the injection buffer layer has a thickness of 5 nanometers to 100 nanometers.

[0083] Specifically, the implantation buffer layer is removed after the ion implantation and annealing processes are completed.

[0084] Then, step 4 is performed to form a fully surrounding gate dielectric layer 41 on the surface of the suspended channel 31, form a gate electrode layer 42 on the surface of the gate dielectric layer 41, and graphically etch the gate electrode layer 42 to expose the preparation area of ​​the source region and the drain region of the top semiconductor layer 30. The gate dielectric layer 41 and the gate electrode layer 42 form a gate. The length of the gate formed above the suspended channel 31 is greater than the length of the gate formed below the suspended channel 31. The gate dielectric layer 41 and the gate electrode layer 42 together fill the groove 21.

[0085] In one embodiment, after removing the portion of the gate dielectric layer 41 outside the portion surrounded by the gate electrode layer 42, a passivation layer 43 is formed on the sidewall of the gate electrode layer 42, and the projection of the passivation layer 43 on the substrate layer 10 extends to the peripheral area of ​​the projection of the groove 21 on the substrate layer 10.

[0086] Finally, step 5 is performed, using the gate electrode layer 42 as a mask, and performing an ion implantation process on the source and drain regions to form the source and drain regions, removing the portion of the gate dielectric layer 41 outside the area surrounded by the gate electrode layer 42; forming a source 44 on the source region, and forming a drain 45 on the drain region.

[0087] Specifically, the position order of the source 44 and the drain 45 is not fixed. In order to distinguish them in the drawings, the present invention uses different position numbers. During actual processing, the positions of the source 44 and the drain 45 can be exchanged and adjusted according to actual processing requirements.

[0088] In summary, the ring-gate transistor structure and preparation method of the present invention can provide a pre-doped layer at the bottom of the semiconductor bosses at both ends of the suspended channel, so that the π-channel structure in the channel region of the device has weaker control ability over the device switch than the full-surround channel structure, thereby reducing the parasitic capacitance and bias electric field between the source, drain and gate while giving full play to the excellent electrical performance of the full-surround gate transistor.

[0089] Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0090] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A gate-all-around transistor structure, characterized in that: The structure comprises: a substrate layer, an insulating layer, a top semiconductor layer, a gate, a source electrode and a drain electrode; The insulating layer is disposed on the substrate layer, and the top semiconductor layer is disposed on the insulating layer; A groove is provided between the insulating layer and the top semiconductor layer, the groove does not penetrate the insulating layer, the top semiconductor layer includes a suspended channel and a semiconductor boss, the semiconductor bosses are provided on both sides of the groove, the semiconductor bosses are connected to the suspended channel, the suspended channel spans the groove, and pre-doped layers are provided on the bottom surfaces of the semiconductor bosses on both sides of the groove to adjust the threshold voltage of the channel corresponding to the pre-doped layer; The surface of the suspended channel is wrapped with a gate dielectric layer, the surface of the gate dielectric layer is wrapped with a gate electrode layer, the gate dielectric layer and the gate electrode layer constitute the gate, the gate dielectric layer and the gate electrode layer together fill the groove, and the length of the gate above and on the sidewall of the suspended channel is greater than the length of the gate below the suspended channel; The top semiconductor layer at both ends of the suspended channel is respectively provided with a source region and a drain region, the source electrode is provided above the source region, and the drain electrode is provided above the drain region.

2. The gate-all-around transistor structure according to claim 1, wherein: The thickness of the suspended channel above the groove is smaller than the thickness of the semiconductor bosses on both sides of the groove.

3. The gate-all-around transistor structure according to claim 1, wherein: When the gate-all-around transistor structure is an NMOS device, the pre-doped layer is N-type doped; when the gate-all-around transistor structure is a PMOS device, the pre-doped layer is P-type doped.

4. The gate-all-around transistor structure according to claim 1, wherein: A passivation layer is provided on the sidewall of the gate above the suspended channel, and the projection of the passivation layer on the substrate layer extends to a peripheral area of ​​the projection of the groove on the substrate layer.

5. A method for preparing a gate-all-around transistor structure, characterized in that: The preparation method is used to prepare the gate-all-around transistor structure according to any one of claims 1 to 4, and the preparation method comprises: Providing a patterned SOI substrate, the SOI substrate comprising a substrate layer, an insulating layer, and a top semiconductor layer, wherein a groove is provided between the top semiconductor layer and the insulating layer, and the groove does not penetrate the insulating layer; Patterning the top semiconductor layer to form a suspended channel that is suspended and spans the groove and a semiconductor boss on both sides of the groove, wherein the semiconductor boss is connected to the suspended channel; doping the semiconductor protrusions on both sides of the groove to form a pre-doped layer on the bottom surface of the semiconductor protrusions close to the insulating layer; A fully surrounding gate dielectric layer is formed on the surface of the suspended channel, a gate electrode layer is formed on the surface of the gate dielectric layer, and the gate electrode layer is graphically etched to expose the preparation areas of the source region and the drain region of the top semiconductor layer. The gate dielectric layer and the gate electrode layer constitute a gate. The length of the gate formed above the suspended channel is greater than the length of the gate formed below the suspended channel. The gate dielectric layer and the gate electrode layer jointly fill the groove; using the gate electrode layer as a mask, an ion implantation process is performed on the preparation areas of the source region and the drain region to form the source region and the drain region, and the portion of the gate dielectric layer other than that surrounded by the gate electrode layer is removed; a source electrode is formed on the source region, and a drain electrode is formed on the drain region.

6. The method for preparing a gate-all-around transistor structure according to claim 5, wherein: The preparation method further includes: after forming the suspended channel, rounding and thinning the suspended channel.

7. The method for preparing a gate-all-around transistor structure according to claim 5, wherein: The preparation method further includes: after removing the portion of the gate dielectric layer outside the portion surrounded by the gate electrode layer, a passivation layer is formed on the sidewall of the gate electrode layer, and the projection of the passivation layer on the substrate layer extends to the peripheral area of ​​the projection of the groove on the substrate layer.

8. The method for preparing a gate-all-around transistor structure according to claim 5, wherein: The pre-doped layer is obtained by self-aligned doping of the top semiconductor layer using an ion implantation method with a preset implantation depth.

9. The method for preparing a gate-all-around transistor structure according to claim 8, wherein: After ion implantation is performed on the top semiconductor layer, an annealing process is performed.

10. The method for preparing a gate-all-around transistor structure according to any one of claims 8 or 9, wherein: The preparation method further includes: before ion implantation into the top semiconductor layer, providing an implantation buffer layer on the top semiconductor layer.

Images