Clock monitoring circuit, microcontroller, and control method thereof

Abstract

A clock monitoring circuit, a microcontroller, and a control method thereof are disclosed. The clock monitoring circuit includes a monitor and an adjustable counter. The monitor monitors a clock under test. The adjustable counter counts an integer based on a reference clock and sets a target number. If a stable signal of the clock under test toggles, the adjustable counter switches the target number from a larger number to a smaller number. The adjustable counter performs an automatic detection procedure to send a check signal to the monitor. In response to the check signal, if the clock under test cannot be detected, the monitor does not send any acknowledgement signal back to the adjustable counter, and the adjustable counter gradually increases the integer. When the integer equals the target number, the adjustable counter generates a fail signal.

Description

TECHNICAL FIELD

[0001] The present invention relates to a clock monitoring circuit, and more particularly, to a clock monitoring circuit with automatic detection function. BACKGROUND

[0002] In conventional microcontrollers, the clock monitoring circuit usually performs the detection procedure after the clock to be detected has been stable. In addition, if the clock to be detected suddenly disappears, it often takes a lot of time to be discovered, which will cause the reliability of the overall system to decrease. Therefore, a new solution is needed to overcome the problems faced by the prior art. SUMMARY

[0003] In a preferred embodiment, the present invention provides a clock monitoring circuit, comprising: a monitor for monitoring a clock to be detected; and an adjustable counter for counting an integer according to a reference clock and setting a target number; wherein if a stable signal with respect to the clock to be detected flips, the adjustable counter will switch the target number from a first number to a second number, wherein the first number is greater than the second number; the adjustable counter can perform an automatic detection procedure to send a check signal to the monitor; in response to the check signal, if the clock to be detected cannot be detected, the monitor will not return any confirmation signal to the adjustable counter, and the adjustable counter will gradually increase the integer; wherein when the integer is equal to the target number, the adjustable counter will generate a failure signal.

[0004] In some embodiments, in response to the check signal, if the clock to be detected can be detected, the monitor will return a confirmation signal to the adjustable counter to reset the integer of the adjustable counter.

[0005] In some embodiments, the stable signal is initially maintained at a low logic level and rises to a high logic level after a certain time.

[0006] In some embodiments, the first number is equal to 100.

[0007] In some embodiments, the second number is equal to 2.

[0008] In some embodiments, the stable signal is at a low logic level in a first stage and at a high logic level in a second stage.

[0009] In some embodiments, the adjustable counter can perform the automatic detection procedure during the first stage and the second stage.

[0010] In some embodiments, the clock monitoring circuit further comprises a resetter, wherein when the fail signal is generated, the resetter will send a return signal to the adjustable counter to pull the fail signal from a high logic level back to a low logic level.

[0011] In another preferred embodiment, the present application proposes a control method comprising the following steps: monitoring a to-be-tested clock by a monitor; calculating an integer according to a reference clock and setting a target number by an adjustable counter; switching the target number from a first number to a second number if a stable signal about the to-be-tested clock flips, wherein the first number is greater than the second number; executing an automatic detection procedure to send a check signal to the monitor; in response to the check signal, if the to-be-tested clock cannot be detected, no confirmation signal will be returned to the adjustable counter, and the integer of the adjustable counter will be gradually increased; and generating a fail signal when the integer equals the target number.

[0012] In some embodiments, the control method further comprises: in response to the check signal, if the to-be-tested clock can be detected, a confirmation signal will be returned to the adjustable counter to reset the integer of the adjustable counter.

[0013] In some embodiments, the control method further comprises: when the fail signal is generated, sending a return signal to the adjustable counter to pull the fail signal from a high logic level back to a low logic level.

[0014] In another preferred embodiment, the present application proposes a microcontroller comprising: a monitor monitoring a to-be-tested clock; and an adjustable counter calculating an integer according to a reference clock and setting a target number; if a stable signal about the to-be-tested clock flips, the adjustable counter will switch the target number from a first number to a second number, wherein the first number is greater than the second number; the adjustable counter can execute an automatic detection procedure to send a check signal to the monitor; in response to the check signal, if the to-be-tested clock cannot be detected, the monitor will not return any confirmation signal to the adjustable counter, and the adjustable counter will gradually increase the integer; wherein when the integer equals the target number, the adjustable counter will generate a fail signal. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 A schematic diagram of a clock monitoring circuit according to an embodiment of the present application is shown.

[0016] Figure 2 A signal waveform diagram of a clock monitoring circuit according to an embodiment of the present application is shown.

[0017] Figure 3 FIG. 4 is a schematic diagram showing a clock monitoring circuit according to another embodiment of the present invention.

[0018] Figure 4A 、 Figure 4B A flow chart of a control method according to an embodiment of the present invention is shown.

[0019] Reference numerals:

[0020] 100,300: Clock monitoring circuit (microcontroller)

[0021] 110: Adjustable counter

[0022] 120: Monitor

[0023] 201: first dotted frame

[0024] 202: Second dotted box

[0025] 203: The third dotted box

[0026] 204: Fourth dotted box

[0027] 330: Resetter

[0028] BG: integer

[0029] BT: Target Number

[0030] SA: Confirmation signal

[0031] SC: Check signal

[0032] SF: Failure signal

[0033] SR: Reply signal

[0034] SS: Stable signal

[0035] RCLK: Reference clock

[0036] TCLK: clock to be measured

[0037] TD: Determined time DETAILED DESCRIPTION

[0038] In order to make the objects, features and advantages of the present invention more clearly understood, specific embodiments of the present invention are given below and described in detail with reference to the accompanying drawings.

[0039] Certain words are used in the specification and claims to refer to specific devices. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same device. This specification and claims do not use differences in name as a way to distinguish devices, but use differences in the functions of the devices as the criteria for distinction. The words "including" and "comprising" mentioned throughout the specification and claims are open-ended terms and should be interpreted as "including but not limited to". The word "substantially" means that within an acceptable error range, those skilled in the art can solve the technical problem and achieve the basic technical effect within a certain error range. In addition, the word "coupling" in this specification includes any direct and indirect electrical connection means. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device via other devices or connection means.

[0040] Figure 1 FIG. 1 is a schematic diagram of a clock monitor circuit 100 according to an embodiment of the present invention. The clock monitor circuit 100 can be applied to a microcontroller, but is not limited thereto. Figure 1 As shown, the clock monitoring circuit 100 includes at least a tunable counter 110 and a monitor 120, both of which can be implemented by an integrated circuit. In other embodiments, the clock monitoring circuit 100 itself can also be replaced by a microcontroller 100.

[0041] The adjustable counter 110 can calculate an integer BG based on a reference clock RCLK and set a target number BT. For example, the integer BG can be initially 0 and can be selectively increased based on the reference clock RCLK, but is not limited thereto. The target number BT can be any integer greater than or equal to 2. In addition, the monitor 120 can monitor a clock under test TCLK. In some embodiments, the clock under test TCLK and the reference clock RCLK can have the same frequency and phase. In other embodiments, the clock under test TCLK and the reference clock RCLK can also have different frequencies and phases.

[0042] Figure 2 is a signal waveform diagram of the clock monitoring circuit 100 according to an embodiment of the present invention. Figure 1 and Figure 2 To understand the present invention, the adjustable counter 110 may also receive a stable signal SS related to the test clock TCLK. In some embodiments, the stable signal SS initially remains at a low logic level (i.e., logic "0") and rises to a high logic level (i.e., logic "1") after a predetermined time TD. Depending on the switching of the stable signal SS, the clock monitoring circuit 100 may operate in a first phase or a second phase. Specifically, in the first phase, the stable signal SS is at a low logic level to indicate that the test signal TCLK has not yet reached a stable state, while in the second phase, the stable signal SS is at a high logic level to indicate that the test signal TCLK has reached a stable state. It should be noted that if the stable signal SS toggles (e.g., rises from a low logic level to a high logic level), the adjustable counter 110 switches the target number BT from a larger number (i.e., a first number) to a smaller number (i.e., a second number). In some embodiments, the larger number is equal to 100, and the smaller number is equal to 2, but they can still be adjusted according to different requirements. Conversely, if the stable signal SS does not toggle (e.g., can remain at a low logic level), the adjustable counter 110 does not change the target number BT (e.g., can remain at a larger number).

[0043] The adjustable counter 110 can execute an automatic detection process to transmit a check signal SC to the monitor 120. In response to the check signal SC, if the monitor 120 is still able to detect the test clock TCLK, the monitor 120 will transmit a confirmation signal SA back to the adjustable counter 110 to reset the integer BG of the adjustable counter 110 to its initial value (e.g., 0), as shown in a first dashed box 201. The check signal SC and the confirmation signal SA can each be a high logic pulse. The automatic detection process can also be performed periodically. For example, after receiving the confirmation signal SA, the adjustable counter 110 can transmit the check signal SC to the monitor 120 again.

[0044] On the other hand, in response to the check signal SC, if the monitor 120 cannot detect the test clock TCLK (or if the test clock TCLK remains at a low logic level), the monitor 120 will not send any confirmation signal SA back to the adjustable counter 110. Since no confirmation signal SA is received, the adjustable counter 110 will not be reset and will gradually increase the integer BG based on the reference clock RCLK. For example, the integer BG of the adjustable counter 110 may increase by 1 at each rising edge of the reference clock RCLK, but this is not limited to this. When the integer BG of the adjustable counter 110 is exactly equal to the target number BT (or a larger number, such as 100), the adjustable counter 110 will generate a fail signal SF to indicate that the test clock TCLK is abnormal, as shown in a second dashed box 202. For example, the fail signal SF may be a high logic pulse. In some embodiments, the adjustable counter 110 may also reset the integer BG to its initial value when the fail signal SF is generated.

[0045] In the above embodiment, the adjustable counter 110 performs an automatic detection process during the first phase. It should be understood that the adjustable counter 110 may also perform an automatic detection process during the second phase. After the stable signal SS flips, as shown in a third dashed box 203, the adjustable counter 110 may perform an automatic detection process to transmit a check signal SC to the monitor 120. In response to the check signal SC, if the monitor 120 can still detect the test clock TCLK, the monitor 120 will transmit a confirmation signal SA back to the adjustable counter 110 to reset the integer BG of the adjustable counter 110 to its initial value.

[0046] As shown in a fourth dashed box 204, in response to the check signal SC, if the monitor 120 fails to detect the test clock TCLK (or if the test clock TCLK remains at a low logic level), the monitor 120 will not send any confirmation signal SA back to the adjustable counter 110. Due to the lack of confirmation signal SA, the adjustable counter 110 will not be reset and will continue to gradually increase the integer BG based on the reference clock RCLK. When the integer BG of the adjustable counter 110 is exactly equal to the target number BT (or a smaller number, such as 2), the adjustable counter 110 will generate a fail signal SF.

[0047] When the test clock TCLK has not yet reached a stable state (i.e., during the first phase), a relatively large target digital BT can prevent the entire system from entering power-saving mode and causing false positives. Conversely, when the test clock TCLK has reached a stable state (i.e., during the second phase), a relatively small target digital BT can prevent an excessively long lead time for generating the fail signal SF. Therefore, the switchable target digital BT significantly improves the efficiency and reliability of the clock monitoring circuit 100.

[0048] Figure 3 FIG. 2 is a schematic diagram of a clock monitoring circuit 300 according to another embodiment of the present invention. Figure 3 and Figure 1 Similar. Figure 3 In the embodiment of the present invention, the clock monitoring circuit 300 further includes a resetter 330. Figure 2 and Figure 3 When the fail signal SF is generated, the resetter 330 transmits a response signal SR to the adjustable counter 110 to pull the fail signal SF back from a high logic level to a low logic level. For example, the response signal SR may be a low logic pulse. It should be understood that the resetter 330 is an optional element and may be removed in other embodiments. Figure 3 The remaining features of the clock monitoring circuit 300 are the same as those of Figure 1 The clock monitoring circuit 100 is similar, so both embodiments can achieve similar operating effects.

[0049] Figure 4A and Figure 4B This is a flow chart of a control method according to an embodiment of the present invention. First, in step S401, a monitor monitors a clock pulse to be tested. In step S402, an adjustable counter calculates an integer based on a reference clock pulse and sets a target number. In step S403, it is determined whether a stable signal related to the clock pulse to be tested has flipped. If so, in step S404, the target number is switched from a larger number to a smaller number, and the process proceeds to step S405. If not, the target number remains unchanged, and the process proceeds directly to step S405. In step S405, an automatic detection procedure is executed to transmit a check signal to the monitor. In step S406, in response to the check signal, it is determined whether the clock pulse to be tested can be detected. If the clock pulse to be tested can be detected, a confirmation signal is transmitted back to the adjustable counter in step S407. Then, in step S408, the integer value of the adjustable counter is reset. If the clock pulse to be tested cannot be detected, no confirmation signal is transmitted back to the adjustable counter in step S409. Then, in step S410, the integer of the adjustable counter is gradually increased. In step S411, it is confirmed whether the integer of the adjustable counter is exactly equal to the target number. If not, the program will return to step S410. If so, in step S412, a failure signal is generated by the adjustable counter. It should be understood that the above steps do not need to be performed in order, but Figures 1 to 3 Each feature of the embodiment can be applied to Figure 4A and Figure 4B of the control methods.

[0050] The present invention provides a novel clock monitoring circuit, microcontroller, and control method thereof. With this design, an adjustable counter and monitor automatically detect whether the clock under test has reached a stable state. Furthermore, because the adjustable counter's target number can be switched based on a stable signal, overall system reliability is significantly improved. Compared to existing technologies, this invention offers advantages such as reduced complexity and high efficiency, making it well-suited for use in a wide variety of electronic devices.

[0051] It is worth noting that the device parameters mentioned above are not limiting conditions of the present invention. Designers can adjust these setting values ​​according to different needs. The clock monitoring circuit, microcontroller, and control method of the present invention are not limited to Figures 1 to 4B The present invention may only include Figures 1 to 4B In other words, not all of the features shown in the figures need to be implemented simultaneously in the clock monitoring circuit, microcontroller, and control method thereof of the present invention.

[0052] The method of the present invention, or a specific form or portion thereof, may be in the form of a program. The program may be contained in a physical medium, such as a floppy disk, a CD, a hard disk, or any other machine-readable (e.g., computer-readable) storage medium, or in a computer program product in a non-external form, wherein when the program is loaded and executed by a machine, such as a computer, the machine becomes an apparatus for performing the present invention. The program may also be transmitted via some transmission medium, such as a wire or cable, an optical fiber, or any other transmission method, wherein when the program is received, loaded, and executed by a machine, such as a computer, the machine becomes an apparatus for performing the present invention. When executed on a general-purpose processing unit, the program, in combination with the processing unit, provides a unique device that operates similarly to an application-specific logic circuit.

[0053] In this specification and claims, ordinal numbers, such as "first", "second", "third", etc., have no sequential relationship with each other and are only used to distinguish two different devices with the same name.

[0054] Although the present invention is disclosed above with reference to preferred embodiments, it is not intended to limit the scope of the invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be based on that defined by the claims.

Claims

1. A clock monitoring circuit, characterized in that: include: a monitor for monitoring a clock pulse to be tested; as well as an adjustable counter for counting an integer according to a reference clock and setting a target number; If a stable signal related to the clock to be measured flips, the adjustable counter switches the target number from a first number to a second number, wherein the first number is greater than the second number; The adjustable counter can execute an automatic detection process to send a detection signal to the monitor; In response to the check signal, if the clock to be tested cannot be detected, the monitor will not send any confirmation signal back to the adjustable counter, and the adjustable counter will gradually increase the integer; When the integer is equal to the target number, the adjustable counter will generate a fail signal.

2. The clock monitoring circuit according to claim 1, wherein: In response to the check signal, if the clock to be tested can be detected, the monitor will send a confirmation signal back to the adjustable counter to reset the integer of the adjustable counter.

3. The clock monitoring circuit according to claim 1, wherein: The stabilization signal initially maintains a low logic level and rises to a high logic level after a predetermined time.

4. The clock monitoring circuit according to claim 1, wherein: The stable signal is at a low logic level in a first phase and at a high logic level in a second phase.

5. The clock monitoring circuit according to claim 4, wherein: The adjustable counter can perform the automatic detection process during both the first phase and the second phase.

6. The clock monitoring circuit according to claim 1, wherein: Also includes: A resetter, wherein when the fail signal is generated, the resetter transmits a recovery signal to the adjustable counter to pull the fail signal back from a high logic level to a low logic level.

7. A control method, characterized in that: The following steps are involved: Monitoring a clock pulse to be tested through a monitor; Counting an integer according to a reference clock through an adjustable counter and setting a target number; If a stable signal related to the clock to be measured flips, the target number is switched from a first number to a second number, wherein the first number is greater than the second number; executing an automatic detection procedure to transmit a check signal to the monitor; In response to the check signal, if the clock to be tested cannot be detected, no confirmation signal is sent back to the adjustable counter, and the integer of the adjustable counter is gradually increased; and When the integer is equal to the target number, a failure signal is generated.

8. The control method according to claim 7, wherein: Also includes: When the fail signal is generated, a recovery signal is sent to the adjustable counter to pull the fail signal back from a high logic level to a low logic level.

9. A microcontroller, characterized in that: include: a monitor for monitoring a clock pulse to be tested; as well as an adjustable counter for counting an integer according to a reference clock and setting a target number; If a stable signal related to the clock to be measured flips, the adjustable counter switches the target number from a first number to a second number, wherein the first number is greater than the second number; The adjustable counter can execute an automatic detection process to send a detection signal to the monitor; In response to the check signal, if the clock to be tested cannot be detected, the monitor will not send any confirmation signal back to the adjustable counter, and the adjustable counter will gradually increase the integer; When the integer is equal to the target number, the adjustable counter will generate a fail signal.

10. The microcontroller according to claim 9, wherein: In response to the check signal, if the clock to be tested can be detected, the monitor will send a confirmation signal back to the adjustable counter to reset the integer of the adjustable counter.

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