Feature image based three-dimensional mask simulation

Abstract

Layout geometry of a photomask is received. The layout geometry is segmented into feature images, for example, selected from a library. The library contains pre-defined feature images and their corresponding pre-computed mask 3D (M3D) filters. The M3D filter for a feature image represents the electromagnetic scattering effect of that feature image for a given source illumination. Mask function contributions from each feature image are computed by convolving the feature image with its corresponding M3D filter. The mask function contributions are combined to determine a mask function of the photomask illuminated by the source illumination.

Description

[0001] Cross-references to related applications

[0002] Pursuant to 35 USC §119(e), this application claims priority to U.S. Provisional Patent Application Serial No. 63 / 079,067, filed September 16, 2020, entitled “Three-Dimensional Mask Simulations Based on Feature Images,” and U.S. Patent Application Serial No. 17 / 463,075, filed August 31, 2021, entitled “Three-Dimensional Mask Simulations Based on Feature Images.” The subject matter of all the foregoing is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to three-dimensional masking simulation, including applications for whole-chip or large-scale computational lithography. Background Technology

[0004] One step in manufacturing semiconductor wafers involves photolithography. In a typical photolithography process, a light source generates light that is collected and guided by collecting / illuminating optics to illuminate a photomask. Projection optics transfer the pattern created by the illuminated mask onto the wafer, exposing a photoresist on the wafer according to the illuminated pattern. The patterned photoresist is then used in processes that fabricate structures on the wafer.

[0005] Various techniques are involved in improving photolithography processes, including the design of photomasks. In computational lithography, the photomask design is used as input to a three-dimensional mask model, which is used to calculate a mask function describing the electromagnetic field scattering characteristics of the mask when illuminated by a light source. This mask function can then be used as input to an optical imaging model (e.g., an Abbe imaging model or a Hopkins imaging model) to predict the printed pattern in the resist. Importantly, the three-dimensional mask model must be both accurate and fast. Summary of the Invention

[0006] In one aspect, the layout geometry of the photolithographic mask is received. The layout geometry is segmented into multiple feature images, such as feature images selected from a library. This library contains predefined feature images and their corresponding pre-computed Mask 3D (M3D) filters. The M3D filter of a feature image represents the electromagnetic scattering effect of that feature image for a given source illumination. The mask function contribution from each feature image is computed by convolving the feature image with its corresponding M3D filter. These mask function contributions are combined to determine the mask function of the mask illuminated by the source illumination.

[0007] Other aspects include components, equipment, systems, improvements, methods, processes, applications, computer-readable media, and other technologies related to any aspect. Attached Figure Description

[0008] This disclosure will be more fully understood from the following detailed description and the accompanying drawings illustrating embodiments of the present disclosure. The drawings are intended to provide knowledge and understanding of embodiments of the present disclosure, but are not intended to limit the scope of the disclosure to these particular embodiments. Furthermore, the drawings are not necessarily drawn to scale.

[0009] Figure 1A Extreme ultraviolet (EUV) lithography processes applicable to embodiments of this disclosure are described.

[0010] Figure 1B This is a flowchart used to calculate the scattering from the mask.

[0011] Figure 2 It describes the segmentation of the mask layout geometry into feature images.

[0012] Figure 3 The feature images in the library are depicted.

[0013] Figure 4A This is a flowchart of the M3D filter used to calculate feature images.

[0014] Figure 4B An example M3D filter calculation is depicted.

[0015] Figure 5 This is a flowchart used for developing a feature image library.

[0016] Figure 6 The results of comparing the method described in this paper with other methods are shown.

[0017] Figure 7 This is a flowchart of various processes used during the design and manufacture of integrated circuits according to some embodiments of the present invention.

[0018] Figure 8 The diagram depicts an example computer system in which embodiments of the present disclosure may operate.

[0019] Specific implementation methods

[0020] This invention relates to three-dimensional mask simulation based on feature images. The illumination pattern of the resist on the exposed wafer depends on the geometry of the photomask and the source illumination, as well as other factors. Simulation of the photolithography process depends on the accurate prediction of the electromagnetic field generated by source illumination incident on the photomask. This field can be predicted using rigorous three-dimensional simulations of Maxwell's equations, taking into account diffraction and scattering effects. However, such simulations are computationally intensive and have long runtimes. Consequently, in many cases, rigorous three-dimensional simulations of the mask area covering the entire chip are prohibited.

[0021] Various aspects of this disclosure relate to calculating the diffraction and scattering characteristics of an electromagnetic field, represented by a mask function (MF), using a set of feature images (also known as “feature vectors”) and corresponding filters (referred to as mask 3D or M3D filters). The feature images represent the fundamental geometry that may exist within the mask, and the corresponding M3D filters represent the scattering effects produced by the feature images. The M3D filters can be determined based on rigorous electromagnetic simulations of the scattering effects of the feature images for a given source illumination.

[0022] In one approach, feature images are selected from a library of predefined feature images and their corresponding pre-computed Mask 3D (M3D) filters. The feature images in the library include, but are not limited to, the following:

[0023] 0 – Edge feature image: Volume area (without edges)

[0024] 1 - Edge feature image: Edges with different orientations

[0025] 2 – Edge Feature Image: A combination of two edges with different orientations and spatial relationships.

[0026] 3+ Edge Feature Image: A combination of three or more edges (e.g., a polygon).

[0027] The advantages of this disclosure include, but are not limited to, the following. It may be better suited for use with both machine learning (ML) and non-ML frameworks, as well as graphics processing units (GPUs). Compared to fully rigorous simulation, this method is more computationally efficient for model creation, training, and calibration, and also reduces runtime, while still producing accurate results for the mask function. The resulting mask function can also be effectively used for both Hopkins and Abbe imaging models, which could be the next step in lithography simulation.

[0028] In more detail, Figure 1AAn EUV lithography process applicable to embodiments of this disclosure is described. In this system, a light source 102 generates EUV light, which is collected and guided by a collecting / illuminating optics 104 to illuminate a mask 110. A projection optics 116 transfers a pattern generated by the illuminating mask onto a wafer 118, exposing a resist on the wafer according to the illumination pattern. The exposed resist is then developed, creating a patterned resist on the wafer. This is used to fabricate structures on the wafer, for example, through deposition, doping, etching, or other processes.

[0029] exist Figure 1A In this lithography system, the light is in the EUV wavelength range, approximately 13.5 nm or in the range of 13.3–13.7 nm. At these wavelengths, components are typically reflective rather than transmissive. Mask 110 is a reflective mask, while optics 104 and 116 are also reflective and off-axis. This is just one example. Other types of lithography systems can also be used, including those using transmissive masks and / or optics at other wavelengths including deep ultraviolet (DUV), and those using positive or negative resists.

[0030] Figure 1B This is a flowchart used to calculate the scattering from mask 110. The diffraction and scattering from mask 110 are represented by the mask function (MF) 190. Figure 1B The process uses a mask description 115 and a library 120 to compute a mask function 190 for the mask. The library contains predefined feature images 125 and corresponding filters 127, which will be referred to as Mask 3D (M3D) filters because they represent the contribution of this type of feature image to the overall mask function for a given source illumination. The M3D filter 127 incorporates the effect of the source illumination.

[0031] like Figure 1B As shown, the layout geometry of the mask is received 130 and segmented 140 into feature images. The mask function (MF) contribution from each feature image is calculated 150 by convolving 125 with its corresponding M3D filter 127. The total mask function for the mask and a given source illumination is determined by combining (e.g., summing) 160 the MF contributions from the individual feature images.

[0032] Figure 2 It describes the segmentation of the mask layout geometry into feature images. Figure 2Two shapes 210 and 220 from the layout geometry are shown, along with the segmentation of shape 210 into feature images. Shape 210 is segmented into the following feature images: a region image, six edge images, six corner images, and two edge-to-edge (E2E) images. Shape 210 can be segmented into feature images based on rules to identify different features present in the mask layout. In this example, the interior regions of polygon 210 and their contribution to the mask function are represented by the region 1 feature image. This defines which regions of the mask are opaque relative to transmission or reflection. The edge feature images (edge ​​1–edge 6) illustrate the diffraction and scattering of electromagnetic waves at the edges.

[0033] The remaining feature images are based on the combination of two edges, where there is an interaction between the two edges. The corner feature images (angle 1–angle 6) illustrate the interaction at the corners, which goes beyond the individual contributions of the two edges. Note that in Figure 2 In this context, angles include both interior and exterior angles. The edge-to-edge (E2E) feature image illustrates the interaction between parallel edges. E2E1 illustrates the interaction between edges 1 and 3. E2E2 illustrates the interaction between edge 2 and the left edge of shape 220.

[0034] Each feature image is an image. For example, a region image could be a polygon of shape 2^10. Each edge image could be a filtered version of the relevant edges. In some cases, rasterization filters are applied to generate the feature images.

[0035] The segmentation of the layout geometry uses predefined feature images 125 from library 120. Feature images from the library can be selected based on an understanding of scattering and what types of geometric features contribute to scattering.

[0036] Figure 3 Some examples of feature images from the library are depicted. The feature images are analyzed based on the number of edges. Figure 3 The feature images in the table are classified. The feature images in the top row have 0 edges, the next row has 1 edge, then 2 edges, and then 3+ edges. These are just examples and not exhaustive.

[0037] In the top row, the region feature image determines which regions of the mask are opaque, transmissive, or reflective. Practical instances of the region feature image can have different shapes, sizes, and locations, depending on the geometric layout of the shapes on the mask. The M3D filter corresponding to the region feature image represents the scattering produced by each point in a region assuming an infinitely large area; that is, the contribution of each point from a large region of the geometric layout to the mask function ignores any edge effects. Therefore, the M3D filter corresponds to instances of the region feature image (e.g., Figure 2The convolution of region 1) in the mask produces MF contributions from large regions of that shape in the mask.

[0038] In the second row, edge feature images are another important type of feature image because the diffraction or scattering of electromagnetic waves occurs at the edges. Figure 3 An edge feature image is shown, but the library can contain many types of edge images. For masks with only Manhattan geometry, the library includes four edge feature images, corresponding to the four possible orientations of the edges in Manhattan geometry. Some masks may also allow edges to be multiples of 45 degrees, or even at arbitrary angles. The M3D filter corresponding to the edge feature image represents the scattering produced by each point along the edge, which is assumed to be infinitely long.

[0039] The third row shows the feature image of another important category, which is a combination of two edges. When two edges become close enough, there will be an interaction between them. Figure 3 Several examples are shown. In the first two examples, the two edges are parallel. This is often referred to as edge-to-edge (in...). Figure 2 (marked as E2E in the middle). Figure 3 Two different polarities are shown, depending on whether the area between the two edges is filled with a mask material. In addition to the two different polarities, the library can also contain edge-to-edge feature images with different spacing between the edges, and the edges are oriented at different angles (horizontal, vertical, multiples of 45 degrees, etc.).

[0040] In the last two examples of the third row, the two edges are perpendicular to each other. These are angular feature images: interior and exterior angles, depending on polarity. The library can contain angles oriented at different angles. Other edge feature images are also possible. For example, the two edges can be at different angles to each other. The two edges can be separated but not parallel. Therefore, the two edges will slowly converge or diverge. Angles that are not 90 degrees are also possible.

[0041] The bottom row shows feature images with three or more edges. The first two examples are tips with two polarities. The library can contain versions with different widths and orientations. The next two examples are holes or passages with two polarities. Different forms can have different widths, heights, and orientations. The last example shows curved edges.

[0042] Each feature image has a corresponding filter for generating the MF contribution from the feature image. That is, the scattering effect of the feature image is captured by the M3D filter. In one approach, rigorous simulations are performed on the feature images, and the rigorous results are used to determine the M3D filter.

[0043] The M3D filter can be computed starting with low-order effects. The effect of the region image (level 0 feature image) depends only on the region's transmission or reflection. In rigorous simulation, the mask structure of this feature image is a plane of constant value. The M3D filter is a constant equal to the transmission or reflection calculated through rigorous simulation.

[0044] Next, consider the edge feature images. The edges in the layout geometry are segmented into region feature images plus edge feature images. Then, a rigorous simulation of edge scattering is modeled by adding the MF contribution from the region feature images to the MF contribution from the edge feature images. The MF contribution from the region feature images has been determined, so the mask function contributions from the edge feature images and the corresponding M3D filters can then be determined.

[0045] After considering all single-edge feature images, consider feature images consisting of two edges. Figure 4A This is a flowchart for calculating the M3D filter for feature images, proceeding from low-order to high-order feature images. Figure 4B Describing for Figure 3 Example M3D filter calculation for the two edge gap feature images shown.

[0046] exist Figure 4B In the example, M3D filters have been computed for feature images with 0 and 1 edges, and the process moves 405 to more complex feature images: two edge feature images. Next, consider 410 a gap feature image with a specific interval Δ. The mask structure of the gap feature image is determined 420 as two edges separated by the interval Δ. A rigorous 3D simulation 430 can be performed on this mask structure to produce a mask function for that mask structure.

[0047] The geometric layout of the mask structure was also segmented into 440 low-order feature images: one region feature image + two edge feature images + a gap feature image of interest. This is in Figure 4B The top row of the figure shows this. The aggregation mask function, calculated through rigorous electromagnetic simulation, is equal to the sum of the MF contributions from each feature image:

[0048]

[0049] Where I i It is a feature image, K i It corresponds to the M3D filter. It is the convolution operator, and N is the number of feature images. MF is the masking function, which in this case is known from rigorous simulations. The MF contribution for low-order feature images can be calculated using the M3D filter previously computed for these images, 450. This leaves an unknown in Equation 1, illustrated in... Figure 4BAt the bottom. This is the M3D filter used for the gap feature image, which can then be computed 460. In some cases, this can be used as M3D filter 127 in library 120.

[0050] The feature image can be a grayscale representation of the features, which allows for sparse sampling of the image. For example, edges have infinite frequency components and would require infinite bandwidth to represent them at 100% fidelity. However, it can also be represented by a low-pass filtered version of the edges, similar to grayscale blurred edges. A low-pass rasterization function can be used to rasterize polygonal shapes in a mask. This eliminates the high-frequency components of the features, retaining only the low-frequency components. This is acceptable because projection optics are essentially low-pass systems, so it will naturally filter out high (spatial) frequency components. To make it more compact and therefore faster in rasterization operations, the low-pass rasterization filter is designed to have a non-uniform response in the frequency passband compared to the uniform response of a sinc or sinc-like function. Regarding the non-uniform response of the low-pass rasterization function in its frequency passband, an equalization filter 470 can be added to compensate for the non-uniform response. The M3D filter 490 is a combination of electromagnetic scattering and equalization.

[0051] The above method can be repeated for gap feature images with different spacing Δ (e.g., in 1 nm increments). It can also be repeated for different orientations and polarities. The process can also be repeated for other two edges and more complex feature images.

[0052] Equation 1 can be computed and solved in the spatial domain using direct convolution. However, it can also be handled in the spatial frequency domain. These quantities are transformed to the spatial frequency domain, and the convolution becomes a product. The equivalent equation is then...

[0053]

[0054] Where FT{} is the Fourier transform.

[0055] In some cases, the feature images included in the library depend on the layout geometry of the mask. Figure 5 This is a flowchart for developing a feature image library. Library 120 can start with a basic set of common feature images, and then supplement these common feature images based on which feature images exist within the layout geometry of the photolithographic mask. Figure 5 In the process, a mask layout is received (510). The layout geometry is compared with feature images already in the library (520). If the library is insufficient, for example, if some features appear in the mask but there is no corresponding feature image in the library, the library can be supplemented with additional feature images (530). The M3D filter for calculating these feature images can be described as above.

[0056] In addition to computations in the spatial domain (Equation 1 and above) or the spatial-frequency domain (Equation 2 and above), computations can also be performed in parallel or sequentially. In a fully parallel approach, all feature images are convolved in parallel with their corresponding M3D filters. The results are then summed.

[0057] Various embodiments of the method described in this paper also have the following features and benefits. It is implementation-friendly for both machine learning (ML) and non-ML frameworks, as well as for graphics processing units (GPUs). As shown above, model formation is based on convolutions between feature images and M3D filters, which is compatible with popular ML frameworks (e.g., TensorFlow) and GPUs. Therefore, it can be directly implemented within these frameworks to leverage the capabilities provided by these ML frameworks for lithography applications (e.g., lithography model calibration / fine-tuning, mask layout optimization, illumination source optimization, etc.) (e.g., optimization engines, hardware acceleration, etc.).

[0058] It can also be effective data for model creation, training, and calibration. Traditional ML-based M3D models rely on machines to generate feature images and filters by learning from data. This is highly empirical and typically requires large amounts of data to avoid overfitting and ensure predictive stability. The amount of data required for generation is computationally expensive and time-consuming. In the method described here, feature images and M3D filters are generated based on physical insights, which is more stable and requires significantly less data.

[0059] It can improve runtime. Feature image generation involves rasterizing a mask polygon into a grayscale image. Traditionally, the mask polygon is rasterized to a thin mask transfer function, which is computationally inefficient because a sinc (or sinc-like) rasterization function must be used for the thin mask transfer function calculation to ensure a uniform frequency response in the passband. In the method described in this paper, a special rasterization function that is more compact than a sinc (or sinc-like) function can be designed, and is therefore computationally more efficient. This new rasterization function does not need to have a uniform frequency response in the passband. Modify the M3D filter ( Figure 4A Step 470) is used to recover the desired frequency response in the convolution between the feature image and the modified M3D filter.

[0060] It is computationally efficient for both the Hopkins and Abbe imaging models. While only one feature image (MF) is needed in the Hopkins imaging simulation, multiple MFs (one for each incident angle) are required in the Abbe imaging simulation, which significantly increases the runtime because the MF is computed multiple times if a traditional Abbe-based method is used. In the method described here, the feature image can be independent of the incident angle and therefore only needs to be computed once. Although multiple sets of M3D filters and convolutions (one for each incident angle) are used, the filters can be pre-computed, and convolutions can be performed efficiently using the FFT method.

[0061] These increases in computational efficiency and runtime make it feasible to simulate the entire mask layout of the chip within a reasonable amount of time.

[0062] Figure 6 The results comparing the above methods with other methods are shown. These experiments simulate EUV masks with different types of patterns on the mask. Figure 6 The root mean square of the CD (critical size) error in spatial images predicted using this method is shown relative to three other methods. Figure 6 In the diagram, the cross-shaded bars represent the method described in this paper, and the white bars represent other methods. The defocus of the four lines in the left group is at -60 nm, the defocus of the central group is at -20 nm, and the defocus of the right group is at +20 nm. In all cases, the method described in this paper has low RMS error.

[0063] Figure 7 A set of exemplary processes 700 are illustrated during the design, verification, and manufacturing of an article of art, such as an integrated circuit, to transform and verify design data and instructions representing an integrated circuit. Each of these processes can be constructed and enabled as multiple modules or operations. The term "EDA" stands for "Electronic Design Automation." These processes begin with the creation of a product concept 710 with information provided by a designer, which is transformed to create an article of art using a set of EDA processes 712. When the design is completed, the design is tape-out 734, which is when the pattern (e.g., geometric pattern) of the integrated circuit is sent to a manufacturing facility to create a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor dies are manufactured 736, and packaging and assembly processes 738 are performed to produce a finished integrated circuit 740.

[0064] The range of specifications for circuits or electronic structures can range from low-level transistor material placement to high-level description languages. High-level abstractions can be used to design circuits and systems using hardware description languages ​​(“HDLs”) such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be translated into logic-level register-transfer-level (“RTL”) descriptions, gate-level descriptions, placement-level descriptions, or mask-level descriptions. Each lower level of abstraction, as a less abstract description, adds more useful details to the design description, such as more details about the modules described. Lower-level abstractions with fewer abstract descriptions can be computer-generated, exported from design libraries, or created by another design automation process. An example of a specification language that specifies more detailed details in a lower-level abstraction language is SPICE, which is used for detailed descriptions of circuits with many simulation components. The description at each level of abstraction can be used by the corresponding tool for that level (e.g., a formal verification tool). The design process can use… Figure 7 The sequence shown. The EDA product (or tool) enables the described process.

[0065] During system design phase 714, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design can be partitioned into different types of modules or components.

[0066] During logic design and functional verification 716, modules or components in a circuit are specified using one or more description languages, and the functional accuracy of the specifications is checked. For example, components of a circuit can be verified to generate outputs that match the specification requirements of the designed circuit or system. Functional verification can use simulators and other programs, such as testbench generators, static HDL checkers, and formal verifiers. In some embodiments, a specific system of components referred to as a “simulator” or “prototype system” is used to accelerate functional verification.

[0067] During the synthesis and design of the 718, HDL code is converted into a netlist. In some embodiments, the netlist can be a graphical structure, where the edges of the graphical structure represent components of the circuit, and the nodes of the graphical structure represent how the components are interconnected. Both HDL code and netlist are tiered artifacts that can be used by EDA products to verify that the integrated circuit is manufactured according to a specified design. The netlist can be optimized for a target semiconductor manufacturing technology. Furthermore, the completed integrated circuit can be tested to verify that it meets specification requirements.

[0068] During netlist verification (720), the netlist is checked to ensure it conforms to timing constraints and HDL code. During design planning (722), the overall layout of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0069] During layout or physical implementation 724, physical placement (location of circuit components such as transistors or capacitors) and routing (connection of circuit components via multiple conductors) occur, and cells can be selected from a library to enable specific logic functions. As used herein, the term "cell" can specify a set of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (such as flip-flops or latches). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and are enabled for physical structure and simulation. Parameters (based on "standard cells"), such as size, are specified for selected cells, and they are made accessible in a database for use in EDA products.

[0070] During Analysis and Extraction 726, circuit functionality is verified at the placement level, allowing for improvements to the placement design. During Physical Inspection 728, the placement design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, and lithographic constraints, and that the circuit functionality matches the HDL design specifications. During Resolution Enhancement 730, the geometry of the placement is transformed to improve how the circuit design is manufactured.

[0071] During the tape-out process, data is created for the production of a photomask (if appropriate, after the application of lithographic enhancement). During mask data preparation 732, the "tape-out" data is used to generate a photomask that is used to produce the finished integrated circuit.

[0072] Computer systems (such as) Figure 8 The storage subsystem of a computer system (800) can be used to store programs and data structures used by some or all of the EDA products described herein, as well as units for developing libraries and products for using the physical and logical designs of the libraries.

[0073] Figure 8 An exemplary machine of computer system 800 is shown, within which a set of instructions can be executed to cause the machine to perform any one or more methods discussed herein. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate with the capabilities of a server or client machine in a client-server network environment, as a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0074] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, web device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) specifying the actions to be taken by the machine. Furthermore, although a single machine is shown, the term "machine" should also be understood to include any collection of machines that individually or jointly execute a set (or more) of instructions to perform any one or more methods discussed herein.

[0075] Example computer system 800 includes processing devices 802 that communicate with each other via bus 830, main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage devices 818.

[0076] Processing device 802 represents one or more processors, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements combinations of instruction sets. Processing device 802 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 802 may be configured to execute instructions 826 for performing the operations and steps described herein.

[0077] The computer system 800 may also include a network interface device 808 for communication. The computer system 800 may also include a video display unit 810 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 812 (e.g., a keyboard), a cursor control device 814 (e.g., a mouse), a graphics processing unit 822, a signal generation device 816 (e.g., a speaker), a graphics processing unit 822, a video processing unit 828, and an audio processing unit 832.

[0078] Data storage device 818 may include machine-readable storage medium 824 (also referred to as non-transitory computer-readable medium) on which one or more sets of instructions 826 or software embodying any one or more methods or functions described herein are stored. During execution of instructions 826 by computer system 800, instructions 826 may also reside wholly or at least partially in main memory 804 and / or processing device 802, which also constitute machine-readable storage media.

[0079] In some implementations, instruction 826 includes instructions that implement the functions corresponding to this disclosure. Although machine-readable storage medium 824 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine and processing device 802 to perform any one or more methods of this disclosure. Therefore, the term "machine-readable storage medium" should be understood to include, but is not limited to, solid-state memories, optical media, and magnetic media.

[0080] Certain parts described in detail above are presented based on algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are methods used by those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. An algorithm can be a sequence of operations that leads to a desired result. These operations are those that require physical manipulation of physical quantities. These quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, items, numbers, etc.

[0081] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. Unless otherwise stated, as is apparent from this disclosure, it should be understood that throughout the specification, certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulate and convert data, expressed as physical (electronic) quantities within the registers and memories of the computer system, into other data, similarly expressed as physical quantities within the computer system's memory or registers or other such information storage devices.

[0082] This disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specifically constructed for the intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0083] The algorithms and demonstrations presented herein do not inherently relate to any particular computer or other device. Various other systems can be used with the program based on the teachings herein, or it may prove convenient to construct more specialized devices to perform the method. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of the invention described herein can be implemented using a variety of programming languages.

[0084] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media include any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media include machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0085] In the foregoing disclosure, implementations of this disclosure have been described with reference to specific example implementations thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the implementations of this disclosure as set forth in the following claims. Where elements are referred to in the singular in this disclosure, more than one element may be depicted in the drawings, and the same elements are labeled with the same numerals. Therefore, this disclosure and the drawings are to be considered illustrative rather than restrictive.

Claims

1. A method comprising: Receive the layout geometry of a photomask, wherein the layout geometry of the photomask comprises a plurality of polygons; The layout geometry is segmented into multiple feature images, including rasterizing the multiple polygons using a low-pass rasterization function that has a non-uniform response in the frequency passband; The processor calculates the mask function MF contribution from the feature images by convolving each of the plurality of feature images with the corresponding mask 3D filter, wherein the mask 3D filter corresponding to the feature image represents the electromagnetic scattering effect of the feature image, and wherein the mask 3D filter includes the effect of an equalization filter that compensates for the non-uniform response. as well as The calculated MF contributions are combined to determine the mask function used for the lithography mask.

2. The method according to claim 1, further comprising: The mask 3D filter is determined based on the feature image illuminated by the source illumination through rigorous electromagnetic simulation of the scattering effect of the mask structure.

3. The method of claim 1, wherein the plurality of feature images are selected from a library containing predefined feature images and corresponding pre-computed mask 3D filters for the predefined feature images.

4. The method of claim 3, wherein the library of predefined feature images comprises feature images of different orders of complexity, and the method further comprises: The mask 3D filter is pre-calculated sequentially according to its complexity.

5. The method of claim 4, wherein determining the mask 3D filter for a feature image of high-order complexity comprises: Determine the mask structure corresponding to the higher-order feature image; The mask structure is segmented into the high-order feature image and one or more low-order feature images; Perform rigorous electromagnetic simulations to predict the mask function used for the mask structure; The MF contribution of each of the plurality of low-order feature images is calculated by convolving the low-order feature image with the corresponding mask 3D filter of the low-order feature image; as well as The mask 3D filter for the high-order feature image is determined by combining the MF contribution from the high-order feature image with the MF contribution from the low-order feature image to generate the predicted mask function for the mask structure corresponding to the high-order feature image.

6. The method of claim 4, further comprising: The predefined feature images in the library are determined based on which feature images exist in the layout geometry of the photomask.

7. The method of claim 6, wherein the library of predefined feature images comprises a common base library of feature images, which is supplemented by higher-order feature images present in the layout geometry of the lithographic mask.

8. The method of claim 1, further comprising: The mask function is applied as input to either the Abbe imaging model or the Hopkins imaging model.

9. A system comprising: A computer-readable storage medium storing instructions and a library, the library comprising predefined feature images and corresponding pre-computed mask 3D filters; as well as A processor, coupled to the computer-readable storage medium and configured to execute the instructions, which, when executed, cause the processor to: The layout geometry of a photolithographic mask is segmented into a plurality of feature images selected from the library, wherein the layout geometry of the photolithographic mask comprises a plurality of polygons, and wherein segmenting the layout geometry into the plurality of feature images comprises rasterizing the plurality of polygons using a low-pass rasterization function having a non-uniform response in the frequency passband. The mask function MF contribution from the feature images is calculated by convolving each of the plurality of feature images with the corresponding mask 3D filter from the library, wherein the mask 3D filter includes the effect of an equalization filter that compensates for the non-uniform response. as well as The calculated MF contributions are combined to determine the mask function used for the lithography mask.

10. The system of claim 9, wherein the library of predefined feature images includes region images, one or more single-edge images, and multiple multi-edge images.

11. The system of claim 10, wherein the library of predefined feature images comprises a plurality of feature images, each feature image consisting of two parallel edges.

12. The system of claim 10, wherein the library of predefined feature images comprises a plurality of feature images, each feature image consisting of two vertical edges forming an angle.

13. The system of claim 10, wherein the library of predefined feature images comprises a plurality of feature images, each feature image comprising a single edge oriented at an angle not a multiple of 45 degrees.

14. The system of claim 10, wherein the library of predefined feature images comprises a plurality of feature images, each feature image consisting of curved edges.

15. The system of claim 10, wherein the library of predefined feature images comprises region images, one or more single-edge images, and multiple double-edge images.

16. A non-transient computer-readable medium including stored instructions, which, when executed by a processor, cause the processor to: The layout geometry of a photolithographic mask is segmented into multiple feature images, wherein the layout geometry of the photolithographic mask comprises multiple polygons, and wherein segmenting the layout geometry into the multiple feature images comprises rasterizing the multiple polygons using a low-pass rasterization function that has a non-uniform response in the frequency passband. Using a mask 3D filter for the feature images, the mask function MF contribution from each of the plurality of feature images is calculated, wherein the mask 3D filter includes the effect of an equalization filter that compensates for the non-uniform response. as well as The calculated MF contributions are combined to determine the mask function used for the lithography mask.

17. The non-transient computer-readable medium of claim 16, wherein the mask 3D filter is based on rigorous electromagnetic simulation.

18. The non-transient computer-readable medium of claim 16, wherein the layout geometry includes a layout geometry for the entire chip.

19. The non-transient computer-readable medium of claim 16, wherein the source illumination of the photomask is extreme ultraviolet (EUV) illumination or deep ultraviolet (DUV) illumination.

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