In-memory computing unit and array

Abstract

The present invention relates to an in-memory computing unit and array, wherein the in-memory unit includes a single-port SRAM and a computing part, the single-port SRAM is used to store weights, and the computing part is used to perform multiplication operations, including a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, and a twelfth MOS transistor; the storage node of the single-port SRAM is respectively connected to the gate of the ninth MOS transistor and the gate of the twelfth MOS transistor; the drain of the ninth MOS transistor is respectively connected to the source of the seventh MOS transistor and the source of the eighth MOS transistor, and the drain of the twelfth MOS transistor is respectively connected to the source of the tenth MOS transistor and the source of the eleventh MOS transistor; the source of the ninth MOS transistor and the source of the twelfth MOS transistor are both grounded; the gates of the seventh MOS transistor, the eighth MOS transistor, the tenth MOS transistor, and the eleventh MOS transistor are respectively connected to a first input terminal, a second input terminal, a third input terminal, and a fourth input terminal, and the drains are respectively connected to a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal. The present invention can perform high-speed and low-power convolution calculations.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to an in-memory computing unit and array. Background Art

[0002] The rapid development of convolutional neural networks (CNNs) in fields such as object detection and image recognition requires greater consideration of power consumption and energy efficiency. However, due to the limitations of the traditional von Neumann architecture, which separates the arithmetic unit and memory, it is unable to achieve the requirements of high speed and low power consumption. Therefore, a memory-computing integrated unit is urgently needed to achieve low-power computing. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide an in-memory computing unit and array that can perform high-speed and low-power convolution calculations.

[0004] The technical solution adopted by the present invention to solve the technical problem is as follows: providing an in-memory computing unit, including a single-port SRAM and a computing part, wherein the single-port SRAM is used to store weights, and the computing part is used to perform multiplication operations, including a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, and a twelfth MOS transistor; the storage node of the single-port SRAM is respectively connected to the gate of the ninth MOS transistor and the gate of the twelfth MOS transistor; the drain of the ninth MOS transistor is respectively connected to the source of the seventh MOS transistor and the source of the eighth MOS transistor. The source of the first MOS transistor is connected to the source of the second MOS transistor, the drain of the twelfth MOS transistor is connected to the source of the tenth MOS transistor and the source of the eleventh MOS transistor respectively; the source of the ninth MOS transistor and the source of the twelfth MOS transistor are both grounded; the gate of the seventh MOS transistor is connected to the first input terminal, and the drain is connected to the first output terminal; the gate of the eighth MOS transistor is connected to the second input terminal, and the drain is connected to the second output terminal; the gate of the tenth MOS transistor is connected to the third input terminal, and the drain is connected to the third output terminal; the gate of the eleventh MOS transistor is connected to the fourth input terminal, and the drain is connected to the fourth output terminal.

[0005] The single-port SRAM is 6TSRAM.

[0006] The first input terminal, the second input terminal, the third input terminal and the fourth input terminal correspond to the least significant bit, the second least significant bit, the second most significant bit and the most significant bit of a 4-bit input signal, respectively.

[0007] There is a time delay between the first input terminal and the second input terminal when a signal is input thereto, and there is a time delay between the third input terminal and the fourth input terminal when a signal is input thereto.

[0008] The technical solution adopted by the present invention to solve the technical problem is: an in-memory computing array, including 4×N 2The above-mentioned in-memory computing units are N 2 The cells are arranged in 4 rows and columns, with the first input terminals of all the in-memory computing units in each row connected together, the second input terminals connected together, the third input terminals connected together, and the fourth input terminals connected together; the first output terminals of all the in-memory computing units in each column are connected together, the second output terminals are connected together, the third output terminals are connected together, and the fourth output terminals are connected together; the connected first output terminal, second output terminal, third output terminal, and fourth output terminal are respectively connected to the input terminal of the ADC module, and the output terminal of the ADC module is connected to the input terminal of the adder module.

[0009] Each row in the in-memory calculation array is used to store a 4-bit weight, and the four in-memory calculation units in each row are used to store the lowest bit, the second lowest bit, the second highest bit and the highest bit of the 4-bit weight in sequence.

[0010] The in-memory computing units in each column of the in-memory computing array store the same weight.

[0011] Beneficial effects

[0012] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art: the present invention adds a computing unit to the storage unit through 6 MOS tubes, overcomes the defect of the separation of the operator and the memory in the traditional von Neumann architecture, and realizes high-speed and low-power convolution calculation. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a schematic diagram of the structure of an in-memory computing unit according to an embodiment of the present invention;

[0014] Figure 2 4-bit input waveform diagram in an embodiment of the present invention;

[0015] Figure 3 It is a structural diagram of the in-memory computing array according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiments are only used to illustrate the present invention and are not used in limiting the scope of the present invention.In addition, should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall equally within the scope limited by the appended claims of the application.

[0017] An embodiment of the present invention relates to an in-memory computing unit, such as Figure 1 As shown, it includes single-port SRAM and calculation part.

[0018] The single-port SRAM is used to store weights. The single-port SRAM in this embodiment is a 6TSRAM composed of MOS transistors M1, MOS transistors M2, MOS transistors M3, MOS transistors M4, MOS transistors M5 and MOS transistors M6. The 6TSRAM is respectively connected to the bit line BL, the bit line non-BLB and the word line WL.

[0019] The calculation part is used to perform multiplication operations, including MOS transistors M7, M8, M9, M10, M11 and M12; the storage node Q of the single-port SRAM is connected to the gate of MOS transistor M9 and the gate of MOS transistor M12 respectively; the drain of MOS transistor M9 is connected to the source of MOS transistor M7 and the source of MOS transistor M8 respectively, and the drain of MOS transistor 12 is connected to the source of MOS transistor M10 and the source of MOS transistor 11 respectively; MOS The source of the MOS transistor M9 and the source of the MOS transistor M12 are both grounded; the gate of the MOS transistor M7 is connected to the first input terminal Vin1, and the drain is connected to the first output terminal Vout1; the gate of the MOS transistor M8 is connected to the second input terminal Vin2, and the drain is connected to the second output terminal Vout2; the gate of the MOS transistor M10 is connected to the third input terminal Vin3, and the drain is connected to the third output terminal Vout3; the gate of the MOS transistor M11 is connected to the fourth input terminal Vin4, and the drain is connected to the fourth output terminal Vout4.

[0020] The MOS transistors M7 and M8 share the discharge MOS transistor M9, and the MOS transistors M10 and 11 share the discharge MOS transistor M12. Therefore, in this embodiment, there is a delay between the signals of the first input terminal Vin1 and the second input terminal Vin2, and there is a delay between the signals of the third input terminal Vin3 and the fourth input terminal Vin4, thereby preventing the input signals from being valid at the same time, which would cause errors in the output results.

[0021] In this embodiment, the first input terminal Vin1, the second input terminal Vin2, the third input terminal Vin3 and the fourth input terminal Vin4 correspond to the least significant bit, the second least significant bit, the second most significant bit and the most significant bit of the 4-bit input signal respectively, so that the in-memory computing unit can realize the multiplication calculation of 1-bit weight multiplied by 4-bit input. The input waveforms of the first input terminal Vin1, the second input terminal Vin2, the third input terminal Vin3 and the fourth input terminal Vin4 are as follows: Figure 2 shown.

[0022] At the beginning of the calculation, the first output terminal Vout1, the second output terminal Vout2, the third output terminal Vout3 and the fourth output terminal Vout4 are precharged to a high level. When the weight is 1, the value of the storage node Q in the 6TSRAM is 1. When the weight is 0, the value of the storage node Q in the 6TSRAM is 0. When the input is 1, Vin is a high level. When the input is 0, Vin is a low level. When the weight Q is 1, the gates of MOS transistors M9 and M12 are high. At this point, if the first input terminal Vin1 is high, MOS transistors M7 and M9 conduct, and the first output terminal Vout1 discharges to ground through MOS transistors M7 and M9, generating a unit voltage drop, representing a calculation result of 1. If the first input terminal Vin1 is low, MOS transistor M7 is not conducting, no discharge path is created, and the first output terminal Vout1 remains unchanged, representing a calculation result of 0. When the weight Q is 0, the gates of MOS transistors M9 and M12 are low, and MOS transistors M9 and M12 are cut off. At this point, no discharge path is formed, regardless of changes in the first input terminal Vin1, and the first output terminal Vout1 remains unchanged, representing a calculation result of 0. Therefore, the first output terminal Vout1 only experiences a voltage drop when the weight Q is 1 and the first input terminal Vin1 is 1. In all other cases, the first output terminal Vout1 remains unchanged. Based on the above principle, 1-bit multiplication calculation is implemented. After the calculation of the first input terminal Vin1 is completed, the second input terminal Vin2 inputs a signal and completes the calculation operation according to the same principle as above. The third input terminal Vin3 and the fourth input terminal Vin4 are symmetrical with the first input terminal Vin1 and the second input terminal Vin2, and the operation principle is exactly the same, which will not be repeated here.

[0023] Figure 3 An in-memory computing array based on the above-mentioned in-memory computing unit is provided in this embodiment, which can be used to implement convolution calculation of 4-bit weight × 4-bit input.

[0024] The in-memory computing array includes sequentially connected SRAM storage units, ADC modules, and adder modules, which can implement convolution operations for 3×3 convolution kernels in CNN. The SRAM storage units are composed of 36 of the above-mentioned in-memory computing units. The first input terminals, second input terminals, third input terminals, and fourth input terminals of all the in-memory computing units in each row are connected together; the first output terminals, second output terminals, third output terminals, and fourth output terminals of all the in-memory computing units in each column are connected together; the connected first output terminals, second output terminals, third output terminals, and fourth output terminals are respectively connected to the input terminals of the ADC module, and the output terminals of the ADC module are connected to the input terminals of the adder module.

[0025] The 36 in-memory computing units are divided into 9 rows and 4 columns. Each of the 9 rows is used to store a 4-bit weight, and the 4 in-memory computing units in a row are used to store the 4-bit weights from low to high in sequence. That is, the first in-memory computing unit in each row stores the lowest bit of the 4-bit weight, the second in-memory computing unit stores the second lowest bit of the 4-bit weight, the third in-memory computing unit stores the second highest bit of the 4-bit weight, and the fourth in-memory computing unit stores the highest bit of the 4-bit weight. The in-memory computing units in each column store the weights of the same weight bits. For example, the 9 12TSRAMs in the first column are all used to store the first bit of the 9 4-bit weight data to ensure that the weight bits output by each column are the same, so that each column can share the outputs Vout1, Vout2, Vout3 and Vout4. Each of the 9 rows shares the input data terminal. For example, the four input data terminals in the 1st row are Vin11, Vin12, Vin13 and Vin14, and the four input data terminals in the 9th row are Vin91, Vin92, Vin93 and Vin94.

[0026] At the beginning of the calculation, the output terminals Vout1, Vout2, Vout3 and Vout4 in each column are precharged to a high level. Then, according to the calculation principle of the in-memory calculation unit, each in-memory calculation unit generates a corresponding voltage drop at Vout1, Vout2, Vout3 and Vout4 according to the weight and the actual value of the input data. Since the in-memory calculation units in each column use the common output terminals Vout1, Vout2, Vout3 and Vout4, accumulation can be achieved at the output terminals Vout1, Vout2, Vout3 and Vout4. For example, when the calculation result of all the in-memory calculation units in a column is 0, the voltages on Vout1, Vout2, Vout3, and Vout4 remain unchanged, indicating that the calculation result is 0. When the calculation result of only one in-memory calculation unit in a column is 1 and the rest are 0, Vout1, Vout2, Vout3, and Vout4 each decrease by 1 unit of voltage, indicating that the calculation result is 1. Similarly, Vout1, Vout2, Vout3, and Vout4 each decrease by a maximum of 9 units of voltage, indicating that the calculation result is 9. After the in-memory calculation unit completes the calculation, the ADC module will perform analog-to-digital conversion based on the analog voltages on the output terminals Vout1, Vout2, Vout3, and Vout4. After the analog-to-digital conversion is completed, the adder module will perform shift addition based on the digital values ​​output by the ADC module to implement convolution calculation and obtain the final result.

[0027] It is not difficult to find that the present invention adds a computing unit to the storage unit through 6 MOS tubes, overcoming the defect of the separation of the operator and the memory in the traditional von Neumann architecture, and realizing high-speed and low-power convolution calculation.

Claims

1. An in-memory computing unit, characterized in that: The device comprises a single-port SRAM and a calculation part, wherein the single-port SRAM is used to store weights, and the calculation part is used to perform multiplication operations, and includes a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, and a twelfth MOS transistor; a storage node of the single-port SRAM is respectively connected to the gate of the ninth MOS transistor and the gate of the twelfth MOS transistor; the drain of the ninth MOS transistor is respectively connected to the source of the seventh MOS transistor and the source of the eighth MOS transistor, and the drain of the twelfth MOS transistor is respectively connected to the source of the tenth MOS transistor and the source of the eleventh MOS transistor; the source of the ninth MOS transistor and the source of the twelfth MOS transistor are both grounded; the gate of the seventh MOS transistor is connected to the first input terminal, and the drain is connected to the first output terminal; the gate of the eighth MOS transistor is connected to the second input terminal, and the drain is connected to the second output terminal; the gate of the tenth MOS transistor is connected to the third input terminal, and the drain is connected to the third output terminal; the gate of the eleventh MOS transistor is connected to the fourth input terminal, and the drain is connected to the fourth output terminal.

2. The in-memory computing unit according to claim 1, wherein: The single-port SRAM is a 6T SRAM.

3. The in-memory computing unit according to claim 1, wherein: The first input terminal, the second input terminal, the third input terminal and the fourth input terminal correspond to the least significant bit, the second least significant bit, the second most significant bit and the most significant bit of a 4-bit input signal, respectively.

4. The in-memory computing unit according to claim 3, wherein: There is a time delay between the first input terminal and the second input terminal when a signal is input thereto, and there is a time delay between the third input terminal and the fourth input terminal when a signal is input thereto.

5. An in-memory computing array, characterized in that: Including 4×N 2 An in-memory computing unit according to any one of claims 1 to 4, wherein the in-memory computing unit is configured to calculate the amount of N 2 The cells are arranged in 4 rows and columns, with the first input terminals of all the in-memory computing units in each row connected together, the second input terminals connected together, the third input terminals connected together, and the fourth input terminals connected together; the first output terminals of all the in-memory computing units in each column are connected together, the second output terminals are connected together, the third output terminals are connected together, and the fourth output terminals are connected together; the connected first output terminal, second output terminal, third output terminal, and fourth output terminal are respectively connected to the input terminal of the ADC module, and the output terminal of the ADC module is connected to the input terminal of the adder module.

6. The in-memory computing array according to claim 5, characterized in that: Each row is used to store a 4-bit weight, and the four in-memory computing units in each row are used to store the lowest bit, the second lowest bit, the second highest bit and the highest bit of the 4-bit weight in sequence.

7. The in-memory computing array according to claim 6, wherein: The in-memory computing units in each column store the same weight.

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