A chip formal verification method and device, electronic equipment and storage medium

Abstract

Embodiments of the present application provide a chip formal verification method and device, electronic equipment and storage medium, and relate to the technical field of chip testing. The method comprises: receiving a file import instruction input by a user, importing a verification space parameter file indicated by the user, and recording, in the verification space parameter file, a verification space tree composed of a basic space as a tree root, a configuration space as a tree trunk, and a test space as a tree leaf; receiving a space selection instruction input by the user, and determining a target basic space, a target configuration space and a target test space indicated by the user; jointly constructing a verification space based on a basic space parameter of the target basic space, a configuration space parameter of the target configuration space and a test space parameter of the target test space; and performing formal verification on a chip based on the constructed verification space and a preset test case. The scheme provided by the embodiments of the present application can perform formal verification on a chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, in particular to a chip formal verification method and device, electronic equipment and storage medium. BACKGROUND

[0002] A chip is an important device configured in an electronic device, and whether the chip can normally run has a normal influence on the normal running of the electronic device. In order to ensure that the chip can normally run, the chip needs to be verified. Formal verification is an important verification method in the field of chip verification at present due to its characteristics of complete verification space, accurate error scene positioning, efficient verification environment and short simulation time. SUMMARY

[0003] The purpose of the embodiment of the present application is to provide a chip formal verification method, device, electronic equipment and storage medium to perform formal verification on the chip. The specific technical solutions are as follows:

[0004] In a first aspect, the embodiment of the present application provides a chip formal verification method, which comprises:

[0005] According to the file import instruction, a verification space parameter file is imported, wherein the verification space parameter file records: a basic space parameter of a basic space, a configuration space parameter of a configuration space and a test space parameter of a test space, and the basic space is taken as a tree root, the configuration space is taken as a tree trunk, and the test space is taken as a tree leaf to form a verification space tree;

[0006] A space selection instruction is obtained, and the target basic space, the target configuration space and the target test space indicated by the space selection instruction are determined from the verification space tree recorded in the verification space parameter file;

[0007] The verification space is constructed based on the basic space parameter of the target basic space, the configuration space parameter of the target configuration space and the test space parameter of the target test space;

[0008] Based on a preset test case, the constructed verification space is used to perform formal verification on the chip.

[0009] In an embodiment of the present application, the verification space parameter file is a single-scene verification space parameter file, and the verification space tree is composed of one basic space, one configuration space and one test space;

[0010] The single-scene verification space parameter file records: a basic space parameter of one basic space, a configuration space parameter of one configuration space and a test space parameter of one test space, and the test space parameter and the configuration space parameter are empty.

[0011] In one embodiment of the present application, the verification space parameter file is a double-scenario verification space parameter file, and the verification space tree is composed of one basic space, one configuration space and two test spaces, each test space corresponding to one verification scenario.

[0012] The double-scenario verification space parameter file records the basic space parameter of one basic space, the configuration space parameter of one configuration space, and the test space parameter of two test spaces corresponding to two verification scenarios.

[0013] The basic space parameter is a parameter included in both verification scenarios.

[0014] The configuration space parameter is empty.

[0015] The test space parameter of the test space corresponding to each verification scenario is a parameter included in the verification space of the scenario in addition to the basic space parameter.

[0016] In one embodiment of the present application, the verification space parameter file is a multi-scenario verification space parameter file, and the verification space tree is composed of one basic space, multiple configuration spaces and multiple test spaces, each configuration space being connected to the basic space, each configuration space being connected to at least one test space, and each test space corresponding to one verification scenario.

[0017] The multi-scenario verification space parameter file records the basic space parameter of one basic space, the configuration space parameter of multiple configuration spaces, and the test space parameter of multiple test spaces.

[0018] The basic space parameter is a parameter included in all verification scenarios.

[0019] The configuration space parameter of each configuration space is a parameter commonly included in the verification scenarios corresponding to the test spaces connected to the configuration space in addition to the basic space parameter.

[0020] The test space parameter of the test space corresponding to each verification scenario is a parameter included in the verification scenario in addition to the basic space parameter and the configuration space parameter of the configuration space connected to the test space.

[0021] In one embodiment of the present application, the space selection instruction is obtained by determining the target basic space, the target configuration space and the target test space indicated by the space selection instruction from the verification space tree recorded in the verification space parameter file.

[0022] Display the identification of the basic space, the configuration space and the test space corresponding to the parameter recorded in the file import instruction.

[0023] receive a space selection instruction containing a target identifier in the displayed identifier, determine a target basic space, a target configuration space and a target test space corresponding to the target identifier from a verification space tree recorded in the verification space parameter file.

[0024] In a second aspect, an embodiment of the present application provides a chip formal verification device, which comprises:

[0025] a file import module configured to import a verification space parameter file according to a file import instruction, wherein the verification space parameter file records a basic space parameter of a basic space, a configuration space parameter of a configuration space and a test space parameter of a test space, and the basic space is taken as a tree root, the configuration space is taken as a tree trunk and the test space is taken as a tree leaf to form a verification space tree;

[0026] an instruction receiving module configured to obtain a space selection instruction and determine a target basic space, a target configuration space and a target test space indicated by the space selection instruction from the verification space tree recorded in the verification space parameter file;

[0027] a verification space constructing module configured to jointly construct a verification space based on the basic space parameter of the target basic space, the configuration space parameter of the target configuration space and the test space parameter of the target test space;

[0028] a verification module configured to perform formal verification on a chip based on a preset test case and the constructed verification space.

[0029] In an embodiment of the present application, the verification space parameter file is a single-scenario verification space parameter file, and the verification space tree is composed of one basic space, one configuration space and one test space;

[0030] The single-scenario verification space parameter file records a basic space parameter of one basic space, a configuration space parameter of one configuration space and a test space parameter of one test space, and the test space parameter and the configuration space parameter are empty.

[0031] In an embodiment of the present application, the verification space parameter file is a double-scenario verification space parameter file, and the verification space tree is composed of one basic space, one configuration space and two test spaces, each test space corresponding to one verification scenario;

[0032] The double-scenario verification space parameter file records a basic space parameter of one basic space, a configuration space parameter of one configuration space and test space parameters of two test spaces corresponding to two verification scenarios respectively;

[0033] The basic space parameter is a parameter contained in both verification scenarios.

[0034] The configuration space parameter is empty.

[0035] The test space parameter of the test space corresponding to each verification scenario is the parameter contained by the verification scenario except the basic space parameter.

[0036] In one embodiment of the present application, the verification space parameter file is a multi-scenario verification space parameter file, the verification space tree is composed of one basic space, multiple configuration spaces and multiple test spaces, the multiple configuration spaces are connected with the basic space, each configuration space is connected with at least one test space, and each test space corresponds to one verification scenario.

[0037] The multi-scenario verification space parameter file records the basic space parameter of one basic space, the configuration space parameter of multiple configuration spaces and the test space parameter of multiple test spaces.

[0038] The basic space parameter is a parameter contained by all verification scenarios.

[0039] The configuration space parameter of each configuration space is a parameter commonly contained by the verification scenarios corresponding to the test spaces connected with the configuration space except the basic space parameter.

[0040] The test space parameter of the test space corresponding to each verification scenario is a parameter contained by the verification scenario except the basic space parameter and the configuration space parameter of the configuration space connected with the test space.

[0041] In one embodiment of the present application, the instruction receiving module is specifically configured to:

[0042] display the identifiers of the basic space, the configuration space and the test space corresponding to the parameters recorded in the file import instruction;

[0043] receive a space selection instruction containing a target identifier in the displayed identifiers, and determine a target basic space, a target configuration space and a target test space corresponding to the target identifier from the verification space tree recorded in the verification space parameter file.

[0044] In a third aspect, an embodiment of the present application provides an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete communication with each other through the communication bus.

[0045] The memory is used for storing a computer program.

[0046] The processor is used for executing the program stored on the memory, and realizes the method steps of any one of the first aspect.

[0047] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the methods described in the first aspect.

[0048] Fifthly, embodiments of the present invention also provide a computer program product containing instructions that, when run on a computer, cause the computer to perform any of the steps described in the first aspect.

[0049] Beneficial effects of the embodiments of the present invention:

[0050] This invention provides a chip formal verification method. First, a verification space parameter file is imported according to a file import instruction. This file records: basic space parameters of the basic space, configuration space parameters of the configuration space, and test space parameters of the test space. A verification space tree is constructed with the basic space as the root, the configuration space as the trunk, and the test space as the leaves. A space selection instruction is obtained, and the target basic space, target configuration space, and target test space indicated by the space selection instruction are determined from the verification space tree recorded in the verification space parameter file. The verification space is constructed based on the basic space parameters of the target basic space, the configuration space parameters of the target configuration space, and the test space parameters of the target test space. Based on preset test cases, the constructed verification space is used to perform formal verification on the chip.

[0051] As can be seen from the above, the solution provided in this embodiment of the invention pre-sets a verification space tree, which consists of a base space, a configuration space, and a test space. According to the space selection instruction, a target base space, a target configuration space, and a target test space can be selected from the verification space tree. The verification space is then constructed based on the base space parameters of the target base space, the configuration space parameters of the target configuration space, and the test space parameters of the target test space. This constructed verification space is then used to perform formal verification of the chip. Furthermore, when writing the verification space parameter file, the operator can configure different parameters of the verification space in the base space, configuration space, and test space respectively. This facilitates the accurate selection of the required target base space, target configuration space, and target test space during formal verification, thereby accurately constructing the required verification space. This avoids over-constraint or constraint crosstalk problems caused by a large discrepancy between the verification space parameters and the actual requirements of formal verification, making the formal verification of the chip more accurate, efficient, and user-friendly. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0053] Figure 1 A flowchart illustrating the first formal chip verification method provided in this embodiment of the invention;

[0054] Figure 2 This is a schematic diagram of the structure of the first verification space tree provided in an embodiment of the present invention;

[0055] Figure 3 This is a schematic diagram of the structure of the second verification space tree provided in an embodiment of the present invention;

[0056] Figure 4 This is a schematic diagram illustrating the relationship between parameters in two verification scenarios provided in an embodiment of the present invention.

[0057] Figure 5 This is a schematic diagram of the structure of the third verification space tree provided in an embodiment of the present invention;

[0058] Figure 6 This is a schematic diagram of parameter file relationships provided in an embodiment of the present invention;

[0059] Figure 7 A schematic diagram of a chip formal verification software system structure provided in an embodiment of the present invention;

[0060] Figure 8 A flowchart illustrating the second chip formal verification method provided in this embodiment of the invention;

[0061] Figure 9 A schematic diagram of a space selection interface provided in an embodiment of the present invention;

[0062] Figure 10 This is a schematic diagram of the structure of a chip formal verification device provided in an embodiment of the present invention;

[0063] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0064] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of the present invention.

[0065] To perform formal verification of chips, embodiments of the present invention provide a chip formal verification method, apparatus, electronic device, and storage medium.

[0066] This invention provides a chip formal verification method, the method comprising:

[0067] Import the verification space parameter file according to the file import command. The verification space parameter file records the basic space parameters of the basic space, the configuration space parameters of the configuration space, and the test space parameters of the test space. The verification space tree is composed of the basic space as the root, the configuration space as the trunk, and the test space as the leaves.

[0068] Obtain the space selection instruction, and determine the target base space, target configuration space, and target test space indicated by the space selection instruction from the verification space tree recorded in the verification space parameter file;

[0069] The verification space is constructed based on the basic space parameters of the target basic space, the configuration space parameters of the target configuration space, and the test space parameters of the target test space.

[0070] Based on pre-set test cases, the chip is formally verified using the constructed verification space.

[0071] As can be seen from the above, the solution provided in this embodiment of the invention pre-sets a verification space tree, which consists of a base space, a configuration space, and a test space. Users can select a target base space, a target configuration space, and a target test space from the verification space tree, and construct the verification space based on the base space parameters of the target base space, the configuration space parameters of the target configuration space, and the test space parameters of the target test space. This constructed verification space is then used to perform formal verification of the chip. Furthermore, when writing the verification space parameter file, operators can configure different parameters of the verification space in the base space, configuration space, and test space respectively. This allows users to accurately select the required target base space, target configuration space, and target test space during formal verification, thereby accurately constructing the required verification space. This avoids over-constraint or constraint crosstalk problems caused by a large discrepancy between the verification space parameters and user requirements, making the formal verification of the chip more accurate, efficient, and user-friendly.

[0072] See Figure 1This is a flowchart illustrating the first formal verification method for chips provided in this embodiment of the invention. This embodiment can be used to perform formal verification on various types of chips, including CPUs, GPUs (Graphics Processing Units), artificial intelligence chips, network chips, and other types of chips. The above method includes the following steps S101-S104.

[0073] S101: Import the verification space parameter file according to the file import command.

[0074] The file import command can be manually entered by the user, who can use a mouse, keyboard, or touchscreen to input the command and control the electronic device to import the specified verification space parameter file. Alternatively, the file import command can be pre-stored or issued by the verification management device. The file import command may record the storage address, filename, or file identifier of the specified verification space parameter file.

[0075] The aforementioned verification space parameter file records: the basic space parameters of the basic space, the configuration space parameters of the configuration space, and the test space parameters of the test space. The verification space tree is constructed with the basic space as the root, the configuration space as the trunk, and the test space as the leaves.

[0076] Specifically, the electronic device executing the embodiments of the present invention can pre-store multiple different verification space parameter files, each containing a different verification space tree, and the required verification space parameter file can be imported according to the file import command.

[0077] In addition, the aforementioned verification space parameter files are divided into single-scene verification space parameter files, dual-scene verification space parameter files, and multi-scene verification space parameter files. For a detailed description of each type of verification space parameter file, please refer to the following text, which will not be elaborated here.

[0078] S102: Obtain the space selection instruction, and determine the target base space, target configuration space, and target test space indicated by the space selection instruction from the verification space tree recorded in the above verification space parameter file.

[0079] In one embodiment of the present invention, the space selection command can be manually input by the user. The user can input the space selection command to select the target basic space, target configuration space, and target test space through a mouse, keyboard, touch screen of an electronic device, etc. The space selection command can also be pre-stored or issued by a verification management device.

[0080] The aforementioned space selection instruction records the identifiers of the target base space, the target configuration space, and the target test space. These identifiers can be the numbers, names, etc., of the target base space, the target configuration space, and the target test space. The identifiers can be represented in the form of numbers, characters, etc., and this embodiment does not limit this.

[0081] Specifically, it can be seen from the following text Figure 8 Steps S102A-S102B shown implement step S102, which will not be described in detail here.

[0082] S103: The verification space is constructed based on the basic space parameters of the target basic space, the configuration space parameters of the target configuration space, and the test space parameters of the target test space.

[0083] Specifically, the union of the basic space parameters of the target basic space, the configuration space parameters of the target configuration space, and the test space parameters of the target test space is used as the parameters of the constructed verification space to construct the verification space.

[0084] The parameters of the aforementioned verification space may include the configuration parameters of each device in the chip, control parameters used to control the chip's operating logic, etc.

[0085] S104: Based on preset test cases, formal verification of the chip is performed using the constructed verification space.

[0086] Specifically, the test cases mentioned above can be pre-set test cases that match the verification space parameter file indicated by the file import command. This embodiment does not limit the specific method of formal verification.

[0087] After formal verification, the verification results can be output or displayed, including successful verification results, results of detected runtime errors, etc., so that users can adjust the chip according to the verification results.

[0088] As can be seen from the above, the solution provided in this embodiment of the invention pre-sets a verification space tree, which consists of a base space, a configuration space, and a test space. According to the space selection instruction, a target base space, a target configuration space, and a target test space can be selected from the verification space tree. The verification space is then constructed based on the base space parameters of the target base space, the configuration space parameters of the target configuration space, and the test space parameters of the target test space. This constructed verification space is then used to perform formal verification of the chip. Furthermore, when writing the verification space parameter file, the operator can configure different parameters of the verification space in the base space, configuration space, and test space respectively. This facilitates the accurate selection of the required target base space, target configuration space, and target test space during formal verification, thereby accurately constructing the required verification space. This avoids over-constraint or constraint crosstalk problems caused by a large discrepancy between the verification space parameters and the actual requirements of formal verification, making the formal verification of the chip more accurate, efficient, and user-friendly.

[0089] The following sections (I)-(III) describe the different types of verification space parameter files.

[0090] (i) The above verification space file can be a single-scenario verification space parameter file. The verification space tree recorded in the above single-scenario verification space consists of a basic space, a configuration space and a test space.

[0091] The single-scenario verification space parameter file records: basic space parameters for a basic space, configuration space parameters for a configuration space, and test space parameters for a test space. The test space parameters and configuration space parameters are empty. In other words, all parameters of the verification space are recorded in the basic space.

[0092] See Figure 2 This is a schematic diagram of the structure of the first verification space tree provided in an embodiment of the present invention.

[0093] Depend on Figure 2As can be seen, the verification space includes a basic space represented by B (Basic), a verification space represented by CFG (Config), and a test space represented by T (Test). The verification space in the diagram is labeled CFG1, and the test space is labeled T1. The parameters of the basic space in B, the verification space parameters in CFG1, and the test space parameters in T1 together constitute the parameters of the verification space, which are used to verify a single verification scenario 1. The connection path between CFG1 and B is path 1, and the connection path between T1 and CFG1 is path 2. All parameters of the verification space are recorded in B. CFG1 is empty, T1 is empty, T1 merges into CFG1 along path 2, and CFG1 merges into B along path 1, resulting in the verification space of verification scenario 1. For example, the above verification scenario 1 can be: a scenario for verifying a control logic in a chip.

[0094] The verification space can be described mathematically as: T1 = Φ, CFG1 = Φ, Here, A represents the complete verification space.

[0095] (II) The aforementioned verification space parameter file can be a dual-scenario verification space parameter file. The verification space tree recorded in the dual-scenario verification space parameter file consists of a basic space, a configuration space, and two test spaces. Each test space corresponds to a verification scenario. For example, the two verification scenarios are: scenarios for verifying control logic 1 and control logic 2 in the chip respectively.

[0096] The aforementioned dual-scenario verification space parameter file records: basic space parameters of a basic space, configuration space parameters of a configuration space, and test space parameters of two test spaces corresponding to the two verification scenarios respectively.

[0097] The above basic spatial parameters are those included in both verification scenarios.

[0098] The above configuration space parameters are empty.

[0099] The test space parameters for each verification scenario are: parameters included in the verification space of that scenario in addition to the basic space parameters mentioned above. That is, each test space records parameters unique to the verification scenario corresponding to that test space.

[0100] Specifically, the aforementioned basic space parameters are the intersection of the parameters contained in the two verification scenarios. For example, the two verification scenarios are the scenario of verifying the control logic 1 of the chip and the scenario of verifying the control logic 2 of the chip, respectively. Both verification scenarios require the chip to be configured. Therefore, the intersection of the parameters of the two verification scenarios can be the parameters for configuring the chip, which are recorded in the basic space. The parameters unique to the two verification scenarios are recorded in the two test spaces respectively. The test space parameters in the two test spaces are different, so the intersection of the test space parameters in the two test spaces is empty.

[0101] The space selection command can instruct the selection of one of two test spaces in the validation space tree as the target test space. Depending on the selected target test space, validation spaces for different validation scenarios can be constructed. The space selection command can also instruct the selection of both test spaces in the validation space tree as target test spaces, thereby constructing a validation space that combines two validation scenarios.

[0102] See Figure 3 This is a schematic diagram of the structure of the second verification space tree provided in an embodiment of the present invention.

[0103] Depend on Figure 3 As can be seen, there are two different verification scenarios: Verification Scenario 1 and Verification Scenario 2. Verification space A contains a base space B, a configuration space CFG1, and two test spaces T1 and T2. B contains the intersection of parameters from Verification Scenario 1 and Verification Scenario 2. T1 contains parameters unique to Verification Scenario 1, T2 contains parameters unique to Verification Scenario 2, and the verification space parameters in CFG1 are empty. The connection path between CFG1 and B is path 1, the connection path between T1 and CFG1 is path 2, and the connection path between T2 and CFG1 is path 3. T1 merges into CFG1 along path 2, and CFG1 merges into B along path 1, resulting in the verification space for Verification Scenario 1. T2 merges into CFG1 along path 3, and CFG1 merges into B along path 1, resulting in the verification space for Verification Scenario 2.

[0104] The verification space can be described mathematically as follows: T1∩T2=Φ, CFG1=Φ, the parameter of verification scenario 1 ∩ the parameter of verification scenario 2=B, T1∪B=the parameter of verification scenario 1, T2∪B=the parameter of verification scenario 2.

[0105] The space selection command can specify T1 as the target test space, CFG1 as the target configuration space, and B as the target base space, thereby constructing the verification space for verification scenario 1. Alternatively, the space selection command can specify T1 and T2 together as the target test space, CFG1 as the target configuration space, and B as the target base space, thereby constructing a hybrid scenario of verification scenario 1 and verification scenario n.

[0106] See Figure 4 This is a schematic diagram illustrating the relationship between parameters in two verification scenarios provided in an embodiment of the present invention.

[0107] In this diagram, the solid circle represents the parameters of verification scenario 1, the dashed circle represents the parameters of verification scenario 2, the overlapping part between the two represents the parameters of the base space B, the part of the solid circle excluding the overlapping part represents the parameters of the test space T1, and the part of the dashed circle excluding the overlapping part represents the parameters of the test space T2.

[0108] As can be seen from the above, the dual-scenario verification space parameter file records parameters for two verification scenarios. Parameters common to both verification scenarios are recorded in the base space, while parameters unique to each scenario are recorded in their respective test spaces. After importing the dual-scenario verification space parameter file, the required target test space, target configuration space, and target base space are selected based on the space selection command, thus flexibly constructing the required verification space according to needs. Furthermore, when writing the dual-scenario verification space parameter file, staff can store the parameters of the verification scenarios in different spaces according to a clear structure, based on the relationship between the two scenarios. This facilitates the differentiation of parameters for different verification scenarios when writing the dual-scenario verification space parameter file, avoiding over-constraints or constraint crosstalk issues in the verification space. Moreover, identical parameters are stored only once in the dual-scenario verification space parameter file, thus avoiding parameter redundancy.

[0109] (III) The above verification space parameter file can be a multi-scenario verification space parameter file. The above verification space tree consists of a base space, multiple configuration spaces, and multiple test spaces. The multiple configuration spaces are all connected to the above base space, and each configuration space is connected to at least one test space. Each test space corresponds to a verification scenario. For example, the multiple verification scenarios are: verification scenario 1-verification scenario n, which verifies control logic 1 to control logic n in the chip respectively.

[0110] The aforementioned multi-scenario verification space parameter file records: basic space parameters for a basic space, configuration space parameters for multiple configuration spaces, and test space parameters for multiple test spaces.

[0111] The above basic spatial parameters are parameters included in all verification scenarios.

[0112] The configuration space parameters for each configuration space are: in addition to the basic space parameters mentioned above, the parameters commonly included in the verification scenarios corresponding to the test spaces connected to this configuration space, that is, the intersection of the parameters of the verification scenarios corresponding to the test spaces connected to this configuration space, in addition to the basic space parameters.

[0113] The test space parameters for each verification scenario are: in addition to the basic space parameters mentioned above and the configuration space parameters of the configuration space connected to the test space, the parameters included in the verification scenario, which are the parameters unique to the verification scenario.

[0114] Specifically, the aforementioned basic space parameters are the intersection of parameters included in all verification scenarios. For example, in a scenario where multiple verification scenarios verify control logic 1 through control logic n of a chip, and all n verification scenarios require chip configuration, the intersection of parameters from multiple verification scenarios can be the chip configuration parameters, recorded in the basic space. Besides the basic space parameters, parameters common to verification scenario 1 and verification scenario 2 can be recorded in one configuration space, parameters common to verification scenario 3 and verification scenario 4 can be recorded in another configuration space, and so on. Parameters unique to each verification scenario are recorded in their respective test spaces. Since the test space parameters in any two test spaces are different, the intersection of test space parameters in any two test spaces is empty. Similarly, since the configuration space parameters in any two configuration spaces are different, the intersection of configuration space parameters in any two configuration spaces is empty.

[0115] The space selection command can instruct the selection of a target test space from multiple test spaces in the verification space tree, and the selection of a target configuration space from multiple configuration spaces. Depending on the selected target test space and target configuration space, verification spaces for different verification scenarios can be constructed.

[0116] See Figure 5 This is a schematic diagram of the structure of the third verification space tree provided in the embodiments of the present invention.

[0117] Depend on Figure 5 As can be seen, there are n different verification scenarios, namely verification scenario 1 to verification scenario n. Verification space A contains a basic space B, n / 2 configuration spaces CFG1 to CFGn / 2, and N test spaces T1 to Tn. B contains the intersection of parameters of verification scenarios 1 to verification scenario n. T1 contains parameters unique to verification scenario 1, T2 contains parameters unique to verification scenario 2, and so on. CFG1 is connected to T1 and T2 respectively, and records the parameters common to T1 and T2 except for the basic space parameters. CFGn / 2 is connected to Tn-1 and Tn respectively, and records the parameters common to Tn-1 and Tn except for the basic space parameters, and so on. The connection path between CFG1 and B is path 1, the connection path between CFGn / 2 and B is path 2, the connection path between T1 and CFG1 is path 3, the connection path between T2 and CFG1 is path 4, the connection path between Tn-1 and CFGn / 2 is path 5, and the connection path between Tn and CFGn / 2 is path 6.

[0118] T1 is fed into CFG1 along path 3, and CFG1 is fed into B along path 1, resulting in the verification space for verification scenario 1. T2 is fed into CFG1 along path 4, and CFG1 is fed into B along path 1, resulting in the verification space for verification scenario 2. Tn-1 is fed into CFGn / 2 along path 5, and CFGn / 2 is fed into B along path 2, resulting in the verification space for verification scenario n-1. Tn is fed into CFGn / 2 along path 6, and CFGn / 2 is fed into B along path 2, resulting in the verification space for verification scenario n.

[0119] The verification space can be described mathematically as follows: T1∩T2=Φ, Tn-1∩Tn=Φ, CFG1∩B=Φ, CFGn / 2∩B=Φ, the parameter of verification scenario 1 ∩ the parameter of verification scenario 2, ... ∩ the parameter of verification scenario n-1 ∩ the parameter of verification scenario n=B, T1∪CFG1∪B=the parameter of verification scenario 1, T2∪CFG1∪B=the parameter of verification scenario 1, Tn-1∪CFGn / 2∪B=the parameter of verification scenario n-1, Tn∪CFGn / 2∪B=the parameter of verification scenario n.

[0120] The space selection command can specify T1 as the target test space, CFG1 as the target configuration space, and B as the target base space, thereby constructing the verification space for verification scenario 1. The space selection command can also specify T1 and Tn as target test spaces, CFG1 and CFGn / 2 as target configuration spaces, and B as the target base space, thereby constructing a hybrid scenario of verification scenario 1 and verification scenario n.

[0121] See Table 1 for the correspondence between multi-scenario verification and parameter control provided in the embodiments of the present invention.

[0122] Table 1

[0123]

[0124]

[0125] The mixed scenarios in the table are all scenarios obtained by mixing two verification scenarios. However, by using the same approach, users can select multiple target test spaces and target configuration spaces to obtain mixed scenarios containing more than two verification spaces. This embodiment will not elaborate on this further.

[0126] In other words, based on the space selection command, one can choose a test space as the target test space, a configuration space as the target configuration space, and a base space as the target base space to construct a verification space for a verification scenario, and then verify that verification scenario. Alternatively, multiple test spaces can be selected as target test spaces, one or more configuration spaces as target configuration spaces, and a base space as the target base space to construct a verification space that combines multiple verification scenarios, and then verify the combined scenario.

[0127] As can be seen from the above, the multi-scenario verification space parameter file records parameters for multiple verification scenarios. Parameters common to all verification scenarios are recorded in the base space, while parameters unique to each scenario are recorded in separate test spaces. Parameters common to some verification scenarios, excluding those in the base space, are recorded in the configuration space. After importing the multi-scenario verification space parameter file, the required target test space, target configuration space, and target base space can be selected based on the space selection command, allowing for flexible construction of the required verification space according to needs. Furthermore, when writing the multi-scenario verification space parameter file, staff can store the parameters of multiple verification scenarios in different spaces according to a clear structure, facilitating the differentiation of parameters for different verification scenarios and avoiding over-constraints or constraint crosstalk issues in the verification space. Additionally, identical parameters are stored only once in the multi-scenario verification space parameter file, thus avoiding parameter redundancy.

[0128] See Figure 6 This is a schematic diagram of the parameter file relationship provided in an embodiment of the present invention.

[0129] Figure 6 The described parameter file relationship is as follows Figure 5 The verification space tree shown represents the relationship between the parameter files of the verification space. As can be seen from the figure, the verification space tree includes the basic space, the configuration space, and the test space. The parameters of the basic space are recorded in the TCL file, specifically in the basic.tcl file. The parameters of the configuration space are recorded in the CFG.sva file, including the CFG1.sva file and the CFGn / 2.sva file. The parameters of the test space are recorded in the TEST.sva file, including the TEST1.sva file, the TEST2.sva file, the TESTn-1.sva file, and the TESTn.sva file.

[0130] See Figure 7 This is a schematic diagram of a chip formal verification software system structure provided in an embodiment of the present invention.

[0131] Depend onFigure 7 As can be seen, the software system includes a spatial parameter display unit, a parameter selection and import unit, a verification scenario construction unit, a test case execution unit, and a test result output unit. After the verification spatial parameter file parameter_control.pm is imported into the system, it is processed by the aforementioned units in sequence to complete the formal verification of the chip.

[0132] See Figure 8 This is a flowchart illustrating the second chip formal verification method provided in this embodiment of the invention, which is consistent with the aforementioned... Figure 1 Compared to the embodiment shown, step S102 can be implemented by the following steps S102A-S102B.

[0133] S102A: Displays the identifiers of the base space, configuration space, and test space corresponding to the parameters recorded in the above file import command.

[0134] Specifically, as seen above, the base space, configuration space, and test space recorded in different verification space parameter files are different. After importing the verification space parameter file, the identifiers of each space contained in the verification space tree recorded in that file can be displayed for the user to view. These identifiers can be the names or numbers of the base space, configuration space, and test space, etc.

[0135] S102B: Receives a space selection instruction containing the target identifier from the displayed identifier, and determines the target base space, target configuration space, and target test space corresponding to the target identifier from the verification space tree recorded in the above verification space parameter file.

[0136] Specifically, the aforementioned space selection instructions can be entered by the user after viewing the displayed icons, using a mouse, keyboard, touch screen of an electronic device, or other similar methods.

[0137] See Figure 9 This is a schematic diagram of a space selection interface provided in an embodiment of the present invention.

[0138] The left side of the interface displays identifiers for each space, including "B" for the basic space, "CFG1" and "CFGn / 2" for the configuration spaces, and "T1," "T2," "Tn-1," and "Tn" for the test spaces. After selecting a basic, configuration, or test space based on its identifier, the user clicks the "==>" button to confirm the selection. The identifier of the selected space is then displayed on the right side of the interface. Alternatively, the user can select a space from the right side and click the "<==" button to deselect that space. Or, the user can click the "clear list" button to deselect all selected spaces.

[0139] In addition, the aforementioned space selection instructions can also be pre-stored or issued by the verification management system.

[0140] As can be seen from the above, the embodiments of the present invention can display the identifiers of the basic space, configuration space and test space contained in the verification space tree recorded in the verification space parameter file, so that users can view the basic space, configuration space and test space from the graphical interface, thereby facilitating the construction of the verification space and completing the formal verification of the chip.

[0141] Corresponding to the aforementioned formal verification method for chips, this embodiment of the invention also provides a formal verification device for chips.

[0142] See Figure 10 This is a schematic diagram of a chip formal verification device provided in an embodiment of the present invention. The device includes:

[0143] The file import module 1001 is used to receive a file import command input by the user and import the verification space parameter file indicated by the user. The verification space parameter file records the basic space parameters of the basic space, the configuration space parameters of the configuration space, and the test space parameters of the test space. The verification space tree is formed with the basic space as the root, the configuration space as the trunk, and the test space as the leaves.

[0144] The instruction receiving module 1002 is used to obtain a space selection instruction and determine the target base space, target configuration space and target test space indicated by the space selection instruction from the verification space tree recorded in the verification space parameter file;

[0145] The verification space construction module 1003 is used to jointly construct the verification space based on the basic space parameters of the target basic space, the configuration space parameters of the target configuration space, and the test space parameters of the target test space.

[0146] Verification module 1004 is used to perform formal verification of the chip based on preset test cases and the constructed verification space.

[0147] As can be seen from the above, the solution provided in this embodiment of the invention pre-sets a verification space tree, which consists of a base space, a configuration space, and a test space. According to the space selection instruction, a target base space, a target configuration space, and a target test space can be selected from the verification space tree. The verification space is then constructed based on the base space parameters of the target base space, the configuration space parameters of the target configuration space, and the test space parameters of the target test space. This constructed verification space is then used to perform formal verification of the chip. Furthermore, when writing the verification space parameter file, the operator can configure different parameters of the verification space in the base space, configuration space, and test space respectively. This facilitates the accurate selection of the required target base space, target configuration space, and target test space during formal verification, thereby accurately constructing the required verification space. This avoids over-constraint or constraint crosstalk problems caused by a large discrepancy between the verification space parameters and the actual requirements of formal verification, making the formal verification of the chip more accurate, efficient, and user-friendly.

[0148] In one embodiment of the present invention, the verification space parameter file is a single-scenario verification space parameter file, and the verification space tree consists of a basic space, a configuration space and a test space;

[0149] The single-scenario verification space parameter file records: basic space parameters of a basic space, configuration space parameters of a configuration space, and test space parameters of a test space. The test space parameters and the configuration space parameters are empty.

[0150] In one embodiment of the present invention, the verification space parameter file is a dual-scenario verification space parameter file, and the verification space tree consists of a basic space, a configuration space and two test spaces, with each test space corresponding to a verification scenario;

[0151] The dual-scenario verification space parameter file records: basic space parameters of a basic space, configuration space parameters of a configuration space, and test space parameters of two test spaces corresponding to the two verification scenarios respectively.

[0152] The basic spatial parameters are those included in both verification scenarios;

[0153] The configuration space parameters are empty;

[0154] The test space parameters for each verification scenario are: parameters included in the verification space of that scenario in addition to the basic space parameters.

[0155] As can be seen from the above, the dual-scenario verification space parameter file records parameters for two verification scenarios. Parameters common to both verification scenarios are recorded in the base space, while parameters unique to each scenario are recorded in their respective test spaces. After importing the dual-scenario verification space parameter file, the required target test space, target configuration space, and target base space are selected based on the space selection command, thus flexibly constructing the required verification space according to needs. Furthermore, when writing the dual-scenario verification space parameter file, staff can store the parameters of the verification scenarios in different spaces according to a clear structure, based on the relationship between the two scenarios. This facilitates the differentiation of parameters for different verification scenarios when writing the dual-scenario verification space parameter file, avoiding over-constraints or constraint crosstalk issues in the verification space. Moreover, identical parameters are stored only once in the dual-scenario verification space parameter file, thus avoiding parameter redundancy.

[0156] In one embodiment of the present invention, the verification space parameter file is a multi-scenario verification space parameter file, and the verification space tree consists of a basic space, multiple configuration spaces and multiple test spaces. The multiple configuration spaces are all connected to the basic space, each configuration space is connected to at least one test space, and each test space corresponds to a verification scenario.

[0157] The multi-scenario verification space parameter file records: basic space parameters of a basic space, configuration space parameters of multiple configuration spaces, and test space parameters of multiple test spaces;

[0158] The basic spatial parameters are those included in all verification scenarios;

[0159] The configuration space parameters for each configuration space are: parameters commonly included in the verification scenarios corresponding to the test spaces connected to this configuration space, in addition to the basic space parameters.

[0160] The test space parameters for each verification scenario are: parameters included in the verification scenario, excluding the basic space parameters and the configuration space parameters of the configuration space connected to the test space.

[0161] As can be seen from the above, the multi-scenario verification space parameter file records parameters for multiple verification scenarios. Parameters common to all verification scenarios are recorded in the base space, while parameters unique to each scenario are recorded in separate test spaces. Parameters common to some verification scenarios, excluding those in the base space, are recorded in the configuration space. After importing the multi-scenario verification space parameter file, the required target test space, target configuration space, and target base space can be selected based on the space selection command, allowing for flexible construction of the required verification space according to needs. Furthermore, when writing the multi-scenario verification space parameter file, staff can store the parameters of multiple verification scenarios in different spaces according to a clear structure, facilitating the differentiation of parameters for different verification scenarios and avoiding over-constraints or constraint crosstalk issues in the verification space. Additionally, identical parameters are stored only once in the multi-scenario verification space parameter file, thus avoiding parameter redundancy.

[0162] In one embodiment of the present invention, the instruction receiving module 1002 is specifically used for:

[0163] Display the identifiers of the base space, configuration space, and test space corresponding to the parameters recorded in the file import command;

[0164] Receive a space selection instruction containing the target identifier from the displayed identifier, and determine the target base space, target configuration space, and target test space corresponding to the target identifier from the verification space tree recorded in the verification space parameter file.

[0165] As can be seen from the above, the embodiments of the present invention can display the identifiers of the basic space, configuration space and test space contained in the verification space tree recorded in the verification space parameter file, so that users can view the basic space, configuration space and test space from the graphical interface, thereby facilitating the construction of the verification space and completing the formal verification of the chip.

[0166] This invention also provides an electronic device, such as... Figure 11 As shown, it includes a processor 1101, a communication interface 1102, a memory 1103, and a communication bus 1104. The processor 1101, communication interface 1102, and memory 1103 communicate with each other via the communication bus 1104.

[0167] Memory 1103 is used to store computer programs;

[0168] When the processor 1101 executes the program stored in the memory 1103, it implements any of the method steps shown in the above-described chip formal verification method.

[0169] When performing formal verification of a chip using the electronic device provided in this embodiment of the invention, the solution provided in this embodiment pre-sets a verification space tree. The verification space tree consists of a base space, a configuration space, and a test space. According to the space selection instruction, a target base space, a target configuration space, and a target test space can be selected from the verification space tree. The verification space is then constructed based on the base space parameters of the target base space, the configuration space parameters of the target configuration space, and the test space parameters of the target test space. The constructed verification space is then used to perform formal verification of the chip. Furthermore, when writing the verification space parameter file, the operator can configure different parameters of the verification space in the base space, configuration space, and test space respectively. This facilitates the accurate selection of the required target base space, target configuration space, and target test space during formal verification, thereby accurately constructing the required verification space. This avoids over-constraint or constraint crosstalk problems caused by a large discrepancy between the parameters of the verification space and the actual requirements of formal verification, making the formal verification of the chip more accurate, efficient, and user-friendly.

[0170] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0171] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0172] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0173] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0174] In another embodiment of the present invention, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, implements the steps of any of the above-described chip formal verification methods.

[0175] When performing formal verification of a chip using a computer program stored on a computer-readable storage medium provided in this embodiment of the invention, a verification space tree is pre-set. This verification space tree consists of a base space, a configuration space, and a test space. According to space selection instructions, a target base space, a target configuration space, and a target test space can be selected from the verification space tree. The verification space is then constructed based on the base space parameters of the target base space, the configuration space parameters of the target configuration space, and the test space parameters of the target test space. This constructed verification space is then used to perform formal verification of the chip. Furthermore, when writing the verification space parameter file, the operator can configure different parameters of the verification space in the base space, configuration space, and test space respectively. This facilitates the accurate selection of the required target base space, target configuration space, and target test space during formal verification, thereby accurately constructing the required verification space. This avoids over-constraint or constraint crosstalk problems caused by a large discrepancy between the verification space parameters and the actual requirements of formal verification, making the formal verification of the chip more accurate, efficient, and user-friendly.

[0176] In another embodiment of the present invention, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute any of the chip formal verification methods described in the above embodiments.

[0177] When performing formal verification of a chip using the computer program product provided in this embodiment of the invention, the solution provided in this embodiment pre-sets a verification space tree. The verification space tree consists of a base space, a configuration space, and a test space. According to the space selection instruction, a target base space, a target configuration space, and a target test space can be selected from the verification space tree. The verification space is then constructed based on the base space parameters of the target base space, the configuration space parameters of the target configuration space, and the test space parameters of the target test space. The constructed verification space is then used to perform formal verification of the chip. Furthermore, when writing the verification space parameter file, the operator can configure different parameters of the verification space in the base space, configuration space, and test space respectively. This facilitates the accurate selection of the required target base space, target configuration space, and target test space during formal verification, thereby accurately constructing the required verification space. This avoids over-constraint or constraint crosstalk problems caused by a large discrepancy between the verification space parameters and the actual requirements of formal verification, making the formal verification of the chip more accurate, efficient, and user-friendly.

[0178] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0179] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0180] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for embodiments of apparatus, electronic devices, computer-readable storage media, and computer program products, since they are basically similar to the method embodiments, the descriptions are relatively simple, and relevant parts can be referred to the descriptions of the method embodiments.

[0181] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A formal verification method for chips, characterized in that, The method includes: Import the verification space parameter file according to the file import command. The verification space parameter file records: the basic space parameters of the basic space, the configuration space parameters of the configuration space, and the test space parameters of the test space. The verification space tree is formed with the basic space as the root, the configuration space as the trunk, and the test space as the leaves. The basic space parameters are the intersection of the parameters contained in all verification scenarios. The parameters unique to each verification scenario are recorded in different test spaces. The configuration space parameters of each configuration space are: the parameters commonly contained in the verification scenarios corresponding to the test spaces connected to the configuration space, excluding the basic space parameters. Obtain the space selection instruction, and determine the target base space, target configuration space, and target test space indicated by the space selection instruction from the verification space tree recorded in the verification space parameter file; The verification space is constructed based on the basic space parameters of the target basic space, the configuration space parameters of the target configuration space, and the test space parameters of the target test space. Based on pre-set test cases, the chip is formally verified using the constructed verification space.

2. The method according to claim 1, characterized in that, The verification space parameter file is a single-scenario verification space parameter file, and the verification space tree consists of a basic space, a configuration space, and a test space. The single-scenario verification space parameter file records: basic space parameters of a basic space, configuration space parameters of a configuration space, and test space parameters of a test space. The test space parameters and the configuration space parameters are empty.

3. The method according to claim 1, characterized in that, The verification space parameter file is a dual-scenario verification space parameter file. The verification space tree consists of a basic space, a configuration space and two test spaces, with each test space corresponding to a verification scenario. The dual-scenario verification space parameter file records: basic space parameters of a basic space, configuration space parameters of a configuration space, and test space parameters of two test spaces corresponding to the two verification scenarios respectively. The basic spatial parameters are those included in both verification scenarios; The configuration space parameters are empty; The test space parameters for each verification scenario are: parameters included in the verification space of that scenario in addition to the basic space parameters.

4. The method according to claim 1, characterized in that, The verification space parameter file is a multi-scenario verification space parameter file. The verification space tree consists of a basic space, multiple configuration spaces and multiple test spaces. The multiple configuration spaces are all connected to the basic space. Each configuration space is connected to at least one test space. Each test space corresponds to a verification scenario. The multi-scenario verification space parameter file records: basic space parameters of a basic space, configuration space parameters of multiple configuration spaces, and test space parameters of multiple test spaces; The basic spatial parameters are those included in all verification scenarios; The configuration space parameters for each configuration space are: parameters commonly included in the verification scenarios corresponding to the test spaces connected to this configuration space, in addition to the basic space parameters. The test space parameters for each verification scenario are: parameters included in the verification scenario, excluding the basic space parameters and the configuration space parameters of the configuration space connected to the test space.

5. The method according to any one of claims 1-4, characterized in that, The process of obtaining the space selection instruction involves determining the target base space, target configuration space, and target test space indicated by the space selection instruction from the verification space tree recorded in the verification space parameter file, including: Display the identifiers of the base space, configuration space, and test space corresponding to the parameters recorded in the file import command; Receive a space selection instruction containing the target identifier from the displayed identifier, and determine the target base space, target configuration space, and target test space corresponding to the target identifier from the verification space tree recorded in the verification space parameter file.

6. A chip formal verification apparatus, characterized in that, The device includes: The file import module is used to import the verification space parameter file according to the file import command. The verification space parameter file records: the basic space parameters of the basic space, the configuration space parameters of the configuration space, and the test space parameters of the test space. The verification space tree is formed with the basic space as the root, the configuration space as the trunk, and the test spaces as the leaves. The basic space parameters are the intersection of the parameters contained in all verification scenarios. The parameters unique to each verification scenario are recorded in different test spaces. The configuration space parameters of each configuration space are: the parameters commonly contained in the verification scenarios corresponding to the test spaces connected to the configuration space, excluding the basic space parameters. The instruction receiving module is used to obtain the space selection instruction and determine the target base space, target configuration space and target test space indicated by the space selection instruction from the verification space tree recorded in the verification space parameter file; The verification space construction module is used to jointly construct the verification space based on the basic space parameters of the target basic space, the configuration space parameters of the target configuration space, and the test space parameters of the target test space. The verification module is used to perform formal verification of the chip based on preset test cases and the constructed verification space.

7. The apparatus according to claim 6, characterized in that, The verification space parameter file is a single-scenario verification space parameter file, and the verification space tree consists of a basic space, a configuration space, and a test space. The single-scenario verification space parameter file records: basic space parameters of a basic space, configuration space parameters of a configuration space, and test space parameters of a test space. The test space parameters and the configuration space parameters are empty.

8. The apparatus according to claim 6, characterized in that, The verification space parameter file is a dual-scenario verification space parameter file. The verification space tree consists of a basic space, a configuration space and two test spaces, with each test space corresponding to a verification scenario. The dual-scenario verification space parameter file records: basic space parameters of a basic space, configuration space parameters of a configuration space, and test space parameters of two test spaces corresponding to the two verification scenarios respectively. The basic spatial parameters are those included in both verification scenarios; The configuration space parameters are empty; The test space parameters for each verification scenario are: parameters included in the verification space of that scenario in addition to the basic space parameters.

9. The apparatus according to claim 6, characterized in that, The verification space parameter file is a multi-scenario verification space parameter file. The verification space tree consists of a basic space, multiple configuration spaces and multiple test spaces. The multiple configuration spaces are all connected to the basic space. Each configuration space is connected to at least one test space. Each test space corresponds to a verification scenario. The multi-scenario verification space parameter file records: basic space parameters of a basic space, configuration space parameters of multiple configuration spaces, and test space parameters of multiple test spaces; The basic spatial parameters are those included in all verification scenarios; The configuration space parameters for each configuration space are: parameters commonly included in the verification scenarios corresponding to the test spaces connected to this configuration space, in addition to the basic space parameters. The test space parameters for each verification scenario are: parameters included in the verification scenario, excluding the basic space parameters and the configuration space parameters of the configuration space connected to the test space.

10. The apparatus according to any one of claims 6-9, characterized in that, The instruction receiving module is specifically used for: Display the identifiers of the base space, configuration space, and test space corresponding to the parameters recorded in the file import command; Receive a space selection instruction containing the target identifier from the displayed identifier, and determine the target base space, target configuration space, and target test space corresponding to the target identifier from the verification space tree recorded in the verification space parameter file.

11. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the steps of the method described in any one of claims 1-5.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1-5.

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