A modeling method for GaN HEMT device model considering dislocation effects

Abstract

To address the problems that existing device models fail to simultaneously consider the effects of dislocations on both drain current and gate leakage current, the models for dislocation effects on drain current fail to dynamically simulate charge capture and release, and the gate leakage current models fail to fully consider the effects of dislocations, the present invention discloses a modeling method for a GaN HEMT device model that considers dislocation effects. The modeling method includes: establishing a model for the effects of dislocations on GaN HEMT drain current; establishing a model for the effects of dislocations on GaN HEMT gate leakage current; integrating the models for the effects of dislocations on GaN HEMT drain current and gate leakage current into a surface potential-based model to obtain a GaN HEMT device model that considers dislocation effects and describes it using the Verilog‑A language; and providing a parameter extraction method for the GaN HEMT device model that considers dislocation effects.

Description

Technical Field

[0001] The present invention relates to the technical field of microelectronics modeling, and in particular to a modeling method for a gallium nitride HEMT device model taking into account the influence of dislocations. Background Art

[0002] Gallium nitride (GaN) represents a new generation of semiconductors, boasting advantages such as high breakdown electric field, high thermal conductivity, high electron mobility, and high operating temperature. Due to these exceptional properties, GaN-based high-mobility transistors (HEMTs) are considered an excellent choice for high-power and high-frequency applications. However, due to factors such as material and manufacturing process requirements, dislocations are inevitably distributed across different regions of GaN HEMTs. Dislocations induce parasitic effects such as negative charge trapping beneath the gate region and hot carrier trapping within the epitaxial structure. Carrier trapping affects the two-dimensional electron gas (2DEG) in the channel region, which in turn affects the drain current, resulting in a reduction in drain current, a shift in threshold voltage, and, consequently, reduced output power. Furthermore, dislocations create significant carrier leakage channels, increasing gate leakage current. Increased gate leakage current can lead to serious electrical reliability issues, resulting in reduced device performance, such as a decrease in breakdown voltage and an increase in noise figure. However, most existing models of dislocation effects only consider the impact of dislocations on either gate leakage or drain current. Furthermore, most gate current models fail to fully account for the impact of dislocations on gate leakage current. Therefore, it is very important to establish a model to predict the impact of dislocations on GaN HEMTs. Summary of the Invention

[0003] The present invention aims to address the deficiencies in existing modeling technologies for the effect of dislocations on GaN HEMT current and to provide a modeling method for a GaN HEMT device model that takes dislocation effects into account. The present invention aims to address the problems that existing dislocation effect models only consider the effect of dislocations on gate leakage current or drain current, that models of dislocation effects on drain current do not dynamically simulate charge capture and release, and that gate leakage current models do not fully consider the effect of dislocations. The present invention thus establishes a GaN HEMT device model that takes dislocation effects into account.

[0004] The present invention proposes a modeling method for a GaN HEMT device model taking into account the influence of dislocations, comprising the following steps:

[0005] S1. Establish a model for the effect of dislocations on GaN HEMT drain current.

[0006] S2. Establish a model for the effect of dislocations on the gate leakage current of GaN HEMTs;

[0007] S3. Combining the physical structure and behavior mechanism of GaN HEMT devices, the model of the effect of dislocations on GaN HEMT drain current obtained in S1 and the model of the effect of dislocations on GaN HEMT gate leakage current obtained in S2 are integrated into the surface potential-based model to obtain a GaN HEMT device model that takes dislocation effects into account.

[0008] S4. The model considering the effect of dislocation on GaN HEMT current established in step S3 is described in Verilog-A language so that the model can be compiled and linked into a library for use in an EDA simulation tool.

[0009] S5. Model parameter extraction and model verification:

[0010] S5-1. Conduct on-wafer testing on actual GaN HEMT devices to obtain the output characteristic curve and gate current curve of the GaN HEMT devices, and extract parameters for the model based on the test data.

[0011] S5-2. Verify the model of the effect of dislocations on GaN HEMT current, and provide a comparison of the output characteristic curves and gate current curves of the tested and simulated devices under different static biases.

[0012] Beneficial effects of the present invention:

[0013] (1) By simulating the charge capture and release process through an RC network with a diode, the drain current drop caused by the traps introduced by dislocations can be modeled. This can solve the problems of the existing trap model that do not dynamically simulate the charge capture and release and do not distinguish the trap charging and discharging paths.

[0014] (2) Taking into account the influence of acceptor-modified dislocations, the effect of dislocations on gate leakage current under reverse bias is characterized by the two-state Poole-Frenkel (PF) emission and the transport mechanism generated by two different electron transport channels introduced by dislocations. This can solve the problem that the existing gate leakage current model does not fully consider the influence of dislocations.

[0015] (3) Models for the effects of dislocations on the drain current and gate leakage current of GaN HEMTs were established separately, solving the problem that existing device models do not consider the effects of dislocations on both drain and gate leakage currents at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Provides the overall process for device testing and model parameter extraction;

[0017] Figure 2 The equivalent circuit topology of the drain current trap model of the GaN HEMT device;

[0018] Figure 3 Schematic diagram of the energy band of GaN HEMT under reverse gate voltage, where (a) is the energy band diagram of PF emission through VIII modified dislocation state, and (b) is the energy band diagram of PF emission through VIII modified dislocation state and pure dislocation state;

[0019] Figure 4 Signal setup diagram for pulse test;

[0020] Figure 5 When T=300K, the pulse I is measured under different static bias conditions. DS -V DS Data and simulation pulse I DS -V DS Data: (a) V gsq =0V, V dsq =0V; (b)V gs =-3V, V dsq =0V; (c)V gsq =-3V, V dsq =28V; (d)V gsq =-5V, V dsq =28V, V gs The value range is -4V to 1V, with a step size of 1V;

[0021] Figure 6 The curves of gate current versus gate voltage for the GaN HEMT test and simulation at T = 300k.

[0022] Figure 7 Extract flow chart for model parameters. DETAILED DESCRIPTION

[0023] The present invention will be further tested, verified, analyzed and explained below in conjunction with the accompanying drawings and specific embodiments.

[0024] The specific implementation of step S1 of establishing a model of the effect of dislocations on the drain current of GaN HEMT is as follows:

[0025] S1-1. Two resistor-capacitor (RC) subcircuits with diodes are used to simulate the trapping effect caused by dislocations. Each RC subcircuit has two resistors, and the diodes separate the charging and discharging paths. The input voltages of the gate and drain are charged and discharged through the subcircuits, and the trap voltage V g_trap and V d_trap Feedback to the model to update the cutoff voltage parameter V off , mobility degradation coefficient μ a and DIBL effect parameter V dscale , characterizing the trapping effect. The model topology is as follows Figure 2 shown.

[0026] The drain current is calculated using the surface potential model:

[0027]

[0028] where μ eff is the effective mobility, including the mobility drop caused by the vertical electric field, and is calculated as follows:

[0029]

[0030] V go Represents the difference between the effective gate voltage and the cut-off voltage, taking into account the DIBL effect, and is calculated as follows:

[0031]

[0032] where ψ ds =ψ d -ψ s , ψ m =(ψ d +ψ s ) / 2. W is the gate width, N is the gate finger, L is the gate length, θ sat is the speed saturation effect parameter, and λ is the channel length modulation effect parameter. ds The model includes accurate modeling of device second-order effects such as DIBL effect, self-heating effect and nonlinear access region resistance to represent real GaN HEMT devices;

[0033] S1-2, through the output characteristic curves under different static bias voltages, find the output characteristic curves under different static bias voltages. gsq and V dsq Changing model parameters, cut-off voltage parameter V off , mobility degradation coefficient μ a and DIBL effect parameter V dscale By adding the trap effect to these model parameters through formula (4), the model parameters can be adjusted with V gsq and V dsq The trend of change was studied, and the model of the effect of dislocations on the drain current of GaN HEMT was completed;

[0034] P=P ref +trP0·V g_trap +trP1·V d_trap (4)

[0035] Where P is the parameter value after adding the trap effect, V g_trap and V d_trap is the trap voltage generated by the trap network, P ref For when V gsq 、V dsThe initial parameter value when it is equal to 0, trP0 and trP1 are fitting parameters.

[0036] The specific implementation of step S2 of establishing the model of the effect of dislocations on the gate leakage current of GaN HEMT is as follows:

[0037] S2-1. Use two-state Poole-Frenkel emission to simulate the gate leakage current under reverse bias, fully considering the effect of dislocations on the gate leakage current. The gate current of GaN HEMT can be expressed as:

[0038] I=Area·(J TE +J PF ) (5)

[0039] Where Area is the gate area, J TE is the thermionic emission (TE) current density, J PF is the Poole-Frenkel (PF) emission current density. PF emission dominates at low to moderate reverse bias. Under reverse bias, J TE Can be ignored;

[0040] PF emission is considered to be the main leakage mechanism for gate current conduction under reverse voltage. Pure threading dislocations introduce deep occupied states above the valence band maximum (VBM) and below the conduction band minimum (CBM) of GaN, forming pure dislocation states and VIII modified dislocation states. Since PF emission originates from electron transport in continuous dislocation states, dual-state FP emission should correspond to two different dislocation states in the AlGaN barrier, namely pure dislocation states and VIII modified dislocation states. A typical conduction band diagram under medium reverse gate voltage that describes this mechanism is shown in Figure 2. Figure 3 As shown, the continuous states are located at the height of the metal Fermi level Φ d1 and Φ d2 Assume that the trap state in the barrier is very close to the metal Fermi level. Figure 3 As shown in (a), electrons first transfer along the low-energy VIII modified dislocation energy level. As the reverse voltage increases, the electrons in the modified dislocation state tend to be saturated. When the excess electrons gain enough energy, the electrons begin to transfer along the pure dislocation state, as shown in Figure 3 (b) PF current density (J PF ) and the electric field (E) is:

[0041]

[0042]

[0043]

[0044] Where C is a parameter related to the trap concentration and E is the electric field in the AlGaN barrier at the metal-semiconductor interface. dn is the barrier height for trap state electron emission, where Φ d1 =0.47eV,Φ d2 =1.07eV, ε0 is the dielectric constant of free space, ε s is the relative dielectric constant at high frequency, q is the electron charge, V T is the threshold voltage. p is the sum of the piezoelectric polarization charge in the barrier and the difference between the spontaneous polarization charge in the barrier and the buffer layer, C g is the gate capacitance, is the surface potential.

[0045] In step S3, the dislocation effect model on drain current obtained in step S1 and the dislocation effect model on gate leakage current obtained in step S2 are integrated into the surface potential-based model based on the physical structure and behavior mechanism of the GaN HEMT device. The specific implementation of the GaN HEMT device model considering the dislocation effect is as follows:

[0046] Before using EDA tools for simulation, the device model is described through the equivalent circuit topology. Figure 2 The physical meanings of the various components in the model topology of the model that models the effect of dislocations on the drain current of GaN HEMTs are explained as follows:

[0047] R g_capt 、R d_capt : The gate, drain charge capture resistor, and diode form the charging path;

[0048] R g_emit 、R d_emit : Gate and drain charge emission resistors form the discharge path;

[0049] C g_trap 、C d_trap : Gate and drain trap capacitance, acting as trap centers;

[0050] Step S4 describes the GaN HEMT device model and model topology structure considering the influence of dislocations established in step S3 using Verilog-A language to obtain a compact model. The specific implementation is as follows:

[0051] The source code for the GaN HEMT device model equations that consider the effects of dislocations is described in Verilog-A. The source code is directly compiled using the compiler provided by the EDA simulation tool and linked to the model library of commercial circuit simulation software. This also addresses the interface issues of the model entering the simulator and supporting design applications. The source code architecture of the model described in Verilog-A is as follows:

[0052]

[0053]

[0054] Step S5: GaN HEMT device model parameter extraction and model verification considering the influence of dislocations:

[0055] S5-1. Perform on-wafer testing on actual GaN HEMT devices to obtain current characteristic test data of the GaN HEMT devices, including device transistor output characteristics and gate current characteristics. Parameters for the model are extracted based on the test data. The specific method is as follows:

[0056] S5-1-1. Pulsed IV measurement is a common method for studying charge capture and emission in GaN HEMTs. Signal generators are used at the drain and gate terminals to provide inputs, such as Figure 3 As shown in Figure 2. Through pulse testing, the circuit component values ​​of the model for the effect of dislocations on the drain current of GaN HEMTs, including the trap resistance R, are extracted based on the capture and emission time constants of the charge. g_capt ,R d_capt ,R g_emit ,R d_emit and the trap capacitance C g_trap and C d_trap ;

[0057] S5-1-2. Measure the pulse I of the device under different static bias voltages DS -V DS Characteristics, commercial EDA software is used to analyze the test data and find the model parameters that change with static voltage, including the cut-off voltage V off , mobility degradation parameter μ a and DIBL effect parameter V dscale ;

[0058] S5-1-3. Fitting the I of the device under different static bias voltages DS -V DS curve, extract the variation coefficients trP0 and trP1 of each model parameter that varies with the static voltage;

[0059] S5-1-4. Measure the gate current characteristic curve under reverse bias and use EDA software to extract the gate current model parameters, including the trap concentration-related model parameter C and the relative dielectric constant ε at high frequencies. s ;

[0060] S5-1-5. Optimize and determine the model parameters extracted in steps S5-1-3 and S5-1-4 using a random optimization algorithm in EDA software. (It should be noted that the random optimization algorithm is a conventional algorithm and is therefore not specifically described or illustrated in this embodiment.)

[0061] S5-2. Verification of the GaN HEMT device model considering the influence of dislocations, and comparison of the device output characteristics and gate current characteristic curves between the test and simulation.

[0062] Table 1 shows the pulse IV test solution for GaN HEMT devices.

[0063] Table 1 Pulse IV test scheme

[0064]

[0065] In this embodiment, Figures 5-6 The test data was compared with the model simulation data. The fit between the device test data and the model simulation results shows that the GaN HEMT device model that considers dislocations can well reflect the effect of dislocations on the GaN HEMT drain current and gate leakage current, with good fitting accuracy. These device test and model simulation results validate the model's practical characterization capabilities and accuracy, demonstrating that the GaN HEMT device model that considers dislocations can well reflect the electrical characteristics of the actual device, confirming the effectiveness of the modeling technique proposed in this paper and the accuracy of the model.

Claims

1. A modeling method for a GaN HEMT device model considering the influence of dislocations, characterized in that The following steps are involved: S1. Establish a model for the effect of dislocations on GaN HEMT drain current. S2. Establish a model for the effect of dislocations on the gate leakage current of GaN HEMTs; S3. Combining the physical structure and behavior mechanism of GaN HEMT devices, the model of the effect of dislocations on GaN HEMT drain current obtained in S1 and the model of the effect of dislocations on GaN HEMT gate leakage current obtained in S2 are integrated into the surface potential-based model to obtain a GaN HEMT device model that takes dislocation effects into account. S4. Describe the GaN HEMT device model considering the influence of dislocations established in step S3 using Verilog-A language so that the model can be compiled and linked into a library for use in an EDA simulation tool; S5. Model parameter extraction and model verification: S5-1. Conduct on-wafer testing on actual GaN HEMT devices to obtain the output characteristic curve and gate current curve of the GaN HEMT devices, and extract parameters for the model based on the test data. S5-2. Verification of the GaN HEMT device model considering the influence of dislocations, providing a comparison of the output characteristic curves and gate current curves of the tested and simulated devices under different static bias conditions; The step S1 is specifically as follows: S1-1. Two resistor-capacitor RC subcircuits with diodes are used to characterize the trapping effect caused by dislocations. Each RC subcircuit has two resistors, and the diodes separate the charging and discharging paths. The input voltages of the gate and drain are charged and discharged through the subcircuits, and the resulting trap voltage V is fed back. g_trap and V d_trap , update the cut-off voltage parameter V off , mobility degradation coefficient μ a , DIBL effect parameter V dscale , characterizing the trap effect; the drain current is calculated using the surface potential model: where μ eff is the effective mobility, including the mobility drop caused by the vertical electric field, and is calculated as follows: V go Represents the difference between the effective gate voltage and the cut-off voltage, taking into account the DIBL effect, and is calculated as follows: where ψ ds =ψ d -ψ s , ψ m =(ψ d +ψ s ) / 2; W is the gate width, N is the gate finger, L is the gate length, θ sat is the velocity saturation effect parameter, λ is the channel length modulation effect parameter; the complete I ds The model includes accurate modeling of device second-order effects such as DIBL effect, self-heating effect and nonlinear access region resistance to represent real GaN HEMT devices; S1-2, through the output characteristic curves under different static bias voltages, find the output characteristic curves under different static bias voltages. gsq and V dsq Changing model parameters, cut-off voltage parameter V off , mobility degradation coefficient μ a and DIBL effect parameter V dscale By adding the trap effect to these model parameters through formula (4), the model parameters can be adjusted with V gsq and V dsq The trend of change was studied, and the model of the effect of dislocation on GaN HEMT drain current was completed; P=P ref +trP0·V g_trap +trP1·V d_trap (4) Where P is the parameter value after adding the trap effect, V g_trap and V d_trap is the trap voltage generated by the trap network, P ref For when V gsq 、V dsq The initial parameter value when it is equal to 0, trP0 and trP1 are fitting parameters; the step S2 is as follows S2-1. Use two-state Poole-Frenkel emission to simulate the gate leakage current under reverse bias, fully considering the effect of dislocations on the gate leakage current. The gate current of GaN HEMT can be expressed as: I=Area·(J TE +J PF ) (5) Where Area is the gate area, J TE is the thermionic emission (TE) current density, J PF is the PF emission current density; PF current density J PF The relationship between and the electric field E is as follows: where C is a parameter related to the trap concentration, E is the electric field in the AlGaN barrier at the metal-semiconductor interface; Φ dn is the barrier height for trap state electron emission, where Φ d1 =0.47eV,Φ d2 =1.07eV, ε0 is the dielectric constant of free space, ε s is the relative dielectric constant at high frequency, q is the electron charge, V T is the threshold voltage; σ p is the sum of the piezoelectric polarization charge in the barrier and the difference between the spontaneous polarization charge in the barrier and the buffer layer, C g is the gate capacitance, is the surface potential.

2. The method for modeling a gallium nitride HEMT device model considering the influence of dislocations according to claim 1, characterized in that: In step S3, the process of obtaining the GaN HEMT device model considering the influence of dislocations includes the following steps: Before using EDA tools for simulation, the device model needs to be described through the equivalent circuit topology. The topology of the model for the effect of dislocation on GaN HEMT drain current includes the gate and drain charge trapping resistors R g_capt and R d_capt , gate and drain charge emission resistance R g_emit and R d_emit , gate and drain trap capacitance C g_trap and C d_trap .

3. The method for modeling a gallium nitride HEMT device model considering the influence of dislocations according to claim 2, characterized in that: In step S4, the specific method of compiling and linking into the library is: The source code of the GaN HEMT device model considering the influence of dislocations is directly compiled by the compiler provided by the EDA simulation tool and linked to the model library of the commercial circuit simulation software.

4. The method for modeling a gallium nitride HEMT device model considering the influence of dislocations according to claim 3, wherein: In step S5-1, the specific method of extracting the parameters is as follows: S5-1-1. Through pulse IV testing, the circuit component values ​​of the dislocation effect model on GaN HEMT drain current are extracted based on the charge capture time constant and emission time constant, including the trap resistance R g_capt ,R d_capt ,R g_emit ,R d_emit and the trap capacitance C g_trap and C d_trap ; S5-1-2. Measure the I of the device at different static bias voltages. DS -V DS Characteristics, use EDA software to analyze the test data and find the model parameters that change with static voltage, including the cut-off voltage V off and the mobility degradation parameter μ a wait; S5-1-3, simulate the I of the device under different static bias voltages using EDA software DS -V DS Data, extract the variation coefficients of model parameters with static voltage, including trP0 and trP1; S5-1-4. Measure the gate current characteristic curve under reverse bias and use EDA software to extract the gate leakage current model parameters, including the trap concentration-related model parameter C and the relative dielectric constant ε at high frequencies. s ; S5-1-5. Optimize and determine the model parameters extracted in steps S5-1-3 to S5-1-4 using a random optimization algorithm of EDA software.

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