Memory system and method of controlling the same

Abstract

A memory system and a method of controlling the same. An embodiment disclosed herein relates to a memory device including a set of memory cells and a memory controller. In one aspect, each of the set of memory cells includes a select transistor and a storage component connected in series between a corresponding bit line and a corresponding source line. In one aspect, the memory controller is to: apply a first write voltage to a bit line coupled to a selected memory cell; apply a second write voltage to a word line coupled to a gate electrode of a select transistor of the selected memory cell during a first time period; and apply a third write voltage to a source line coupled to the selected memory cell. The second write voltage can be between the first write voltage and the third write voltage.

Description

Technical Field

[0001] One embodiment of this case relates to a memory device, and more particularly to a memory device comprising a memory controller. Background Technology

[0002] The development of electronic devices such as computers, portable devices, smartphones, and Internet of Things (IoT) devices has driven increased demand for memory devices. Memory devices are typically classified as volatile memory (VRAM) or non-volatile memory (NDRAM). VRAM stores data while powered on, but may lose this data when power is off. Unlike VRAM, NDRAM retains data even after power is off, but may be slower than VRAM. Summary of the Invention

[0003] According to one embodiment of this invention, a memory system is provided, comprising: a group of memory cells and a memory controller, each of the memory cells including a select transistor and a storage component connected in series between a corresponding bit line and a corresponding source line. The memory controller is coupled to the group of memory cells, and during a first time period, the memory controller applies a first write voltage to a bit line coupled to a selected memory cell in the group of memory cells to write data to the selected memory cell. During the first time period, the memory controller applies a second write voltage to a word line coupled to the gate electrode of the select transistor of the selected memory cell. During the first time period, the memory controller applies a third write voltage to a source line coupled to the selected memory cell. The second write voltage is between the first write voltage and the third write voltage.

[0004] According to one embodiment of this invention, a memory system is provided, comprising: a memory array and a memory controller. The memory array includes: a first memory cell, a second memory cell, a first word line, a first source line, and a second source line. The first word line is coupled to the first memory cell and the second memory cell. The first source line is coupled to the first memory cell. The second source line is coupled to the second memory cell. During a first time period, the memory controller applies a first write voltage to the first word line to write data to the first memory cell. During the first time period, the memory controller applies a second write voltage to the first source line. During the first time period, the memory controller applies a first write voltage to the second source line.

[0005] A method for controlling a memory system includes: applying a first write voltage to a bit line during a time period to write data to a selected memory cell by a memory controller; applying a second write voltage to a word line during the time period by the memory controller; applying a third write voltage to a first source line during the time period by the memory controller; and applying a second write voltage to a second source line during the time period by the memory controller. The bit line is coupled to a selected memory cell and an unselected memory cell. The word line is coupled to the selected memory cell and the unselected memory cell. The first source line is coupled to the selected memory cell. The second source line is coupled to the unselected memory cell. Attached Figure Description

[0006] The appearance of one embodiment of this disclosure is best understood when read in conjunction with the accompanying drawings, based on the following detailed description. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In practice, the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 A schematic block diagram illustrating an example memory device according to some embodiments;

[0008] Figure 2 A schematic diagram illustrating a memory array according to some embodiments;

[0009] Figure 3A This describes an instance voltage for writing data to a selected memory cell according to some embodiments;

[0010] Figure 3B This diagram illustrates the timing of the voltage used to write data to a selected memory cell according to some embodiments.

[0011] Figure 4A This describes an instance voltage for writing data to a selected memory cell according to some embodiments;

[0012] Figure 4B This diagram illustrates the timing of the voltage used to write data to a selected memory cell according to some embodiments.

[0013] Figure 5A This describes an instance voltage for reading data stored in a selected memory cell, according to some embodiments;

[0014] Figure 5B This diagram illustrates the timing of the voltage used to read data stored in a selected memory cell, according to some embodiments.

[0015] Figure 6A This describes an instance voltage for reading data stored in a selected memory cell, according to some embodiments;

[0016] Figure 6B This diagram illustrates the timing of the voltage used to read data stored in a selected memory cell, according to some embodiments.

[0017] Figure 7 A schematic diagram illustrating a memory array according to some embodiments;

[0018] Figure 8A This describes an instance voltage for writing data to a selected memory cell according to some embodiments;

[0019] Figure 8B This diagram illustrates the timing of the voltage used to write data to a selected memory cell according to some embodiments.

[0020] Figure 9A This describes an instance voltage for writing data to a selected memory cell according to some embodiments;

[0021] Figure 9B This diagram illustrates the timing of the voltage used to write data to a selected memory cell according to some embodiments.

[0022] Figure 10A This describes an instance voltage for reading data stored in a selected memory cell, according to some embodiments;

[0023] Figure 10B This diagram illustrates the timing of the voltage used to read data stored in a selected memory cell, according to some embodiments.

[0024] Figure 11A This describes an instance voltage for reading data stored in a selected memory cell, according to some embodiments;

[0025] Figure 11B This diagram illustrates the timing of the voltage used to read data stored in a selected memory cell, according to some embodiments.

[0026] Figure 12 A schematic diagram illustrating a memory array according to some embodiments;

[0027] Figure 13 A schematic diagram illustrating a memory array according to some embodiments;

[0028] Figure 14 A flowchart illustrating the writing of data to one or more memory cells according to some embodiments; and

[0029] Figure 15 This is an example block diagram of a computing system according to some embodiments.

[0030] [Symbol Explanation]

[0031] 100, 1510: Memory devices

[0032] 105,1540: Memory controller

[0033] 110: Timing Controller

[0034] 112: Bit Line Controller

[0035] 114: Character Line Controller

[0036] 118: Source Wire Controller

[0037] 120, 120A, 120B, 120C, 120D, 1545: Memory Array

[0038] 125, 125A, 125B, 125C, 125D, 125E, 125F: Memory cells

[0039] 210, 210A, 210B, 210C, 710, 710A, 710B, 710C, 1210, 1310, 1310A, 1310B, 1310C: Storage components

[0040] 220, 220A, 220B, 220C, 720, 720A, 720B, 720C: Select transistor

[0041] 300, 400, 500, 600, 800, 900, 1000, 1100: Timing Diagram

[0042] 1400: Process

[0043] 1410, 1420, 1430: Steps

[0044] 1500: Computing System

[0045] 1505: Main unit

[0046] 1515: Input device

[0047] 1520: Output device

[0048] 1525A, 1525B, 1525C: Interface

[0049] 1530A~1530N: Central Processing Unit Core

[0050] 1535: Standard Unit Application

[0051] BL, BL0~BLK: Bitline

[0052] SL,SL0~SLJ: Source lines

[0053] BL_sel,BL_unsel,SL_sel,SL_unsel,WL_sel,WL_unsel: Voltage waveforms

[0054] T0~T8: Time period

[0055] VR1, VR2, VR3: Read voltage

[0056] VW1, VW2, VW3: Write voltage

[0057] WL, WL0~WLK: Character lines Detailed Implementation

[0058] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these specific examples are merely illustrative and not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0059] Additionally, for ease of description, one embodiment herein may use spatially relative terms (such as "below," "under," "lower than," "above," "upper," "top," "bottom," and the like) to describe the relationship between one component or feature and another as illustrated in the accompanying drawings. Besides the orientations depicted in the drawings, the spatially relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and therefore the spatially relative descriptive terms used in one embodiment herein may be interpreted accordingly.

[0060] One embodiment disclosed herein relates to a memory device having independently controllable or configurable source lines. In some embodiments, the memory device includes a memory array and a memory controller. The memory array includes an array of memory cells and bit lines, word lines, and source lines coupled to the memory cell array. The bit lines and word lines may extend parallel to each other along a first direction, and the source lines may extend in a second direction traversing the first direction. Each memory cell may include a select transistor and a storage component connected in series between a corresponding bit line and a corresponding source line. The storage component may be an electrofused component, a magnetic tunnel junction (MTJ) cell, a metal-insulator-metal (MIM) capacitor, or any data-storing element. The transistor can be a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), a high-voltage transistor, a high-frequency transistor, a fin field effect transistor, a planar metal oxide semiconductor field effect transistor with convex source / drain, a nanosheet field effect transistor, a nanowire field effect transistor, or the like.

[0061] In some embodiments, the memory device includes a memory controller for applying various voltages to write data to selected memory cells. In one embodiment, during a first time period, the memory controller applies a first write voltage to a bit line coupled to a selected memory cell in the set of memory cells. During the first time period, the memory controller may apply a second write voltage to a word line coupled to the gate electrode of a select transistor of the selected memory cell. During the first time period, the memory controller may apply a third write voltage to a source line coupled to the selected memory cell. The second write voltage may be between the first write voltage and the third write voltage. In one embodiment, a first difference between the first write voltage and the second write voltage may be less than the allowable stress voltage of the select transistor, and a second difference between the second write voltage and the third write voltage may be less than the allowable stress voltage of the select transistor.

[0062] Advantageously, the memory device can be implemented in a compact form and operate reliably. In one embodiment, programming data to or writing to a selected memory cell involves applying a high voltage to the bit line and word line to burn out the storage component or change its resistance. However, applying a high voltage exceeding the allowable stress voltage of the select transistor between the word line and the source line may damage the select transistor. In one embodiment, two or more transistors connected in series may be provided in each memory cell to prevent excessive voltage from being applied to the transistors. However, this implementation may increase the area of ​​the memory device. In one embodiment disclosed herein, each memory cell may include a single select transistor and a single storage component to form a 1T1R or 1T1C configuration to achieve area efficiency, while applying a second write voltage to the word line such that excessive voltage is not applied to the source transistor, thus protecting the source transistor and ensuring reliable operation.

[0063] Figure 1 This is a diagram of a memory device 100 (or memory system 100) according to one embodiment. In some embodiments, the memory device 100 includes a memory controller 105 and a memory array 120. The memory array 120 may include a plurality of storage circuits or memory cells 125 configured in a two-dimensional or three-dimensional array. Each memory cell 125 may be coupled to a corresponding word line WL, a corresponding bit line BL, and a corresponding source line SL. The memory controller 105 may write data to or read data from the memory array 120 according to electrical signals via the word line WL, the bit line BL, and the source line SL. In other embodiments, the memory device 100 includes a... Figure 1 The diagram shows more, fewer, or different elements.

[0064] Memory array 120 is a hardware element for storing data. In one embodiment, memory array 120 is embodied as a semiconductor memory device. Memory array 120 includes a plurality of storage circuits or memory cells 125. Memory array 120 includes: source lines SL0, SL1, ..., SLJ, each extending in a first direction (e.g., the X direction); word lines WL0, WL1, ..., WLK, each extending in a second direction (e.g., the Y direction); and bit lines BL0, BL1, ..., BLK, each extending in the second direction. The source lines SL, word lines WL, and bit lines BL may be conductive metal or conductive rails. In one embodiment, each memory cell 125 is coupled to a corresponding word line WL, a corresponding bit line BL, and a corresponding source line SL, and can operate according to voltage or current passing through the corresponding word line WL, the corresponding bit line BL, and the corresponding source line SL. Each memory cell 125 may include volatile memory, non-volatile memory, or a combination thereof. In some embodiments, the memory array 120 includes additional wiring (e.g., reference lines, reference control lines, power rails, etc.).

[0065] Memory controller 105 is a hardware element that controls the operation of memory array 120. In some embodiments, memory controller 105 includes bit line controller 112, word line controller 114, source line controller 118, and timing controller 110. Bit line controller 112, word line controller 114, source line controller 118, and timing controller 110 may be implemented as logic circuits, analog circuits, or a combination thereof. In one configuration, word line controller 114 is circuitry that provides voltage or current via one or more word lines WL of memory array 120. Bit line controller 112 is circuitry that provides or reads voltage or current via one or more bit lines BL of memory array 120, and source line controller 118 is circuitry that provides or reads voltage or current via one or more source lines SL of memory array 120. In one configuration, timing controller 110 is circuitry that provides control signals or clock signals to synchronize the operation of bit line controller 112, word line controller 114, and source line controller 118. Bit line controller 112 is coupled to bit line BL of memory array 120, word line controller 114 is coupled to word line WL of memory array 120, and source line controller 118 is coupled to source line SL of memory array 120. In some embodiments, memory controller 105 includes a bit line controller BL. Figure 1 The diagram shows more, fewer, or different elements.

[0066] In one state, timing controller 110 determines a selected memory cell 125 from a plurality of memory cells in memory array 120, and causes bit line controller 112, word line controller 114, and source line controller 118 to apply different voltages to the selected and unselected wires. The selected wire may be a wire coupled to the selected memory cell, while the unselected wire may be a wire not coupled to the selected memory cell. Data can be programmed into the selected memory cell 125 or accessed by applying specific voltages to the selected bit line, selected source line, and selected word line. See below for further details. Figures 2 to 14 A detailed description is provided of the operations of bit line controller 112, word line controller 114 and source line controller 118 in writing data to memory unit 125 and reading data stored in memory unit 125.

[0067] Figure 2 This diagram illustrates a memory array 120A according to some embodiments. The memory array 120A may be... Figure 1 This is part of a memory array 120. The memory array 120A may include an array of memory cells 125 (e.g., 125A, 125B, 125C). The memory array 120A may also include source lines SL0, ..., SL3 extending along a first direction (e.g., the X direction), bit lines BL0, ..., BL3 extending along a second direction (e.g., the Y direction), and word lines WL0, ..., WL3 extending along a second direction (e.g., the Y direction).

[0068] Each memory cell 125 may include a select transistor 220 and a storage component 210 connected in series between a corresponding bit line BL and a corresponding source line SL. The storage component 210 may be a fuse component, an MTJ cell, or any programmable resistor. The select transistor 220 may be an N-type transistor (e.g., an N-type MOSFET, an N-type BJT, an N-type fin field-effect transistor, etc.). In one configuration, one end of the storage component 210 is coupled to the corresponding bit line BL, and the other end of the storage component 210 is coupled to the drain electrode of the select transistor 220. In another configuration, the gate electrode of the select transistor 220 is coupled to the corresponding word line WL, and the source electrode of the select transistor 220 is coupled to the corresponding source line SL. In this configuration, the memory cell 125 may have a T1R configuration to have a small form factor. In some embodiments, the select transistor 220 may be replaced by an element capable of performing the functionality of the select transistor 220 described herein.

[0069] Figure 3A This describes an example voltage applied to memory array 120A according to some embodiments to write data to selected memory cells (e.g., 125A). In one example, memory controller 105... Figure 3AThe diagram illustrates that write voltages VW1, VW2, and VW3 are applied to the source line SL, bit line BL, and word line WL to write data to a selected memory cell 125A containing storage unit 210A and select transistor 220A. In one example, write voltage VW1 may be a high voltage (e.g., above 1.5V) sufficient to burn out or change the resistance of storage unit 210. Write voltage VW3 may be ground voltage (e.g., 0V). Write voltage VW2 may be the voltage between write voltages VW1 and VW3 (e.g., 0.6V to 1.0V). In one instance, the difference between write voltages VW2 and VW3 may be greater than the threshold voltage of select transistor 220 but less than the allowable stress voltage of select transistor 220. Additionally, the difference between write voltages VW1 and VW2 may be less than the allowable stress voltage of select transistor 220.

[0070] In a state, such as Figure 3A The write voltages VW1, VW2, and VW3 applied as shown allow the selected memory cell 125A to be programmed. For example, write voltage VW1 is applied to storage unit 210A via bit line BL1, write voltage VW3 is applied to the source electrode of select transistor 220A via source line SL2, and write voltage VW2 is applied to the gate electrode of select transistor 220A via word line WL1. Because a voltage difference greater than the threshold voltage (e.g., VW2-VW3) can be applied between the gate electrode and source electrode of select transistor 220A, select transistor 220A can be enabled, allowing a large voltage difference (e.g., VW1-VW3) to be applied across storage unit 210A. By applying a large voltage difference (e.g., VW1-VW3) across storage unit 210A, storage unit 210A can be burned out and programmed accordingly.

[0071] At the same time, such as Figure 3A The write voltages VW1, VW2, and VW3 applied to the ground plane as shown prevent the unselected memory cell 125B, which is coupled to the selected word line WL1 and the unselected source line SL1, from being programmed, while simultaneously programming the selected memory cell 125A. For example, write voltage VW1 is applied to the storage unit 210B via bit line BL1, and write voltage VW2 is applied to the source electrode of the select transistor 220B via source line SL1, and also to the gate electrode of the select transistor 220B via word line WL1. Because a voltage difference smaller than a threshold voltage (e.g., 0V or VW2-VW2) can be applied between the gate and source electrodes of the select transistor 220B, the select transistor 220B can be disabled to prevent the storage unit 210B from being programmed.

[0072] Similarly, such as Figure 3AThe write voltages VW1, VW2, and VW3 applied to the ground as shown prevent the unselected memory cell 125C, which is coupled to the selected source line SL2 and the unselected word line WL0, from being programmed, while simultaneously programming the selected memory cell 125A. For example, write voltage VW3 is applied to the storage unit 210C via bit line BL0, and simultaneously applied to the source electrode of the select transistor 220C via source line SL2, and to the gate electrode of the select transistor 220C via word line WL0. Because a voltage difference smaller than a threshold voltage (e.g., 0V or VW3-VW3) can be applied between the gate and source electrodes of the select transistor 220C, the select transistor 220C can be disabled to prevent the storage unit 210C from being programmed.

[0073] Figure 3B This illustrates a timing diagram 300 illustrating the voltage for writing data to a selected memory cell 125A according to some embodiments. In one method, the memory controller 105 applies different voltage waveforms at different stages, such as... Figure 3B As shown, data is written to a selected memory cell 125A. For example, the memory controller 105 may apply a voltage waveform SL_sel to a selected source line (e.g., SL2) coupled to the selected memory cell (e.g., 125A) and apply a voltage waveform SL_unsel to unselected source lines (e.g., SL0, SL1, SL3). For example, the memory controller 105 may apply a voltage waveform WL_sel to a selected word line (e.g., WL1) coupled to the selected memory cell (e.g., 125A) and apply a voltage waveform WL_unsel to unselected word lines (e.g., WL0, WL2, WL3). For example, the memory controller 105 may apply a voltage waveform BL_sel to a selected bit line (e.g., BL1) coupled to the selected memory cell (e.g., 125A) and apply a voltage waveform BL_unsel to unselected bit lines (e.g., BL0, BL2, BL3).

[0074] In one example, during time period T0, a write voltage VW3 (e.g., ground voltage) can be applied to bit line BL, source line SL, and word line WL. By applying the write voltage VW3 (e.g., 0V) to bit line BL, source line SL, and word line WL, memory cell 125 can be left unprogrammed.

[0075] During time period T1, a write voltage VW2 (e.g., 0.6V to 1.0V) can be applied to the source lines (e.g., SL0 to SL3). Simultaneously, the write voltage VW2 can be applied to the selected bit lines (e.g., BL1) coupled to the selected memory cell 125A, and the write voltage VW3 can be applied to the unselected bit lines (e.g., BL0, BL2, BL3). Additionally, the write voltage VW3 can be applied to the word lines (e.g., WL0 to WL3). Because a voltage difference smaller than the threshold voltage (e.g., -VW2 or VW3-VW2) can be applied between the gate and source electrodes of the memory cell selection transistor 220, the selection transistor 220 of the memory cell 125 can be disabled, and the memory cell 125 can be left unprogrammed.

[0076] During time period T2, a write voltage VW2 (e.g., 0.6V to 1.0V) can be applied to the source lines (e.g., SL0 to SL3). Additionally, a write voltage VW2 can be applied to the selected bit line (e.g., BL1) coupled to the selected memory cell 125A, and a write voltage VW3 can be applied to the unselected bit lines (e.g., BL0, BL2, BL3). During time period T2, a write voltage VW2 (e.g., 0.6V to 1.0V) is applied to the selected word line (e.g., WL1) coupled to the selected memory cell (e.g., 125A), while a write voltage VW3 (e.g., 0V) is applied to the unselected word lines (e.g., WL0, WL2, WL3). Even if a write voltage VW2 is applied to a selected word line (e.g., WL1) coupled to a selected memory cell (e.g., 125A) during time period T2, a voltage difference (e.g., 0V or VW2-VW2) smaller than the threshold voltage can be applied between the gate and source electrodes of the select transistors (e.g., 220A, 220B) coupled to the selected word line (e.g., WL1), such that the select transistors (e.g., 220A, 220B) coupled to the selected word line (e.g., WL1) can be disabled, and the memory cell 125 coupled to the selected word line (e.g., WL1) can be unprogrammed.

[0077] During time period T3, a write voltage VW2 (e.g., 0.6V to 1.0V) can be applied to the source lines (e.g., SL0 to SL3). Additionally, a write voltage VW1 (e.g., above 1.5V) can be applied to the selected bit line (e.g., BL1) coupled to the selected memory cell 125A, and a write voltage VW3 can be applied to the unselected bit lines (e.g., BL0, BL2, BL3). During time period T3, a write voltage VW2 (e.g., 0.6V to 1.0V) is applied to the selected word line (e.g., WL1) coupled to the selected memory cell (e.g., 125A), while a write voltage VW3 (e.g., 0V) is applied to the unselected word lines (e.g., WL0, WL2, WL3). Furthermore, even if a write voltage VW2 is applied to a selected word line (e.g., WL1) coupled to a selected memory cell (e.g., 125A) during time period T3, the selected transistor (e.g., 220A, 220B) coupled to the selected word line (e.g., WL1) can be disabled because a voltage difference (e.g., 0V or VW2-VW2) less than the threshold voltage can be applied between the gate and source electrodes of the selected transistor (e.g., 220A, 220B) coupled to the selected word line (e.g., WL1), and the memory cell 125 coupled to the selected word line (e.g., WL1) does not need to be programmed.

[0078] During time period T4, a write voltage VW3 (e.g., 0V) can be applied to a selected source line (e.g., SL2) coupled to a selected memory cell (e.g., 125A), while a write voltage VW2 (e.g., 0.6V to 1.0V) can be applied to unselected source lines (e.g., SL0, SL1, SL3). Additionally, a write voltage VW1 (e.g., above 1.5V) can be applied to a selected bit line (e.g., BL1) coupled to the selected memory cell 125A, and a write voltage VW3 can be applied to unselected bit lines (e.g., BL0, BL2, BL3). During time period T4, a write voltage VW2 (e.g., 0.6V to 1.0V) can be applied to a selected word line (e.g., WL1) coupled to the selected memory cell (e.g., 125A), while a write voltage VW3 (e.g., 0V) can be applied to unselected word lines (e.g., WL0, WL2, WL3). During time period T4, the select transistor (e.g., 220A) of the selected memory cell (e.g., 125A) can be enabled because a voltage difference (e.g., VW2 or VW2-VW3) greater than the threshold voltage can be applied between the gate and source electrodes of the select transistor (e.g., 220A) of the selected memory cell (e.g., 125A) coupled to the selected word line (e.g., WL1) and the selected source line (e.g., SL2). By enabling the select transistor (e.g., 220A) of the selected memory cell (e.g., 125A), a high voltage (e.g., VW1-VW3) can be applied to the storage component (e.g., 210A) of the selected memory cell (e.g., 125A) to program data. Meanwhile, during time period T4, since a voltage difference (e.g., 0V or VW2-VW2) less than the threshold voltage can be applied between the gate and source electrodes of the selection transistor (e.g., 220B) of the unselected memory cell 125 coupled to the selected word line (e.g., WL1) and the unselected source line (e.g., SL0, SL1, SL3), the selection transistor (e.g., 220B) coupled to the selected word line (e.g., WL1) and the unselected source line (e.g., SL0, SL1, SL3) can be disabled to prevent the unselected memory cell 125 coupled to the selected word line (e.g., WL1) and the unselected source line (e.g., SL0, SL1, SL3) from being programmed. Additionally, during time period T4, since a voltage difference (e.g., 0V or VW3-VW3) less than the threshold voltage can be applied between the gate and source electrodes of the selection transistor (e.g., 220C) of the unselected memory cell 125 coupled to the selected source line (e.g., SL2) and the unselected word line (e.g., WL0, WL2, WL3), the selection transistor (e.g., 220C) coupled to the selected source line (e.g., SL2) and the unselected word line (e.g., WL0, WL2, WL3) can be disabled to prevent the unselected memory cell 125 coupled to the selected source line (e.g., SL2) and the unselected word line (e.g., WL0, WL2, WL3) from being programmed.

[0079] In one state, the transition periods (e.g., T1, T2, T3) are shorter than the programming period (e.g., T4). For example, the transition periods (e.g., T1, T2, T3) can be from 0.1 ns to 5 ns to ensure that the bit line BL, word line WL, and source line SL have sufficient time to charge or discharge to a steady-state voltage, thus avoiding unwanted current flowing through memory cell 125 during the transition. Meanwhile, the programming period (e.g., T4) can be from 1 μs to 10 μs to allow sufficient current to flow through memory cell 125 and ensure proper programming.

[0080] After programming the selected memory cell (e.g., 125A), the memory controller 105 can apply voltages during time periods T5, T6, T7, and T8, respectively, as the voltages applied during time periods T3, T2, T1, and T0. For example, during time period T5, the memory controller 105 applies voltages to the source line SL, word line WL, and bit line BL, as the voltages applied during time period T3. For example, during time period T6, the memory controller 105 applies voltages to the source line SL, word line WL, and bit line BL, as the voltages applied during time period T2. For example, during time period T7, the memory controller 105 applies voltages to the source line SL, word line WL, and bit line BL, as the voltages applied during time period T1. For example, during time period T8, the memory controller 105 applies voltages to the source line SL, word line WL, and bit line BL, as the voltages applied during time period T0. Therefore, for the sake of brevity, a detailed description of its repeated parts is omitted in one embodiment of this document.

[0081] Advantageously, the memory array 120A can be reliably programmed and operated. In one state, the difference between the write voltage VW2 and the write voltage VW3 can be greater than the threshold voltage of the select transistor 220, but less than the allowable stress voltage of the select transistor 220. Furthermore, the difference between the write voltage VW1 and the write voltage VW2 can be less than the allowable stress voltage of the select transistor 220. Therefore, during programming, excessive voltage can be avoided by applying it to the select transistor 220, allowing the memory cell 125 to be programmed without damaging the select transistor 220.

[0082] Figure 4A This describes example voltages applied to memory array 120A according to some embodiments to write data to selected memory cells (e.g., 125A). In addition to applying the write voltage VW2 to unselected bit lines (e.g., BL0, BL2, BL3), Figure 4A The voltage applied in is similar to Figure 3AThe voltage applied in the process. Therefore, for the sake of brevity, a detailed description of its repeated parts is omitted in one embodiment herein. In one state, applying a write voltage VW2 to the unselected bit lines BL (e.g., BL0, BL2, BL3) ensures that no voltage stress is applied to the memory cell 125 coupled to the unselected bit lines BL (e.g., BL0, BL2, BL3).

[0083] Figure 4B Timing diagram 400 illustrates the voltage for writing data to a selected memory cell (e.g., 125A) according to some embodiments. Timing diagram 400 is similar to timing diagram 300 except that a write voltage VW2 is applied to unselected bit lines BL (e.g., BL0, BL2, BL3) during time periods T1 to T7. By applying the write voltage VW2 to the unselected bit lines BL (e.g., BL0, BL2, BL3), no voltage stress can be applied to the memory cell 125 coupled to the unselected bit lines BL (e.g., BL0, BL2, BL3).

[0084] Figure 5A This describes an example voltage applied to memory array 120A according to some embodiments to read data stored by selected memory cells 125A. In one example, memory controller 105, as... Figure 5A The diagram illustrates that read voltages VR1, VR2, and VR3 are applied to the source line SL, bit line BL, and word line WL to read data stored in a selected memory cell 125A, which includes a storage component 210A and a select transistor 220A. In one example, read voltage VR1 may be a voltage (e.g., 0.3V to 0.7V) that allows current to flow through the selected memory cell (e.g., 125A). Read voltage VR3 may be ground voltage (e.g., 0V). Read voltage VR2 may be a voltage greater than the threshold voltage of select transistor 220 (e.g., 0.6V to 1.0V). Read voltage VR2 may be greater than read voltage VR1.

[0085] In a state, such as Figure 5AThe read voltages VR1, VR2, and VR3 applied to the ground as shown allow selected memory cell 125A to conduct current. For example, read voltage VR1 is applied to storage unit 210A via bit line BL1, read voltage VR3 is applied to the source electrode of select transistor 220A via source line SL2, and read voltage VR2 is applied to the gate electrode of select transistor 220A via word line WL1. Because a voltage difference greater than the threshold voltage (e.g., VR2-VR3) can be applied between the gate and source electrodes of select transistor 220A, select transistor 220A can be enabled and conduct current according to the programmed state of storage unit 210A. For example, if storage unit 210A is burned out or programmed, no current flows through select transistor 220A. For example, if storage unit 210A is not burned out or programmed, current can flow through select transistor 220A. Bit line controller 112 can read the current via the selected bit line BL coupled to the selected memory cell 125, or source line controller 118 can read the current via the selected source line SL coupled to the selected memory cell 125, to determine the programmed state of the selected memory cell 125 based on the read current.

[0086] At the same time, such as Figure 5A The read voltages VR1, VR2, and VR3 applied to the ground as shown prevent current conduction in the unselected memory cell 125B coupled to the selected word line WL1 and the unselected source line SL1, while the selected memory cell 125A can conduct current according to a programmed state. For example, read voltage VR1 is applied to the storage unit 210B via bit line BL1, and simultaneously, read voltage VR1 is applied to the source electrode of the select transistor 220B via source line SL1, and read voltage VR2 is applied to the gate electrode of the select transistor 220B via word line WL1. Because the source electrode of the select transistor 220B and the storage unit 210B have the same voltage, no current flows through the select transistor 220B and the storage unit 210B regardless of whether the select transistor 220B is enabled or not.

[0087] Similarly, such as Figure 5AThe read voltages VR1, VR2, and VR3 applied to the ground as shown prevent current conduction in the unselected memory cell 125C coupled to the selected source line SL2 and the unselected word line WL0, while the selected memory cell 125A can conduct current according to a programmed state. For example, read voltage VR3 is applied to the storage unit 210C via bit line BL0, and simultaneously applied to the source electrode of the select transistor 220C via source line SL2, and to the gate electrode of the select transistor 220C via word line WL0. Because a voltage difference less than a threshold voltage (e.g., 0V) can be applied between the gate and source electrodes of the select transistor 220C, the select transistor 220C can be disabled and can not conduct current. Even when the select transistor 220C is enabled, the source electrode of the select transistor 220C and the storage unit 210C have the same voltage, so that no current can flow through the select transistor 220C and the storage unit 210C.

[0088] Figure 5B A timing diagram 500 illustrates the voltage used to read data stored in a selected memory cell (e.g., 125A) according to some embodiments. In one method, the memory controller 105 applies different voltage waveforms at different stages, such as... Figure 5B As shown, data stored in a selected memory cell 125A can be read. For example, the memory controller 105 may apply a voltage waveform SL_sel to a selected source line (e.g., SL2) coupled to the selected memory cell (e.g., 125A) and apply a voltage waveform SL_unsel to unselected source lines (e.g., SL0, SL1, SL3). For example, the memory controller 105 may apply a voltage waveform WL_sel to a selected word line (e.g., WL1) coupled to the selected memory cell (e.g., 125A) and apply a voltage waveform WL_unsel to unselected word lines (e.g., WL0, WL2, WL3). For example, the memory controller 105 may apply a voltage waveform BL_sel to a selected bit line (e.g., BL1) coupled to the selected memory cell (e.g., 125A) and apply a voltage waveform BL_unsel to unselected bit lines (e.g., BL0, BL2, BL3).

[0089] In one example, during time period T0, a read voltage VR3 (e.g., ground voltage) can be applied to bit line BL, source line SL, and word line WL. By applying the read voltage VR3 (e.g., 0V) to bit line BL, source line SL, and word line WL, memory cell 125 can not conduct current.

[0090] During time period T1, a read voltage VR1 (e.g., 0.3V to 1.0V) can be applied to the source lines (e.g., SL0 to SL3). Simultaneously, the read voltage VR1 can be applied to the selected bit lines (e.g., BL1) coupled to the selected memory cell 125A, and the read voltage VR3 can be applied to the unselected bit lines (e.g., BL0, BL2, BL3). Additionally, the read voltage VR3 can be applied to the word lines (e.g., WL0 to WL3). Because a voltage difference smaller than the threshold voltage (e.g., -VR1 or VR3-VR1) can be applied between the gate and source electrodes of the select transistor 220, the select transistor 220 can be disabled, and the memory cell 125 can not conduct current.

[0091] During time period T2, a read voltage VR1 (e.g., 0.3V to 1.0V) can be applied to the source lines (e.g., SL0 to SL3). Additionally, read voltage VR1 can be applied to the selected bit line (e.g., BL1) coupled to the selected memory cell 125A, and read voltage VR3 can be applied to the unselected bit lines (e.g., BL0, BL2, BL3). During time period T2, read voltage VR2 (e.g., 0.6V to 1.0V) is applied to the selected word line (e.g., WL1) coupled to the selected memory cell (e.g., 125A), while read voltage VR3 (e.g., 0V) is applied to the unselected word lines (e.g., WL0, WL2, WL3). Even if the read voltage VR2 is applied to the selected word line (e.g., WL1) during the time period T2, the source electrodes of the select transistors (e.g., 220A, 220B) and the storage components (e.g., 210A, 210B) coupled to the selected word line WL can have the same voltage, so that no current can flow through the select transistors (e.g., 220A, 220B) and storage components (e.g., 210A, 210B) coupled to the selected word line WL.

[0092] During time period T3, a read voltage VR3 (e.g., 0V) can be applied to a selected source line (e.g., SL2) coupled to a selected memory cell (e.g., 125A), while a read voltage VR1 (e.g., 0.3V to 1.0V) can be applied to unselected source lines (e.g., SL0, SL1, SL3). Additionally, a read voltage VR1 can be applied to a selected bit line (e.g., BL1) coupled to the selected memory cell 125A, and a read voltage VR3 can be applied to unselected bit lines (e.g., BL0, BL2, BL3). During time period T3, a read voltage VR2 (e.g., 0.6V to 1.0V) can be applied to a selected word line (e.g., WL1) coupled to the selected memory cell (e.g., 125A), while a read voltage VR3 (e.g., 0V) can be applied to unselected word lines (e.g., WL0, WL2, WL3). During time period T3, the select transistor (e.g., 220A) of the selected memory cell (e.g., 125A) can be enabled because a voltage difference greater than the threshold voltage (e.g., VR2 or VR2-VR3) can be applied between the gate and source electrodes of the select transistor (e.g., 220A) of the selected memory cell (e.g., 125A) coupled to the selected word line (e.g., WL1) and the selected source line (e.g., SL2). Depending on the programmed state of the storage unit 210A, current can flow through the select transistor (e.g., 220A) of the selected memory cell (e.g., 125A) and the storage unit (e.g., 210A) by enabling the select transistor (e.g., 220A) of the selected memory cell (e.g., 125A). Meanwhile, during time period T3, because the source electrode of the selection transistor (e.g., 220B) and the storage component (e.g., 210B) of the unselected memory cell (e.g., 125B) coupled to the selected word line (e.g., WL1) and the unselected source line (e.g., SL0, SL1, SL3) have the same voltage, current does not flow through the unselected memory cell 125 coupled to the selected word line WL and the unselected source line SL. Furthermore, during time period T3, because a voltage difference (e.g., 0V or VR3-VR3) less than the threshold voltage can be applied between the gate and source electrodes of the selection transistor (e.g., 220C) of the unselected memory cell (e.g., 125C) coupled to the selected source line (e.g., SL2) and the unselected word line (e.g., WL0, WL2, WL3), the unselected memory cell 125 coupled to the selected source line (e.g., SL2) and the unselected word line (e.g., WL0, WL2, WL3) can not conduct current. Therefore, the programmed state of the selected memory cell 125A can be determined by reading the current through the selected node line (e.g., BL1) or the selected source line (e.g., SL2) coupled to the selected memory cell 125A.

[0093] In one state, the transition period (e.g., T1, T2) is shorter than the read period (e.g., T3). For example, the transition period (e.g., T1, T2) can be from 0.1 ns to 5 ns to ensure that the bit line BL, word line WL, and source line SL have sufficient time to charge or discharge to a steady-state voltage, thus avoiding unnecessary current flowing through the memory cell 125 during the transition. Meanwhile, the read period (e.g., T3) can be from 1 μs to 10 μs to allow sufficient current to flow through the memory cell 125 and ensure correct reading.

[0094] After reading data stored in a selected memory cell (e.g., 125A), the memory controller 105 may apply voltages during time periods T4, T5, and T6, respectively, as voltages applied during time periods T2, T1, and T0. For example, during time period T4, the memory controller 105 applies voltages to the source line SL, word line WL, and bit line BL, as voltages applied during time period T2. For example, during time period T5, the memory controller 105 applies voltages to the source line SL, word line WL, and bit line BL, as voltages applied during time period T1. For example, during time period T6, the memory controller 105 applies voltages to the source line SL, word line WL, and bit line BL, as voltages applied during time period T0. Therefore, for the sake of brevity, a detailed description of its repeated parts is omitted in this embodiment.

[0095] Figure 6A This describes an example voltage for reading data stored in a selected memory cell, according to some embodiments. In one example, the memory controller 105, as... Figure 6A The diagram illustrates that read voltages VR1, VR2, and VR3 are applied to the source line SL, bit line BL, and word line WL to read data stored in a selected memory cell 125A, which includes a storage component 210A and a select transistor 220A. In one example, read voltage VR1 may be a voltage (e.g., 0.3V to 0.7V) that allows current to flow through the selected memory cell (e.g., 125A). Read voltage VR3 may be ground voltage (e.g., 0V). Read voltage VR2 may be a voltage greater than the threshold voltage of select transistor 220 (e.g., 0.6V to 1.0V). Read voltage VR2 may be greater than read voltage VR1.

[0096] In a state, such as Figure 6AThe read voltages VR1, VR2, and VR3 applied to the ground as shown allow selected memory cell 125A to conduct current. For example, read voltage VR3 is applied to storage unit 210A via bit line BL1, read voltage VR1 is applied to the drain electrode of select transistor 220A via source line SL2, and read voltage VR2 is applied to the gate electrode of select transistor 220A via word line WL1. Because a voltage difference greater than the threshold voltage (e.g., VR2-VR3) can be applied between the gate and source electrodes of select transistor 220A, select transistor 220A can be enabled and conduct current according to the programmed state of storage unit 210A. For example, if storage unit 210A is burned out or programmed, no current flows through select transistor 220A. For example, if storage unit 210A is not burned out or programmed, current can flow through select transistor 220A. Bit line controller 112 can read the current via the selected bit line BL coupled to the selected memory cell 125, or source line controller 118 can read the current via the selected source line SL coupled to the selected memory cell 125, to determine the programmed state of the selected memory cell 125.

[0097] At the same time, such as Figure 6A The read voltages VR1, VR2, and VR3 applied to the ground as shown prevent current conduction in the unselected memory cell 125B coupled to the selected word line WL1 and the unselected source line SL1, while the selected memory cell 125A can conduct current according to a programmed state. For example, read voltage VR3 is applied to the storage unit 210B via bit line BL1, and simultaneously applied to the drain electrode of the select transistor 220B via source line SL1, while read voltage VR2 is applied to the gate electrode of the select transistor 220B via word line WL1. Because the drain electrode of the select transistor 220B and the storage unit 210B have the same voltage, no current flows through the select transistor 220B and the storage unit 210B regardless of whether the select transistor 220B is enabled or not.

[0098] Similarly, such as Figure 6AThe read voltages VR1, VR2, and VR3 applied to the ground as shown prevent current conduction in the unselected memory cell 125C coupled to the selected source line SL2 and the unselected word line WL0, while the selected memory cell 125A can conduct current according to a programmed state. For example, read voltage VR3 is applied to the storage unit 210C via bit line BL0, while read voltage VR1 is applied to the drain electrode of the select transistor 220C via source line SL2, and read voltage VR3 is applied to the gate electrode of the select transistor 220C via word line WL0. Because a voltage difference less than a threshold voltage (e.g., 0V) can be applied between the gate and source electrodes of the select transistor 220C, the select transistor 220C can be disabled and can not conduct current.

[0099] In a state, with Figure 5A Compared to the voltage applied to ground shown, Figure 6A The applied voltage can be simplified. For example, when read voltage VR2 is applied to the selected word line WL1 and read voltage VR1 is applied to the selected source line SL2, read voltage VR3 is applied to bit lines BL0 to BL3, unselected source lines SL0, SL1, SL3, and unselected word lines WL0, WL2, WL3. However, with Figure 5A Unlike in China, in Figure 6A In this process, current can flow in the reverse direction from the source line SL to the bit line BL.

[0100] Figure 6B A timing diagram 600 illustrates the voltage used to read data stored in a selected memory cell (e.g., 125A) according to some embodiments. In one method, the memory controller 105 applies different voltage waveforms at different stages, such as... Figure 6B As shown, data stored in a selected memory cell 125A can be read. For example, the memory controller 105 may apply a voltage waveform SL_sel to a selected source line (e.g., SL2) coupled to the selected memory cell (e.g., 125A) and apply a voltage waveform SL_unsel to unselected source lines (e.g., SL0, SL1, SL3). For example, the memory controller 105 may apply a voltage waveform WL_sel to a selected word line (e.g., WL1) coupled to the selected memory cell (e.g., 125A) and apply a voltage waveform WL_unsel to unselected word lines (e.g., WL0, WL2, WL3). For example, the memory controller 105 may apply a voltage waveform BL_sel to a selected bit line (e.g., BL1) coupled to the selected memory cell (e.g., 125A) and apply a voltage waveform BL_unsel to unselected bit lines (e.g., BL0, BL2, BL3).

[0101] In one example, during time period T0, a read voltage VR3 (e.g., ground voltage) can be applied to bit line BL, source line SL, and word line WL. By applying the read voltage VR3 (e.g., 0V) to bit line BL, source line SL, and word line WL, memory cell 125 can not conduct current.

[0102] During time period T1, a read voltage VR1 (e.g., 0.3V to 1.0V) can be applied to a selected source line (e.g., SL2) coupled to a selected memory cell (e.g., 125A), while a read voltage VR3 (e.g., 0V) can be applied to unselected source lines (e.g., SL0, SL1, SL3). Additionally, read voltage VR3 can be applied to bit lines (e.g., BL0 to BL3). During time period T1, a read voltage VR2 (e.g., 0.6V to 1.0V) can be applied to a selected word line (e.g., WL1) coupled to a selected memory cell (e.g., 125A), while read voltage VR3 (e.g., 0V) can be applied to unselected word lines (e.g., WL0, WL2, WL3). During time period T1, the select transistor (e.g., 220A) of the selected memory cell (e.g., 125A) can be enabled because a voltage difference greater than the threshold voltage (e.g., VR2 or VR2-VR3) can be applied between the gate and source electrodes of the select transistor (e.g., 220A) of the selected memory cell (e.g., 125A) coupled to the selected word line (e.g., WL1) and the selected source line (e.g., SL2). Depending on the programmed state of the storage unit 210A, current can flow through the select transistor (e.g., 220A) of the selected memory cell (e.g., 125A) and the storage unit (e.g., 210A) by enabling the select transistor (e.g., 220A) of the selected memory cell (e.g., 125A). Meanwhile, during time period T1, because the drain electrode of the selection transistor (e.g., 220B) and the storage component (e.g., 210B) of the unselected memory cell (e.g., 125B) coupled to the selected word line (e.g., WL1) and the unselected source line (e.g., SL0, SL1, SL3) have the same voltage, current does not flow through the unselected memory cell 125 coupled to the selected word line WL and the unselected source line SL. Furthermore, during time period T1, because a voltage difference (e.g., 0V or VR3-VR3) less than the threshold voltage can be applied between the gate and source electrodes of the selection transistor (e.g., 220C) of the unselected memory cell (e.g., 125C) coupled to the selected source line (e.g., SL2) and the unselected word line (e.g., WL0, WL2, WL3), the unselected memory cell 125 coupled to the selected source line (e.g., SL2) and the unselected word line (e.g., WL0, WL2, WL3) can not conduct current. Therefore, the programmed state of the selected memory cell 125A can be determined by reading the current through the selected node line (e.g., BL1) or the selected source line (e.g., SL2) coupled to the selected memory cell 125A.

[0103] After reading data stored in a selected memory cell (e.g., 125A), during time period T2, the memory controller 105 applies voltage to the source line SL, word line WL, and bit line BL as the voltage applied during time period T0. Therefore, for the sake of brevity, a detailed description of its repetitive parts is omitted in this embodiment.

[0104] Advantageously, such as Figure 6B The voltage applied to the ground shown simplifies the process of reading data stored in memory cell 125. Furthermore, by changing only the voltage applied to the selected source line SL and the selected word line WL, read operations can be performed quickly and reliably.

[0105] Figure 7 This diagram illustrates a memory array 120B according to some embodiments. The memory array 120B can be... Figure 1 This is a portion of a memory array 120. The memory array 120B may include an array of memory cells 125 (e.g., 125D, 125E, 125F). The memory array 120B may also include source lines SL0, ..., SL3 extending along a first direction (e.g., the X direction), bit lines BL0, ..., BL3 extending along a second direction (e.g., the Y direction), and word lines WL0, ..., WL3 extending along a second direction (e.g., the Y direction).

[0106] Each memory cell 125 may include a select transistor 720 and a storage component 710 connected in series between a corresponding bit line BL and a corresponding source line SL. The storage component 710 may be a fuse component, an MTJ cell, or any programmable resistor. The select transistor 720 may be a P-type transistor (e.g., a P-type MOSFET, a P-type BJT, a P-type fin field-effect transistor, etc.). In one configuration, one end of the storage component 710 is coupled to the corresponding bit line BL, and the other end is coupled to the drain electrode of the select transistor 720. In another configuration, the gate electrode of the select transistor 720 is coupled to the corresponding word line WL, and the source electrode of the select transistor 720 is coupled to the corresponding source line SL. In this configuration, the memory cell 125 may have a 1T1R structure to have a small form factor. In some embodiments, the select transistor 720 may be replaced by an element capable of performing the functionality of the select transistor 720 described herein.

[0107] Figure 8A This describes an example voltage applied to memory array 120B to write data to selected memory cells (e.g., 125D) according to some embodiments. In one example, memory controller 105... Figure 8AThe diagram illustrates that write voltages VW1, VW2, and VW3 are applied to the source line SL, bit line BL, and word line WL to write data to a selected memory cell 125D containing storage unit 710A and select transistor 720A. In one example, write voltage VW1 may be a high voltage (e.g., above 1.5V) sufficient to burn out or change the resistance of storage unit 710. Write voltage VW3 may be ground voltage (e.g., 0V). Write voltage VW2 may be the voltage between write voltages VW1 and VW3 (e.g., 0.6V to 1.0V). In one instance, the difference between write voltages VW1 and VW2 may be greater than the threshold voltage of select transistor 720 but less than the allowable stress voltage of select transistor 720. Additionally, the difference between write voltages VW2 and VW3 may be less than the allowable stress voltage of select transistor 720.

[0108] In a state, such as Figure 8A The write voltages VW1, VW2, and VW3 applied as shown allow the selected memory cell 125D to be programmed. For example, write voltage VW3 is applied to storage unit 710A via bit line BL1, write voltage VW1 is applied to the source electrode of select transistor 720A via source line SL1, and write voltage VW2 is applied to the gate electrode of select transistor 720A via word line WL1. Because a voltage difference greater than the threshold voltage (e.g., VW1-VW2) can be applied between the gate electrode and source electrode of select transistor 720A, select transistor 720A can be enabled, allowing a large voltage difference (e.g., VW1-VW3) to be applied across storage unit 710A. By applying a large voltage difference (e.g., VW1-VW3) across storage unit 710A, storage unit 710A can be burned out and programmed accordingly.

[0109] At the same time, such as Figure 8A The write voltages VW1, VW2, and VW3 applied as shown prevent unselected memory cell 125F, which is coupled to the selected word line WL1 and the unselected source line SL0, from being programmed, while programming the selected memory cell 125D. For example, write voltage VW3 is applied to storage unit 710C via bit line BL1, while write voltage VW2 is applied to the source electrode of select transistor 720C via source line SL0, and write voltage VW2 is applied to the gate electrode of select transistor 720C via word line WL1. Because a voltage difference smaller than the threshold voltage (e.g., 0V or VW2-VW2) can be applied between the gate and source electrodes of select transistor 720C, select transistor 720C can be disabled to prevent storage unit 710C from being programmed.

[0110] Similarly, such as Figure 8AThe write voltages VW1, VW2, and VW3 applied to the ground as shown prevent the unselected memory cell 125E, which is coupled to the selected source line SL1 and the unselected word line WL2, from being programmed, while simultaneously programming the selected memory cell 125D. For example, write voltage VW2 is applied to the storage unit 710B via bit line BL2, while write voltage VW1 is applied to the source electrode of the select transistor 720B via source line SL1 and to the gate electrode of the select transistor 720B via word line WL2. Because a voltage difference smaller than a threshold voltage (e.g., 0V or VW1-VW1) can be applied between the gate and source electrodes of the select transistor 720B, the select transistor 720B can be disabled to prevent the storage unit 710B from being programmed.

[0111] Figure 8B A timing diagram 800 illustrates the voltage for writing data to a selected memory cell 125D according to some embodiments. In one method, the memory controller 105 applies different voltage waveforms at different stages, such as... Figure 8B As shown, data is written to a selected memory cell 125D. For example, the memory controller 105 may apply a voltage waveform SL_sel to a selected source line (e.g., SL1) coupled to the selected memory cell (e.g., 125D) and apply a voltage waveform SL_unsel to unselected source lines (e.g., SL0, SL2, SL3). For example, the memory controller 105 may apply a voltage waveform WL_sel to a selected word line (e.g., WL1) coupled to the selected memory cell (e.g., 125D) and apply a voltage waveform WL_unsel to unselected word lines (e.g., WL0, WL2, WL3). For example, the memory controller 105 may apply a voltage waveform BL_sel to a selected bit line (e.g., BL1) coupled to the selected memory cell (e.g., 125D) and apply a voltage waveform BL_unsel to unselected bit lines (e.g., BL0, BL2, BL3).

[0112] In one example, during time period T0, a write voltage VW3 (e.g., ground voltage) can be applied to bit line BL, source line SL, and word line WL. By applying the write voltage VW3 (e.g., 0V) to bit line BL, source line SL, and word line WL, memory cell 125 can be left unprogrammed.

[0113] During time period T1, a write voltage VW3 (e.g., 0V) can be applied to the source lines (e.g., SL0 to SL3). Simultaneously, a write voltage VW3 can be applied to the bit lines (e.g., BL0 to BL3). Additionally, a write voltage VW2 (e.g., 0.6V to 1.0V) can be applied to the word lines (e.g., WL0 to WL3). Because a voltage difference smaller than the threshold voltage (e.g., -VW2 or VW3-VW2) can be applied between the gate and source electrodes of the select transistor 720 of memory cell 125, the select transistor 720 can be disabled, and memory cell 125 can be left unprogrammed.

[0114] During time period T2, a write voltage VW2 (e.g., 0.6V to 1.0V) can be applied to the source lines (e.g., SL0 to SL3). Additionally, a write voltage VW3 can be applied to the selected bit line (e.g., BL1) coupled to the selected memory cell 125D, and a write voltage VW2 can be applied to the unselected bit lines (e.g., BL0, BL2, BL3). During time period T2, a write voltage VW2 (e.g., 0.6V to 1.0V) is applied to the selected word line (e.g., WL1) coupled to the selected memory cell (e.g., 125D), while a write voltage VW1 (e.g., above 1.5V) is applied to the unselected word lines (e.g., WL0, WL2, WL3). Even if a write voltage VW2 is applied to a selected word line (e.g., WL1) coupled to a selected memory cell (e.g., 125D) during time period T2, a voltage difference (e.g., 0V or VW2-VW2) smaller than the threshold voltage can be applied between the gate and source electrodes of the select transistor (e.g., 720A, 720C) coupled to the selected word line (e.g., WL1), such that the select transistor (e.g., 720A, 720C) coupled to the selected word line (e.g., WL1) can be disabled, and the memory cell 125 coupled to the selected word line (e.g., WL1) can be unprogrammed.

[0115] During time period T3, a write voltage VW1 (e.g., higher than 1.5V) can be applied to a selected source line (e.g., SL1) coupled to a selected memory cell (e.g., 125D), while a write voltage VW2 (e.g., 0.6V to 1.0V) can be applied to unselected source lines (e.g., SL0, SL2, SL3). Additionally, a write voltage VW3 can be applied to a selected bit line (e.g., BL1) coupled to the selected memory cell 125D, and a write voltage VW2 can be applied to unselected bit lines (e.g., BL0, BL2, BL3). During time period T3, a write voltage VW2 (e.g., 0.6V to 1.0V) can be applied to a selected word line (e.g., WL1) coupled to the selected memory cell (e.g., 125D), while a write voltage VW1 (e.g., higher than 1.5V) can be applied to unselected word lines (e.g., WL0, WL2, WL3). During time period T3, the select transistor (e.g., 720A) of the selected memory cell (e.g., 125D) can be enabled because a voltage difference (e.g., VW1-VW2) greater than the threshold voltage can be applied between the gate and source electrodes of the select transistor (e.g., 720A) of the selected memory cell (e.g., 125D) coupled to the selected word line (e.g., WL1) and the selected source line (e.g., SL1). By enabling the select transistor (e.g., 720A) of the selected memory cell (e.g., 125D), a high voltage (e.g., VW1-VW3) can be applied to the storage component (e.g., 710A) of the selected memory cell (e.g., 125D) to program data. Meanwhile, during time period T3, since a voltage difference (e.g., 0V or VW2-VW2) less than the threshold voltage can be applied between the gate and source electrodes of the selection transistor (e.g., 720C) of the unselected memory cell 125 coupled to the selected word line (e.g., WL1) and the unselected source line (e.g., SL0, SL2, SL3), the selection transistor (e.g., 720C) coupled to the selected word line (e.g., WL1) and the unselected source line (e.g., SL0, SL2, SL3) can be disabled, and the unselected memory cell 125 coupled to the selected word line (e.g., WL1) and the unselected source line (e.g., SL0, SL2, SL3) can be left unprogrammed. Additionally, during time period T3, since a voltage difference (e.g., 0V or VW1-VW1) less than the threshold voltage can be applied between the gate and source electrodes of the selection transistor (e.g., 720B) of the unselected memory cell 125 coupled to the selected source line (e.g., SL1) and the unselected word line (e.g., WL0, WL2, WL3), the selection transistor (e.g., 720B) coupled to the selected source line (e.g., SL1) and the unselected word line (e.g., WL0, WL2, WL3) can be disabled, and the unselected memory cell 125 coupled to the selected source line (e.g., SL1) and the unselected word line (e.g., WL0, WL2, WL3) can be left unprogrammed.

[0116] In one state, the transition period (e.g., T1, T2) is shorter than the programming period (e.g., T3). For example, the transition period (e.g., T1, T2) can be 0.1 ns to 5 ns to ensure that the bit line BL, word line WL, and source line SL have sufficient time to charge or discharge to a steady-state voltage, thus avoiding unwanted current flowing through memory cell 125 during the transition. Meanwhile, the programming period (e.g., T3) can be 1 μs to 10 μs to allow sufficient current to flow through memory cell 125 and ensure proper programming.

[0117] After the selected memory cell (e.g., 125D) is programmed, the memory controller 105 can apply voltages during time periods T4, T5, and T6, respectively, as the voltages applied during time periods T2, T1, and T0. For example, during time period T4, the memory controller 105 applies voltages to the source line SL, word line WL, and bit line BL, as the voltages applied during time period T2. For example, during time period T5, the memory controller 105 applies voltages to the source line SL, word line WL, and bit line BL, as the voltages applied during time period T1. For example, during time period T6, the memory controller 105 applies voltages to the source line SL, word line WL, and bit line BL, as the voltages applied during time period T0. Therefore, for the sake of brevity, a detailed description of its repeated parts is omitted in this embodiment.

[0118] Advantageously, the memory array 120B can be reliably programmed and operated. In one state, the difference between the write voltage VW1 and the write voltage VW2 can be greater than the threshold voltage of the select transistor 720, but less than the allowable stress voltage of the select transistor 720. Furthermore, the difference between the write voltage VW2 and the write voltage VW3 can be less than the allowable stress voltage of the select transistor 720. Therefore, during programming, excessive voltage can be avoided by applying it to the select transistor 720, allowing the memory cell 125 to be programmed without damaging the select transistor 720.

[0119] Figure 9A This describes example voltages for writing data to selected memory cells according to some embodiments. In addition to applying a write voltage VW1 to unselected bit lines (e.g., BL0, BL2, BL3), Figure 9A The voltage applied in is similar to Figure 8A The voltage applied in the process. Therefore, for the sake of brevity, a detailed description of its repeated parts is omitted in one embodiment herein. In one state, applying a write voltage VW1 to the unselected bit lines (e.g., BL0, BL2, BL3) ensures that no voltage stress is applied to the memory cell 125 coupled to the unselected bit lines (e.g., BL0, BL2, BL3).

[0120] Figure 9B This describes a timing diagram of the voltage used to write data to selected memory cells according to some embodiments. Timing diagram 900 is similar to timing diagram 800, except that a write voltage VW1 is applied to the unselected bit lines (e.g., BL0, BL2, BL3) during time period T3. By applying the write voltage VW1 to the unselected bit lines (e.g., BL0, BL2, BL3), no voltage stress can be applied to the memory cells 125 coupled to the unselected bit lines (e.g., BL0, BL2, BL3).

[0121] Figure 10A This describes an example voltage applied to memory array 120B according to some embodiments to read data stored by selected memory cells 125D. In one example, memory controller 105, as... Figure 10A The diagram illustrates that read voltages VR1, VR2, and VR3 are applied to the source line SL, bit line BL, and word line WL to read data stored in a selected memory cell 125D, which includes a storage component 710A and a select transistor 720A. In one example, read voltage VR1 may be a voltage (e.g., 0.3V to 0.7V) that allows current to flow through the selected memory cell (e.g., 125D). Read voltage VR3 may be ground voltage (e.g., 0V). Read voltage VR2 may be a voltage greater than read voltage VR1 (e.g., 0.6V to 1.0V).

[0122] In a state, such as Figure 10A The read voltages VR1, VR2, and VR3 applied to the ground as shown allow selected memory cell 125D to conduct current according to its programmed state. For example, read voltage VR1 is applied to storage unit 710A via bit line BL1, while read voltage VR2 is applied to the source electrode of select transistor 720A via source line SL1, and read voltage VR3 is applied to the gate electrode of select transistor 720A via word line WL1. Because a voltage difference greater than the threshold voltage (e.g., VR2-VR3) can be applied between the gate and source electrodes of select transistor 720A, select transistor 720A can be enabled and conduct current according to the programmed state of storage unit 710A. For example, if storage unit 710A is burned out or programmed, no current flows through select transistor 720A. For example, if storage unit 710A is not burned out or programmed, current can flow through select transistor 720A. Bit line controller 112 can read the current via the selected bit line BL coupled to the selected memory cell 125, or source line controller 118 can read the current via the selected source line SL coupled to the selected memory cell 125, to determine the programmed state of the selected memory cell 125.

[0123] At the same time, such as Figure 10A The read voltages VR1, VR2, and VR3 applied to ground as shown prevent current conduction in the unselected memory cell 125F coupled to the selected word line WL1 and the unselected source line SL0, while the selected memory cell 125D can conduct current according to a programmed state. For example, read voltage VR1 is applied to the storage unit 710C via bit line BL1, while read voltage VR3 is applied to the source electrode of the select transistor 720C via source line SL0, and read voltage VR3 is applied to the gate electrode of the select transistor 720C via word line WL1. Because a voltage difference smaller than a threshold voltage (e.g., 0V or VR3-VR3) can be applied between the gate and source electrodes of the select transistor 720C, the select transistor 720C can be disabled, and the unselected memory cell 125F can not conduct current.

[0124] Similarly, such as Figure 10A The read voltages VR1, VR2, and VR3 applied to the ground as shown prevent current conduction in the unselected memory cell 125E coupled to the selected source line SL1 and the unselected word line WL2, while the selected memory cell 125D can conduct current according to a programmed state. For example, read voltage VR3 is applied to the storage unit 710B via bit line BL2, while read voltage VR2 is applied to the source electrode of the select transistor 720B via source line SL1 and to the gate electrode of the select transistor 720B via word line WL2. Because a voltage difference less than a threshold voltage (e.g., 0V) can be applied between the gate and source electrodes of the select transistor 720B, the select transistor 720B can be disabled, and the unselected memory cell 125E can not conduct current.

[0125] Figure 10B A timing diagram 1000 illustrates the voltage used to read data stored in a selected memory cell (e.g., 125D) according to some embodiments. In one method, the memory controller 105 applies different voltage waveforms at different stages, such as... Figure 10BAs shown, data stored in a selected memory cell 125D can be read. For example, the memory controller 105 may apply a voltage waveform SL_sel to a selected source line (e.g., SL1) coupled to the selected memory cell (e.g., 125D) and apply a voltage waveform SL_unsel to unselected source lines (e.g., SL0, SL2, SL3). For example, the memory controller 105 may apply a voltage waveform WL_sel to a selected word line (e.g., WL1) coupled to the selected memory cell (e.g., 125D) and apply a voltage waveform WL_unsel to unselected word lines (e.g., WL0, WL2, WL3). For example, the memory controller 105 may apply a voltage waveform BL_sel to a selected bit line (e.g., BL1) coupled to the selected memory cell (e.g., 125D) and apply a voltage waveform BL_unsel to unselected bit lines (e.g., BL0, BL2, BL3).

[0126] In one example, during time period T0, a read voltage VR3 (e.g., ground voltage) can be applied to bit line BL, source line SL, and word line WL. By applying the read voltage VR3 (e.g., 0V) to bit line BL, source line SL, and word line WL, memory cell 125 can not conduct current.

[0127] During time period T1, a read voltage VR3 (e.g., 0V) can be applied to the source lines (e.g., SL0 to SL3). Simultaneously, a read voltage VR3 can be applied to the bit lines (e.g., BL0 to BL3). Additionally, a read voltage VR2 (e.g., 0.6V to 1.0V) can be applied to the word lines (e.g., WL0 to WL3). Because a voltage difference smaller than the threshold voltage (e.g., -VR2 or VR3-VR2) can be applied between the gate and source electrodes of the select transistor 720, the select transistor 720 can be disabled, and the memory cell 125 can not conduct current.

[0128] During time period T2, a read voltage VR2 (e.g., 0.6V to 1.0V) can be applied to a selected source line (e.g., SL1) coupled to a selected memory cell 125D, while a read voltage VR3 can be applied to unselected source lines (e.g., SL0, SL2, SL3). Additionally, a read voltage VR1 (e.g., 0.3V to 1.0V) can be applied to a selected bit line (e.g., BL1) coupled to a selected memory cell 125D, and a read voltage VR3 can be applied to unselected bit lines (e.g., BL0, BL2, BL3). During time period T2, a read voltage VR2 (e.g., 0.6V to 1.0V) can be applied to word lines (e.g., WL0 to WL3). By applying the read voltage VR2 to the word lines (e.g., WL0 to WL3), the select transistor 720 is disabled, and no current flows through the memory cell 125D.

[0129] During time period T3, a read voltage VR2 (e.g., 0.6V to 1.0V) can be applied to a selected source line (e.g., SL1) coupled to a selected memory cell 125D, while a read voltage VR3 can be applied to unselected source lines (e.g., SL0, SL2, SL3). Alternatively, a read voltage VR1 (e.g., 0.3V to 1.0V) can be applied to a selected bit line (e.g., BL1) coupled to a selected memory cell 125D, and a read voltage VR3 can be applied to unselected bit lines (e.g., BL0, BL2, BL3). During time period T3, a read voltage VR3 (e.g., 0V) can be applied to a selected word line (e.g., WL1), while a read voltage VR2 can be applied to unselected word lines (e.g., WL0, WL2, WL3). During time period T3, the select transistor (e.g., 720A) of the selected memory cell (e.g., 125D) can be enabled because a voltage difference greater than the threshold voltage (e.g., VR2 or VR2-VR3) can be applied between the gate and source electrodes of the select transistor (e.g., 720A) of the selected memory cell (e.g., 125D) coupled to the selected word line (e.g., WL1) and the selected source line (e.g., SL1). Depending on the programmed state of the storage unit 710A, current can flow through the select transistor (e.g., 720A) of the selected memory cell (e.g., 125D) and the storage unit (e.g., 710A) by enabling the select transistor (e.g., 720A) of the selected memory cell (e.g., 125D). Meanwhile, during time period T3, since the source electrode of the selection transistor (e.g., 720C) coupled to the selected word line (e.g., WL1) and the unselected source line (e.g., SL0, SL2, SL3) of the unselected memory cell (e.g., 125F) and the storage component (e.g., 710C) have the same voltage, the selection transistor (e.g., 720C) coupled to the selected word line (e.g., WL1) and the unselected source line (e.g., SL0, SL2, SL3) of the unselected memory cell (e.g., 125F) can be disabled to prevent current from flowing through the unselected memory cell 125 coupled to the selected word line (e.g., WL1) and the unselected source line (e.g., SL0, SL2, SL3). Additionally, during time period T3, since the source electrode of the selection transistor (e.g., 720B) and the storage component (e.g., 710B) of the unselected memory cell (e.g., 125E) coupled to the selected source line (e.g., SL1) and the unselected word line (e.g., WL0, WL2, WL3) have the same voltage, the selection transistor (e.g., 720B) and the storage component (e.g., 710B) of the unselected memory cell (e.g., 125E) coupled to the selected source line (e.g., SL1) and the unselected word line (e.g., WL0, WL2, WL3) can be disabled to prevent current from flowing through the unselected memory cell (125E) coupled to the selected source line (e.g., SL1) and the unselected word line (e.g., WL0, WL2, WL3).Therefore, the programmed state of the selected memory cell 125D can be determined by reading the current via the selected source line (e.g., BL1) or the selected source line (e.g., SL1) coupled to the selected memory cell 125D.

[0130] In one state, the transition period (e.g., T1, T2) is shorter than the read period (e.g., T3). For example, the transition period (e.g., T1, T2) can be from 0.1 ns to 5 ns to ensure that the bit line BL, word line WL, and source line SL have sufficient time to charge or discharge to a steady-state voltage, thus avoiding unnecessary current flowing through the memory cell 125 during the transition. Meanwhile, the read period (e.g., T3) can be from 1 μs to 10 μs to allow sufficient current to flow through the memory cell 125 and ensure correct reading.

[0131] After reading data stored in a selected memory cell (e.g., 125D), the memory controller 105 may apply voltages during time periods T4, T5, and T6, respectively, as voltages applied during time periods T2, T1, and T0. For example, during time period T4, the memory controller 105 applies voltages to the source line SL, word line WL, and bit line BL, as voltages applied during time period T2. For example, during time period T5, the memory controller 105 applies voltages to the source line SL, word line WL, and bit line BL, as voltages applied during time period T1. For example, during time period T6, the memory controller 105 applies voltages to the source line SL, word line WL, and bit line BL, as voltages applied during time period T0. Therefore, for the sake of brevity, a detailed description of its repeated parts is omitted in this embodiment.

[0132] Figure 11A This describes an example voltage for reading data stored in a selected memory cell, according to some embodiments. In one example, the memory controller 105, as... Figure 11A The diagram illustrates that read voltages VR1, VR2, and VR3 are applied to the source line SL, bit line BL, and word line WL to read data stored in a selected memory cell 125D, which includes a storage component 710A and a select transistor 720A. In one example, read voltage VR1 may be a voltage (e.g., 0.3V to 0.7V) that allows current to flow through the selected memory cell (e.g., 125D). Read voltage VR3 may be ground voltage (e.g., 0V). Read voltage VR2 may be a voltage greater than read voltage VR1 (e.g., 0.6V to 1.0V).

[0133] In a state, such as Figure 11AThe read voltages VR1, VR2, and VR3 applied to the ground as shown allow selected memory cell 125D to conduct current according to its programmed state. For example, read voltage VR2 is applied to storage unit 710A via bit line BL1, while read voltage VR1 is applied to the source electrode of select transistor 720A via source line SL1, and read voltage VR3 is applied to the gate electrode of select transistor 720A via word line WL1. Because a voltage difference greater than the threshold voltage (e.g., VR3-VR1) can be applied between the gate and source electrodes of select transistor 720A, select transistor 720A can be enabled and conduct current according to the programmed state of storage unit 710A. For example, if storage unit 710A is burned out or programmed, no current flows through select transistor 720A. For example, if storage unit 710A is not burned out or programmed, current can flow through select transistor 720A. Bit line controller 112 can read the current via the selected bit line BL coupled to the selected memory cell 125, or source line controller 118 can read the current via the selected source line SL coupled to the selected memory cell 125, to determine the programmed state of the selected memory cell 125.

[0134] At the same time, such as Figure 11A The read voltages VR1, VR2, and VR3 applied to the ground shown prevent current conduction in the unselected memory cell 125F coupled to the selected word line WL1 and the unselected source line SL0, while the selected memory cell 125D can conduct current according to a programmed state. For example, read voltage VR2 is applied to the storage unit 710C via bit line BL1, and simultaneously applied to the source electrode of the select transistor 720C via source line SL0, and read voltage VR3 is applied to the gate electrode of the select transistor 720C via word line WL1. Because the storage unit 710C and the source electrode of transistor 720C have the same voltage, the unselected memory cell 125F may not conduct current.

[0135] Similarly, such as Figure 11AThe read voltages VR1, VR2, and VR3 applied to the ground as shown prevent current conduction in the unselected memory cell 125E coupled to the selected source line SL1 and the unselected word line WL2, while the selected memory cell 125D can conduct current according to a programmed state. For example, read voltage VR3 is applied to the storage unit 710B via bit line BL2, while read voltage VR1 is applied to the source electrode of the select transistor 720B via source line SL1, and read voltage VR2 is applied to the gate electrode of the select transistor 720B via word line WL2. Because a voltage difference smaller than a threshold voltage (e.g., VR1-VR2) can be applied between the gate and source electrodes of the select transistor 720B, the select transistor 720B can be disabled, and the unselected memory cell 125E can not conduct current.

[0136] Figure 11B A timing diagram 1100 illustrates the voltage used to read data stored in a selected memory cell (e.g., 125D) according to some embodiments. In one method, the memory controller 105 applies different voltage waveforms at different stages, such as... Figure 11B As shown, data stored in a selected memory cell 125D can be read. For example, the memory controller 105 may apply a voltage waveform SL_sel to a selected source line (e.g., SL1) coupled to the selected memory cell (e.g., 125D) and apply a voltage waveform SL_unsel to unselected source lines (e.g., SL0, SL2, SL3). For example, the memory controller 105 may apply a voltage waveform WL_sel to a selected word line (e.g., WL1) coupled to the selected memory cell (e.g., 125D) and apply a voltage waveform WL_unsel to unselected word lines (e.g., WL0, WL2, WL3). For example, the memory controller 105 may apply a voltage waveform BL_sel to a selected bit line (e.g., BL1) coupled to the selected memory cell (e.g., 125D) and apply a voltage waveform BL_unsel to unselected bit lines (e.g., BL0, BL2, BL3). In one configuration, timing diagram 1100 is similar to timing diagram 1000 except that during time periods T2 to T4, read voltage VR1, instead of read voltage VR2, is applied to the selected source line; during time periods T2 to T4, read voltage VR2, instead of read voltage VR3, is applied to the unselected source line; and during time periods T2 to T4, read voltage VR2, instead of read voltage VR1, is applied to the selected source line. Therefore, for the sake of brevity, a detailed description of its repeated portions is omitted in this embodiment.

[0137] Figure 12 This diagram illustrates a memory array 120C according to some embodiments. The memory array 120C can be... Figure 1This is part of the memory array 120. Except that each memory cell 125 in the memory array 120C contains a storage component 1210 instead of a storage component 210, the memory array 120C is similar to... Figure 2 The memory array 120A is described above. Storage component 1210 can be a MIM capacitor or any capacitor. Therefore, memory cell 125 can have a 1T1C configuration. Memory array 120C can be related to the above... Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A and Figure 6B The operation and configuration are similar to those described. In one configuration, the 1T1R cell has low impedance (short circuit) before programming and high impedance (open circuit) after programming because the resistive storage component (e.g., 210) or the metal rail breaks after programming. Similarly, the 1T1C cell has high impedance (open circuit) before programming and low impedance (short circuit) after programming because the capacitive storage component (e.g., 1210) or the insulator breaks after programming, forming a short channel.

[0138] Figure 13 This diagram illustrates a memory array 120D according to some embodiments. The memory array 120D can be... Figure 1 This is part of the memory array 120. Except that each memory cell 125 in the memory array 120D contains a storage component 1310 instead of a storage component 710, the memory array 120D is similar to... Figure 7 The memory array 120B is described above. Storage component 1310 can be a MIM capacitor or any capacitor. Memory array 120C can be related to the above... Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A and Figure 11B The operation and configuration are similar to those described.

[0139] Figure 14 A flowchart illustrating process 1400, according to some embodiments, of writing data to one or more memory cells 125 by selectively controlling or configuring source lines SL. In some embodiments, process 1400 is performed by a memory controller 105. In some embodiments, process 1400 is performed by other entities. In some embodiments, process 1400 includes... Figure 14 The diagram shows more, fewer, or different operations.

[0140] In one approach, memory controller 105 applies a first write voltage (e.g., VW1) 1410 to a selected bit line (e.g., BL1). The selected bit line may be coupled to a selected memory cell (e.g., 125A) and one or more unselected memory cells (e.g., 125B). Bit line controller 112 may apply the first write voltage to the selected bit line while simultaneously applying different write voltages (e.g., VW2 or VW3) to unselected bit lines (e.g., BL0, BL2, BL3).

[0141] In one method, memory controller 105 applies a second write voltage (e.g., VW2) 1420 to a selected word line (e.g., WL1). The selected word line may be coupled to a selected memory cell (e.g., 125A) and one or more unselected memory cells (e.g., 125B). Word line controller 114 may apply the second write voltage to the selected word line while simultaneously applying different write voltages (e.g., VW3) to the unselected word lines (e.g., WL0, WL2, WL3).

[0142] In one method, memory controller 105 applies a third write voltage (e.g., VW3) 1430 to a selected source line (e.g., SL2) coupled to a selected memory cell. The selected source line may be coupled to a selected memory cell (e.g., 125A) and one or more unselected memory cells (e.g., 125C). Source line controller 118 may apply the third write voltage to the selected source line while applying different write voltages (e.g., VW2) to unselected source lines (e.g., SL0, SL2, SL3). By applying voltages as in steps 1410, 1420, 1430, the select transistor (e.g., 220) of the selected memory cell (e.g., 125A) may be enabled, allowing high voltages (e.g., VW1-VW3) to be applied to the storage components (e.g., 210) of the selected memory cell, and the storage components of the selected memory cell may be programmed accordingly. At the same time, the selection transistors (e.g., 220) of unselected memory cells (e.g., 125B, 125C) can be disabled, so that high voltages (e.g., VW1-VW3) cannot be applied to the storage components of unselected memory cells (e.g., 210), and the storage components of unselected memory cells cannot be programmed.

[0143] Advantageously, the memory cell can be reliably programmed and operated. In one state, the difference between the write voltage VW2 and the write voltage VW3 can be greater than the threshold voltage of the select transistor 220, but less than the allowable stress voltage of the select transistor 220. Additionally, the difference between the write voltage VW1 and the write voltage VW2 can be less than the allowable stress voltage of the select transistor 220. Therefore, during programming, excessive voltage can be avoided by applying it to the select transistor 220, allowing the memory cell 125 to be programmed without damaging the select transistor 220. Furthermore, each memory cell 125 can have a simple configuration (e.g., 1T1R or 1T1C) to achieve area efficiency.

[0144] Now for reference Figure 15 This diagram illustrates an example block diagram of a computing system 1500 according to some embodiments of the present disclosure. The computing system 1500 can be used by circuit or layout designers for integrated circuit design. As used in one embodiment herein, "circuit" refers to the interconnection of electrical components such as resistors, transistors, switches, batteries, inductors, or other types of semiconductor devices used to implement desired functionality. The computing system 1500 includes a host device 1505 associated with a memory device 1510. The host device 1505 can be used to receive input from one or more input devices 1515 and provide output to one or more output devices 1520. The host device 1505 can be used to communicate with the memory device 1510, the input device 1515, and the output device 1520 via appropriate interfaces 1525A, 1525B, and 1525C, respectively. The computing system 1500 can be implemented in various computing devices, such as computers (e.g., desktop computers, laptop computers, servers, data centers, etc.), tablet computers, personal digital assistants, mobile devices, other handheld or portable devices, or any other computing unit suitable for performing schematic designs and / or layout designs using the host device 1505.

[0145] Input device 1515 may include any of a variety of input technologies, such as a keyboard, stylus, touchscreen, mouse, trackball, keypad, microphone, voice recognition, motion recognition, remote control, input port, one or more buttons, dial pad, joystick, and any other input peripheral associated with host device 1505 that allows an external source (such as a user (e.g., a circuit or layout designer)) to type information (e.g., data) into the host device and send instructions to the host device. Similarly, output device 1520 may include a variety of output technologies, such as external memory, printer, speaker, display, microphone, LED, headphones, video device, and any other output peripheral for receiving information (e.g., data) from host device 1505. "Data" input into and / or output from host device 1505 may include any of a variety of text data, circuit data, signal data, semiconductor device data, graphic data, combinations thereof, or other types of analog and / or digital data suitable for processing using computing system 1500.

[0146] Host device 1505 includes or is associated with one or more processing units / processors, such as Central Processing Unit (CPU) cores 1530A to 1530N. CPU cores 1530A to 1530N can be implemented as Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), or any other type of processing unit. Each of CPU cores 1530A to 1530N can be used to execute instructions for running one or more applications of host device 1505. In some embodiments, the instructions and data for running one or more applications can be stored in memory device 1510. Host device 1505 can also be used to store the results of running one or more applications in memory device 1510. Therefore, host device 1505 can be used to request memory device 1510 to perform various operations. For example, host device 1505 can request memory device 1510 to read data, write data, update or delete data, and / or perform management or other operations. One such application that the host device 1505 can run may be a standard cell application 1535. The standard cell application 1535 may be part of a suite of computer-aided design or electronic design automation software that can be used by a user of the host device 1505 to use, create, or modify circuits. In some embodiments, instructions for executing or running the standard cell application 1535 may be stored in memory device 1510. The standard cell application 1535 may be executed by one or more CPU cores 1530A to 1530N using instructions associated with the standard cell application 1535 from memory device 1510. In one instance, the standard cell application 1535 allows a user to assist in integrated circuit design using a pre-generated schematic and / or layout design of memory device 100 or a portion thereof. After the layout design of the integrated circuits is completed, multiple integrated circuits (e.g., containing memory device 100 or any portion thereof) may be manufactured according to the layout design using a manufacturing facility.

[0147] Still referencing Figure 15The memory device 1510 includes a memory controller 1540 for reading data from or writing data to the memory array 1545. The memory array 1545 may include various volatile and / or non-volatile memory. For example, in some embodiments, the memory array 1545 may include NAND flash memory cores. In other embodiments, the memory array 1545 may include NOR flash memory cores, SRAM cores, Static Random Access Memory (SRAM) cores, Dynamic Random Access Memory (DRAM) cores, Magnetoresistive Random Access Memory (MRAM) cores, Phase Change Memory (PCM) cores, Resistive Random Access Memory (ReRAM) cores, 3D XPoint memory cores, ferroelectric random-access memory (FeRAM) cores, and other types of memory cores suitable for use within the memory array. The memories within the memory array 1545 can be controlled individually and independently by the memory controller 1540. In other words, the memory controller 1540 can be used to communicate individually and independently with each memory within the memory array 1545. By communicating with memory array 1545, memory controller 1540 can be used to read data from or write data to memory array 1545 in response to instructions received from host device 1505. Although shown as part of memory device 1510, in some embodiments, memory controller 1540 may be part of host device 1505 or another element of computing system 1500 and associated with memory device 1510. Memory controller 1540 may be implemented as software, hardware, firmware, or a combination thereof as logic circuitry to perform the functions described in one embodiment herein. For example, in some embodiments, memory controller 1540 may be used to retrieve instructions associated with standard unit application 1535 stored in memory array 1545 of memory device 1510 upon receiving a request from host device 1505.

[0148] It should be understood that Figure 15Only some elements of the computing system 1500 are shown and described herein. However, the computing system 1500 may include other elements such as various batteries and power supplies, network interfaces, routers, switches, external memory systems, controllers, etc. Generally, the computing system 1500 may include any of the various hardware, software, and / or firmware elements required or deemed necessary for performing the functions described in one embodiment herein. Similarly, the host device 1505, input device 1515, output device 1520, and memory device 1510 including memory controller 1540 and memory array 1545 may include other hardware, software, and / or firmware elements deemed necessary or necessary for performing the functions described in one embodiment herein.

[0149] In one embodiment of this disclosure, a memory device is disclosed. In some embodiments, the memory device includes a set of memory cells, each of which includes a select transistor and a storage component connected in series between a corresponding bit line and a corresponding source line. In some embodiments, the memory device includes a memory controller coupled to the set of memory cells. In some embodiments, the memory controller is configured to apply a first write voltage to a bit line coupled to a selected memory cell in the set of memory cells during a first time period to write data to the selected memory cell. In some embodiments, the memory controller is configured to apply a second write voltage to a word line coupled to the gate electrode of the select transistor of the selected memory cell during the first time period. In some embodiments, the memory controller is configured to apply a third write voltage to a source line coupled to the selected memory cell during the first time period. The second write voltage may be between the first write voltage and the third write voltage.

[0150] In one embodiment, a first difference between a first write voltage and a second write voltage of the memory system is less than the allowable stress voltage of each select transistor, and a second difference between a second write voltage and a third write voltage is less than the allowable stress voltage of each select transistor.

[0151] In one embodiment, during a first time period, the memory controller of the memory system applies a second write voltage to another source line coupled to an unselected memory cell, which is coupled to a bit line.

[0152] In one embodiment, during a first time period, the memory controller of the memory system applies a third write voltage to another word line coupled to an unselected memory cell, which is coupled to a source line. During the same first time period, the memory controller also applies the third write voltage to another word line coupled to another gate electrode of another select transistor of the unselected memory cell.

[0153] In one embodiment, during a first time period, the memory controller of the memory system applies a second write voltage to another word line coupled to an unselected memory cell, which is coupled to a source line. During the same first time period, the memory controller also applies a third write voltage to another word line coupled to another gate electrode of another select transistor of the unselected memory cell.

[0154] In one embodiment, during a second time period, the memory controller of the memory system applies a first read voltage to another word line coupled to another selected memory cell in the group of memory cells to read data stored in the other selected memory cell. During the second time period, the memory controller of the memory system applies a second read voltage to another source line coupled to the other selected memory cell. During the second time period, the memory controller of the memory system applies a third read voltage to another word line coupled to another gate electrode of the other selected memory cell, with the first read voltage occurring between the second and third read voltages.

[0155] In one embodiment, during a second time period, the memory controller of the memory system applies a first read voltage to an additional source line coupled to an unselected memory cell, which is coupled to another source line.

[0156] In one embodiment, during a second time period, the memory controller of the memory system applies a second read voltage to an additional bit line coupled to an unselected memory cell, which is coupled to another source line. During the second time period, the memory controller of the memory system also applies a second read voltage to an additional word line coupled to an additional gate electrode of the unselected memory cell.

[0157] In one embodiment, during a second time period, the memory controller of the memory system applies a first read voltage to another word line coupled to another selected memory cell in the group of memory cells to read data stored in the other selected memory cell. During the second time period, the memory controller applies a second read voltage to another source line coupled to the other selected memory cell. During the second time period, the memory controller applies a third read voltage to another word line coupled to another gate electrode of another select transistor, the second read voltage being between the first read voltage and the third read voltage.

[0158] In one embodiment, during a second time period, the memory controller of the memory system applies a first read voltage to an additional source line coupled to an unselected memory cell, which is coupled to another source line.

[0159] In one embodiment, during a second time period, the memory controller of the memory system applies a first read voltage to an additional bit line coupled to an unselected memory cell, which is coupled to another source line. During the second time period, the memory controller also applies the first read voltage to an additional word line coupled to an additional gate electrode of the unselected memory cell.

[0160] In one embodiment, the storage component of the memory system is an electric fuse component.

[0161] In one embodiment, the storage component of the memory system is a magnetic tunneling interface unit.

[0162] In one embodiment, the storage component of the memory system is a metal-insulating-metal capacitor.

[0163] In one embodiment, the word lines of the memory system extend parallel to the bit lines along a first direction.

[0164] In another embodiment of this disclosure, a memory system is disclosed. In some embodiments, the memory system includes a memory array comprising a first memory cell, a second memory cell, a first word line coupled to the first memory cell and the second memory cell, a first source line coupled to the first memory cell, and a second source line coupled to the second memory cell. In some embodiments, the memory system includes a memory controller configured to apply a first write voltage to the first word line during a first time period to write data to the first memory cell, apply a second write voltage to the first source line during the first time period, and apply the first write voltage to the second source line during the first time period.

[0165] In one embodiment, the memory array of the memory system further includes: a third memory cell, a second word line, a first bit line, and a second bit line. The third memory cell is coupled to a first source line. The second word line is coupled to the third memory cell. The first bit line is coupled to both the first and second memory cells. The second bit line is coupled to the third memory cell. A memory controller applies a third write voltage to the first bit line during a first time period. During the first time period, the memory controller applies a second write voltage to the second bit line and the second word line.

[0166] In one embodiment, the memory array of the memory system further includes: a third memory cell, a second word line, a first word line, and a second bit line. The third memory cell is coupled to a first source line. The second word line is coupled to the third memory cell. The first word line is coupled to the first memory cell and the second memory cell. The second bit line is coupled to the third memory cell. A memory controller applies a third write voltage to the first word line during a first time period. During the first time period, the memory controller applies a first write voltage to the second bit line and the second word line.

[0167] In another embodiment of this disclosure, a method for controlling a memory system is disclosed. In some embodiments, the method includes applying a first write voltage to a bit line by a memory controller during a time period to write data to a selected memory cell, wherein the bit line is coupled to a selected memory cell and an unselected memory cell. In some embodiments, the method includes applying a second write voltage to a word line by the memory controller during a time period, the word line being coupled to the selected memory cell and the unselected memory cell. In some embodiments, the method includes applying a third write voltage to a first source line by the memory controller during a time period, wherein the first source line is coupled to the selected memory cell. In some embodiments, the method includes applying a second write voltage to a second source line by the memory controller during a time period, wherein the second source line is coupled to the unselected memory cell.

[0168] In one embodiment, a first difference between a first write voltage and a second write voltage in the method of controlling the memory system is less than the allowable stress voltage of each select transistor, and a second difference between a second write voltage and a third write voltage is less than the allowable stress voltage of each select transistor.

[0169] The term "coupling" and its variations encompass two components that are directly or indirectly connected to each other. The term "electrical coupling" and its variations encompass two components that are directly or indirectly connected to each other via a conductive material (e.g., metal or copper traces). This connection can be static (e.g., permanent or fixed) or movable (e.g., removable or detachable). This connection can be achieved by directly coupling two components or coupling them to each other, wherein the two components are coupled to each other using a separate intermediate component and any additional intermediate components are coupled to each other, or wherein the two components are coupled to each other using an intermediate component that forms a single unit with one of the two components. If "coupling" or its variations are modified by an additional term (e.g., direct coupling), the general definition of "coupling" provided above is modified by the simple linguistic meaning of the additional term (e.g., "direct coupling" means two components connected without any separate intermediate component), resulting in a narrower definition than the general definition of "coupling" provided above. This coupling can be mechanical, electrical, or fluid coupling.

[0170] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the appearance of an embodiment disclosed herein. Those skilled in the art should understand that an embodiment disclosed herein can be readily used as the basis for designing or modifying other processes and structures to achieve the same purpose and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of an embodiment disclosed herein, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of an embodiment disclosed herein.

Claims

1. A memory system, characterized in that, Include: A set of memory cells, each of which includes a select transistor and a storage component connected in series between a corresponding bit line and a corresponding source line; and A memory controller, coupled to the group of memory cells, is used for: During a first time period, a first write voltage is applied to a bit line of a selected memory cell in the group of memory cells to write data to the selected memory cell. During the first time period, a second write voltage is applied to a word line that is coupled to a gate electrode of a select transistor of the selected memory cell; and During the first time period, a third write voltage is applied to a source line coupled to the selected memory cell, and the second write voltage is between the first write voltage and the third write voltage. A first difference between the first write voltage and the second write voltage is less than a permissible stress voltage for each select transistor, and a second difference between the second write voltage and the third write voltage is less than the permissible stress voltage for each select transistor.

2. The memory system as described in claim 1, characterized in that, Each select transistor is an N-type transistor.

3. The memory system as described in claim 1, characterized in that, This memory controller is used for: During the first time period, the second write voltage is applied to another source line coupled to an unselected memory cell coupled to the bit line.

4. The memory system as described in claim 1, characterized in that, This memory controller is used for: During the first time period, the third write voltage is applied to another source line coupled to an unselected memory cell, which is coupled to the source line; and During the first time period, the third write voltage is applied to another word line of another gate electrode of another select transistor coupled to the unselected memory cell.

5. The memory system as described in claim 1, characterized in that, This memory controller is used for: During the first time period, the second write voltage is applied to another source line coupled to an unselected memory cell, which is coupled to the source line; and During the first time period, the third write voltage is applied to another word line of another gate electrode of another select transistor coupled to the unselected memory cell.

6. The memory system as claimed in claim 1, characterized in that, This memory controller is used for: During a second time period, a first read voltage is applied to a second memory line coupled to another selected memory cell in the group of memory cells to read data stored in the other selected memory cell; During the second time period, a second read voltage is applied to another source line coupled to the other selected memory cell; and During the second time period, a third read voltage is applied to another word line coupled to another gate electrode of the other selected memory cell, the first read voltage being between the second read voltage and the third read voltage.

7. The memory system as claimed in claim 6, characterized in that, This memory controller is used for: During the second time period, the first read voltage is applied to an additional source line coupled to an unselected memory cell, which is coupled to the other source line.

8. The memory system as described in claim 6, characterized in that, This memory controller is used for: During the second time period, the second read voltage is applied to an additional bit line coupled to an unselected memory cell coupled to the other source line; and During the second time period, the second read voltage is applied to an additional word line coupled to an additional gate electrode of the unselected memory cell.

9. The memory system as claimed in claim 1, characterized in that, This memory controller is used for: During a second time period, a first read voltage is applied to a second memory line coupled to another selected memory cell in the group of memory cells to read data stored in the other selected memory cell; During the second time period, a second read voltage is applied to another source line coupled to the other selected memory cell; and During the second time period, a third read voltage is applied to another word line coupled to another gate electrode of another select transistor, the second read voltage being between the first read voltage and the third read voltage.

10. The memory system as claimed in claim 9, characterized in that, This memory controller is used for: During the second time period, the first read voltage is applied to an additional source line coupled to an unselected memory cell, which is coupled to the other source line.

11. The memory system as claimed in claim 9, characterized in that, This memory controller is used for: During the second time period, the first read voltage is applied to an additional bit line coupled to an unselected memory cell coupled to the other source line; and During the second time period, the first read voltage is applied to an additional word line coupled to an additional gate electrode of the unselected memory cell.

12. The memory system as claimed in claim 9, characterized in that, The storage component is an electric fuse component.

13. The memory system as claimed in claim 9, characterized in that, The storage component is a magnetic tunneling interface unit.

14. The memory system as claimed in claim 9, characterized in that, The storage component is a metal-insulating-metal capacitor.

15. The memory system as claimed in claim 9, characterized in that, The character line extends parallel to the bit line along a first direction.

16. A memory system, characterized in that, Include: A memory array containing: First memory unit; A second memory unit; A first character line is coupled to the first memory cell and the second memory cell; A first source line is coupled to the first memory cell; and A second source line is coupled to the second memory cell; A first bit line is coupled to the first memory cell and the second memory cell. Each of the first memory cell and the second memory cell includes a select transistor and a storage component connected in series between the first source line and the first source line; and A memory controller, used for: During a first time period, a first write voltage is applied to the first word line to write data to the first memory cell; During the first time period, a second write voltage is applied to the first source line; During the first time period, the first write voltage is applied to the second source line; and During the first time period, a third write voltage is applied to the first bit line. A first difference between the third write voltage and the first write voltage is less than a permissible stress voltage for each select transistor, and a second difference between the second write voltage and the third write voltage is less than the permissible stress voltage for each select transistor.

17. The memory system as claimed in claim 16, characterized in that, The memory array further includes: A third memory cell is coupled to the first source line; A second character line is coupled to the third memory cell; and A second bit line is coupled to the third memory cell; and The memory controller is used for: During the first time period, the second write voltage is applied to the second bit line and the second word line.

18. The memory system as claimed in claim 16, characterized in that, The memory array further includes: A third memory cell is coupled to the first source line; A second character line is coupled to the third memory cell; A first bit line is coupled to the first memory cell and the second memory cell; and A second bit line is coupled to the third memory cell, and The memory controller is used for: A third write voltage is applied to the first bit line during the first time period; and During the first time period, the first write voltage is applied to the second bit line and the second word line.

19. A method for controlling a memory system, characterized in that, include: A memory controller applies a first write voltage to a bit line during a time period to write data to a selected memory cell, the bit line being coupled to the selected memory cell and an unselected memory cell; During the time period, the memory controller applies a second write voltage to a word line, which is coupled to the selected memory cell and the unselected memory cell. During the time period, the memory controller applies a third write voltage to a first source line, which is coupled to the selected memory cell. and The memory controller applies the second write voltage to a second source line coupled to the unselected memory cell during the time period. A first difference between the first write voltage and the second write voltage is less than a permissible stress voltage for each select transistor, and a second difference between the second write voltage and the third write voltage is less than the permissible stress voltage for each select transistor.

20. The control method as described in claim 19, characterized in that, Each select transistor is an N-type transistor.

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