Semiconductor device, memory device, and operating method thereof

Abstract

The present application relates to semiconductor devices, memory devices, and methods of operating the same. A memory device includes a memory structure and a control circuit. The memory structure includes a plurality of page buffers coupled to nonvolatile memory cells. Each nonvolatile memory cell is capable of storing data. The plurality of page buffers is disposed in a predetermined direction. The control circuit is configured to separate reset sections of two page buffers from each other by a time corresponding to at least one of the reset sections. The two page buffers are disposed adjacent to each other among the plurality of page buffers.

Description

Technical Field

[0001] The embodiments of this disclosure described herein relate to semiconductor devices, and more specifically, to an apparatus and method for reducing signal interference in a semiconductor device. Background Technology

[0002] Recently, the paradigm of computing environments has shifted to ubiquitous computing, enabling computer systems to be accessed virtually anytime, anywhere. As a result, the use of portable electronic devices (e.g., mobile phones, digital cameras, laptops, etc.) is rapidly increasing. These portable electronic devices each may use or include a memory system with at least one memory device. The memory system can be a data storage device. The data storage device can serve as the primary or secondary storage device for the portable electronic device.

[0003] Unlike hard drives, this data storage device uses non-volatile semiconductor memory, exhibiting improved stability and durability. It lacks mechanical drive components (e.g., robotic arms), thus providing high data access speeds and relatively low power consumption. Examples of data storage devices with these advantages include, but are not limited to, Universal Serial Bus (USB) memory devices, memory cards with various interfaces, solid-state drives (SSDs), and the like. Summary of the Invention

[0004] Embodiments of this disclosure provide an apparatus and method for reducing signal interference in semiconductor devices. Furthermore, embodiments of this disclosure provide an apparatus and method capable of improving the integration density of memory devices.

[0005] In one embodiment, a memory device may include: a memory structure including a plurality of page buffers coupled to non-volatile memory cells, each non-volatile memory cell capable of storing data, wherein the plurality of page buffers are arranged in a predetermined direction; and control circuitry configured to separate reset segments of two page buffers from each other at a time corresponding to at least one of the reset segments. The two page buffers may be arranged adjacent to each other among the plurality of page buffers.

[0006] The memory structure may include: a bit line that connects at least one non-volatile memory cell to at least one page buffer among a plurality of page buffers; and a switching circuit configured to control the connection between the bit line and at least one non-volatile memory cell.

[0007] The page buffer may include: a sensing node connected to a switching circuit; and two latches connected to the sensing node.

[0008] The control circuitry can be configured to transmit a control signal for resetting one of the two latches included in the page buffer.

[0009] The control circuit can separate the reset segment by outputting a first control signal and a second control signal to be applied to the two page buffers. The first enable segment of the first control signal and the second enable segment of the second control signal can be separated from each other at a time corresponding to at least one of the first enable segment or the second enable segment.

[0010] The first and second enabled segments are identical to each other.

[0011] Two page buffers can be positioned between adjacent isolation pads formed in a semiconductor substrate.

[0012] At least one of the two page buffers located between adjacent isolation pads may have partially overlapping enabled sections with at least one of the page buffers located outside the adjacent isolation pads.

[0013] In a planar view, the page buffer may have a width corresponding to 3.5 or 5 lines formed in the semiconductor substrate.

[0014] In another embodiment, a semiconductor device may include: a structure comprising a plurality of buffers disposed in a predetermined direction, each buffer including a latch for storing data; and control circuitry configured to separate corresponding enable segments of two buffers from each other at a time corresponding to at least one of the enable segments. The two buffers may be disposed adjacent to each other among the plurality of buffers.

[0015] The buffer may include: a sensing node for receiving or outputting data; and two latches connected to the sensing node.

[0016] The control circuitry can be configured to transmit a control signal for resetting one of the two latches included in the buffer.

[0017] The control circuit can separate the activation segment by outputting a first control signal and a second control signal to be applied to two buffers. The first activation segment of the first control signal and the second activation segment of the second control signal can be separated from each other at a time corresponding to at least one of the first activation segment or the second activation segment.

[0018] The first and second enabled segments can be the same.

[0019] Two buffers can be positioned between adjacent isolation pads formed in a semiconductor substrate.

[0020] At least one of two buffers positioned between adjacent isolation pads and at least one of two buffers positioned outside adjacent isolation pads may have partially overlapping enabled sections.

[0021] In a planar view, the buffer may have a width corresponding to 3.5 or 5 lines formed in the semiconductor substrate.

[0022] In another embodiment, a method for operating a memory device may include the steps of: applying a first control signal having a first enable segment to a first page buffer of two page buffers arranged adjacent to each other among a plurality of page buffers; and applying a second control signal having a second enable segment to a second page buffer of the two page buffers. The first enable segment and the second enable segment may be separated from each other at a time corresponding to at least one of the first enable segment or the second enable segment.

[0023] The first page buffer and the second page buffer can be disposed between adjacent isolation pads formed in the semiconductor substrate.

[0024] The first and second enabled segments can be the same.

[0025] In another embodiment, a memory device may include: an array of memory cells arranged in columns; a first page buffer and a second page buffer, which are physically adjacent to each other and each include a first latch and a second latch connected to a corresponding column, the second latch of the first page buffer being physically adjacent to the first latch of the second page buffer; and control circuitry configured to apply a first signal and a second signal to a corresponding first latch to reset the first latch. The first signal and the second signal may remain enabled during a corresponding amount of time that is separated according to any one of the time amounts. Attached Figure Description

[0026] The description in this article refers to the accompanying drawings, in which the same reference numerals are used throughout the drawings to denote the same parts.

[0027] Figure 1 A data processing system according to an embodiment of the present disclosure is shown.

[0028] Figure 2 A memory device according to an embodiment of the present disclosure is shown.

[0029] Figure 3 A first example of control signals and page buffers in a memory device according to an embodiment of the present disclosure is shown.

[0030] Figure 4 A first structure of a page buffer circuit in a memory device according to an embodiment of the present disclosure is shown.

[0031] Figure 5 A second structure of a page buffer circuit in a memory device according to an embodiment of the present disclosure is shown.

[0032] Figure 6A second example of control signals and page buffers in a memory device according to an embodiment of the present disclosure is shown.

[0033] Figure 7 A third example of control signals and page buffers in a memory device according to an embodiment of the present disclosure is shown.

[0034] Figure 8 A page buffer included in a memory device according to an embodiment of the present disclosure is shown.

[0035] Figure 9 A first method of operation for controlling the page buffer included in a memory device is shown.

[0036] Figure 10 This illustrates the interference that occurs when the memory device is operated via the first operating method.

[0037] Figure 11 Showing due to Figure 10 The data distortion caused by the interference shown.

[0038] Figure 12 A second method of operation for controlling a page buffer included in a memory device according to an embodiment of the present disclosure is shown.

[0039] Figure 13 This illustrates how, according to embodiments of the present disclosure, interference that occurs when the memory device is operated via a second operating method is avoided.

[0040] Figure 14 This illustrates how to avoid data distortion according to the second operating method, based on embodiments of the present disclosure. Detailed Implementation

[0041] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0042] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “implementation,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc., are intended to indicate that any of these features are included in one or more embodiments of this disclosure, but may not necessarily be combined in the same embodiment.

[0043] In this disclosure, the terms “comprising” and “including” are open-ended. As used in the appended claims, these terms specify the presence of the said element but do not exclude the presence or addition of one or more other elements. Terms in the claims do not exclude the inclusion of additional components (e.g., interface units, circuitry, etc.).

[0044] In this disclosure, various units, circuits, or other components may be described or declared as "configured to" perform a task. In such a context, "configured to" is used to imply a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, a block / unit / circuit / component may be said to be configured to perform a task even when the specified block / unit / circuit / component is currently inoperable (e.g., not turned on or not enabled). Blocks / units / circuits / components used with the language "configured to" include hardware (e.g., circuits), memory storing program instructions executable to perform operations, etc. Additionally, "configured to" may include general structures (e.g., general-purpose circuits) manipulated by software and / or firmware (e.g., FPGAs or general-purpose processors executing software) to operate in a manner capable of performing the relevant tasks. "Configured to" may also include adjusting manufacturing processes (e.g., semiconductor manufacturing facilities) to manufacture means (e.g., integrated circuits) suitable for implementing or performing one or more tasks.

[0045] As used in this disclosure, the terms “circuit” or “logic” refer to all of the following: (a) a hardware circuit implementation only (e.g., an implementation in analog and / or digital circuits only); and (b) a combination of circuitry and software (and / or firmware), such as (applicable to): (i) a combination of processors or (ii) a portion of processor / software (including digital signal processors), memory, and software working together to enable a device such as a mobile phone or server to perform various functions; and (c) a circuit such as a microprocessor or a portion of a microprocessor that requires software or firmware to operate, even if the software or firmware does not actually exist. This definition of “circuit” or “logic” applies to all uses of the term in this application (including in any claim). As a further example, as used in this application, the terms “circuit” or “logic” also cover implementations of processors (or processors) or portions of processors and their accompanying software and / or firmware only. The terms “circuit” or “logic” also cover (e.g., and if applicable to elements of a particular claim) integrated circuits for storage devices.

[0046] As used herein, the terms “first,” “second,” “third,” etc., serve as labels for the nouns preceding them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily imply that the first value must precede the second value. Furthermore, while these terms may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another that would otherwise have the same or similar names. For example, a first circuit can be distinguished from a second circuit.

[0047] Furthermore, the term "based on" is used to describe factors influencing a determination. This term does not exclude additional factors that may influence the determination. That is, the determination may be based solely on those factors or at least partially on those factors. Consider the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, this phrase does not exclude the possibility that the determination of A is also based on C. In other cases, A may be determined solely based on B.

[0048] In this document, a data item or data entry can be a sequence of bits. For example, a data item may include the contents of a file, a portion of a file, a page in memory, an object in an object-oriented program, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a sequence of bits. According to one embodiment, a data item may include discrete objects. According to another embodiment, a data item may include information units within a transmission packet between two different components.

[0049] Embodiments of this disclosure will now be described with reference to the accompanying drawings, wherein the same reference numerals refer to the same elements.

[0050] Embodiments of this disclosure may provide a memory system, a data processing system, and a method for operating the memory system and the data processing system. The data processing system includes components and resources such as a memory system and a host, and is capable of dynamically allocating multiple data paths for data communication between components based on the use of the components and resources.

[0051] Figure 1 A data processing system 100 according to an embodiment of the present disclosure is shown.

[0052] Reference Figure 1 The data processing system 100 may include a host 102 that is coupled to or connected to a memory system (e.g., memory system 110). For example, the host 102 and the memory system 110 may be connected to each other via a data bus, host cable, etc. to perform data communication.

[0053] The memory system 110 may include a memory device 150 and a controller 130. The memory device 150 and the controller 130 in the memory system 110 may be considered as physically separate components or elements. The memory device 150 and the controller 130 may be connected via at least one data path. For example, the data path may include a channel and / or a path.

[0054] According to embodiments, the memory device 150 and the controller 130 may be functionally separated components or elements. Furthermore, according to embodiments, the memory device 150 and the controller 130 may be implemented using a single chip or multiple chips. The controller 130 may perform data input / output operations in response to a request input from an external device. For example, when the controller 130 performs a read operation in response to a read request input from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the controller 130.

[0055] like Figure 1 As shown, memory device 150 may include multiple memory blocks 152, 154, and 156. Memory blocks 152, 154, and 156 can be understood as a group of non-volatile memory cells in which data is erased together by a single erase operation. Although not shown, memory blocks 152, 154, and 156 may include pages, which are groups of non-volatile memory cells that store data together during a single programming operation or output data together during a single read operation. For example, a memory block may include multiple pages.

[0056] For example, memory device 150 may include multiple memory planes or multiple memory dies. According to an embodiment, a memory plane may be considered as a logical or physical partition including at least one memory block, drive circuitry capable of controlling an array including multiple non-volatile memory cells, and a buffer capable of temporarily storing data input to or output from the non-volatile memory cells.

[0057] Additionally, according to an embodiment, a memory die may include at least one memory plane. A memory die can be understood as a collection of components implemented on a physically distinguishable substrate. Each memory die may be connected to the controller 130 via a data path. Each memory die may include an interface for exchanging data items and signals with the controller 130.

[0058] According to an embodiment, the memory device 150 may include at least one memory block 152, 154, 156, at least one memory plane, or at least one memory die. Figure 1 The internal configuration of the illustrated memory device 150 may vary depending on the performance of the memory system 110. Embodiments of this disclosure are not limited to... Figure 2 The internal configuration shown.

[0059] Reference Figure 1 The memory device 150 may include a voltage supply circuit 170 capable of supplying at least some voltages to the memory blocks 152, 154, and 156. (See reference...) Figures 4 to 8 The voltage supply circuit 170 may include a voltage generation circuit for generating target voltages used in memory blocks 152, 154, and 156. The voltage supply circuit 170 may supply a read voltage Vrd, a programming voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the non-volatile memory cells included in the memory blocks. For example, during a read operation for reading data stored in the non-volatile memory cells included in memory blocks 152, 154, and 156, the voltage supply circuit 170 may supply a read voltage Vrd to the selected non-volatile memory cell. During a programming operation for storing data in the non-volatile memory cells included in memory blocks 152, 154, and 156, the voltage supply circuit 170 may supply a programming voltage Vprog to the selected non-volatile memory cell. Additionally, during a read or programming operation performed on a selected non-volatile memory cell, the voltage supply circuit 170 may supply a pass voltage Vpass to a non-selected non-volatile memory cell. During an erase operation to erase data stored in the non-volatile memory cells included in memory blocks 152, 154, and 156, voltage supply circuit 170 may supply an erase voltage Vers to the memory blocks.

[0060] Memory device 150 may store information about various voltages supplied to memory blocks 152, 154, and 156 based on its operation. For example, when the non-volatile memory cells in memory blocks 152, 154, and 156 can store multi-bit data, multiple levels of read voltage Vrd may be needed to identify or read multi-bit data items. Memory device 150 may include a table corresponding to multi-bit data items, which includes information corresponding to multiple levels of read voltage Vrd. For example, the table may include bias values ​​stored in registers, each bias value corresponding to a specific level of read voltage Vrd. The number of bias values ​​of read voltage Vrd used for read operations may be limited to a preset range. In addition, the bias values ​​may be quantized.

[0061] The host device 102 may include portable electronic devices (e.g., mobile phones, MP3 players, laptops, etc.) or non-portable electronic devices (e.g., desktop computers, game consoles, televisions, projectors, etc.). According to an embodiment, the host device 102 may include the central processing unit (CPU) included in both portable and non-portable electronic devices.

[0062] Host 102 may also include at least one operating system (OS) that controls the functions and operations performed within host 102. The OS provides interoperability between host 102, which is operatively coupled to memory system 110, and users who intend to store data in memory system 110. The OS can support functions and operations corresponding to user requests. By way of example and not limitation, OS can be classified as a general operating system and a mobile operating system based on the mobility of host 102. General operating systems can be further divided into personal operating systems and enterprise operating systems based on system requirements or user environment. Compared to personal operating systems, enterprise operating systems are designed specifically to ensure and support high-performance computing.

[0063] The mobile operating system may allow support for services or functions for mobility (e.g., power-saving features). Host 102 may include multiple operating systems. In response to a user's request, host 102 may execute multiple operating systems linked to memory system 110. Host 102 may send multiple commands corresponding to the user's request to memory system 110, thereby executing operations corresponding to the multiple commands within memory system 110.

[0064] The controller 130 in the memory system 110 can control the memory device 150 in response to a request or command input from the host 102. For example, the controller 130 can perform a read operation to provide data read from the memory device 150 to the host 102 and can perform a write operation (or programming operation) to store data input from the host 102 in the memory device 150. In order to perform data input / output (I / O) operations, the controller 130 can control and manage internal operations such as reading data, programming data, erasing data, etc.

[0065] According to an embodiment, the controller 130 may include a host interface 132, a processor 134, an error correction circuit (ECC) 138, a power management unit (PMU) 140, a memory interface 142, and a memory 144. (Included in...) Figure 2 The components in the controller 130 shown may vary depending on the structure, function, and operational performance of the memory system 110.

[0066] For example, memory system 110 may be implemented using any of a variety of storage devices (which can be electrically connected to host 102) according to the host interface protocol. Non-limiting examples of suitable storage devices include solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), reduced-size MMCs (RS-MMCs), micro MMCs, secure digital cards (SDs), mini SDs, micro SDs, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, etc. Components may be added to or omitted from controller 130 depending on the implementation of memory system 110.

[0067] Both host 102 and memory system 110 may include interfaces or controllers for sending and receiving signals, data, etc., according to one or more predetermined protocols. For example, host interface 132 in memory system 110 may include devices capable of sending signals, data, etc. to host 102 or receiving signals, data, etc. from host 102.

[0068] The host interface 132 included in the controller 130 can receive signals, commands (or requests), and / or data input from the host 102. For example, the host 102 and the memory system 110 can use predetermined protocols to send and receive data between them. Examples of communication standards, protocols, or interfaces supported by the host 102 and the memory system 110 for sending and receiving data include Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), High-Speed ​​Peripheral Component Interconnect (PCIe or PCI-e), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industry Processor Interface (MIPI), etc. According to embodiments, the host interface 132 is a layer for exchanging data with the host 102 and is implemented or driven by firmware called the Host Interface Layer (HIL).

[0069] Integrated Drive Electronics (IDE) or Advanced Technology Accessory (ATA) can be used as one of the interfaces for sending and receiving data, and a cable, for example, comprising 40 leads connected in parallel, can be used to support data transmission and reception between host 102 and memory system 110. When multiple memory systems 110 are connected to a single host 102, the multiple memory systems 110 can be divided into master and slave devices using the positions or DIP switches to which the multiple memory systems 110 are connected. The memory system 110 set as the master device can be used as the master memory device. IDE (ATA) may include, for example, Fast-ATA, ATAPI, or Enhanced IDE (EIDE).

[0070] The Serial Advanced Technology Attachment (SATA) interface is a serial data communication interface compatible with various ATA standards for parallel data communication interfaces used by Integrated Drive Electronic Devices (IDE) devices. The 40 pins in an IDE interface can be reduced to 6 pins in a SATA interface. For example, the 40 parallel signals of IDE can be converted to the 6 serial signals of a SATA interface. The SATA interface is widely used in host 102 for data transmission and reception due to its faster data transmission and reception rates and lower resource consumption. The SATA interface can connect up to 30 external devices to a single transceiver included in host 102. Furthermore, the SATA interface supports hot-plugging, allowing external devices to be attached to or detached from host 102 even while data communication between host 102 and another device is in progress. Therefore, even when host 102 is powered on, memory system 110 can be connected or disconnected as an attachment device, similar to devices supported by Universal Serial Bus (USB). For example, in a host 102 with an eSATA port, the storage system 110 can be freely attached to or detached from the host 102, similar to an external hard drive.

[0071] Small Computer System Interface (SCSI) is a serial data communication interface used to connect a computer or server to other peripheral devices. Compared to other interfaces such as IDE and SATA, SCSI offers high transfer speeds. In SCSI, the host 102 and at least one peripheral device (e.g., memory system 110) are connected in series, but data transmission and reception between the host 102 and the various peripheral devices can be performed through parallel data communication. In SCSI, devices such as memory system 110 can be easily connected to or disconnected from the host 102. SCSI can support up to 15 other devices connected to a single transceiver included in the host 102.

[0072] Serial Attached SCSI (SAS) can be understood as a serial data communication version of SCSI. In SAS, the host 102 and multiple peripheral devices are connected in series, and data transmission and reception between the host 102 and each peripheral device can be performed according to a serial data communication scheme. SAS supports connections between the host 102 and peripheral devices via serial cables instead of parallel cables, making it easier to use SAS to manage devices and enhance or improve operational reliability and communication performance. SAS can support up to eight external devices connected to a single transceiver included in the host 102.

[0073] High-speed non-volatile memory (NVMe) is an interface based at least on high-speed peripheral component interconnect (PCIe) designed to increase the performance and design flexibility of a host 102, server, computing device, etc., equipped with a non-volatile memory system 110. PCIe uses slots or specific cables to connect computing devices (e.g., host 102) and peripheral devices (e.g., memory system 110). For example, PCIe can use multiple pins (e.g., 18-pin, 32-pin, 49-pin, or 82-pin) and at least one lead (e.g., x1, x4, x8, or x16) to achieve high-speed data communication exceeding several hundred MB / s (e.g., 250 MB / s, 500 MB / s, 984.6250 MB / s, or 1969 MB / s). Depending on the implementation, PCIe schemes can achieve bandwidths from tens to hundreds of gigabits per second. NVMe can support operating speeds of non-volatile memory systems 110 such as SSDs, which are faster than hard drives.

[0074] According to one implementation, host 102 and memory system 110 can be connected via Universal Serial Bus (USB). Universal Serial Bus (USB) is a scalable, hot-pluggable, plug-and-play serial interface that provides cost-effective standard connectivity between host 102 and peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, video cameras, etc. Multiple peripheral devices, such as memory system 110, can be connected to a single transceiver included in host 102.

[0075] Reference Figure 2 Error correction circuit 138 can correct erroneous bits in data read from memory device 150 and may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder performs error correction coding on data to be programmed into memory device 150 to generate encoded data with added parity bits, and stores the encoded data in memory device 150. When controller 130 reads data stored in memory device 150, ECC decoder can detect and correct erroneous bits contained in the data read from memory device 150. For example, after performing error correction decoding on data read from memory device 150, error correction circuit 138 determines whether the error correction decoding was successful and outputs a command signal (e.g., a correction success signal or a correction failure signal) based on the result of the error correction decoding. Error correction circuit 138 may use parity bits generated during ECC encoding processing of data stored in memory device 150 to correct erroneous bits in the read data. When the number of erroneous bits is greater than or equal to the number of correctable erroneous bits, error correction circuit 138 may not correct the erroneous bits, but instead may output a correction failure signal indicating that the correction of erroneous bits failed.

[0076] According to an embodiment, the error correction circuit 138 may perform error correction operations based on coding modulation such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc. The error correction circuit 138 may include all circuits, modules, systems, and / or devices for performing error correction operations based on at least one of the aforementioned codes. Figure 2 The error correction circuit 138 shown may include at least some of the components included in the controller 130.

[0077] For example, the ECC decoder can perform hard decision decoding or soft decision decoding on data sent from memory device 150. Hard decision decoding can be understood as one of two broadly classified methods for error correction. Hard decision decoding may include the operation of correcting erroneous bits by reading digital data "0" or "1" from non-volatile memory cells in memory device 150. Because hard decision decoding processes binary logic signals, the circuit / algorithm design or configuration can be simpler and the processing speed can be faster than soft decision decoding.

[0078] Soft-decision decoding can quantize the threshold voltage of a non-volatile memory cell in memory device 150 using two or more quantization values ​​(e.g., multi-bit data, approximations, analog values, etc.) to correct erroneous bits based on the two or more quantization values. Controller 130 can receive two or more letters or quantization values ​​from a plurality of non-volatile memory cells in memory device 150 and then perform decoding based on information generated by characterizing the quantization values ​​as a combination of information such as conditional probabilities or likelihoods.

[0079] According to the implementation, the ECC decoder can use Low-Density Parity-Generator Matrix (LDPC-GM) codes designed for soft-decision decoding. LDPC codes use an algorithm that reads several bits of data value from memory device 150 based on reliability, rather than simply data 1 or 0 as in hard-decision decoding, and iteratively repeats this through message exchange to improve the reliability of the values. These values ​​are then ultimately determined to be data 1 or 0. For example, the decoding algorithm using LDPC codes can be understood as probabilistic decoding. In hard-decision decoding, the value output from the non-volatile memory cell is decoded as 0 or 1. Compared to hard-decision decoding, soft-decision decoding can determine the value stored in the non-volatile memory cell based on random information. Regarding bit flips that can be considered errors that may occur in memory device 150, soft-decision decoding can improve the probability of correcting errors and recovering data, and provide the reliability and stability of the corrected data. LDPC-GM codes may have a scheme where internal LDGM codes can be cascaded with high-speed LDPC codes.

[0080] According to the implementation, the ECC decoder can use, for example, low-density parity-check convolutional codes (LDPC-CC) for soft-decision decoding. LDPC-CC can have a scheme that uses linear-time encoding and pipelined decoding based on variable block length and shift registers.

[0081] According to implementation methods, the ECC decoder may use, for example, a log-likelihood ratio Turbo code (LLR-TC) for soft decision decoding. The log-likelihood ratio (LLR) can be calculated as a nonlinear function of the distance between a sampled value and an ideal value. Alternatively, the Turbo code (TC) may include a simple two-dimensional or three-dimensional code (e.g., Hamming code) and be repeatedly decoded in both row and column directions to improve the reliability of the values.

[0082] The power management unit (PMU) 140 controls the power supplied to the controller 130. The PMU 140 monitors the power supplied to the memory system 110 (e.g., the voltage supplied to the controller 130) and supplies power to components included in the controller 130. The PMU 140 not only detects power on or off, but also generates a trigger signal when the power supply to the memory system 110 is unstable, enabling the memory system 110 to perform an emergency backup of its current state. According to embodiments, the PMU 140 may include means or components capable of accumulating power available for use in emergency situations.

[0083] The memory interface 142 can be used as an interface for processing commands and data transferred between the controller 130 and the memory device 150, so that the controller 130 can control the memory device 150 in response to commands or requests input from the host 102. When the memory device 150 is flash memory, the memory interface 142 can generate control signals for the memory device 150 and can process data input to or output from the memory device 150 under the control of the processor 134.

[0084] For example, when the memory device 150 includes NAND flash memory, the memory interface 142 includes a NAND flash memory controller (NFC). The memory interface 142 provides an interface for processing commands and data between the controller 130 and the memory device 150. According to an embodiment, the memory interface 142 may be implemented or driven by firmware called a flash interface layer (FIL) for exchanging data with the memory device 150.

[0085] According to the implementation, the memory interface 142 may support an Open NAND Flash Interface (ONFi), switching modes, etc., for data input / output with the memory device 150. For example, ONFi may use a data path (e.g., channel, path, etc.) including at least one signal line capable of bidirectional transmission and reception in units of 8 bits or 16 bits of data. Data communication between the controller 130 and the memory device 150 may be implemented through at least one interface relating to Asynchronous Single Data Rate (SDR), Synchronous Double Data Rate (DDR), Switched Double Data Rate (DDR), etc.

[0086] Memory 144 can be used as working memory for memory system 110 or controller 130, while temporarily storing transaction data for operations performed in memory system 110 and controller 130. For example, memory 144 can temporarily store read data output from memory device 150 in response to a read request from host 102 before the read data is output to host 102. Additionally, controller 130 can temporarily store write data input from host 102 in memory 144 before programming write data into memory device 150. When controller 130 controls the operation of memory device 150 (e.g., data read operation, data write or programming operation, data erase operation, etc.), data transmitted between controller 130 of memory system 110 and memory device 150 can be temporarily stored in memory 144.

[0087] In addition to reading or writing data, memory 144 may store information (e.g., mapped data, read requests, programming requests, etc.) for inputting or outputting data between host 102 and memory device 150. According to embodiments, memory 144 may include one or more of a command queue, program memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, mapping buffer / cache, etc. Controller 130 may allocate some storage space in memory 144 for components established to perform data input / output operations. For example, a write buffer established in memory 144 may be used to temporarily store target data undergoing programming operations.

[0088] In implementations, memory 144 may be implemented using volatile memory. For example, memory 144 may be implemented using static random access memory (SRAM), dynamic random access memory (DRAM), or both. Although Figure 2 A memory 144 is shown, for example, located within the controller 130, but the implementation is not limited thereto. The memory 144 may be located inside or outside the controller 130. For example, the memory 144 may be implemented as an external volatile memory having a memory interface for transferring data and / or signals between the memory 144 and the controller 130.

[0089] Processor 134 can control the overall operation of memory system 110. For example, processor 134 can control programming or reading operations of memory device 150 in response to write or read requests input from host 102. According to embodiments, processor 134 can execute firmware to control programming or reading operations in memory system 110. Herein, firmware may be referred to as flash translation layer (FTL). According to embodiments, processor 134 may be implemented using a microprocessor, central processing unit (CPU), etc.

[0090] According to one implementation, the memory system 110 may be implemented using at least one multi-core processor. A multi-core processor is a circuit or chip that integrates two or more cores (considered as different processing regions). For example, the data input / output speed (or performance) of the memory system 110 can be improved when multiple cores in the multi-core processor independently drive or execute multiple flash translation layers (FTLs). According to another implementation, data input / output (I / O) operations in the memory system 110 can be performed independently by different cores in the multi-core processor.

[0091] The processor 134 in the controller 130 can perform operations corresponding to requests or commands input from the host 102. Furthermore, the memory system 110 can perform operations independently of commands or requests input from the host 102. In one case, operations performed by the controller 130 in response to requests or commands input from the host 102 can be considered foreground operations, while operations performed by the controller 130 independently of requests or commands input from the host 102 can be considered background operations. The controller 130 can perform foreground or background operations for reading, writing, or erasing data in the memory device 150. Additionally, parameter setting operations corresponding to setting parameter commands or setting feature commands sent from the host 102 can be considered foreground operations. Background operations can be performed without commands sent from the host 102. For example, the controller 130 can perform garbage collection (GC), wear leveling (WL), bad block management (identifying and handling bad blocks), etc.

[0092] According to the implementation, substantially similar operations can be performed as both foreground and background operations. For example, garbage collection can be considered a foreground operation when the memory system 110 performs garbage collection (e.g., manual GC) in response to a request or command input from the host 102. Garbage collection can be considered a background operation when the memory system 110 performs garbage collection independently of the host 102 (e.g., automatic GC).

[0093] When the memory device 150 includes multiple dies (or chips), each comprising a plurality of non-volatile memory cells, the controller 130 can perform parallel processing on multiple requests or commands input from the host 102 to improve the performance of the memory system 110. For example, the sent requests or commands may be divided into multiple groups, including at least some of the multiple planes, dies, or chips included in the memory device 150, and the multiple groups of requests or commands may be processed individually or in parallel in each plane, die, or chip.

[0094] The memory interface 142 in controller 130 can be connected to multiple dies or chips in memory device 150 via at least one channel and at least one path. When controller 130 distributes and stores data across multiple dies via the respective channels or paths in response to a request or command associated with multiple pages including non-volatile memory cells, multiple operations corresponding to the request or command can be executed simultaneously or in parallel across multiple dies or planes. This processing method or scheme can be considered an interleaving method. Since the data input / output speed of memory system 110 is increased by operating in an interleaving manner, the data I / O performance of memory system 110 can be improved.

[0095] As an example and not a limitation, controller 130 may identify the status of multiple channels (or pathways) associated with multiple dies included in memory device 150. Controller 130 may determine the status of each channel or pathway as one of a busy state, a ready state, an active state, an idle state, a normal state, and an abnormal state. The determination of which channel (and / or data) the controller transmits may be associated with a physical block address. Controller 130 may reference descriptors transmitted from memory device 150. Descriptors may include blocks or pages describing parameters about certain contents of memory device 150. Descriptors may have a predetermined format or structure. For example, descriptors may include device descriptors, configuration descriptors, cell descriptors, etc. Controller 130 may refer to or use descriptors to determine which channel(s) ...

[0096] Reference Figure 1 The memory device 150 in the memory system 110 may include a plurality of memory blocks 152, 154, and 156. Each of the plurality of memory blocks 152, 154, and 156 includes a plurality of non-volatile memory cells. According to an embodiment, memory blocks 152, 154, and 156 may be a group of non-volatile memory cells that are erased together. Memory blocks 152, 154, and 156 may include a plurality of pages as a group of non-volatile memory cells that are read or programmed together.

[0097] In this implementation, for high integration, each memory block 152, 154, or 156 may have a three-dimensional stacked structure. Furthermore, the memory device 150 may include multiple dies, each die including multiple planes, and each plane including multiple memory blocks 152, 154, and 156. The configuration of the memory device 150 may be varied depending on the performance of the memory system 110.

[0098] Figure 1 A memory device 150 is shown comprising multiple memory blocks 152, 154, and 156. Depending on the number of bits that can be stored in a single memory cell, the multiple memory blocks 152, 154, and 156 can be any of a single-level cell (SLC) memory block, a multi-level cell (MLC) memory block, etc. An SLC memory block comprises multiple pages implemented from memory cells, each memory cell storing one bit of data. SLC memory blocks can have higher data I / O performance and greater endurance than MLC memory blocks. An MLC memory block comprises multiple pages implemented from memory cells, each memory cell storing multiple bits of data (e.g., two or more bits of data). Compared to SLC memory blocks, MLC memory blocks can have a larger storage capacity for the same space. Considering storage capacity, MLC memory blocks can be highly integrated.

[0099] In one embodiment, the memory device 150 may be implemented using MLC memory blocks such as two-level cell (DLC) memory blocks, three-level cell (TLC) memory blocks, four-level cell (QLC) memory blocks, and combinations thereof. A DLC memory block may include multiple pages implemented from memory cells, each memory cell capable of storing 2 bits of data. A TLC memory block may include multiple pages implemented from memory cells, each memory cell capable of storing 3 bits of data. A QLC memory block may include multiple pages implemented from memory cells, each memory cell capable of storing 4 bits of data. In another embodiment, the memory device 150 may be implemented using blocks comprising multiple pages implemented from memory cells, each memory cell capable of storing 5 bits or more of data.

[0100] According to one implementation, the controller 130 may use an MLC (Multi-Level Cell) memory block included in the memory device 150 as an SLC (Simplified Level Cell) memory block that stores one bit of data in a memory cell. The data input / output speed of a Multi-Level Cell (MLC) memory block may be slower than that of an SLC memory block. That is, when an MLC memory block is used as an SLC memory block, the margin for read or programmable operations may be reduced. For example, when an MLC memory block is used as an SLC memory block, the controller 130 can perform data input / output operations at a higher speed. Therefore, the controller 130 may use the MLC memory block as an SLC buffer to temporarily store data, since a buffer may require a high data input / output speed to improve the performance of the memory system 110.

[0101] Furthermore, according to an embodiment, the controller 130 can program data into the MLC multiple times without performing an erase operation on a specific MLC memory block included in the memory device 150. Typically, non-volatile memory cells do not support data overwriting. However, the controller 130 can use the feature of the MLC capable of storing multi-bit data to program 1-bit data into the MLC multiple times. For an MLC overwrite operation, when 1-bit data is programmed into the MLC, the controller 130 can store the number of programming times as separate operation information. According to an embodiment, an operation to evenly level the threshold voltage of the MLC can be performed before another 1-bit data is programmed into the same MLC where each 1-bit data is stored.

[0102] In one embodiment, the memory device 150 is specifically implemented as a non-volatile memory such as flash memory, e.g., NAND flash memory, NOR flash memory, etc. In another embodiment, the memory device 150 may be implemented by at least one of phase-change random access memory (PCRAM), ferroelectric random access memory (FRAM), spin-torque random access memory (STT-RAM), and spin-torque magnetic random access memory (STT-MRAM).

[0103] Figure 2 A memory system according to an embodiment of the present disclosure is shown. Specifically, Figure 2 The memory cell array circuit of the memory die included in the memory device according to an embodiment of the present disclosure is schematically shown.

[0104] Reference Figure 2 The memory die may include a memory bank 330, which includes a plurality of non-volatile memory cells. The memory bank 330 may include a plurality of cell strings 340. Each cell string 340 includes a plurality of non-volatile memory cells connected to each of a plurality of bit lines BL0 to BLm-1. Each cell string 340 disposed in a column of the memory bank 330 may include at least one drain select transistor (DST) and at least one string select transistor (or source select transistor) (SST). A plurality of non-volatile memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the drain select transistor DST and the string select transistor SST. For example, each of the non-volatile memory cells MC0 to MCn-1 may be configured as a multi-level cell (MLC), each cell storing a data item with multiple bits. Each cell string 340 may be individually electrically connected to a corresponding bit line BL0 to BLm-1.

[0105] Figure 2 A memory bank 330 including NAND flash memory cells is shown as an example. However, the memory bank 330 included in the memory device 150 according to embodiments of the present disclosure is not limited to NAND flash memory. In another embodiment, the memory bank 330 may also be implemented as NOR flash memory, hybrid flash memory that mixes or combines at least two different types of memory cells, or monolithic NAND flash memory in which the controller is embedded in a single memory chip. Additionally, the memory bank 330 according to embodiments of the present disclosure may include flash memory cells including a charge-trapped flash (CTF) layer (including a conductive floating gate or insulating layer).

[0106] According to embodiments of this disclosure, Figure 2 The memory group 330 shown may include Figure 2 The illustrated memory device 150 includes at least one memory block 152, 154, 156. According to embodiments, the memory device 150 may have a two-dimensional (2D) or three-dimensional (3D) structure. For example, each of the memory blocks 152, 154, 156 in the memory device 150 may be implemented as a 3D structure (or a vertical structure). Each of the memory blocks 152, 154, 156 may have a three-dimensional structure extending along a first to a third direction (e.g., the x-axis, y-axis, and z-axis directions).

[0107] Memory group 330, comprising multiple memory blocks 152, 154, and 156 constituting memory device 150, can be connected to multiple bit lines BL, multiple string select lines SSL, multiple drain select lines DSL, multiple word lines WL, multiple dummy word lines DWL (not shown), and multiple common source lines CSL. Memory group 300 may include multiple NAND strings NS, each NAND string NS including multiple memory cells MC. In memory group 330, each NAND string NS can be connected to each bit line BL. In addition, the string select transistor SST of each NAND string NS can be connected to the common source line CSL, and the drain select transistor DST of each NAND string NS can be connected to the corresponding bit line BL. Here, the memory cells MC can be arranged between the string select transistor SST and the drain select transistor DST of each NAND string NS.

[0108] Reference Figure 2 The voltage supply circuit 170 in the memory device 150 can supply word line voltages (e.g., target voltages such as programming voltage, read voltage, and pass voltage) via each word line according to the operating mode, or supply voltage to a block body (e.g., a well region) forming individual memory blocks including memory cells MC. In this case, the voltage generation operation of the voltage supply circuit 170 can be performed under the control of a control circuit (not shown). Additionally, the voltage supply circuit 170 can generate multiple variable read voltages to distinguish multiple data items from each other. In response to the control of the control circuit, one of the memory blocks (or sectors) of the memory cell array can be selected, and one of the word lines of the selected memory block can be selected. Word line voltages can be supplied individually to the selected word line and the unselected word line. The voltage supply circuit 170 may include a voltage generation circuit for generating target voltages with various levels. The voltage supply circuit 170 may be coupled to a first pin or pad that receives a first power supply voltage VCC applied from an external source (e.g., an external device) and a second pin or pad that receives a second power supply voltage VPP applied from an external device. Here, the second power supply voltage VPP may have a voltage level that is two or more times higher than the voltage level of the first power supply voltage VCC. For example, the first power supply voltage VCC may have a voltage level of 2.0V to 5.5V, while the second power supply voltage may have a voltage level of 9V to 13V. The voltage supply circuit 170 according to embodiments of this disclosure may include a voltage generation circuit for more quickly generating target voltages of various levels used in the memory group 330. The voltage generation circuit may use the second power supply voltage VPP to generate target voltages with voltage levels higher than the second power supply voltage VPP.

[0109] The read / write circuit 320, controlled by the control circuitry of the memory device 150, can operate as a sense amplifier or a write driver depending on the operating mode. For example, in verification and read operations, the read / write circuit 320 can operate as a sense amplifier for reading data items from the memory cell array. Additionally, in programming operations, the read / write circuit 320 can operate as a write driver for controlling the potential of bit lines based on the data items to be stored in the memory cell array. During programming operations, the read / write circuit 320 can receive data items to be programmed into the cell array from page buffers (not shown). The read / write circuit 320 can drive bit lines based on the input data items. For this purpose, the read / write circuit 320 includes a plurality of page buffers (PB) 322, 324, 326, each page buffer corresponding to a column (or bit line) or a column pair (or bit line pair). According to an embodiment, a plurality of latches (not shown) may be included in each of the page buffers 322, 324, 326.

[0110] Although not shown, page buffers 322, 324, and 326 can be connected to data input / output devices (e.g., serial circuits or serializers) via multiple buses. When each of page buffers 322, 324, and 326 is connected to a data input / output device via a different bus, the latency that may occur in data transmission from page buffers 322, 324, and 326 can be reduced. For example, each page buffer 322, 324, and 326 can perform data transmission without any waiting time.

[0111] According to an embodiment, the memory device 150 may receive a write command, write data, and information about the location where the write data is to be stored (e.g., a physical address). The control circuit 180 causes the voltage supply circuit 170 to generate programming pulses, pass voltages, etc., for programming operations performed in response to the write command, and to generate various voltages for verification operations performed after the programming operation.

[0112] Figure 3 A first example of control signals and page buffers in a memory device according to an embodiment of the present disclosure is shown. Specifically, Figure 3 Show Figure 2 Examples of page buffers (PB) 322, 324, 326 included in the read / write circuitry 320 of the memory device 150 shown.

[0113] Reference Figure 3 Multiple page buffers PB in the read / write circuit 320 can be arranged adjacent to each other in both the row and column directions. According to an embodiment, the multiple page buffers PB can be arranged in a three-dimensional structure. Here, the page buffers PB can correspond to a reference... Figure 2 Page buffers 322, 324, and 326 are described.

[0114] Reference Figure 2 and Figure 3 A page buffer (PB) can receive and temporarily store data stored in non-volatile memory cells via bit lines. The page buffer (PB) includes at least one latch. After data is transferred to the component, the latch temporarily storing data may be reset to store new data. Figure 2 The control circuit 180 shown can send a control signal XRST for resetting the page buffer PB. <0> XRST <1> In response to the control signal XRST <0> XRST <1> The latches included in the page buffer PB can be initialized. Figure 3 The control signal XRST described in [the document] <0> XRST <1> Can correspond to being applied to Figure 8 The latches shown are reset signals MRST, DRST, and SRST.

[0115] Figure 3 The two sequence control signals XRST described in the document <0> XRST <1> No adjacent page buffers PB are applied to adjacent page buffers. Two sequential control signals XRST are enabled sequentially in control circuit 180. <0> XRST <1> Or two sequential control signals XRST <0> XRST <1> When the enabled sections at least partially overlap, interference can occur between adjacent page buffers (PB). Therefore, the two sequence control signals XRST... <0> XRST <1> It can be applied to page buffers PB that are spaced apart by a preset distance. When two sequence control signals XRST... <0> XRST <1> When applied to page buffers PB arranged at a preset distance from each other, even if two sequential control signals XRST are applied... <0> XRST <1> The enabled segments overlap at least partially with each other, and data distortion caused by interference can be avoided because the page buffers (PB) are spaced apart by a preset distance.

[0116] The following is for reference Figures 4 to 5 This describes an example of a memory device 150 having a masked bit line structure (masked BL architecture). The page buffer PB can be understood as sensing and latching circuitry. (See reference...) Figure 2 The memory device 150 may have a structure where a page buffer 322 can be connected to a bit line BL (full BL architecture). See reference. Figures 4 to 5 This describes a masked bitline architecture where a page buffer PB is connected to two or more bit lines BL.

[0117] For example, the non-volatile memory cells included in the memory bank 330 of the memory device 150 can read or store 16 kilobytes of data at a time. The read / write circuitry 320 may include a number of sensing and latching devices corresponding to 16 kilobytes of data. For example, multiple sensing and latching devices included in the read / write circuitry 320 may be arranged adjacent to each other in rows (horizontal level) and columns (vertical level). Similarly, multiple sensing and latching devices included in the read / write circuitry 320 may be arranged adjacent to each other in rows (horizontal level) and columns (vertical level). However, the number of levels of the page buffer PB included in the read / write circuitry 320 of the memory device 150 may be designed differently to improve or enhance the integration of the memory device 150 (e.g., to reduce the size of the memory device 150 even with the same storage capacity).

[0118] For example, as the number of stages of sensing and latching devices increases in the longitudinal direction parallel to the bit lines, the integration density of the memory device 150 can be reduced. (Refer to...) Figure 2 As the number of sensing and latching stages decreases in the longitudinal direction parallel to the bit lines, a larger number of page buffers 322, 324, 326 in the read / write circuit 320 can be arranged in the horizontal direction intersecting the bit lines BL0, BL1, ..., BLm-1. As the number of sensing and latching stages in the longitudinal direction parallel to the bit lines BL0, BL1, ..., BLm-1 increases, a smaller number of page buffers 322, 324, 326 in the read / write circuit 320 can be arranged in the longitudinal direction parallel to the bit lines BL0, BL1, ..., BLm-1.

[0119] Figure 4 A first structure of a page buffer circuit in a memory device according to an embodiment of the present disclosure is shown. (Refer to...) Figure 4 Multiple page buffers PB in the read / write circuitry 320 can be arranged for a non-volatile memory cell that stores 16KB of data in 12 levels within a 13mm width. Each page buffer PB can have five lines. That is, each page buffer PB can be designed and formed to have a size corresponding to at least five lines.

[0120] Figure 5 This illustrates a second structure of a page buffer circuit in a memory device. (Refer to...) Figure 5 Multiple page buffers PB in the read / write circuit 320 can be arranged for a non-volatile memory cell that stores 16k bytes of data in 8 levels within a width of 13mm. Each page buffer PB can have 3.5 lines.

[0121] Reference Figure 4 and Figure 5 The same number of sensing and latching devices can be set in different levels within the same area (e.g., a width of 13 mm). (Refer to...) Figure 4 The page buffer PB in the first described structure can be configured with five lines, while in the reference... Figure 5 The page buffer PB in the described second structure can have 3.5 lines. Since each line can be implemented in a semiconductor substrate with minimal width using semiconductor device manufacturing processes, the integration density of the read / write circuit 320 with the second structure can be higher than that of the first structure.

[0122] Figure 6 A second example of control signals and page buffers in a memory device according to an embodiment of the present disclosure is shown.

[0123] Reference Figure 6 Leads or wires for applying control signals XRST<0:7> to the multiple page buffers PB included in the read / write circuit 320 can be arranged in a horizontal direction. Control signals XRST<0:7> associated with the multiple page buffers PB are applied individually to each stage of the page buffer PB. Each stage of the page buffer PB can be controlled by a separate control signal. Eight control signals XRST<0:7> can be applied separately to a reference... Figure 5 The page buffer PB is described as having eight levels.

[0124] Figure 7 A third example of control signals and page buffers in a memory device according to an embodiment of the present disclosure is shown.

[0125] Reference Figure 7 The leads for applying control signals XRST<0:7> to multiple page buffers PB in the read / write circuit 320 can be arranged in the vertical direction. The control signals XRST<0:7> to the multiple page buffers PB have a structure that applies them individually to each region of the page buffer PB. Each region of the page buffer PB can be controlled by a separate control signal. Eight control signals XRST<0:7> can be applied to the reference... Figure 5 The page buffers PB in the eight zones described.

[0126] Reference Figure 6 and Figure 7 Multiple control signals XRST<0:7> applied to multiple page buffers PB can be applied along wiring that is set or arranged in a horizontal (row) direction (e.g., the direction intersecting the bit lines) or a vertical (column) direction (e.g., the direction parallel to the bit lines).

[0127] Figure 8 A page buffer included in a memory device according to an embodiment of the present disclosure is shown. Figure 8 This illustrates the internal configuration of a page buffer (PB) with either a full bitline structure (full BL architecture) or a masked bitline structure (masked BL architecture).

[0128] Reference Figure 2 and Figure 8 Page buffer 322 can be connected to bit line (BL) BLCM via a switching element. The switching element can be controlled by the page buffer control signal PB_SENSE. When the switching element is turned on via the page buffer control signal PB_SENSE, bit line (BL) BLCM can be connected to page buffer 322. When the switching element is turned off via the page buffer control signal PB_SENSE, bit line (BL) BLCM and page buffer 322 can be electrically disconnected.

[0129] According to an embodiment, page buffer 322 may include a main register 430, a first sub-register 410, and a second sub-register 420. Each of the main register 430, the first sub-register 410, and the second sub-register 420 may include an inverter latch. Each of the main register 430, the first sub-register 410, and the second sub-register 420 may be connected to a sensing node SO via control signals TRANM, TRAND, and TRANS. The inverter latch included in the main register 430 may include two nodes QS and QS_N that maintain a potential corresponding to the opposite value. The inverter latch included in the first sub-register 410 may include two nodes QM and QM_N that maintain a potential corresponding to the opposite value. The inverter latch included in the second sub-register 420 may include two nodes QD and QD_N that maintain a potential corresponding to the opposite value. In addition, the inverter latch included in each of the main register 430, the first sub-register 410, and the second sub-register 420 may store a value initialized by reset signals MRST, DRST, and SRST.

[0130] Page buffer 322, connected to the bit line BLCM, can be controlled for programming, verification, or read operations. For example, when a verification operation performed based on a sub-verification voltage identifies a threshold voltage of a non-volatile memory cell as greater than the sub-verification voltage, a first positive voltage with a voltage level lower than the programming prohibition voltage can be applied to the bit line BLCM during a first programming operation following the verification operation, based on data stored in the first sub-register 410. The second sub-register 420 can be configured to apply a second positive voltage with a voltage level higher than the first positive voltage to the bit line BLCM during a second programming operation following the first programming operation, based on data transmitted through the first sub-register 410.

[0131] When the threshold voltage of the memory cell is less than the target verification voltage, the main register 430 can be configured to discharge the bit line BLCM according to the stored data before the first positive voltage or the second positive voltage is applied to the bit line BLCM. When the threshold voltage of the memory cell is equal to or greater than the target verification voltage, the main register 430 can be configured to disable the voltage applied to the bit line BLCM according to the stored data before the first positive voltage or the second positive voltage is applied to the bit line BLCM.

[0132] In this implementation, although the second sub-register 420 is used to apply a second positive voltage to the bit line BLCM, the first sub-register 410 can also be used to apply a first positive voltage to the bit line BLCM. This method increases driveability, thereby reducing the time spent pre-charging the bit line BLCM for programming operations.

[0133] Figure 8 The document describes a page buffer (PB) 322 comprising two sub-registers 410 and 420. When the page buffer 322 includes two sub-resistors 410 and 420, two positive voltages with different voltage levels (e.g., a first positive voltage and a second positive voltage) can be applied to the bit line BLCM. This operation method can have the same effect as the level of programming with a step pulse of voltage reduction during programming operations. According to an embodiment, when the page buffer (PB) 322 includes three sub-registers, three different positive voltages can be applied to the bit line BLCM to allow for more precise control over the degree of programming in the non-volatile memory cells.

[0134] Figure 9 A first method of operation for controlling the page buffer included in a memory device is shown.

[0135] Reference Figure 2 and Figure 9 The control circuit 180 can output a page buffer reset signal PB_xRST to the read / write circuit 320. The read / write circuit 320 can divide the page buffer reset signal PB_xRST into multiple control signals xRST_E<0:7>. The read / write circuit 320 may also include a splitter capable of dividing the page buffer reset signal PB_xRST into multiple control signals xRST_E<0:7>.

[0136] According to the implementation method, the control circuit 180 can output multiple control signals xRST_E<0:7> to the read / write circuit 320.

[0137] Reference Figure 9 Multiple control signals xRST_E<0:7> applied to multiple page buffers PB can be enabled sequentially. (See reference...) Figure 6 and Figure 7Multiple control signals xRST_E<0:7> can be applied to individual levels or regions of multiple page buffers PB. Adjacent control signals (e.g., xRST_E) are applied to adjacent levels or regions of multiple page buffers PB. <0> xRST_E <1> The enabled sections can partially overlap with each other.

[0138] Figure 10 This illustrates the interference that occurs when the memory device is operated via the first operating method. (Refer to...) Figure 5 Similar to the multiple page buffers PB in the read / write circuit 320, 3.5 lines can be arranged in each of the first page buffer PB_i and the second page buffer PB_i+1.

[0139] Reference Figure 10 When the first control signal XRST <0> Second control signal XRST <1> When applied to the first page buffer PB_i and the second page buffer PB_i+1, the values ​​stored in nodes QM2 and QM3 of the latches included in the first page buffer PB_i and the second page buffer PB_i+1 can be individually reset or initialized. This is due to the first control signal XRST. <0> The other node QM_N3 is not electrically connected to the latch in the second page buffer PB_i+1, which is adjacent to the first page buffer PB_i, so the first control signal XRST is preferred. <0> This does not affect the latch corresponding to node QM_N3 in the second page buffer PB_i+1. However, the memory device 150 has a very high degree of integration. Adjacent latches (i.e., adjacent latches) included in the two adjacent page buffers PB_i, PB_i+1, or nodes QM2, QM_N3 included in adjacent latches, can affect each other. This is due to the first control signal XRST. <0> Interference can occur between two adjacent page buffers PB_i and PB_i+1.

[0140] Node QM3, included in the latch in the second page buffer PB_i+1, can be controlled by the second control signal XRST. <1> Initialization. However, the potential of the sensing node SO3 in the second page buffer PB_i+1 can be affected by the first control signal XRST. <0> Impact. Additionally, the first control signal XRST <0> Second control signal XRST <1> The enabled sections partially overlap. This is due to the first control signal XRST applied to the first page buffer PB_i. <0> Interference occurs in the second page buffer PB_i+1. This is due to the second control signal XRST applied to the second page buffer PB_i+1. <1> Interference can occur in the first page buffer PB_i.

[0141] Figure 11 Showing due to Figure 10 The data distortion caused by the interference shown.

[0142] Reference Figure 10 and Figure 11 When the first control signal XRST has at least partially overlapping activation periods <0> Second control signal XRST <1> Interference occurs when applied to adjacent page buffers PB_i and PB_i+1.

[0143] When the first control signal XRST <0> When enabled, the potential of node QM2, which includes latches in the first page buffer PB_i, can be reduced to a logic low level (e.g., ground voltage). As the potential of node QM2, which includes latches in the first page buffer PB_i, decreases, the potential of node QM3_N, which includes latches in the second page buffer PB_i+1, fluctuates towards a logic low level (e.g., ground voltage). As the potential of node QM3_N, which includes latches in the second page buffer PB_i+1, decreases, the potential of sensing node SO3, which includes sensing node SO3 in the second page buffer PB_i+1, fluctuates towards a logic low level (e.g., ground voltage).

[0144] Reference Figure 11 When the second control signal XRST <1> When enabled, the potential of node QM3_N, which includes the latch in the second page buffer PB_i+1, becomes logic high (e.g., the supply voltage indicated by the dashed line). However, as described above, as the potential of sensing node SO3 decreases to logic low (e.g., ground voltage), the potential of node QM3_N, which includes the latch in the second page buffer PB_i+1, can rise due to interference. Therefore, the latch included in the second page buffer PB_i+1 will not respond to the second control signal XRST. <1> Initialization. That is, the potential of node QM3_N of the latch included in the second page buffer PB_i+1 will not rise to a logic high level (e.g., the supply voltage indicated by the dashed line). See reference. Figure 8 The potential of another node QM3 of the latch included in the second page buffer PB_i+1 can also fluctuate so that the latch included in the second page buffer PB_i+1 will not be initialized or reset.

[0145] Figure 12 A second method of operation for controlling a page buffer included in a memory device, according to an embodiment of the present disclosure, is shown.

[0146] Reference Figure 12 The enable segments of adjacent control signals among multiple control signals xRST<0:7> and xSET_E<0:7> applied to multiple page buffers PB can be separated from each other by a preset time. For example, when adjacent control signals xRST <0> xRST <1> Apply to pads or pads located on adjacent insulating structures (see...) Figure 10 and Figure 13When two adjacent page buffers PB_i and PB_i+1 are between, the first control signal xRST is activated. <0> Second control signal xRST <1> The enabled sections can be separated from each other and controlled by the first control signal XRST. <0> Second control signal XRST <1> At least one corresponding time within the enabled segment. Two other adjacent control signals (e.g., a third control signal xRST). <2> and the fourth control signal xRST <3> The enabled sections can also be spaced apart from each other and the third control signal xRST. <2> and the fourth control signal xRST <3> At least one corresponding time within the enabled segment. Additionally, two other adjacent control signals (e.g., the fifth control signal xRST). <4> and the sixth control signal xRST <5> The enabled sections can also be separated from each other and controlled by the fifth control signal xRST. <4> and the sixth control signal xRST <5> At least one corresponding time within the enabled segment. Similarly, two other adjacent control signals (e.g., the seventh control signal xRST) <6> and the eighth control signal xRST <7> It can have a seventh control signal xRST that is spaced apart from each other. <6> and the eighth control signal xRST <7> At least one corresponding time-based activation segment in the activation segment.

[0147] Reference Figure 9 and Figure 12 The enabled sections of the eight control signals xRST<0:7> are substantially the same. Therefore, the operating margins of the multiple page buffers based on the eight control signals xRST<0:7> can be substantially the same. The data input / output speed of the memory device 150 will not be reduced. However, the first control signal XRST among the eight control signals xRST<0:7>... <0> Second control signal XRST <1> The first page buffer PB_i and the second page buffer PB_i+1, which are located between adjacent insulating pads, are applied. In this document, the first control signal XRST... <0> Second control signal XRST <1> The enabled sections will not overlap. First control signal XRST <0> Second control signal XRST <1> The enabled sections can be spaced apart from each other.

[0148] Figure 13 This illustrates how, according to embodiments of the present disclosure, interference that occurs when the memory device is operated via a second operating method is avoided. (See also...) Figure 5 and Figure 10 Similar to the multiple page buffers PB in the read / write circuit 320, 3.5 lines can be arranged in each of the first page buffer PB_i and the second page buffer PB_i+1.

[0149] Reference Figure 13When the first control signal XRST <0> Second control signal XRST <1> When applied to the first page buffer PB_i and the second page buffer PB_i+1, the values ​​stored in nodes QM2 and QM3 of the latches included in the first page buffer PB_i and the second page buffer PB_i+1 can be individually reset or initialized. This is due to the first control signal XRST. <0> Since there is no other node QM_N3 electrically connected to the latch in the second page buffer PB_i+1 adjacent to the first page buffer PB_i, the first control signal XRST is preferred. <0> This will not affect the latch corresponding to node QM_N3 in the second page buffer PB_i+1. However, the memory device 150 has a very high degree of integration. Adjacent latches (i.e., latches arranged adjacently) included in the two adjacent page buffers PB_i, PB_i+1, or nodes QM2, QM_N3 included in adjacent latches, can affect each other. This is due to the first control signal XRST. <0> Interference can occur between two adjacent page buffers PB_i and PB_i+1.

[0150] In reference Figure 13 In the described implementation method, compared with the reference Figure 10 The described implementation methods differ, with the second control signal XRST. <1> Not enabled, and the first control signal XRST <0> Enabled. Even if the latches included in the second page buffer PB_i+1 are affected by the first control signal XRST. <0> The resulting interference affects the second control signal XRST. <1> It can be applied to the second page buffer PB_i+1 after a preset time has elapsed. The node QM3 included in the latch in the other page buffer PB_i+1 can be controlled via the second control signal XRST. <1> Initialization. Even if the potential of the sensing node SO3 in the second page buffer PB_i+1 is affected by the first control signal XRST. <0> The resulting interference affects the second control signal XRST. <1> This can be enabled later so that the second page buffer PB_i+1 can be accessed via the second control signal XRST. <1> Normal reset or initialization.

[0151] Despite Figure 13 The enable segments of the eight control signals XRST<0:7> are described as substantially the same as each other, but the enable segments of the eight control signals XRST<0:7> may differ depending on the implementation. In an implementation, some enable segments may be the same, but others may be different to avoid overlap.

[0152] Figure 14 This illustrates how data distortion can be avoided according to a second operating method based on an embodiment of the present disclosure. (Refer to...) Figure 13 and Figure 14When the first control signal XRST of the time period TG_C is activated at intervals, <0> Second control signal XRST <1> When applied individually to the first page buffer PB_i and the second page buffer PB_i+1 of adjacent settings, it describes how to properly initialize or reset the latches to avoid data distortion even in the event of interference.

[0153] When the first control signal XRST <0> When enabled, the potential of node QM2, which includes latches in the first page buffer PB_i, can drop to a logic low level (e.g., ground voltage). As the potential of node QM2, which includes latches in the first page buffer PB_i, decreases, the potential of node QM3_N, which includes latches in the second page buffer PB_i+1, fluctuates towards a logic low level (e.g., ground voltage). As the potential of node QM3_N, which includes latches in the second page buffer PB_i+1, decreases, the potential of sensing node SO3, which includes sensing node SO3 in the second page buffer PB_i+1, fluctuates towards a logic low level (e.g., ground voltage). Due to the high integration density, it may be difficult to suppress interference caused by latches in adjacent configurations.

[0154] However, despite the first control signal XRST <0> Enabled, but the second control signal XRST <1> Not enabled. See reference. Figure 13 First control signal XRST <0> Enabled section and second control signal XRST <1> The enabled sections can be spaced apart from each other and the first control signal XRST <0> Second control signal XRST <1> At least one corresponding time in the enabled segment.

[0155] Reference Figure 14 Because when the first control signal XRST <0> The disturbances generated when the first page buffer PB_i is enabled and applied include potential fluctuations in the latch node QM3_N in the second page buffer PB_i+1. After the preset time TG_C has elapsed, the second control signal XRST... <1> Enabled. When the second control signal XRST... <1> When enabled, the potential of node QM3_N, which includes the latch in the second page buffer PB_i+1, can rise to a logic high level (e.g., the supply voltage). Even if the potential fluctuates due to interference, the potential of the latch node QM3_N, which includes the latch in the second page buffer PB_i+1, can be controlled by the second control signal XRST. <1> And thus, the latch included in the second page buffer PB_i+1 can respond to the second control signal XRST. <1> And initialize normally.

[0156] The semiconductor device according to embodiments of the present disclosure can separate signals to avoid overlap between the operating times, margins, or time periods of adjacent circuits with high integration, and to avoid signal or data distortion caused by interference from adjacent circuits.

[0157] Furthermore, in a memory device with highly integrated page buffers connected to multiple non-volatile memory cells for temporary data storage for input / output, the control circuitry can avoid overlap between enable segments of control signals used to enable adjacent page buffers, thereby reducing or avoiding interference.

[0158] Although this teaching has been shown and described with reference to specific embodiments, it will be apparent to those skilled in the art from this disclosure that various changes and modifications may be made without departing from the spirit and scope of this disclosure as defined in the following claims. Furthermore, these embodiments may be combined to form additional embodiments.

[0159] Cross-references to related applications

[0160] This patent application claims the benefit of Korean Patent Application No. 10-2021-0162035, filed on November 23, 2021, the full disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: A memory structure including multiple page buffers coupled to non-volatile memory cells, each non-volatile memory cell capable of storing data, wherein the multiple page buffers are arranged in a predetermined direction; and A control circuit that separates the reset segments of the two page buffers from each other by a time length corresponding to at least one of the reset segments. The two page buffers are arranged directly adjacent to each other among the plurality of page buffers.

2. The memory device according to claim 1, wherein, The memory structure includes: Bit lines that connect at least one of the non-volatile memory cells to at least one of the plurality of page buffers; and A switching circuit that controls the connection between the bit line and the at least one non-volatile memory cell.

3. The memory device according to claim 2, wherein, The page buffer includes: A sensing node, which is connected to the switching circuit; and Two latches are connected to the sensing node.

4. The memory device according to claim 3, wherein, The control circuit transmits a control signal for resetting one of the two latches included in the page buffer.

5. The memory device according to claim 1, in, The control circuit separates the reset section by outputting a first control signal and a second control signal to be applied to the two page buffers, and The first activation segment of the first control signal and the second activation segment of the second control signal are separated from each other by a time length corresponding to at least one of the first activation segment or the second activation segment.

6. The memory device according to claim 5, wherein, The first enabled segment and the second enabled segment are identical to each other.

7. The memory device according to claim 5, wherein, The two page buffers are disposed between adjacent isolation pads formed in the semiconductor substrate.

8. The memory device according to claim 7, wherein, At least one of the two page buffers located between the adjacent isolation pads and at least one of the page buffers located outside the adjacent isolation pads have partially overlapping enabled sections.

9. The memory device according to claim 1, wherein, In the plan view, the page buffer has a width corresponding to 3.5 or 5 lines formed in the semiconductor substrate.

10. A semiconductor device comprising: The structure includes multiple buffers arranged in a predetermined direction, each buffer including a latch for storing data; as well as A control circuit that separates the corresponding enable segments of the two buffers from each other for a time length corresponding to at least one of the enable segments. The two buffers are arranged directly adjacent to each other among the plurality of buffers.

11. The semiconductor device according to claim 10, wherein, The buffer includes: A sensing node, which is used to receive or output the data; and Two latches are connected to the sensing node.

12. The semiconductor device according to claim 11, wherein, The control circuit transmits a control signal for resetting one of the two latches included in the buffer.

13. The semiconductor device according to claim 12, in, The control circuit separates the enabled section by outputting a first control signal and a second control signal to be applied to the two buffers, and The first activation segment of the first control signal and the second activation segment of the second control signal are separated from each other by a time length corresponding to at least one of the first activation segment or the second activation segment.

14. The semiconductor device according to claim 13, wherein, The first enabled segment and the second enabled segment are identical to each other.

15. The semiconductor device according to claim 13, wherein, The two buffers are disposed between adjacent isolation pads formed in the semiconductor substrate.

16. The semiconductor device according to claim 15, wherein, At least one of the two buffers disposed between the adjacent isolation pads and at least one of the buffers disposed outside the adjacent isolation pads have partially overlapping enabled sections.

17. The semiconductor device according to claim 12, wherein, In the plan view, the buffer has a width corresponding to 3.5 or 5 lines formed in the semiconductor substrate.

18. A method of operating a memory device, the method comprising the steps of: A first control signal having a first enable segment is applied to the first page buffer of two page buffers that are directly adjacent to each other among a plurality of page buffers; as well as A second control signal with a second enable segment is applied to the second page buffer of the two page buffers. The first enabled segment and the second enabled segment are separated from each other for a period of time, and the time period corresponds to at least one of the first enabled segment or the second enabled segment.

19. The method according to claim 18, wherein, The first page buffer and the second page buffer are disposed between adjacent isolation pads formed in the semiconductor substrate.

20. The method according to claim 18, wherein, The first enabled segment and the second enabled segment are identical to each other.

21. A memory device comprising: An array of memory cells arranged in rows; A first page buffer and a second page buffer are physically adjacent to each other and each includes a first latch and a second latch connected to a corresponding column. The second latch of the first page buffer is directly adjacent to the first latch of the second page buffer. as well as A control circuit applies a first signal and a second signal to a corresponding first latch to reset the first latch. The first signal and the second signal remain enabled for a corresponding time period, which is separated according to any one of the time periods.

Images