Memory element with dynamic pull-up write assist circuit

Abstract

Integrated circuits having an array of memory cells are provided. Each memory cell can include at least a pair of cross-coupled inverters, a write access transistor, and optionally a separate read port. The cross-coupled inverters in each memory cell can have a positive supply terminal. The positive supply terminal of each memory cell along a given column in the array can be coupled to a respective pull-up transistor. The pull-up transistor can receive a control signal from a pull-up weakening control circuit. The control signal can be temporarily raised during a write operation, otherwise can be driven back to ground to help optimize read performance. The pull-up weakening control circuit can be implemented using a chain of N-channel transistors or resistors.

Description

[0001] This application is a divisional application of the application filed on March 7, 2017, with application number 201780020754.5 and titled "Memory element with dynamic pull-up weakening write auxiliary circuit".

[0002] Cross-reference to related applications

[0003] This application claims priority to U.S. Patent Application No. 15 / 140,188, filed April 27, 2016, which is incorporated herein by reference in its entirety. Technical Field

[0004] This application relates to integrated circuits having memory, and more specifically, to volatile memory elements. Background Technology

[0005] Integrated circuits typically contain volatile memory elements. Volatile memory elements retain data only when the integrated circuit is powered. In the event of a power loss, the data in the volatile memory element is lost. Although non-volatile memory elements, such as those based on electrically erasable programmable read-only memory technology, do not suffer data loss in this way, it is generally not expected or possible to manufacture non-volatile memory elements as part of a given integrated circuit.

[0006] Therefore, volatile memory elements are often used. For example, a static random access memory (SRAM) chip contains SRAM cells, which are a type of volatile memory element. In programmable logic device (PLD) integrated circuits, SRAM cells can be used as configuration random access memory (CRAM) cells. A PLD is a type of integrated circuit that can be programmed by a user to implement desired custom logic functions. CRAM cells are used to store configuration data provided by the user. Once loaded, the CRAM cell provides control signals to the transistors to configure them and thus implement the desired logic function.

[0007] Volatile memory elements (such as SRAM and CRAM cells) are typically based on cross-coupled inverters (latches). In each memory element, the cross-coupled inverter is connected to an address transistor, which is turned on when data is read from or written to the memory element. When no data is being read from or written to the memory element, the address transistor is turned off to isolate the memory element.

[0008] As semiconductor technology advances towards smaller dimensions, lower supply voltages can be used to power integrated circuits. Lower supply voltages and smaller devices can lead to reduced read / write margins for volatile memory elements. This can pose challenges to reliable device operation. Summary of the Invention

[0009] An integrated circuit with memory cells is provided. The integrated circuit may include control circuitry that controls the array of memory cells. The control circuitry may include circuitry such as addressing circuitry, data register circuitry, and read / write circuitry.

[0010] The memory cell array may include groups of memory cells arranged in rows and columns. Each memory cell may have a bistable storage portion including at least first and second cross-coupled inverting circuits. Each inverting circuit may have a positive power supply terminal. According to an embodiment, the positive power supply terminal of the inverting circuit within a memory cell arranged along a given column may be coupled to only one corresponding pull-up weakening transistor (e.g., a single p-channel transistor may be shared between columns of memory cells).

[0011] Each pull-up transistor associated with a column of memory cells can receive a control signal from the pull-up weakening control circuitry. This control signal can be driven to the ground supply voltage level during read operations to help maximize read performance, and can be temporarily adjusted to a level greater than the ground supply voltage level during write operations to temporarily weaken the pull-up transistors.

[0012] The pull-up weakening control circuit can be configured to a first mode, wherein the control signal is biased to a first predetermined voltage level during a write operation, or configured to a second mode, wherein the control signal is biased to a second predetermined voltage level different from the first predetermined voltage level during a write operation. In one variation, the pull-up weakening control circuit may include a series-coupled diode-connected n-channel transistor chain. In another variation, the pull-up weakening control circuit may include a series-coupled resistor chain.

[0013] The pull-up weakening control circuit can be controlled by a write trace signal. A digital flip-flop (as an example) can be used to generate the write trace signal. The flip-flop can receive a write enable signal at the data input, a clock signal at the clock input, and a self-timed write complete signal at the reset input. Configured in this way, the write trace signal can be asserted after the rising edge of the clock signal (assuming the write enable signal is asserted) until the write operation is complete, at which point it is signaled by the write complete signal.

[0014] Further features, properties, and various advantages of the invention will become more apparent from the accompanying drawings and the detailed description below. Attached Figure Description

[0015] Figure 1 This is a diagram of an illustrative programmable integrated circuit according to an embodiment.

[0016] Figure 2This is a diagram of an illustrative memory element array according to an embodiment.

[0017] Figure 3 This is a diagram of a memory element array coupled to a pull-up weakening circuit according to an embodiment.

[0018] Figure 4 This is a diagram of an illustrative pull-up weakening control circuit according to an embodiment.

[0019] Figure 5 The illustration is based on the embodiment and Figure 4 The timing diagram shows the relevant waveforms associated with the operation of the pull-up weakening control circuit.

[0020] Figure 6A This is a diagram of an illustrative circuit that can be used to generate a write tracking signal according to an embodiment.

[0021] Figure 6B The illustration is based on the embodiment and Figure 6A The timing diagram shown is associated with the relevant waveforms of the operation of writing to the tracking signal generator circuit.

[0022] Figure 7 This is a circuit diagram illustrating a resistor implementation of a pull-up weakening control circuit according to an embodiment.

[0023] Figure 8 It is an operational combination according to the embodiment. Figure 3 , 4 A flowchart illustrating the steps involved in using a pull-up weakening circuit of the type shown in Figure 7. Detailed Implementation

[0024] This relates to integrated circuit memory elements that exhibit improved write margins without compromising read margins. A memory element, sometimes referred to as a cell, can contain any suitable number of transistors. For example, a memory cell may include two cross-coupled inverting circuits, three cross-coupled inverting circuits, four cross-coupled inverting circuits, or more than four cross-coupled inverting circuits coupled to one or more access transistors. If desired, the voltage levels associated with the power supply signals, control signals, transistor body bias signals, and / or data signals of the memory cell can be adjusted in real time to improve performance.

[0025] Memory elements can be used in any suitable integrated circuit that utilizes memory. These integrated circuits can be memory chips, digital signal processing circuits with memory arrays, microprocessors, application-specific integrated circuits (ASICs) with memory arrays, programmable integrated circuits such as programmable logic device (PLD) integrated circuits (where memory elements are used to configure memory), or any other suitable integrated circuit. For clarity, the invention will sometimes be described in conjunction with PLD integrated circuits. However, this is merely illustrative. Memory cells according to embodiments of the invention can be used in any suitable circuit.

[0026] In integrated circuits such as memory chips or other circuits that require memory to store processed data, the memory element that performs the function of a static random access memory (RAM) cell is sometimes called an SRAM cell. In the context of programmable logic device integrated circuits, memory elements can be used to store configuration data, and are therefore sometimes referred to as configuration random access memory (CRAM) cells in this context.

[0027] Figure 1 An illustrative integrated circuit, such as a programmable logic device 10, is shown according to an embodiment of the present invention.

[0028] Device 10 may have input / output circuitry 13 for driving signal shutdown of device 10 and for receiving signals from other devices via input / output pins 14. Interconnect resources 16 (e.g., global and local vertical and horizontal conductive lines and buses) may be used to transmit signals on device 10. Interconnect resources 16 include fixed interconnects (conductive lines) and programmable interconnects (i.e., programmable connections between corresponding fixed interconnects). Programmable logic 11 may include combinational logic circuitry and sequential logic circuitry. Programmable logic 11 can be configured to perform custom logic functions. Programmable interconnects associated with interconnect resources can be considered part of programmable logic 11.

[0029] Programmable logic device 10 includes volatile memory elements 18, which can be loaded with configuration data (also referred to as programming data) using pin 14 and input-output circuitry 13. Once loaded, each memory element provides a corresponding static control output signal that controls the state of the associated logic components in programmable logic device 11. If desired, memory elements 18 can be used in an SRAM-type memory array (e.g., to store data for processing circuitry during operation of device 10).

[0030] Each memory element 18 can be formed from a plurality of transistors configured to form a bistable circuit. Complementary metal-oxide-semiconductor (CMOS) integrated circuit technology is used to form the memory element 18 using a suitable method; therefore, a CMOS-based memory element implementation will be described herein as an example. Other integrated circuit technologies can be used to form the memory elements and integrated circuits (wherein the memory elements are used to form a memory array) if desired.

[0031] The memory element can be loaded from an external erasable programmable read-only memory and control chip or other suitable data source via pin 14 and input / output circuitry 13. The loaded CRAM memory element 18 can provide static control signals applied to the terminals (e.g., gates) of circuit elements (e.g., metal-oxide-semiconductor transistors) in programmable logic 11 to control those elements (e.g., turn certain transistors on or off), thereby configuring the logic in programmable logic 11. The circuit elements can be transistors, such as transfer transistors, portions of multiplexers, lookup tables, logic arrays, AND, OR, NAND, and NOR logic gates, etc.

[0032] The memory elements 18 are arranged in an array. In a typical modern programmable logic device, there may be millions of memory elements 18 on each chip. During programming operations, configuration data is provided to the array of memory elements by a user (e.g., a logic designer). Once the configuration data is loaded, the memory elements 18 selectively control portions of the circuitry within the programmable logic 11, thereby customizing its functionality to operate as needed.

[0033] The circuitry of device 10 can be organized using any suitable architecture. As an example, the logic of programmable logic device 10 can be organized into a series of rows and columns of larger programmable logic regions, each containing multiple smaller logic regions. The logic resources of device 10 can be interconnected by interconnect resources 15, such as associated vertical and horizontal conductors. These conductors can include global conductive lines that generally span all of device 10, fractional lines such as half-lines or quarter-lines that span a portion of device 10, staggered lines of a specific length (e.g., sufficient to interconnect several logic regions), smaller local lines, or any other suitable arrangement of interconnect resources. If desired, the logic of device 10 can be arranged in more levels or layers, where multiple large regions are interconnected to form larger logic sections. Other device arrangements can also use logic that is not arranged in rows and columns.

[0034] When memory elements 18 are arranged in an array, configuration data can be loaded onto the memory elements using horizontal and vertical conductors and associated loading circuitry. Any suitable memory array architecture can be used for memory elements 18. Figure 2 A suitable arrangement is shown in the diagram. Figure 2 The illustrative array has only three rows and three columns of memory cells 18, but in general, there may be hundreds or thousands of rows and columns in memory array 17. Array 17 may be one of multiple arrays on a given device 10, may be a subarray as part of a larger array, or may be a group of any other suitable memory cells 18.

[0035] Each memory element 18 may be formed by a plurality of transistors configured to form a bistable circuit (e.g., a latch-type circuit). The true data storage node and the complementary data storage node in the bistable circuit element may store the corresponding true and complementary forms of data bits.

[0036] Bistable circuit elements can be based on any suitable number of transistors. For example, the bistable portion of each memory element can be formed by cross-coupled inverters, groups of multiple inverter-like circuits (e.g., in a distributed configuration, which provide enhanced immunity to soft error disturbances, etc.). Arrangements with bistable elements formed by cross-coupled inverters are sometimes described herein as examples. However, this is merely illustrative. Any suitable memory cell architecture can be used to form memory element 18.

[0037] Each memory element can provide a corresponding output signal OUT at its corresponding output path 19. In the CRAM array, each signal OUT is a static output control signal that can be transmitted on its corresponding path 26 and can be used to configure a corresponding transistor, such as transistor 24 or other circuit elements, in the associated programmable logic circuit.

[0038] Integrated circuit 10 may have control circuitry 12 for providing signals to memory array 17. Control circuitry 12 may receive power supply voltages, data, and other signals from external sources using pin 14, and may also receive power supply voltages, data, and other signals from internal sources using paths such as path 16. Control circuitry 12 may include circuitry such as addressing circuitry, data register circuitry, write circuitry, read circuitry, etc. Control circuitry 12 may use the power supply voltage provided by pin 14 to generate desired time-varying and fixed signals on paths such as paths 20 and 22.

[0039] Typically, any suitable number of conductive lines can be associated with paths 20 and 22. For example, each row of array 17 can have associated address lines (e.g., true address lines and complementary address lines) and associated read / write enable lines in the corresponding path 20 (as an example). Each column of array 17 can have a corresponding path 20 including data lines (e.g., true data lines and complementary data lines). A clear signal can be simultaneously transmitted to all cells in array 17 via a common clear line. The clear line can be vertically oriented, such that there is a branch of the clear line in each path 22, or it can be horizontally oriented, such that there is a branch of the clear line in each path 20. Clear lines are not required.

[0040] Power supplies can also be distributed in this global manner. For example, the positive power supply voltage Vcc can similarly be supplied to cell 18 in parallel using a pattern of shared horizontal or vertical conductors. The ground voltage Vss can similarly be supplied to cell 18 in parallel using a pattern of shared horizontal or vertical lines. Control lines, such as address lines and data lines, are typically orthogonal to each other (e.g., address lines are vertical while data lines are horizontal, or vice versa).

[0041] The terms "row" and "column" simply refer to one way of referring to a group of specific cells 18 in memory array 17, and are sometimes used interchangeably. Other line patterns can be used in paths 20 and 22 if needed. For example, different numbers of power signals, data signals, and address signals can be used.

[0042] The signals provided to memory element 18 can sometimes be collectively referred to as control signals. In a specific context, some of these signals may be called power signals, clear signals, data signals, address signals, etc. These different signal types are not mutually exclusive. For example, the clear signal used for array 17 can also be used as a type of control (address) signal that can be used to clear array 17. The clear signal can also be used as a power signal by supplying power to the inverter-like circuitry in cell 18. Similarly, because the clear operation is used to place logic zeros in memory cell 18, the clear signal can be used as a type of data signal.

[0043] The positive supply voltage Vcc can be provided via the positive supply line. The ground voltage Vss can be provided via the ground supply line. Any suitable value can be used for the positive supply voltage Vcc and the ground voltage Vss. For example, the positive supply voltage Vcc can be 1.2 volts, 1.1 volts, 1.0 volts, 0.9 volts, 0.8 volts, less than 0.8 volts, or any other suitable voltage. The ground voltage Vss can be zero volts (as an example). In a typical arrangement, the supply voltage Vcc can be 1.0 volt, Vss can be zero volts, and the signal levels for address, data, and clear signals can range from zero volts (when low) to 1.0 volts (when high). Arrangements can also be used where Vcc varies over time, where Vss is less than zero volts, and where control signals are overdriven (i.e., where control signals have a signal strength greater than Vcc - Vss).

[0044] Figure 3 This is a diagram showing an array of memory cells 18 that can be coupled to the pull-up weakening circuit 308. (See diagram for example.) Figure 3 As shown, memory cells 18 can be arranged in multiple columns. Each column of memory cells 18 can be connected to a corresponding group of bit lines BL and BL / . Each memory cell 18 can have a storage section including cross-coupled inverting circuits, such as inverters 300 and 302, each inverting circuit having an input, an output, and at least one power supply terminal 301 (e.g., a positive power supply terminal configured to receive the memory cell power supply voltage Vcell).

[0045] Specifically, the input of circuit 300 can be coupled to the output of circuit 302, and the input of 302 can be coupled to the output of circuit 300. The output of circuit 300 can be used as a first internal data storage node X1 of unit 18, while the output of circuit 302 can be used as a second internal data storage node X2 of unit 18. The storage portion of unit 18 configured in this way can be used to store a single data bit (e.g., data storage nodes X1 and X2 can store the true form and complement form of a single data bit, respectively). As an example, unit 18 storing high data bits can have data storage nodes X1 and X2 driven to "0" and "1", respectively. As another example, unit 18 storing low data bits can have data storage nodes X1 and X2 driven to "1" and "0", respectively.

[0046] The storage portion of memory cell 18 can be coupled to access transistors (sometimes referred to as memory “address” transistors or memory “transfer gate” transistors), such as transistors 304 and 306, to perform read and / or write operations. Figure 3In the example, access transistor 304 may be coupled between a first bit line (e.g., a true data line on which the true data signal BL is provided) and a first data storage node X1, while access transistor 306 may be coupled between a second bit line (e.g., a supplementary data line on which the supplementary data signal BL / is provided) and a second data storage node X2. Both transistors 304 and 306 may have gates coupled to word (address) lines on which word line signals WL are transmitted. Memory cells 18 arranged along the first row of the memory array may receive word line signals WL1 via the first address line; memory cells 18 arranged along the second row of the memory array may receive word line signals WL2 via the second address line; memory cells 18 arranged along the third row of the memory array may receive word line signals WL3 via the third address line; and so on.

[0047] During normal operation, the true and padded lines can be nominally driven to zero volts to minimize leakage current while the word line signal is deasserted (e.g., the address signal can be pulled low to disable access transistors 304 and 306). For example, the word line signal WL can be driven to -0.1V to reduce leakage current through access transistors 304 and 306. If needed, the word line signal can be driven to -0.2V or other negative voltages to further reduce leakage through the access transistors.

[0048] During a write operation, the desired data signal can be presented on the first and second bit lines (also referred to as data lines). Then, one of the selected word line signals can be asserted so that the corresponding access transistors 304 and 306 can load the desired value into memory cell 18. For example, bit line signals BL and BL / can be driven to logic "0" and "1" respectively to load the high data bit into memory cell 18 using activated transmission gates 304 and 306. As another example, bit line signals BL and BL / can be driven to logic "1" and "0" respectively to load the low data bit into memory cell 18 using activated transmission gates 304 and 306.

[0049] The read performance of memory cell 18 can be characterized by a metric commonly referred to as read noise margin or static noise margin (SNM), while the write performance of memory cell 18 can be characterized by another metric commonly referred to as write noise margin (WNM). Static noise margin can depend on the relative drive strength between the transfer gate (e.g., access transistors PG1 and PG2) and any pull-down transistors in the memory portion of memory cell 18. Specifically, it may be desirable to minimize the ratio of transfer gate drive strength to pull-down drive strength in order to optimize static noise margin (e.g., it may be desirable to increase the drive capability of the pull-down transistors in INV1 and INV2 relative to the transfer gate to ensure that data is not unintentionally flipped during read operations).

[0050] On the other hand, the write noise margin can depend on the relative drive strength between the transfer gate and the pull-up current path of memory cell 18. Specifically, it may be desirable to maximize the ratio of the transfer gate drive strength to the pull-up drive strength in order to optimize the write noise margin (e.g., it may be desirable to increase the resistance of the pull-up current path to ensure that new data can be properly loaded into cell 18 during a write operation).

[0051] In some embodiments, each memory cell 18 may also be provided with an additional read port, such as read circuitry 370. Figure 3 As shown, the read circuit 30 may include two pull-down transistors, such as n-channel transistors 376 and 378, series-coupled between the read bit line 374 and ground line 380 (e.g., a ground power supply line providing a ground power supply voltage Vss). Transistor 376 may have a gate terminal coupled to the output node X2 of the associated memory cell 18 via path 372. Transistor 378 may have a gate terminal for receiving the read word line signal RWL.

[0052] In this configuration, the read word line signal RWL (sometimes called the read address signal) can be asserted to perform a read operation on a given memory cell. Before asserting the control signal RWL, the read bit line signal RBL on the read data line 374 can be precharged high. When the read word line RWL is asserted, and if node X2 is high, the read bit line signal RBL will be pulled to ground via transistors 376 and 378. If node X2 is low, transistor 376 will remain off, and the read bit line signal RBL will remain high. Therefore, a high read bit line signal RBL indicates a low data bit stored on internal node X2, while a low read bit line signal RBL indicates a high data bit stored on internal node X2.

[0053] When using a separate read port such as read circuit 370, the read noise margin does not depend on the relative ratio of the transmit gate to the pull-down transistor, assuming that all write word line signals (e.g., WL1, WL2, WL3, etc.) are deasserted during the read operation. However, the read speed will depend on the memory cell power supply level Vcell. Generally, a higher Vcell will allow node X2 to be pulled high, thus turning on transistor 376 more. On the other hand, a lower Vcell results in a lower node X2, which reduces the drive strength of transistor 376 and causes a slower response time for read circuit 370.

[0054] According to an embodiment, memory cell 18 may be coupled to pull-up weakening circuitry 308, which is configured to dynamically improve write margin without affecting read performance. Pull-up weakening circuitry 308 may include pull-up weakening switches such as P-channel transistors and pull-up weakening control circuitry such as control circuitry 320, which simultaneously controls each pull-up transistor 310. Each memory cell 18 in a given column may be coupled to a corresponding pull-up weakening transistor 310.

[0055] Specifically, the pull-up weakening transistor 310 may have a source terminal connected to the positive power supply line 312 (e.g., a power supply terminal on which the positive power supply voltage Vcc is provided), a gate terminal receiving the control voltage Vg from the control circuitry 320, and a drain terminal connected to the positive power supply terminal 301 (see, e.g., via path 311) of each inverter 300 and inverter 302 in the associated column of memory cell 18. Connected in this way, each pull-up weakening transistor 310 can be used to transfer voltage Vcell to a column of memory cells via path 311. Only one pull-up weakening transistor 310 is needed per column (instead of multiple series p-channel transistors per memory cell as seen in other pull-up weakening techniques), which helps minimize any area overhead and reduce cost.

[0056] Pull-up weakening control circuit 320 can be used to generate a pull-up weakening control signal Vg. During a read operation, the control signal Vg can be driven up to ground voltage Vss (e.g., to zero volts or optionally below ground) to fully turn on transistor 310, causing Vcell to be driven up to the positive supply level Vcc. Operating in this way, read performance is unaffected by the presence of pull-up weakening transistor 310. This technique, combined with the use of read circuitry 370, helps to maximize read noise margin without reducing read speed, which directly allows memory cells to operate at lower voltage levels and helps to minimize overall power consumption.

[0057] During a write operation, control circuitry 320 can temporarily adjust signal Vg to an intermediate voltage level (e.g., the intermediate voltage level between positive power supply Vcc and ground power supply Vss) to temporarily reduce the pull-up drive strength of transistor 310. For example, during a data loading operation, Vg can be temporarily increased from 0V to 0.1V, 0.2V, 0.5V, or other analog voltage levels. This technique provides a flexible, effective, and efficient way to reduce the pull-up drive strength of the memory portion of each memory cell 18. This approach is particularly useful when the mobility of p-channel transistors begins to exceed that of n-channel transistors, as is sometimes observed in newer processing techniques.

[0058] Figure 4This is a circuit diagram of a suitable implementation of the pull-up weakening control circuit 320. For example... Figure 4 As shown, the pull-up weakening control circuit 320 may include n-channel transistors, such as transistors 400, 402, 404, 406, 408, 410, 412, and 414. Transistor 400 may have a drain terminal connected to the positive power supply line 312, a gate terminal shorted to its drain terminal, and a source terminal. Transistor 402 may have a drain terminal connected to the source terminal of transistor 400, a gate terminal connected to its drain terminal, and a source terminal. Transistor 404 may have a drain terminal connected to the source terminal of transistor 402, a gate terminal connected to its drain terminal, and a source terminal.

[0059] Transistors 400, 402, and 404 (with their gate terminals shorted to the drain terminal) are sometimes referred to as a "diode-connected" configuration. Transistors 400, 402, and 404 can typically have the same dimensions and can exhibit the same threshold voltage level Vt. Connected in this way, a voltage level (Vcc - Vt) can be provided at the source terminal of transistor 400; a voltage level (Vcc - 2 * Vt) can be provided at the source terminal of transistor 402; and a voltage level (Vcc - 3 * Vt) can be provided at the source terminal of transistor 404.

[0060] Transistor 406 may have a drain terminal connected to the gate terminal of transistor 402 (also short-circuited to the source terminal of transistor 400), a source terminal connected to intermediate node Y, and a gate terminal coupled to a first random access memory (RAM) bit cell R1. Transistor 408 may have a drain terminal connected to the gate terminal of transistor 404 (also short-circuited to the source terminal of transistor 402), a source terminal connected to intermediate node Y, and a gate terminal coupled to a second RAM bit cell R2. Transistor 410 may have a drain terminal connected to the source terminal of transistor 404, a source terminal connected to intermediate node Y, and a gate terminal coupled to a third RAM bit cell R3.

[0061] Transistors 412 and 414 are coupled in series between node Y and ground (e.g., a ground power supply line providing ground voltage Vss). Transistor 414 has a gate terminal that receives the write track signal Vwrite_track, while transistor 412 has a gate terminal that receives the signal Vwrite_track in an inverted form via inverter 416. Inverter 416 can be powered by the supply voltage VCC. The node where transistor 412 is connected to transistor 414 can serve as an output terminal of control circuit 320, at which a pull-up weakening control signal Vg is provided.

[0062] In this configuration, whenever the signal Vwrite_track is high, the signal Vg will be driven to ground Vss by transistor 414, and whenever the signal Vwrite_track is low, the signal Vg will be driven to some intermediate voltage level greater than the ground voltage Vss but less than the positive supply voltage Vcc, such that the pull-up weakening transistor 310 is only partially turned on—but not completely turned off—during the write operation. The voltage level of the signal Vg during the write operation can depend on the value of the bit stored in bit cells R1-R3. At any given time, only one cell R1-R3 should store a high bit. If cell R1 stores "1", transistor 406 is turned on to pull node Y to (Vcc-Vt). Conversely, if cell R2 stores "1", transistor 408 will be turned on to pull node Y to (Vcc-2*Vt). On the other hand, if cell R3 stores "1", transistor 410 is activated to pull node Y to (Vcc-3*Vt). Generally, a higher Vg provides more pull-up weakening than a relatively lower Vg. Therefore, the degree of pull-up weakening can be adjusted by controlling the values ​​stored in components R1-R3.

[0063] Figure 4 The example (where only three different adjustable voltage levels are provided at the output terminals) is merely illustrative and not intended to limit the scope of this embodiment. Circuit 320 can be expanded to support fewer than three different intermediate voltage levels or more than three different intermediate voltage levels if needed.

[0064] Figure 5 It is shown that... Figure 4 The timing diagram shows the relevant waveforms associated with the operation of the pull-up weakening control circuit 320. Figure 5 The diagram illustrates the memory clock signal CLK, the write enable signal WE, the registered write enable signal WE_Reg (e.g., clock-triggered and latched form of signal WE), the signal Vwrite_track, the write word line signal WL, and the pull-up weakening control signal Vg. At time tl, the signal CLK rises to sample the asserted write enable signal WE, which causes the registered signals WE_Reg and Vwrite_track to be driven low (as shown by arrows 500 and 502, respectively). When the signal Vwrite_track is driven low (i.e., when the signal Vwrite_track is asserted), the gate control signal Vg can begin to rise to a predetermined intermediate voltage level (as shown by arrow 504).

[0065] The write word line signal WL can be pulsed high at time t2. The signal Vg has sufficient time to stabilize at a predetermined voltage level between times t1 and t2. Depending on the configuration of the control circuit 320, the signal Vg can reach different voltage levels. In a first configuration, the signal Vg can be driven to a first voltage level (as indicated by line 548 when the signal WL is high). In a second configuration, the signal Vg can be driven to a second voltage level lower than the first voltage level (as indicated by line 550 when asserting the signal WL). In a third configuration, the signal Vg can be driven to a third voltage level lower than the second voltage level (as indicated by line 552 when the signal WL is pulsed high). Typically, a higher Vg signal provides stronger attenuation in the pull-up path of the memory cell.

[0066] At time t3, the word line signal WL can be deasserted (e.g., signal WL can be driven low). The duration between times t2 and t3 is sometimes referred to as the write cycle or write window ΔTwrite. When a low pulse is applied to signal WL, signal Vwrite_track rises (as shown by arrow 510), which also causes signal Vg to be driven back to ground, as shown by arrow 512. While signal Vg is driven all the way to zero volts, transistor 310 (see...) Figure 3 The pull-up drive strength is maximized, so that read performance is not affected by temporary pull-up weakening.

[0067] Figure 5 The operation (where the signal Vwrite_track is time-varying) is sometimes referred to as a "dynamic" pull-up weakening scheme. In other suitable embodiments, a "static" pull-up weakening scheme can also be implemented, such that the signal Vwrite_track is continuously driven low through normal operation of the memory cell (e.g., the signal Vwrite_track can be asserted during write, read, and hold modes). Configured in this way, the signal Vg will be fixed at a predetermined intermediate voltage level, which may even cause the pull-up drive strength of the memory cell to decrease during read operations.

[0068] Figure 6A This is a diagram of an illustrative circuit that can be used to generate the write track signal Vwrite_track according to an embodiment. Figure 6AAs shown, a clock-triggered element such as a digital flip-flop 600 can be used to output the signal Vwrite_track. The flip-flop may include a data input that receives the write enable signal WE, a clock input that receives the memory clock signal CLK, a reset input that receives the write completion signal Wdone, and a data bar output Qb that provides the signal Vwrite_track. The data bar output generates an inverted form of the latch signal at the data input. The signal Wdone is a self-timing signal that is automatically asserted at the end of the write time period ΔTwrite (see [link to documentation]). Figure 5 (and 6b). When the Wdone signal is asserted at the reset input of flip-flop 600, the Vwrite_track signal will be forced high. Figure 6A The write tracking signal generator is merely illustrative and is not intended to limit the scope of this embodiment.

[0069] Figure 6B It is shown that... Figure 6A The timing diagram shown is associated with the relevant waveforms of the operation of writing to the tracking signal generator circuit. Figure 6B The memory clock signal CLK, write enable signal WE, signal Vwrite_track, write word line signal WL, and write complete signal Wdone are shown. At time tl, signal CLK rises to sample the asserted write enable signal WE, which causes signal Vwrite_track to reset low at the output of flip-flop 600 (as shown by arrow 602) and signal Wdone to be pulsed low for a predetermined self-timed period ΔTself-timed (as shown by arrow 604). The duration of the period ΔTself-timed can be timed using a precision counter circuit included in control circuitry 320 (not shown).

[0070] At time t2, signal Wdone rises high, which causes signal WL to be driven low (as shown by arrow 606) and signal Vwrite_track to be driven high (as shown by arrow 608). Operating in this way, signal Vwrite_track can be asserted after the rising clock edge at signal CLK, allowing the pull-up weakening circuitry to reach a predetermined intermediate voltage level before the rising edge of word line signal WL, and the assertion can be de-asserted when the write word line signal WL falls low at the end of the write operation.

[0071] Figure 4 The circuit implementation (in which the threshold voltages of stacked n-channel transistors are used to provide different intermediate voltage levels) represents a suitable arrangement of the pull-up weakening control circuit 320. Figure 7Another suitable arrangement of a pull-up weakening control circuit (e.g., control circuit 320') is shown, which is implemented using a resistor chain. Figure 7 As shown, the control circuit 320' may include resistors R1-R4 and n-channel transistors, such as transistors 700, 702-1, 702-2, 702-3, 702-4, 706, and 708.

[0072] Resistors R1-R4 and transistor 700 can be sequentially coupled in series between the positive power supply line 312 and the ground line. This connection allows for the provision of a first predetermined intermediate voltage level V4 at node 750 coupled between resistors R1 and R2; a second predetermined intermediate voltage level V3 at node 752 coupled between resistors R2 and R3; a third predetermined intermediate voltage level V2 at node 754 coupled between resistors R3 and R4; and a fourth predetermined intermediate voltage level V1 at node 756 coupled between resistor R4 and transistor 700, wherein the voltage levels V4 > V3 > V2 > V1 as long as transistor 700 is on. Transistor 700 can receive an inverted signal Vwrite_track via inverter 702, such that transistor 700 is turned off when Vwrite_track is driven high.

[0073] Transistor 702-1 may have a drain terminal connected to node 756, a source terminal connected to intermediate node Z, and a gate terminal coupled to a first RAM bit cell R1. Transistor 702-2 may have a drain terminal connected to node 754, a source terminal connected to intermediate node Z, and a gate terminal coupled to a second RAM bit cell R2. Transistor 702-3 may have a drain terminal connected to node 752, a source terminal connected to intermediate node Z, and a gate terminal coupled to a third RAM bit cell R3. Transistor 702-4 may have a drain terminal connected to node 750, a source terminal connected to intermediate node Z, and a gate terminal coupled to a fourth RAM bit cell R4.

[0074] Transistors 706 and 708 are coupled in series between node Z and ground (e.g., a ground power supply line providing ground voltage Vss). Transistor 708 has a gate terminal that receives the write track signal Vwrite_track, while transistor 706 has a gate terminal that receives the inverted form of the signal Vwrite_track via inverter 710. The node where transistor 706 is connected to transistor 708 can serve as an output terminal of control circuit 320', at which a pull-up weakening control signal Vg is provided.

[0075] With this configuration, whenever the signal Vwrite_track is high, the signal Vg will be driven to ground Vss by transistor 708, and whenever the signal Vwrite_track is low, the signal Vg will be driven to some intermediate voltage level that is greater than the ground voltage Vss but less than the positive supply voltage Vcc, so that the pull-up weakening transistor 310 is only partially turned on (but not completely turned off) during the write operation.

[0076] The voltage level of signal Vg during a write operation can depend on the value of the bit stored in bit cells R1-R4. At any given time, only one of cells R1-R4 should store a high bit. If cell R1 stores "1", transistor 702-1 is turned on to pull node Z up to V1. Conversely, if cell R2 stores "1", transistor 702-2 will be turned on to pull node Z up to V2. On the other hand, if cell R3 stores "1", transistor 702-3 is activated to pull node Z up to V3. If cell R4 stores "1", transistor 702-4 is activated to pull node Z up to V4. Generally, a higher Vg provides more pull-up attenuation than a relatively lower Vg. Therefore, the degree of pull-up attenuation can be adjusted by controlling the values ​​stored in elements R1-R4.

[0077] Figure 7 The example (where only four different adjustable voltage levels are provided at the output terminals) is merely illustrative and not intended to limit the scope of this embodiment. If needed, circuit 320' can be expanded to support fewer than four different predetermined intermediate voltage levels or more than four different predetermined intermediate voltage levels.

[0078] Figure 8 This is a flowchart illustrating the steps of operating a pull-up weakening circuit, which is combined with... Figure 3 , 4 The type shown in Figure 7. In step 800, the pull-up weakening circuit 308 may wait for the rising edge of the signal CLK. When the rising edge of the signal CLK is detected, step 802 may be executed. In step 802, if the write enable signal WE is asserted, the write track signal Vwrite_track may be asserted to temporarily weaken the pull-up current path of each memory cell (e.g., by driving the signal VG to a desired predetermined voltage level to weaken the pull-up transistor 310).

[0079] In step 804, a high pulse can be applied to the write word line signal WL to initiate the data loading operation. On the falling edge of the word line signal WL, the signal Vwrite_track can be deasserted, causing the memory cell power supply voltage Vcell to be continuously pulled to the positive power supply VCC, thereby optimizing read performance (step 806). Processing can then return to step 800 to monitor the next write cycle, as shown in path 808.

[0080] These steps are merely illustrative. Existing steps may be modified or omitted, additional steps may be added, and the order of certain steps may be changed without departing from the scope of this embodiment.

[0081] To date, embodiments have been described with respect to integrated circuits. The methods and apparatus described herein can be incorporated into any suitable circuit. For example, they can be incorporated into various types of devices, such as programmable logic devices, application-specific standard products (ASSPs), and application-specific integrated circuits (ASICs). Examples of programmable logic devices include programmable array logic (PAL), programmable logic array (PLA), field-programmable logic array (FPLA), electrically programmable logic device (EPLD), electrically erasable programmable logic device (EEPLD), logic cell array (LCA), composite programmable logic device (CPLD), and field-programmable gate array (FPGA), to name just a few.

[0082] The programmable logic device described in one or more embodiments herein can be part of a data processing system that includes one or more of the following components: a processor; memory; I / O circuitry; and peripheral devices. Data processing can be used in a wide variety of applications, such as computer networks, data networks, instrumentation, video processing, digital signal processing, or any other suitable application where the advantages of programmable or reprogrammable logic are required. The programmable logic device can be used to perform a variety of different logical functions. For example, a programmable logic device can be configured as a processor or controller that cooperates with a system processor. The programmable logic device can also be used as an arbitrator to arbitrate access to shared resources in the data processing system. In yet another example, the programmable logic device can be configured as an interface between the processor and one of the other components in the system. In one embodiment, the programmable logic device can be one of a family of devices owned by ALTERA Corporation.

[0083] Additional Examples :

[0084] Additional Embodiment 1. An integrated circuit includes: a pair of bit lines; and a column of memory cells coupled to the pair of bit lines, wherein each memory cell in the column of memory cells includes a cross-coupled inverter having a positive power supply terminal, and wherein the positive power supply terminal of each memory cell in the column of memory cells is coupled only to a first pull-up transistor having a gate terminal for receiving an adjustable control signal.

[0085] Additional Embodiment 2. The integrated circuit according to Additional Embodiment 1 further includes: an additional pair of bit lines; and an additional column of memory cells coupled to the additional pair of bit lines, wherein each memory cell in the additional column of memory cells includes a cross-coupled inverter having a positive power supply terminal, and wherein the positive power supply terminal of each memory cell in the additional column of memory cells is coupled only to a second pull-up transistor having a gate terminal for receiving the adjustable control signal.

[0086] Additional Embodiment 3. The integrated circuit according to Additional Embodiment 1 further includes: a positive power supply line directly connected to the first pull-up transistor, wherein the first pull-up transistor includes a p-channel transistor.

[0087] Additional Embodiment 4. The integrated circuit according to Additional Embodiment 1 further includes: a pull-up weakening control circuit that outputs the adjustable control signal, wherein the pull-up weakening control circuit drives the adjustable control signal to the ground power supply level during a read operation and temporarily raises the adjustable control signal above the ground power supply level during a write operation.

[0088] Additional Embodiment 5. According to the integrated circuit of Additional Embodiment 4, the pull-up weakening control circuit comprises a chain of series-connected diode-connected n-channel transistors.

[0089] Additional Embodiment 6. According to the integrated circuit of Additional Embodiment 5, each diode in the chain is connected to an n-channel transistor having a gate terminal and a drain terminal shorted together.

[0090] Additional Embodiment 7. According to the integrated circuit of Additional Embodiment 5, the pull-up weakening control circuit further includes: a first transistor having a drain terminal connected only to an n-channel transistor connected to a first diode in the chain; and a second transistor having a drain terminal connected only to an n-channel transistor connected to a second diode in the chain, which is different from the n-channel transistor connected to the first diode.

[0091] Additional Embodiment 8. The integrated circuit according to Additional Embodiment 7 further includes: a first configuration memory element that provides a static control bit to the gate terminal of the first transistor; and a second configuration memory element that provides a static control bit to the gate terminal of the second transistor.

[0092] Additional Embodiment 9. According to the integrated circuit of Additional Embodiment 4, the pull-up weakening control circuit includes a chain of resistors connected in series.

[0093] Additional Embodiment 10. According to the integrated circuit of Additional Embodiment 9, wherein the pull-up weakening control circuit further comprises: a first transistor having a drain terminal connected only to a first intermediate node between a first resistor and a second resistor in the chain and a source terminal; and a second transistor having a drain terminal connected only to a second intermediate node between the second resistor and a third resistor in the chain and a source terminal, the source terminal being short-circuited to the source terminal of the first transistor.

[0094] Additional Example 11. A method of operating an integrated circuit having pull-up transistors shared in a row of memory cells, the method comprising: using a pull-up weakening control circuit to output a control signal at a ground supply voltage level to the pull-up transistor during a read operation; and using the pull-up weakening control circuit to temporarily adjust the control signal during a write operation so that the control signal is different from the ground supply voltage level.

[0095] Additional Example 12. The method according to Additional Example 11 further includes: generating a write trace signal to control the pull-up weakening control circuit.

[0096] Additional Example 13. According to the method of Additional Example 12, generating the write trace signal includes: using a trigger to generate the write trace signal.

[0097] Additional Example 14. According to the method of Additional Example 13, using the trigger to generate the write tracking signal includes: using the trigger to receive a write enable signal, a clock signal, and a self-timed write complete signal.

[0098] Additional Example 15. The method according to Additional Example 13 further includes: when the pull-up weakening control circuit is configured in a first state, adjusting the control signal to a first predetermined voltage level during the write operation; and when the pull-up weakening control is configured in a second state, adjusting the control signal to a second predetermined voltage level different from the first predetermined voltage level during the write operation.

[0099] Additional Example 16. An integrated circuit includes: a set of memory cells, each memory cell in the set of memory cells including an inverter circuit having a power supply terminal; a single pull-up transistor coupled to the power supply terminal of the inverter in each memory cell in the set of memory cells, wherein the pull-up transistor is shared among the set of memory cells; and a pull-up weakening control circuit configured to output a control signal at a first predetermined voltage level to the pull-up transistor in a first mode, and the pull-up weakening control circuit is configured to output a control signal at a second predetermined voltage level different from the first predetermined voltage level to the pull-up transistor in a second mode during a write operation.

[0100] Additional Embodiment 17. The integrated circuit according to Additional Embodiment 16 further includes: an additional set of memory cells, each memory cell in the additional set of memory cells including an inverter circuit having a power supply terminal; and another single pull-up transistor coupled to the power supply terminal of the inverter in each memory cell of the additional set of memory cells, wherein the other single pull-up transistor is shared among the additional set of memory cells, and wherein the other pull-up transistor also receives a control signal generated by the pull-up weakening control circuit.

[0101] Additional Embodiment 18. The integrated circuit according to Additional Embodiment 16, wherein the pull-up weakening control circuit comprises a chain of series-connected diode-connected n-channel transistors.

[0102] Additional Embodiment 19. The integrated circuit according to Additional Embodiment 16, wherein the pull-up weakening control circuit comprises a chain of resistors connected in series.

[0103] Additional Embodiment 20. According to the integrated circuit of Additional Embodiment 16, wherein the pull-up weakening control circuit includes: a first transistor having a source terminal; a second transistor having a source terminal shorted to the source terminal of the first transistor; a first memory element providing a first control bit to the first transistor; a second memory element providing a second control bit to the second transistor, wherein only the first control bit is asserted in the first mode and only the second control bit is asserted in the second mode; a third transistor; and a fourth transistor coupled in series with the third transistor between the source terminal of the first transistor and ground, wherein the third transistor receives a write track signal, and wherein the fourth transistor receives an inverted form of the write track signal.

[0104] The above description only illustrates the principles of the present invention, and those skilled in the art can make various modifications. The above embodiments can be implemented individually or in any combination.

Claims

1. An integrated circuit, comprising: A pair of bit lines; A column of memory cells coupled to the pair of bit lines, wherein each memory cell in the column includes a cross-coupled inverter with a positive power supply terminal, and wherein the positive power supply terminal of each memory cell in the column is coupled only to a first pull-up transistor having a gate terminal for receiving an adjustable control signal; and A pull-up weakening control circuit outputs the adjustable control signal, which drives the adjustable control signal to the ground power supply level during a read operation and temporarily raises the adjustable control signal above the ground power supply level during a write operation. The read circuit, coupled to the output node of the associated memory cell, is used to read data from the associated memory cell to maximize read noise margin without reducing read speed.

2. The integrated circuit of claim 1, wherein the read circuit includes a first pull-down transistor and a second pull-down transistor series coupled between the read bit line and the ground line.

3. The integrated circuit of claim 2, wherein the first pull-down transistor has a gate terminal coupled to the output node of the associated memory cell, and the second pull-down transistor has a gate terminal for receiving a corresponding read word line signal.

4. The integrated circuit according to claim 2 or 3, wherein the first pull-up transistor is configured to be fully turned on during a read operation, such that the memory cell power supply voltage is driven to a positive power supply level.

5. The integrated circuit according to claim 2 or 3, wherein the first pull-down transistor and the second pull-down transistor are n-channel transistors.

6. The integrated circuit according to claim 1, further comprising: An additional pair of bit lines; as well as An additional column of memory cells coupled to the additional pair of bit lines, wherein each memory cell in the additional column of memory cells includes a cross-coupled inverter with a positive power supply terminal, and wherein the positive power supply terminal of each memory cell in the additional column of memory cells is coupled only to a second pull-up transistor having a gate terminal for receiving the adjustable control signal.

7. The integrated circuit according to claim 1, wherein, The pull-up weakening control circuit includes a chain of resistors connected in series.

8. The integrated circuit according to claim 7, wherein, The pull-up weakening control circuit further includes: A first transistor having a drain terminal connected only to a first intermediate node between a first resistor and a second resistor in the chain, and a source terminal; and The second transistor has a drain terminal connected only to a second intermediate node between the second and third resistors in the chain, and a source terminal, the source terminal of the second transistor being short-circuited to the source terminal of the first transistor.

9. A method of operating an integrated circuit according to any one of claims 1-8, the integrated circuit having pull-up transistors shared in a column of memory cells, the method comprising: By utilizing a pull-up weakening control circuit, a control signal at the ground power supply voltage level is output to the pull-up transistor during the read operation; as well as The pull-up weakening control circuit is used to temporarily adjust the control signal to an intermediate voltage level between the positive power supply voltage level and the ground power supply voltage level during the write operation.

10. The method of claim 9, further comprising: A write trace signal is generated to control the pull-up weakening control circuit.

11. The method according to claim 10, wherein, Generating the write trace signal includes using a trigger to generate the write trace signal.

12. The method according to claim 11, wherein, Using the trigger to generate the write tracking signal includes using the trigger to receive a write enable signal, a clock signal, and a self-timed write complete signal.

13. The method of claim 11, further comprising: When the pull-up weakening control circuit is configured in the first state, the control signal is adjusted to a first predetermined voltage level during the write operation; as well as When the pull-up weakening control circuit is configured in the second state, it adjusts the control signal to a second predetermined voltage level that is different from the first predetermined voltage level during the write operation.

14. An integrated circuit, comprising: A set of memory cells, each of the memory cells comprising an inverting circuit having a power supply terminal; A single pull-up transistor coupled to the power supply terminal of an inverter in each of the group of memory cells, wherein the pull-up transistor is shared among the group of memory cells; and A pull-up weakening control circuit is configured to output a control signal at a first predetermined voltage level to the pull-up transistor in a first mode, and the pull-up weakening control circuit is configured to output a control signal at a second predetermined voltage level different from the first predetermined voltage level to the pull-up transistor in a second mode during a write operation. The read circuit, coupled to the output node of the associated memory cell, is used to read data from the associated memory cell to maximize read noise margin without reducing read speed.

15. The integrated circuit of claim 14, wherein the read circuit includes a first pull-down transistor and a second pull-down transistor series coupled between the read bit line and the ground line.

16. The integrated circuit of claim 15, wherein the first pull-down transistor has a gate terminal coupled to an output node of an associated memory cell, and the second pull-down transistor has a gate terminal for receiving a corresponding read word line signal.

17. The integrated circuit of claim 15 or 16, wherein the pull-up transistor is configured to be fully turned on during a read operation, such that the memory cell power supply voltage is driven to a positive power supply level.

18. The integrated circuit of claim 15 or 16, wherein the first pull-down transistor and the second pull-down transistor are n-channel transistors.

19. The integrated circuit of claim 14, further comprising: An additional set of memory cells, each of which includes an inverting circuit having a power supply terminal; as well as Another single pull-up transistor is coupled to the power supply terminal of the inverter in each of the additional set of memory cells, wherein the other single pull-up transistor is shared among the additional set of memory cells, and wherein the other single pull-up transistor also receives a control signal generated by the pull-up weakening control circuit.

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