Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a base and a layer to be etched on the base; forming an initial ice etch on the substrate; patterning the initial ice etch using an electron beam etching process to form the ice etch and a plurality of patterned openings within the ice etch, the patterned openings exposing a top surface of the substrate; forming a mask layer on the top surface of the ice etch; and etching the layer to be etched using the mask layer and the ice etch as a mask until the top surface of the base is exposed, thereby forming a patterned structure. The mask layer provides excellent protection for the ice etch, reducing damage to the ice etch during etching and thus effectively improving the accuracy of pattern transfer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] In semiconductor integrated circuit manufacturing, a series of processes, such as deposition, photolithography, and etching, are used to form semiconductor structures on a semiconductor substrate. Photolithography is used to create the desired pattern in photoresist, resulting in patterned photoresist that defines the areas to be etched. Etching is then used to transfer the patterned photoresist pattern to the layer to be etched.

[0003] However, there are still many problems with the graphical transmission of existing technologies. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the accuracy of pattern transfer.

[0005] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a base and a layer to be etched located on the base; forming an ice etchant on the substrate, the ice etchant exposing a portion of the top surface of the substrate; forming a mask layer on the top surface of the ice etchant; etching the layer to be etched using the mask layer and the ice etchant as a mask until the top surface of the base is exposed, thereby forming a patterned structure.

[0006] Optionally, the method for forming the ice etchant includes: forming an initial ice etchant on the substrate; and patterning the initial ice etchant to form the ice etchant.

[0007] Optionally, the method for forming the initial ice etchant on the substrate includes: performing a cryogenic treatment on the substrate; and introducing ice etchant gas into the top surface of the cryogenically treated substrate to form the initial ice etchant.

[0008] Optionally, the temperature range of the low-temperature treatment is -20 degrees Celsius to 0 degrees Celsius.

[0009] Optionally, the ice etchant gas includes: H2O, C7H8O, C8H 18 C9H 20 C 11 H 24 And C 14 H 30 The gas flow rate is controlled by the vapor pressure drop of the gas injection system, which ranges from 0.01 Torr to 0.5 Torr; the gas flow time is from 5 minutes to 20 minutes.

[0010] Optionally, the thickness of the ice etchant is 100 angstroms to 1000 angstroms.

[0011] Optionally, the thickness of the mask layer is 50 angstroms to 300 angstroms.

[0012] Optionally, the method of forming a mask layer on the top surface of the ice etchant includes: forming a mask material layer on the sidewalls and top surface of the ice etchant and on the top surface of the substrate, wherein the thickness of the mask material layer on the top surface of the ice etchant is greater than the thickness of the mask material layer on the top surface of the substrate; and etching back the mask material layer until the top surface of the substrate is exposed, thereby forming the mask layer.

[0013] Optionally, the deposition process for forming the mask material layer includes: space atomic layer deposition process or plasma-enhanced atomic layer deposition process.

[0014] Optionally, the process of etching the layer to be etched using the mask layer and the ice etchant as a mask includes: plasma etching process; the etching gas of the plasma etching process includes: Cl2, O2, SF6, CH2F2, Ar and He.

[0015] Optionally, the material of the layer to be etched includes: a semiconductor material; the semiconductor material includes: silicon or silicon germanium.

[0016] Optionally, the graphical structure includes a fin.

[0017] Optionally, after forming several of the patterned structures, the method further includes removing the mask layer and the ice etchant.

[0018] Optionally, the process for removing the mask layer includes an ashing process.

[0019] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0020] In the semiconductor structure formation method of the present invention, a mask layer is formed on the top surface of the ice etchant; the layer to be etched is etched using the mask layer and the ice etchant as a mask until the top surface of the substrate is exposed, thereby forming a patterned structure. The mask layer provides excellent protection for the ice etchant, reducing damage to the ice etchant during etching and thus effectively improving the accuracy of pattern transfer.

[0021] Furthermore, the thickness of the mask layer is 50 angstroms to 300 angstroms. Since the mask layer is also consumed during the etching process of the layer to be etched, a mask layer of a predetermined thickness is needed to provide continuous protection for the ice etchant. When the thickness of the mask layer is less than 50 angstroms, it is easily completely consumed during subsequent etching, thus damaging the ice etchant; when the thickness of the mask layer is greater than 300 angstroms, it increases the time required to fabricate the mask layer, thereby affecting production efficiency. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a semiconductor structure formation method;

[0023] Figures 2 to 6 This is a schematic diagram of the steps in an embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0024] As described in the background section, there are still many problems with the graphical representation of existing technologies. These will be explained in detail below with reference to the accompanying drawings.

[0025] Figure 1 This is a schematic diagram of a semiconductor structure formation method.

[0026] Please refer to Figure 1 The method includes: providing a substrate, the substrate including a base 100 and an etchable layer (not shown) located on the base 100; forming an initial ice etch (not shown) on the substrate; exposing the initial ice etch using an electron beam etching process to form an ice etch 101 and a plurality of patterned openings (not shown) located in the ice etch 101, the patterned openings exposing the top surface of the substrate; etching the etchable layer using the ice etch 101 as a mask until the top surface of the base 100 is exposed, forming a patterned structure 102.

[0027] In this embodiment, ice lithography is used to achieve pattern transfer. Compared with traditional photoresist processes, ice lithography eliminates the need for spin coating and chemical development steps, and the ice lithography can uniformly cover non-planar substrates. For example, ice lithography can be used to fabricate nanostructures on the tip of an atomic force microscope probe, and can also "string" nanoparticles onto carbon nanotubes with a diameter of only a few nanometers. These are extremely challenging for traditional technologies. In addition, thanks to the very low electron sensitivity of water ice, existing structures covered with ice lithography can still be clearly seen by electron scanning imaging. This unique advantage of ice lithography is highly beneficial for achieving nanometer-precision alignment in micro- and nano-fabrication processes, and also greatly improves etching accuracy.

[0028] However, in this embodiment, after the ice etchant 101 is formed, the ice etchant 101 is directly used as a mask to etch the layer to be etched. Since the etching process for the layer to be etched is a plasma etching process, the structure of the ice etchant 101 is relatively fragile and can easily be damaged under the bombardment of the plasma, thereby affecting the final etching accuracy.

[0029] Based on this, the present invention provides a method for forming a semiconductor structure, which involves forming a mask layer on the top surface of an ice etchant; using the mask layer and the ice etchant as a mask, etching the layer to be etched until the top surface of the substrate is exposed, thereby forming a patterned structure. The mask layer provides excellent protection for the ice etchant, reducing damage during etching and effectively improving the accuracy of pattern transfer.

[0030] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0031] Figures 2 to 6 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0032] Please refer to Figure 2 A substrate is provided, the substrate including a base 200 and an etchable layer 201 located on the base 200.

[0033] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0034] In this embodiment, the material of the layer 201 to be etched is a semiconductor material; the semiconductor material is silicon. In other embodiments, the semiconductor material may also be silicon-germanium.

[0035] In other embodiments, the material of the layer to be etched 201 may also be metal.

[0036] After providing the substrate, the process further includes: forming an ice etchant on the substrate, the ice etchant exposing a portion of the top surface of the substrate. For details of the formation process, please refer to [reference needed]. Figure 3 and Figure 4 .

[0037] Please refer to Figure 3 An initial ice etchant 202 is formed on the substrate.

[0038] In this embodiment, the method for forming initial ice etchant 202 on the substrate includes: performing a low-temperature treatment on the substrate; and introducing ice etchant gas into the top surface of the substrate after the low-temperature treatment to form the initial ice etchant 202.

[0039] In this embodiment, the ice etchant gas includes: H2O, C7H8O, and C8H2O. 18 C9H 20 C 11 H 24 And C14H30; gas flow rate: controlled by the vapor pressure drop of the gas injection system, the vapor pressure drop range is 0.01 Torr to 0.5 Torr; introduction time: 5 minutes to 20 minutes.

[0040] In this embodiment, the temperature range of the low-temperature treatment is -20 degrees Celsius to 0 degrees Celsius.

[0041] Please refer to Figure 4 The initial ice etchant 202 is patterned to form the ice etchant 203.

[0042] In this embodiment, the ice etchant 203 replaces the photoresist used in traditional processes, employing an ice etch process to achieve pattern transfer. Compared to traditional photoresist processes, ice etch eliminates the need for spin coating and chemical development steps, and the ice etchant 203 can uniformly cover non-planar substrates. For example, ice etch can be used to fabricate nanostructures on the tip of an atomic force microscope probe, and nanoparticles can be "stringed" onto carbon nanotubes with diameters of only a few nanometers. These are extremely challenging for traditional technologies. Furthermore, thanks to the very low electron sensitivity of water ice, existing structures covered with the ice etchant can still be clearly seen by electron scanning imaging. This unique advantage of the ice etch process is highly beneficial for achieving nanometer-precision alignment in micro-nano fabrication processes, and also significantly improves etching accuracy.

[0043] In this embodiment, the initial ice resist 202 is patterned using an electron beam etching process; the process parameters of the electron beam etching process include: electron beam energy (keV), where the electron beam energy is 1 / log 10 (D100 / D0), D0 is the maximum electron dose of the resist before it is affected by electron beam exposure. D100, also known as the critical dose, is the minimum electron dose required for the photoresist to be fully exposed; photodose sensitivity (D50, mC / cm2), D50 is the dose at which the exposure feature reaches half the thickness of the photoresist, either the original positive resist or the fully exposed negative resist.

[0044] In this embodiment, the thickness of the ice etchant 203 is 100 angstroms to 1000 angstroms.

[0045] Please refer to Figure 5 After forming the ice etchant 203, a mask layer 205 is formed on the top surface of the ice etchant 203.

[0046] In this embodiment, the method of forming a mask layer 205 on the top surface of the ice etch 203 includes: forming a mask material layer (not shown) on the sidewalls and top surface of the ice etch 203 and the top surface of the substrate, wherein the thickness of the mask material layer on the top surface of the ice etch 203 is greater than the thickness of the mask material layer on the top surface of the substrate; etching the mask material layer back until the top surface of the substrate is exposed, thereby forming the mask layer 205.

[0047] In this embodiment, since the mask material layer has the characteristic of selective growth between the ice etchant 203 and the substrate, the thickness of the mask material layer on the top surface of the ice etchant 203 is greater than the thickness of the mask material layer on the top surface of the substrate. Therefore, when the mask material layer is etched back until the top surface of the substrate is exposed, the top surface of the ice etchant 203 still retains the mask material layer.

[0048] It should be noted that if the thickness of the mask material layer retained on the top surface of the ice etch 203 reaches the preset thickness, then there is no need to perform repeated deposition-back etching of the mask material layer, and the mask material layer retained on the top surface of the ice etch 203 is used as the mask layer 205; if the thickness of the mask material layer retained on the top surface of the ice etch 203 does not reach the preset thickness, then several deposition-back etching processes of the mask material layer are required until the stacked thickness of the mask material layer on the top surface of the ice etch 203 reaches the preset thickness, and the stacked mask material layer is used as the mask layer 205.

[0049] The method for forming the mask material layer includes: applying Si to harden the surface after depositing a C / H / F-based polymer; or applying SiO2 to harden the surface after depositing a C / H / O-based polymer.

[0050] In this embodiment, the method for forming the mask material layer is as follows: depositing and curing a CxHy-based polymer, then using CO2-based materials to trim and form a C / H / O-based polymer, and finally using SiO2 to harden the surface.

[0051] The deposition process for forming the mask material layer includes either space atomic layer deposition (SALD) or plasma-enhanced atomic layer deposition (ALD). In this embodiment, the deposition process for forming the mask material layer employs space atomic layer deposition (SALD). SALD is a thin film growth technology developed based on atomic layer deposition (ALD). Compared to traditional ALD processes, SALD offers advantages such as large-area, large-scale production, and continuous manufacturing capabilities. It can even be applied to flexible substrates, making it a promising technology for thin film deposition.

[0052] In this embodiment, the thickness of the mask layer 205 is 50 angstroms to 300 angstroms. Since the mask layer 205 is also consumed during the etching of the layer to be etched 201, a mask layer 205 of a predetermined thickness is needed to provide continuous protection for the ice etchant 203. When the thickness of the mask layer 205 is less than 50 angstroms, it is easily completely consumed during subsequent etching, thereby damaging the ice etchant 203; when the thickness of the mask layer 205 is greater than 300 angstroms, it increases the fabrication time of the mask layer 205, thus affecting production efficiency.

[0053] Please refer to Figure 6 Using the mask layer 205 and the ice etchant 203 as a mask, the layer to be etched 201 is etched until the top surface of the substrate 200 is exposed, forming a patterned structure 204.

[0054] In this embodiment, a mask layer 205 is formed on the top surface of the ice etchant 203; the layer to be etched 201 is etched using the mask layer 205 and the ice etchant 203 as a mask until the top surface of the substrate 200 is exposed, forming a patterned structure 204. The mask layer 205 provides excellent protection for the ice etchant 203, reducing damage to the ice etchant 203 during etching, thereby effectively improving the accuracy of pattern transfer.

[0055] In this embodiment, the process of etching the layer 201 to be etched using the mask layer 205 and the ice etchant 203 as masks is a plasma etching process.

[0056] In this embodiment, since the layer to be etched 201 is a semiconductor material, and the semiconductor material is silicon, the corresponding patterned structure 204 is a fin; the etching gas of the corresponding plasma etching process includes: Cl2, O2, SF6, CH2F2, Ar and He.

[0057] In other embodiments, when the material of the layer to be etched is a metal, the patterned structure may also be a conductive layer.

[0058] Please continue to refer to this. Figure 6 In this embodiment, after forming the patterned structure 204, the method further includes removing the mask layer 205 and the ice etchant 203.

[0059] In this embodiment, the process of removing the mask layer 205 includes: an ashing process; the gas used in the ashing process is an oxygen-containing gas, such as oxygen or ozone.

[0060] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a base and a layer to be etched on the base; An ice etchant is formed on the substrate, the ice etchant exposing a portion of the top surface of the substrate; A mask layer is formed on the top surface of the ice etchant; The layer to be etched is etched using the mask layer and the ice etchant as a mask until the top surface of the substrate is exposed, forming a patterned structure; wherein, A method for forming a mask layer on the top surface of the ice etchant includes: forming a mask material layer on the sidewalls and top surface of the ice etchant and on the top surface of the substrate based on selective growth characteristics, wherein the thickness of the mask material layer on the top surface of the ice etchant is greater than the thickness of the mask material layer on the top surface of the substrate; and etching back the mask material layer until the top surface of the substrate is exposed, thereby forming the mask layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the ice etchant includes: forming an initial ice etchant on the substrate; and patterning the initial ice etchant to form the ice etchant.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The method for forming an initial ice etchant on the substrate includes: performing a low-temperature treatment on the substrate; and introducing ice etchant gas into the top surface of the substrate after the low-temperature treatment to form the initial ice etchant.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The temperature range for the low-temperature treatment is -20 degrees Celsius to 0 degrees Celsius.

5. The method for forming a semiconductor structure as described in claim 3, characterized in that, The ice etchant gas includes: H2O, C7H8O, and C8H. 18 C9H 20 C 11 H 24 And C 14 H 30 The gas flow rate is controlled by the vapor pressure drop of the gas injection system, which ranges from 0.01 Torr to 0.5 Torr; the inlet time is 5 minutes to 20 minutes.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the ice etchant is 100 angstroms to 1000 angstroms.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the mask layer is 50 angstroms to 300 angstroms.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The deposition process for forming the mask material layer includes: space atomic layer deposition process or plasma-enhanced atomic layer deposition process.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process of etching the layer to be etched using the mask layer and the ice etchant as a mask includes: plasma etching process; the etching gas of the plasma etching process includes: Cl2, O2, SF6, CH2F2, Ar and He.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the layer to be etched includes: semiconductor material; the semiconductor material includes: silicon or silicon germanium.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The graphical structure includes: fins.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming several of the patterned structures, the process further includes removing the mask layer and the ice etchant.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The process for removing the mask layer includes: an ashing process.

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